lpc43xx_hic,system: use defines where possible

Adrian Negreanu · Adrian Negreanu · commit 41102e8a59a7 · 2022-01-09T21:21:12.000+02:00
diff --git a/source/hic_hal/nxp/lpc4322/system_LPC43xx.c b/source/hic_hal/nxp/lpc4322/system_LPC43xx.c
@@ -465,7 +465,7 @@ static void SetClock (void) {
 
   /* CPU base clock is in the mid frequency range before final clock set      */
   LPC_CGU->BASE_M4_CLK     = (0x01 << 11) |  /* Autoblock En                  */
-                             (0x09 << 24) ;  /* Clock source: PLL1            */
+                             (CLK_SRC_PLL1 << 24) ;  /* Clock source: PLL1    */
 
   /* Wait 20us */
   WaitUs(20, (CLK_XTAL * (PLL1_MSEL + 1)) / ((PLL1_NSEL + 1) * 2));
@@ -576,7 +576,7 @@ uint32_t MeasureFreq (uint32_t clk_sel) {
     }
   }
   fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
-  fout = fcnt * (12000000U/511U);                 /* FCNT * (IRC_CLK / RCNT)  */
+  fout = fcnt * (CLK_IRC/511U);                 /* FCNT * (IRC_CLK / RCNT)  */
 
   return (fout);
 }

Original file line number	Diff line number	Diff line change
`@@ -465,7 +465,7 @@ static void SetClock (void) {`
`465`	`465`
`466`	`466`	`/* CPU base clock is in the mid frequency range before final clock set */`
`467`	`467`	`LPC_CGU->BASE_M4_CLK = (0x01 << 11) \| /* Autoblock En */`
`468`		`- (0x09 << 24) ; /* Clock source: PLL1 */`
	`468`	`+ (CLK_SRC_PLL1 << 24) ; /* Clock source: PLL1 */`
`469`	`469`
`470`	`470`	`/* Wait 20us */`
`471`	`471`	`WaitUs(20, (CLK_XTAL * (PLL1_MSEL + 1)) / ((PLL1_NSEL + 1) * 2));`
`@@ -576,7 +576,7 @@ uint32_t MeasureFreq (uint32_t clk_sel) {`
`576`	`576`	`}`
`577`	`577`	`}`
`578`	`578`	`fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;`
`579`		`- fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */`
	`579`	`+ fout = fcnt * (CLK_IRC/511U); /* FCNT * (IRC_CLK / RCNT) */`
`580`	`580`
`581`	`581`	`return (fout);`
`582`	`582`	`}`