From dab6a539a19c1867a21a6175a41191d1453c9b68 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Arthur=20de=20Ara=C3=BAjo=20Farias?= Date: Fri, 6 Oct 2023 21:37:15 +0200 Subject: [PATCH] Upgraded STM32Cube_FW to version 1.27.1 Update README.md --- targets/TARGET_STM/README.md | 2 +- .../STM32Cube_FW/CMSIS/stm32f401xc.h | 34 +- .../STM32Cube_FW/CMSIS/stm32f401xe.h | 34 +- .../STM32Cube_FW/CMSIS/stm32f405xx.h | 34 +- .../STM32Cube_FW/CMSIS/stm32f407xx.h | 94 +- .../STM32Cube_FW/CMSIS/stm32f410cx.h | 34 +- .../STM32Cube_FW/CMSIS/stm32f410rx.h | 34 +- .../STM32Cube_FW/CMSIS/stm32f410tx.h | 34 +- .../STM32Cube_FW/CMSIS/stm32f411xe.h | 34 +- .../STM32Cube_FW/CMSIS/stm32f412cx.h | 34 +- .../STM32Cube_FW/CMSIS/stm32f412rx.h | 36 +- .../STM32Cube_FW/CMSIS/stm32f412vx.h | 38 +- .../STM32Cube_FW/CMSIS/stm32f412zx.h | 36 +- .../STM32Cube_FW/CMSIS/stm32f413xx.h | 36 +- .../STM32Cube_FW/CMSIS/stm32f415xx.h | 34 +- .../STM32Cube_FW/CMSIS/stm32f417xx.h | 94 +- .../STM32Cube_FW/CMSIS/stm32f423xx.h | 36 +- .../STM32Cube_FW/CMSIS/stm32f427xx.h | 98 +- .../STM32Cube_FW/CMSIS/stm32f429xx.h | 102 +- .../STM32Cube_FW/CMSIS/stm32f437xx.h | 98 +- .../STM32Cube_FW/CMSIS/stm32f439xx.h | 102 +- .../STM32Cube_FW/CMSIS/stm32f446xx.h | 38 +- .../STM32Cube_FW/CMSIS/stm32f469xx.h | 106 +- .../STM32Cube_FW/CMSIS/stm32f479xx.h | 106 +- .../STM32Cube_FW/CMSIS/stm32f4xx.h | 80 +- .../STM32Cube_FW/CMSIS/system_stm32f4xx.h | 30 +- .../STM32Cube_FW/CMakeLists.txt | 106 +- .../Legacy/stm32_hal_legacy.h | 310 +- .../Legacy/stm32f4xx_hal_can_legacy.c | 42 +- .../Legacy/stm32f4xx_hal_can_legacy.h | 30 +- .../Legacy/stm32f4xx_hal_eth_legacy.c | 2307 +++++++++ .../Legacy/stm32f4xx_hal_eth_legacy.h | 2209 ++++++++ .../STM32F4xx_HAL_Driver/stm32f4xx_hal.c | 30 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal.h | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.c | 917 ++-- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.h | 180 +- .../stm32f4xx_hal_adc_ex.c | 460 +- .../stm32f4xx_hal_adc_ex.h | 106 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_can.c | 146 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_can.h | 63 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.c | 85 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.h | 38 +- .../stm32f4xx_hal_cortex.c | 13 +- .../stm32f4xx_hal_cortex.h | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.c | 36 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.h | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c | 167 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.h | 12 +- .../stm32f4xx_hal_cryp_ex.c | 23 +- .../stm32f4xx_hal_cryp_ex.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.c | 49 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.h | 32 +- .../stm32f4xx_hal_dac_ex.c | 24 +- .../stm32f4xx_hal_dac_ex.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.c | 47 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.h | 14 +- .../stm32f4xx_hal_dcmi_ex.c | 23 +- .../stm32f4xx_hal_dcmi_ex.h | 14 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_def.h | 15 +- .../stm32f4xx_hal_dfsdm.c | 568 ++- .../stm32f4xx_hal_dfsdm.h | 267 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.c | 74 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.h | 12 +- .../stm32f4xx_hal_dma2d.c | 24 +- .../stm32f4xx_hal_dma2d.h | 23 +- .../stm32f4xx_hal_dma_ex.c | 12 +- .../stm32f4xx_hal_dma_ex.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.c | 456 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.h | 284 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.c | 4495 ++++++++++------- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.h | 2725 +++++----- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.c | 44 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.h | 12 +- .../stm32f4xx_hal_flash.c | 13 +- .../stm32f4xx_hal_flash.h | 13 +- .../stm32f4xx_hal_flash_ex.c | 617 ++- .../stm32f4xx_hal_flash_ex.h | 13 +- .../stm32f4xx_hal_flash_ramfunc.c | 13 +- .../stm32f4xx_hal_flash_ramfunc.h | 13 +- .../stm32f4xx_hal_fmpi2c.c | 1575 ++++-- .../stm32f4xx_hal_fmpi2c.h | 142 +- .../stm32f4xx_hal_fmpi2c_ex.c | 54 +- .../stm32f4xx_hal_fmpi2c_ex.h | 27 +- .../stm32f4xx_hal_fmpsmbus.c | 335 +- .../stm32f4xx_hal_fmpsmbus.h | 195 +- .../stm32f4xx_hal_fmpsmbus_ex.c | 45 +- .../stm32f4xx_hal_fmpsmbus_ex.h | 32 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.c | 63 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.h | 90 +- .../stm32f4xx_hal_gpio_ex.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.c | 58 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.h | 19 +- .../stm32f4xx_hal_hash_ex.c | 25 +- .../stm32f4xx_hal_hash_ex.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.c | 146 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.h | 27 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.c | 516 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.h | 12 +- .../stm32f4xx_hal_i2c_ex.c | 24 +- .../stm32f4xx_hal_i2c_ex.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.c | 39 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.h | 12 +- .../stm32f4xx_hal_i2s_ex.c | 23 +- .../stm32f4xx_hal_i2s_ex.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.c | 107 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.h | 24 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.c | 33 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.h | 13 +- .../stm32f4xx_hal_lptim.c | 192 +- .../stm32f4xx_hal_lptim.h | 47 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.c | 122 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.h | 111 +- .../stm32f4xx_hal_ltdc_ex.c | 24 +- .../stm32f4xx_hal_ltdc_ex.h | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.c | 478 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.h | 28 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.c | 2852 ++++++----- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.h | 217 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.c | 1504 +++--- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.h | 190 +- .../stm32f4xx_hal_pccard.c | 586 +-- .../stm32f4xx_hal_pccard.h | 106 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.c | 257 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.h | 69 +- .../stm32f4xx_hal_pcd_ex.c | 55 +- .../stm32f4xx_hal_pcd_ex.h | 17 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.c | 20 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.h | 14 +- .../stm32f4xx_hal_pwr_ex.c | 14 +- .../stm32f4xx_hal_pwr_ex.h | 14 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.c | 332 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.h | 41 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.c | 17 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.h | 15 +- .../stm32f4xx_hal_rcc_ex.c | 13 +- .../stm32f4xx_hal_rcc_ex.h | 17 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.c | 82 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.h | 37 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.c | 1318 ++--- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.h | 464 +- .../stm32f4xx_hal_rtc_ex.c | 968 ++-- .../stm32f4xx_hal_rtc_ex.h | 718 +-- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.c | 44 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.h | 18 +- .../stm32f4xx_hal_sai_ex.c | 27 +- .../stm32f4xx_hal_sai_ex.h | 16 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.c | 43 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.h | 13 +- .../stm32f4xx_hal_sdram.c | 1112 ++-- .../stm32f4xx_hal_sdram.h | 118 +- .../stm32f4xx_hal_smartcard.c | 69 +- .../stm32f4xx_hal_smartcard.h | 28 +- .../stm32f4xx_hal_smbus.c | 152 +- .../stm32f4xx_hal_smbus.h | 12 +- .../stm32f4xx_hal_spdifrx.c | 190 +- .../stm32f4xx_hal_spdifrx.h | 98 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.c | 159 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.h | 15 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.c | 978 ++-- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.h | 198 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.c | 1059 ++-- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.h | 209 +- .../stm32f4xx_hal_tim_ex.c | 369 +- .../stm32f4xx_hal_tim_ex.h | 34 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.c | 440 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.h | 78 +- .../stm32f4xx_hal_usart.c | 150 +- .../stm32f4xx_hal_usart.h | 51 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c | 26 +- .../STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.h | 15 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.c | 211 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.h | 343 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_bus.h | 13 +- .../stm32f4xx_ll_cortex.h | 15 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.c | 16 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.h | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.c | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.h | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.c | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.h | 18 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.c | 14 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.h | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.c | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.c | 1656 +++--- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.h | 1307 ++--- .../stm32f4xx_ll_fmpi2c.c | 15 +- .../stm32f4xx_ll_fmpi2c.h | 269 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.c | 1019 ++-- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.h | 895 ++-- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.c | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.c | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_iwdg.h | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.c | 25 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.h | 144 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.c | 14 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.h | 14 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.c | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.h | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.c | 47 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.h | 12 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.c | 76 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.h | 446 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.c | 193 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.h | 34 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.c | 14 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.h | 14 +- .../stm32f4xx_ll_system.h | 29 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.c | 115 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.h | 337 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.c | 52 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.h | 176 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.c | 276 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.h | 71 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.c | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.h | 13 +- .../STM32F4xx_HAL_Driver/stm32f4xx_ll_wwdg.h | 13 +- .../STM32Cube_FW/stm32f4xx_hal_conf.h | 86 +- .../STM32Cube_FW/system_stm32f4xx.c | 12 +- 221 files changed, 28241 insertions(+), 18996 deletions(-) create mode 100644 targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_eth_legacy.c create mode 100644 targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_eth_legacy.h diff --git a/targets/TARGET_STM/README.md b/targets/TARGET_STM/README.md index 11c63ad37b7..7000d6a4c4e 100644 --- a/targets/TARGET_STM/README.md +++ b/targets/TARGET_STM/README.md @@ -107,7 +107,7 @@ This table summarizes the STM32Cube versions currently used in Mbed OS master br | F1 | 1.8.3 | https://github.com/STMicroelectronics/STM32CubeF1 | | F2 | 1.6.0 | https://github.com/STMicroelectronics/STM32CubeF2 | | F3 | 1.11.2 | https://github.com/STMicroelectronics/STM32CubeF3 | -| F4 | 1.26.1 | https://github.com/STMicroelectronics/STM32CubeF4 | +| F4 | 1.27.1 | https://github.com/STMicroelectronics/STM32CubeF4 | | F7 | 1.16.1 | https://github.com/STMicroelectronics/STM32CubeF7 | | G0 | 1.5.0 | https://github.com/STMicroelectronics/STM32CubeG0 | | G4 | 1.4.0 | https://github.com/STMicroelectronics/STM32CubeG4 | diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f401xc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f401xc.h index 68a8dee7fb1..5445f5f7f3f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f401xc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f401xc.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -814,7 +815,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2371,6 +2380,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -8397,7 +8409,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -8629,7 +8641,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F401xC_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f401xe.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f401xe.h index 71a719cc883..fce4c2db85f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f401xe.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f401xe.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -814,7 +815,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2371,6 +2380,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -8397,7 +8409,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -8629,7 +8641,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F401xE_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f405xx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f405xx.h index 3294cb4ebe3..01b6d02e46e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f405xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f405xx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1044,7 +1045,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6460,6 +6469,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -13993,7 +14005,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -14298,7 +14310,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F405xx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f407xx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f407xx.h index 8bd71e47b4a..30056638b60 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f407xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f407xx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1148,7 +1149,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6760,6 +6769,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -13236,7 +13248,7 @@ typedef struct /* Ethernet MMC Registers bits definition */ /******************************************************************************/ -/* Bit definition for Ethernet MMC Contol Register */ +/* Bit definition for Ethernet MMC Control Register */ #define ETH_MMCCR_MCFHP_Pos (5U) #define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */ #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */ @@ -13320,7 +13332,7 @@ typedef struct #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */ -/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */ #define ETH_MMCRFAECR_RFAEC_Pos (0U) #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */ @@ -13334,34 +13346,37 @@ typedef struct /* Ethernet PTP Registers bits definition */ /******************************************************************************/ -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +/* Bit definition for Ethernet PTP Time Stamp Control Register */ +#define ETH_PTPTSCR_TSPFFMAE_Pos (18U) +#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */ +#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */ #define ETH_PTPTSCR_TSCNT_Pos (16U) #define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */ #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */ -#define ETH_PTPTSSR_TSSMRME_Pos (15U) -#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */ -#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ -#define ETH_PTPTSSR_TSSEME_Pos (14U) -#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */ -#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */ -#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U) -#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */ -#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ -#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U) -#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */ -#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ -#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U) -#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ -#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ -#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U) -#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ -#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ -#define ETH_PTPTSSR_TSSSR_Pos (9U) -#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */ -#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ -#define ETH_PTPTSSR_TSSARFE_Pos (8U) -#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */ -#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ +#define ETH_PTPTSCR_TSSMRME_Pos (15U) +#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */ +#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSCR_TSSEME_Pos (14U) +#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */ +#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U) +#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */ +#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U) +#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */ +#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U) +#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ +#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U) +#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ +#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSCR_TSSSR_Pos (9U) +#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */ +#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSCR_TSSARFE_Pos (8U) +#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */ +#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ #define ETH_PTPTSCR_TSARU_Pos (5U) #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */ @@ -13441,6 +13456,9 @@ typedef struct /******************************************************************************/ /* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_MB_Pos (26U) +#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */ +#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */ #define ETH_DMABMR_AAB_Pos (25U) #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */ #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */ @@ -15284,7 +15302,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -15589,7 +15607,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F407xx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410cx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410cx.h index 6673b3b6aa1..f497f98114f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410cx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410cx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -712,7 +713,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2450,6 +2459,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -7172,7 +7184,7 @@ typedef struct /********************** TIM Instances : 32 bit Counter ************************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM5)) @@ -7345,7 +7357,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F410Cx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410rx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410rx.h index d92437c63fd..2d8dafc0025 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410rx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410rx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -712,7 +713,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2450,6 +2459,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -7176,7 +7188,7 @@ typedef struct /********************** TIM Instances : 32 bit Counter ************************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM5)) @@ -7349,7 +7361,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F410Rx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410tx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410tx.h index 8c660d54cee..f8dbd38788e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410tx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f410tx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -702,7 +703,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2440,6 +2449,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -7126,7 +7138,7 @@ typedef struct /********************** TIM Instances : 32 bit Counter ************************/ #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)((INSTANCE) == TIM5) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM5)) @@ -7294,7 +7306,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F410Tx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f411xe.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f411xe.h index c3b3620d63e..2836aaf164f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f411xe.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f411xe.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -817,7 +818,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -2374,6 +2383,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -8432,7 +8444,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -8668,7 +8680,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F411xE_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f412cx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f412cx.h index daddb7dade2..9ed24c75eaf 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f412cx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f412cx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1007,7 +1008,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6524,6 +6533,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -13210,7 +13222,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -13495,7 +13507,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F412Cx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f412rx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f412rx.h index ad194a7c254..666de00b762 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f412rx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f412rx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1061,7 +1062,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6578,6 +6587,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -6708,7 +6720,7 @@ typedef struct #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -915,8 +916,6 @@ typedef struct #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL) #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL) #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL) -#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL) -#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL) #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL) #define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL) #define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL) @@ -1065,7 +1064,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6582,6 +6589,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -6712,7 +6722,7 @@ typedef struct #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1067,7 +1068,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6584,6 +6593,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -6714,7 +6726,7 @@ typedef struct #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1196,7 +1197,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6900,6 +6909,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -7034,7 +7046,7 @@ typedef struct #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1118,7 +1119,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6642,6 +6651,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -14278,7 +14290,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -14583,7 +14595,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F415xx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f417xx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f417xx.h index 1ad357e4862..7991625414b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f417xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f417xx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1222,7 +1223,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6939,6 +6948,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -13516,7 +13528,7 @@ typedef struct /* Ethernet MMC Registers bits definition */ /******************************************************************************/ -/* Bit definition for Ethernet MMC Contol Register */ +/* Bit definition for Ethernet MMC Control Register */ #define ETH_MMCCR_MCFHP_Pos (5U) #define ETH_MMCCR_MCFHP_Msk (0x1UL << ETH_MMCCR_MCFHP_Pos) /*!< 0x00000020 */ #define ETH_MMCCR_MCFHP ETH_MMCCR_MCFHP_Msk /* MMC counter Full-Half preset */ @@ -13600,7 +13612,7 @@ typedef struct #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */ -/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ +/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */ #define ETH_MMCRFAECR_RFAEC_Pos (0U) #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */ #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */ @@ -13614,34 +13626,37 @@ typedef struct /* Ethernet PTP Registers bits definition */ /******************************************************************************/ -/* Bit definition for Ethernet PTP Time Stamp Contol Register */ +/* Bit definition for Ethernet PTP Time Stamp Control Register */ +#define ETH_PTPTSCR_TSPFFMAE_Pos (18U) +#define ETH_PTPTSCR_TSPFFMAE_Msk (0x1UL << ETH_PTPTSCR_TSPFFMAE_Pos) /*!< 0x00008000 */ +#define ETH_PTPTSCR_TSPFFMAE ETH_PTPTSCR_TSPFFMAE_Msk /* Time stamp PTP frame filtering MAC address enable */ #define ETH_PTPTSCR_TSCNT_Pos (16U) #define ETH_PTPTSCR_TSCNT_Msk (0x3UL << ETH_PTPTSCR_TSCNT_Pos) /*!< 0x00030000 */ #define ETH_PTPTSCR_TSCNT ETH_PTPTSCR_TSCNT_Msk /* Time stamp clock node type */ -#define ETH_PTPTSSR_TSSMRME_Pos (15U) -#define ETH_PTPTSSR_TSSMRME_Msk (0x1UL << ETH_PTPTSSR_TSSMRME_Pos) /*!< 0x00008000 */ -#define ETH_PTPTSSR_TSSMRME ETH_PTPTSSR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ -#define ETH_PTPTSSR_TSSEME_Pos (14U) -#define ETH_PTPTSSR_TSSEME_Msk (0x1UL << ETH_PTPTSSR_TSSEME_Pos) /*!< 0x00004000 */ -#define ETH_PTPTSSR_TSSEME ETH_PTPTSSR_TSSEME_Msk /* Time stamp snapshot for event message enable */ -#define ETH_PTPTSSR_TSSIPV4FE_Pos (13U) -#define ETH_PTPTSSR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV4FE_Pos) /*!< 0x00002000 */ -#define ETH_PTPTSSR_TSSIPV4FE ETH_PTPTSSR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ -#define ETH_PTPTSSR_TSSIPV6FE_Pos (12U) -#define ETH_PTPTSSR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSSR_TSSIPV6FE_Pos) /*!< 0x00001000 */ -#define ETH_PTPTSSR_TSSIPV6FE ETH_PTPTSSR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ -#define ETH_PTPTSSR_TSSPTPOEFE_Pos (11U) -#define ETH_PTPTSSR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSSR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ -#define ETH_PTPTSSR_TSSPTPOEFE ETH_PTPTSSR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ -#define ETH_PTPTSSR_TSPTPPSV2E_Pos (10U) -#define ETH_PTPTSSR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSSR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ -#define ETH_PTPTSSR_TSPTPPSV2E ETH_PTPTSSR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ -#define ETH_PTPTSSR_TSSSR_Pos (9U) -#define ETH_PTPTSSR_TSSSR_Msk (0x1UL << ETH_PTPTSSR_TSSSR_Pos) /*!< 0x00000200 */ -#define ETH_PTPTSSR_TSSSR ETH_PTPTSSR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ -#define ETH_PTPTSSR_TSSARFE_Pos (8U) -#define ETH_PTPTSSR_TSSARFE_Msk (0x1UL << ETH_PTPTSSR_TSSARFE_Pos) /*!< 0x00000100 */ -#define ETH_PTPTSSR_TSSARFE ETH_PTPTSSR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ +#define ETH_PTPTSCR_TSSMRME_Pos (15U) +#define ETH_PTPTSCR_TSSMRME_Msk (0x1UL << ETH_PTPTSCR_TSSMRME_Pos) /*!< 0x00008000 */ +#define ETH_PTPTSCR_TSSMRME ETH_PTPTSCR_TSSMRME_Msk /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSCR_TSSEME_Pos (14U) +#define ETH_PTPTSCR_TSSEME_Msk (0x1UL << ETH_PTPTSCR_TSSEME_Pos) /*!< 0x00004000 */ +#define ETH_PTPTSCR_TSSEME ETH_PTPTSCR_TSSEME_Msk /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSCR_TSSIPV4FE_Pos (13U) +#define ETH_PTPTSCR_TSSIPV4FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV4FE_Pos) /*!< 0x00002000 */ +#define ETH_PTPTSCR_TSSIPV4FE ETH_PTPTSCR_TSSIPV4FE_Msk /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSCR_TSSIPV6FE_Pos (12U) +#define ETH_PTPTSCR_TSSIPV6FE_Msk (0x1UL << ETH_PTPTSCR_TSSIPV6FE_Pos) /*!< 0x00001000 */ +#define ETH_PTPTSCR_TSSIPV6FE ETH_PTPTSCR_TSSIPV6FE_Msk /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSCR_TSSPTPOEFE_Pos (11U) +#define ETH_PTPTSCR_TSSPTPOEFE_Msk (0x1UL << ETH_PTPTSCR_TSSPTPOEFE_Pos) /*!< 0x00000800 */ +#define ETH_PTPTSCR_TSSPTPOEFE ETH_PTPTSCR_TSSPTPOEFE_Msk /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSCR_TSPTPPSV2E_Pos (10U) +#define ETH_PTPTSCR_TSPTPPSV2E_Msk (0x1UL << ETH_PTPTSCR_TSPTPPSV2E_Pos) /*!< 0x00000400 */ +#define ETH_PTPTSCR_TSPTPPSV2E ETH_PTPTSCR_TSPTPPSV2E_Msk /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSCR_TSSSR_Pos (9U) +#define ETH_PTPTSCR_TSSSR_Msk (0x1UL << ETH_PTPTSCR_TSSSR_Pos) /*!< 0x00000200 */ +#define ETH_PTPTSCR_TSSSR ETH_PTPTSCR_TSSSR_Msk /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSCR_TSSARFE_Pos (8U) +#define ETH_PTPTSCR_TSSARFE_Msk (0x1UL << ETH_PTPTSCR_TSSARFE_Pos) /*!< 0x00000100 */ +#define ETH_PTPTSCR_TSSARFE ETH_PTPTSCR_TSSARFE_Msk /* Time stamp snapshot for all received frames enable */ #define ETH_PTPTSCR_TSARU_Pos (5U) #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */ @@ -13721,6 +13736,9 @@ typedef struct /******************************************************************************/ /* Bit definition for Ethernet DMA Bus Mode Register */ +#define ETH_DMABMR_MB_Pos (26U) +#define ETH_DMABMR_MB_Msk (0x1UL << ETH_DMABMR_MB_Pos) /*!< 0x04000000 */ +#define ETH_DMABMR_MB ETH_DMABMR_MB_Msk /* Mixed Burst */ #define ETH_DMABMR_AAB_Pos (25U) #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */ #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */ @@ -15564,7 +15582,7 @@ typedef struct #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM5)) -/***************** TIM Instances : external trigger input availabe ************/ +/***************** TIM Instances : external trigger input available ************/ #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ ((INSTANCE) == TIM2) || \ ((INSTANCE) == TIM3) || \ @@ -15869,7 +15887,3 @@ typedef struct #endif /* __cplusplus */ #endif /* __STM32F417xx_H */ - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f423xx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f423xx.h index c7135f42f76..d382c54f446 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f423xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/stm32f423xx.h @@ -12,13 +12,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1232,7 +1233,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6936,6 +6945,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -7070,7 +7082,7 @@ typedef struct #define FSMC_BCR1_CBURSTRW FSMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1242,7 +1243,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -7147,6 +7156,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -7289,7 +7301,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1298,7 +1299,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -7206,6 +7215,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -7348,7 +7360,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1320,7 +1321,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -7339,6 +7348,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -7481,7 +7493,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1374,7 +1375,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -7393,6 +7402,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -7535,7 +7547,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -1165,7 +1166,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6943,6 +6952,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -7082,7 +7094,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -459,7 +460,7 @@ typedef struct uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ - __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ @@ -1389,7 +1390,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -6818,7 +6827,7 @@ typedef struct #define DSI_LCOLCR_LPE_Pos (8U) #define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */ -#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */ +#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */ /******************* Bit definition for DSI_LPCR register ***************/ #define DSI_LPCR_DEP_Pos (0U) @@ -10383,6 +10392,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -10522,7 +10534,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,7 +48,9 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present */ +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 1U /*!< FPU present */ +#endif /** * @} @@ -460,7 +461,7 @@ typedef struct uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */ __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ - __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ @@ -1465,7 +1466,15 @@ typedef struct /** @addtogroup Exported_constants * @{ */ - + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */ +/** + * @} + */ + /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ @@ -7008,7 +7017,7 @@ typedef struct #define DSI_LCOLCR_LPE_Pos (8U) #define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */ -#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */ +#define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosely Packet Enable */ /******************* Bit definition for DSI_LPCR register ***************/ #define DSI_LPCR_DEP_Pos (0U) @@ -10573,6 +10582,9 @@ typedef struct #define FLASH_CR_EOPIE_Pos (24U) #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk #define FLASH_CR_LOCK_Pos (31U) #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk @@ -10712,7 +10724,7 @@ typedef struct #define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!
© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.
+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -106,16 +105,16 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS version number V2.6.6 + * @brief CMSIS version number V2.6.8 */ #define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */ #define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ +#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */ #define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\ |(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\ |(__STM32F4xx_CMSIS_VERSION_SUB2 << 8 )\ - |(__STM32F4xx_CMSIS_VERSION)) + |(__STM32F4xx_CMSIS_VERSION_RC)) /** * @} @@ -225,6 +224,60 @@ typedef enum #define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) /** * @} @@ -246,8 +299,3 @@ typedef enum /** * @} */ - - - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/system_stm32f4xx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/system_stm32f4xx.h index 99cb936c6fe..a979ef50467 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/system_stm32f4xx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMSIS/system_stm32f4xx.h @@ -3,32 +3,15 @@ * @file system_stm32f4xx.h * @author MCD Application Team * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. - ****************************************************************************** + ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -119,4 +102,3 @@ extern void SystemCoreClockUpdate(void); /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMakeLists.txt index ae0a4b831bd..629f190e5b3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMakeLists.txt +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/CMakeLists.txt @@ -3,106 +3,20 @@ add_library(mbed-stm32f4cube-fw INTERFACE) +file(GLOB STM32F4xx_HAL_Driver_SOURCES STM32F4xx_HAL_Driver/*.c) +file(GLOB STM32F4xx_HAL_Driver_Legacy_SOURCES STM32F4xx_HAL_Driver/Legacy/*.c) + target_sources(mbed-stm32f4cube-fw INTERFACE - STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_can_legacy.c - STM32F4xx_HAL_Driver/stm32f4xx_hal.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_adc_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_can.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_cortex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_dac_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_dfsdm.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_dma2d.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_flash.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ramfunc.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_hash_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_lptim.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_pccard.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_sai_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_sdram.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_smartcard.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_smbus.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_spdifrx.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_tim_ex.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_usart.c - STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_fmpi2c.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.c - STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.c - system_stm32f4xx.c + system_stm32f4xx.c + ${STM32F4xx_HAL_Driver_SOURCES} + ${STM32F4xx_HAL_Driver_Legacy_SOURCES} ) target_include_directories(mbed-stm32f4cube-fw INTERFACE - . - CMSIS - STM32F4xx_HAL_Driver - STM32F4xx_HAL_Driver/Legacy + . + CMSIS + STM32F4xx_HAL_Driver + STM32F4xx_HAL_Driver/Legacy ) diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32_hal_legacy.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32_hal_legacy.h index 299ed70498f..06cded950ef 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32_hal_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32_hal_legacy.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2019 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -38,6 +37,16 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR +#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#define CRYP_DATATYPE_32B CRYP_NO_SWAP +#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP +#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP +#define CRYP_DATATYPE_1B CRYP_BIT_SWAP +#if defined(STM32U5) +#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF +#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF +#endif /* STM32U5 */ +#endif /* STM32U5 || STM32H7 || STM32MP1 */ /** * @} */ @@ -97,6 +106,13 @@ extern "C" { #if defined(STM32H7) #define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT #endif /* STM32H7 */ + +#if defined(STM32U5) +#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES +#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES +#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 +#endif /* STM32U5 */ + /** * @} */ @@ -206,6 +222,23 @@ extern "C" { * @{ */ #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig +#if defined(STM32U5) +#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE +#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE +#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup CRC_Aliases CRC API aliases + * @{ + */ +#if defined(STM32C0) +#else +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#endif /** * @} */ @@ -235,11 +268,18 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32H7) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif +#if defined(STM32U5) +#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 +#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 +#endif + #if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID @@ -383,6 +423,9 @@ extern "C" { #endif /* STM32H7 */ +#if defined(STM32U5) +#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -462,7 +505,7 @@ extern "C" { #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) +#if defined(STM32G0) || defined(STM32C0) #define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE #define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH #else @@ -470,15 +513,24 @@ extern "C" { #define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE #endif #if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#define FLASH_FLAG_WDW FLASH_FLAG_WBNE -#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL +#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 +#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 +#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 +#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 +#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 +#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 +#define FLASH_FLAG_WDW FLASH_FLAG_WBNE +#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32U5) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U5 */ /** * @} @@ -521,6 +573,7 @@ extern "C" { #define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ + /** * @} */ @@ -595,12 +648,12 @@ extern "C" { #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB*/ +#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ #if defined(STM32L1) #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW @@ -616,6 +669,24 @@ extern "C" { #endif /* STM32F0 || STM32F3 || STM32F1 */ #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 + +#if defined(STM32U5) +#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 */ +#if defined(STM32U5) +#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP +#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 +#endif /* STM32U5 */ +/** + * @} + */ + +/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose + * @{ + */ +#if defined(STM32U5) +#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI +#endif /* STM32U5 */ /** * @} */ @@ -853,6 +924,20 @@ extern "C" { #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue +/** + * @} + */ + +#if defined(STM32U5) +#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF +#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF +#define LPTIM_CHANNEL_ALL 0x00000000U +#endif /* STM32U5 */ /** * @} */ @@ -1004,8 +1089,8 @@ extern "C" { #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 +#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE @@ -1016,15 +1101,22 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 +#if defined(STM32F7) +#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK +#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK +#endif /* STM32F7 */ + #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT +#endif /* STM32H7 */ +#if defined(STM32F7) || defined(STM32H7) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL -#endif /* STM32H7 */ +#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP +#endif /* STM32F7 || STM32H7 */ /** * @} @@ -1191,6 +1283,10 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif +#if defined(STM32U5) +#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS +#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK +#endif /** * @} */ @@ -1379,6 +1475,20 @@ extern "C" { */ #endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ +#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ + || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ + || defined(STM32H7) || defined(STM32U5) +/** @defgroup DMA2D_Aliases DMA2D API Aliases + * @{ + */ +#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort + for compatibility with legacy code */ +/** + * @} + */ + +#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ + /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose * @{ */ @@ -1397,6 +1507,29 @@ extern "C" { * @} */ +/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose + * @{ + */ + +#if defined(STM32U5) +#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr +#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT +#endif /* STM32U5 */ + +/** + * @} + */ + +#if !defined(STM32F2) +/** @defgroup HASH_alias HASH API alias + * @{ + */ +#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ +/** + * + * @} + */ +#endif /* STM32F2 */ /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose * @{ */ @@ -1584,6 +1717,79 @@ extern "C" { #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL +#if defined (STM32U5) +#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP +#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP +#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP +#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP +#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP +#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP +#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP +#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP +#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP +#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP +#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP +#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP +#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP + +#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP +#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP +#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP + +#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP +#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP +#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP +#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP +#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP +#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP +#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP +#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP +#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP +#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP +#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP +#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP +#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP +#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP + +#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP + +#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP +#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP +#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP +#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP +#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP +#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP +#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP +#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP +#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP +#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP +#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP +#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP +#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP +#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP + +#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP +#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP +#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP +#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP +#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP +#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP +#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP +#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP + +#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY +#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY +#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY + +#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN +#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN +#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN +#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN +#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN + +#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK +#endif + /** * @} */ @@ -3217,7 +3423,7 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3329,6 +3535,38 @@ extern "C" { #define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 #define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 +#if defined(STM32U5) +#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL +#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL +#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE +#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE +#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE +#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE +#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE +#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE +#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE +#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE +#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE +#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT +#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK +#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 +#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 +#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 +#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK +#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE +#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE +#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED +#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED +#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET +#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE +#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE +#endif /* STM32U5 */ /** * @} @@ -3346,7 +3584,9 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \ + defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32C0) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3403,13 +3643,22 @@ extern "C" { * @} */ -/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose +/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose * @{ */ #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS +#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) +#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE +#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE +#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV +#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV +#endif + #if defined(STM32F4) || defined(STM32F2) #define SD_SDMMC_DISABLED SD_SDIO_DISABLED #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY @@ -3738,6 +3987,16 @@ extern "C" { * @} */ +/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#if defined (STM32F7) +#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE +#endif /* STM32F7 */ +/** + * @} + */ + /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose * @{ */ @@ -3752,5 +4011,4 @@ extern "C" { #endif /* STM32_HAL_LEGACY */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_can_legacy.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_can_legacy.c index d92b7e7e114..e1751422581 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_can_legacy.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_can_legacy.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### User NOTE ##### @@ -79,33 +90,6 @@ @endverbatim - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * ****************************************************************************** */ @@ -136,7 +120,7 @@ #error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f4xx_hal_conf.h file' #endif /* HAL_CAN_MODULE_ENABLED */ -// #warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' +#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver' /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -1693,5 +1677,3 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_can_legacy.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_can_legacy.h index aacf0f0727d..e4d774b0d53 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_can_legacy.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_can_legacy.h @@ -6,29 +6,12 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -780,6 +763,3 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); #endif #endif /* __STM32F4xx_HAL_CAN_LEGACY_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_eth_legacy.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_eth_legacy.c new file mode 100644 index 00000000000..8de9453a8b6 --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_eth_legacy.c @@ -0,0 +1,2307 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_eth.c + * @author MCD Application Team + * @brief ETH HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Ethernet (ETH) peripheral: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a ETH_HandleTypeDef handle structure, for example: + ETH_HandleTypeDef heth; + + (#)Fill parameters of Init structure in heth handle + + (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) + + (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: + (##) Enable the Ethernet interface clock using + (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); + (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); + (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); + + (##) Initialize the related GPIO clocks + (##) Configure Ethernet pin-out + (##) Configure Ethernet NVIC interrupt (IT mode) + + (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: + (##) HAL_ETH_DMATxDescListInit(); for Transmission process + (##) HAL_ETH_DMARxDescListInit(); for Reception process + + (#)Enable MAC and DMA transmission and reception: + (##) HAL_ETH_Start(); + + (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer + the frame to MAC TX FIFO: + (##) HAL_ETH_TransmitFrame(); + + (#)Poll for a received frame in ETH RX DMA Descriptors and get received + frame parameters + (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) + + (#) Get a received frame when an ETH RX interrupt occurs: + (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) + + (#) Communicate with external PHY device: + (##) Read a specific register from the PHY + HAL_ETH_ReadPHYRegister(); + (##) Write data to a specific RHY register: + HAL_ETH_WritePHYRegister(); + + (#) Configure the Ethernet MAC after ETH peripheral initialization + HAL_ETH_ConfigMAC(); all MAC parameters should be filled. + + (#) Configure the Ethernet DMA after ETH peripheral initialization + HAL_ETH_ConfigDMA(); all DMA parameters should be filled. + + -@- The PTP protocol and the DMA descriptors ring mode are not supported + in this driver +*** Callback registration *** + ============================================= + + The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback. + + Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) DMAErrorCallback : DMA Error Callback. + (+) MspInitCallback : MspInit Callback. + (+) MspDeInitCallback: MspDeInit Callback. + + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default + weak function. + @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxCpltCallback : Tx Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) DMAErrorCallback : DMA Error Callback. + (+) MspInitCallback : MspInit Callback. + (+) MspDeInitCallback: MspDeInit Callback. + + By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback(). + Exception done for MspInit and MspDeInit functions that are + reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when + these callbacks are null (not registered beforehand). + if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit + keep and use the user MspInit/MspDeInit callbacks (registered beforehand) + + Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state, + thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit + or HAL_ETH_Init function. + + When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available and all callbacks + are set to the corresponding weak functions. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @defgroup ETH ETH + * @brief ETH HAL module driver + * @{ + */ + +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + +#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Constants ETH Private Constants + * @{ + */ +#define ETH_TIMEOUT_SWRESET 500U +#define ETH_TIMEOUT_LINKED_STATE 5000U +#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U + +/** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ETH_Private_Functions ETH Private Functions + * @{ + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err); +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); +static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth); +static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth); +static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth); +static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth); +static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth); +static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth); +static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth); +static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth); +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); +static void ETH_Delay(uint32_t mdelay); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup ETH_Exported_Functions ETH Exported Functions + * @{ + */ + +/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the Ethernet peripheral + (+) De-initialize the Ethernet peripheral + + @endverbatim + * @{ + */ + +/** + * @brief Initializes the Ethernet MAC and DMA according to default + * parameters. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) +{ + uint32_t tmpreg1 = 0U, phyreg = 0U; + uint32_t hclk = 60000000U; + uint32_t tickstart = 0U; + uint32_t err = ETH_SUCCESS; + + /* Check the ETH peripheral state */ + if(heth == NULL) + { + return HAL_ERROR; + } + + /* Check parameters */ + assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); + assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); + assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); + assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); + + if(heth->State == HAL_ETH_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + heth->Lock = HAL_UNLOCKED; +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + ETH_InitCallbacksToDefault(heth); + + if(heth->MspInitCallback == NULL) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + heth->MspInitCallback = HAL_ETH_MspInit; + } + heth->MspInitCallback(heth); + +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspInit(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + + /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Select MII or RMII Mode*/ + SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); + SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + (heth->Instance)->DMABMR |= ETH_DMABMR_SR; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for software reset */ + while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET) + { + heth->State= HAL_ETH_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are + not available, please check your external PHY or the IO configuration */ + return HAL_TIMEOUT; + } + } + + /*-------------------------------- MAC Initialization ----------------------*/ + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = (heth->Instance)->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg1 &= ETH_MACMIIAR_CR_MASK; + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + + /* Set CR bits depending on hclk value */ + if((hclk >= 20000000U)&&(hclk < 35000000U)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16; + } + else if((hclk >= 35000000U)&&(hclk < 60000000U)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26; + } + else if((hclk >= 60000000U)&&(hclk < 100000000U)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else if((hclk >= 100000000U)&&(hclk < 150000000U)) + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */ + { + /* CSR Clock Range between 150-183 MHz */ + tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102; + } + + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1; + + /*-------------------- PHY initialization and configuration ----------------*/ + /* Put the PHY in reset mode */ + if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set the ETH peripheral state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return HAL_ERROR */ + return HAL_ERROR; + } + + /* Delay to assure PHY reset */ + HAL_Delay(PHY_RESET_DELAY); + + if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) + { + /* Get tick */ + tickstart = HAL_GetTick(); + + /* We wait for linked status */ + do + { + HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); + + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_TIMEOUT; + } + } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); + + + /* Enable Auto-Negotiation */ + if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set the ETH peripheral state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return HAL_ERROR */ + return HAL_ERROR; + } + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait until the auto-negotiation will be completed */ + do + { + HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); + + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_TIMEOUT; + } + + } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); + + /* Read the result of the auto-negotiation */ + if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set the ETH peripheral state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return HAL_ERROR */ + return HAL_ERROR; + } + + /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ + if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) + { + /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ + (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; + } + else + { + /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ + (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; + } + /* Configure the MAC with the speed fixed by the auto-negotiation process */ + if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS) + { + /* Set Ethernet speed to 10M following the auto-negotiation */ + (heth->Init).Speed = ETH_SPEED_10M; + } + else + { + /* Set Ethernet speed to 100M following the auto-negotiation */ + (heth->Init).Speed = ETH_SPEED_100M; + } + } + else /* AutoNegotiation Disable */ + { + /* Check parameters */ + assert_param(IS_ETH_SPEED(heth->Init.Speed)); + assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); + + /* Set MAC Speed and Duplex Mode */ + if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) | + (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK) + { + /* In case of write timeout */ + err = ETH_ERROR; + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set the ETH peripheral state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return HAL_ERROR */ + return HAL_ERROR; + } + + /* Delay to assure PHY configuration */ + HAL_Delay(PHY_CONFIG_DELAY); + } + + /* Config MAC and DMA */ + ETH_MACDMAConfig(heth, err); + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief De-Initializes the ETH peripheral. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) +{ + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + if(heth->MspDeInitCallback == NULL) + { + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + } + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + heth->MspDeInitCallback(heth); +#else + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + HAL_ETH_MspDeInit(heth); +#endif + + /* Set ETH HAL state to Disabled */ + heth->State= HAL_ETH_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DMA Tx descriptors in chain mode. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param DMATxDescTab Pointer to the first Tx desc list + * @param TxBuff Pointer to the first TxBuffer list + * @param TxBuffCount Number of the used Tx desc in the list + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0U; + ETH_DMADescTypeDef *dmatxdesc; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ + heth->TxDesc = DMATxDescTab; + + /* Fill each DMATxDesc descriptor with the right values */ + for(i=0U; i < TxBuffCount; i++) + { + /* Get the pointer on the ith member of the Tx Desc list */ + dmatxdesc = DMATxDescTab + i; + + /* Set Second Address Chained bit */ + dmatxdesc->Status = ETH_DMATXDESC_TCH; + + /* Set Buffer1 address pointer */ + dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); + + if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) + { + /* Set the DMA Tx descriptors checksum insertion */ + dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; + } + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if(i < (TxBuffCount-1U)) + { + /* Set next descriptor address register with next descriptor base address */ + dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; + } + } + + /* Set Transmit Descriptor List Address Register */ + (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab; + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param DMARxDescTab Pointer to the first Rx desc list + * @param RxBuff Pointer to the first RxBuffer list + * @param RxBuffCount Number of the used Rx desc in the list + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0U; + ETH_DMADescTypeDef *DMARxDesc; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */ + heth->RxDesc = DMARxDescTab; + + /* Fill each DMARxDesc descriptor with the right values */ + for(i=0U; i < RxBuffCount; i++) + { + /* Get the pointer on the ith member of the Rx Desc list */ + DMARxDesc = DMARxDescTab+i; + + /* Set Own bit of the Rx descriptor Status */ + DMARxDesc->Status = ETH_DMARXDESC_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; + + /* Set Buffer1 address pointer */ + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); + + if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) + { + /* Enable Ethernet DMA Rx Descriptor interrupt */ + DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC; + } + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + if(i < (RxBuffCount-1U)) + { + /* Set next descriptor address register with next descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U); + } + else + { + /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + /* Set Receive Descriptor List Address Register */ + (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab; + + /* Set ETH HAL State to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Initializes the ETH MSP. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes ETH MSP. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_MspDeInit could be implemented in the user file + */ +} + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User ETH Callback + * To be used instead of the weak predefined callback + * @param heth eth handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID + * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID + * @param pCallback pointer to the Callback function + * @retval status + */ +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if(pCallback == NULL) + { + return HAL_ERROR; + } + /* Process locked */ + __HAL_LOCK(heth); + + if(heth->State == HAL_ETH_STATE_READY) + { + switch (CallbackID) + { + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = pCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = pCallback; + break; + + case HAL_ETH_DMA_ERROR_CB_ID : + heth->DMAErrorCallback = pCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(heth->State == HAL_ETH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(heth); + + return status; +} + +/** + * @brief Unregister an ETH Callback + * ETH callabck is redirected to the weak predefined callback + * @param heth eth handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID + * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID + * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID + * @retval status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process locked */ + __HAL_LOCK(heth); + + if(heth->State == HAL_ETH_STATE_READY) + { + switch (CallbackID) + { + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; + break; + + case HAL_ETH_DMA_ERROR_CB_ID : + heth->DMAErrorCallback = HAL_ETH_ErrorCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else if(heth->State == HAL_ETH_STATE_RESET) + { + switch (CallbackID) + { + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; + } + } + else + { + /* Return error status */ + status = HAL_ERROR; + } + + /* Release Lock */ + __HAL_UNLOCK(heth); + + return status; +} +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * + @verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Transmit a frame + HAL_ETH_TransmitFrame(); + (+) Receive a frame + HAL_ETH_GetReceivedFrame(); + HAL_ETH_GetReceivedFrame_IT(); + (+) Read from an External PHY register + HAL_ETH_ReadPHYRegister(); + (+) Write to an External PHY register + HAL_ETH_WritePHYRegister(); + + @endverbatim + + * @{ + */ + +/** + * @brief Sends an Ethernet frame. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param FrameLength Amount of data to be sent + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) +{ + uint32_t bufcount = 0U, size = 0U, i = 0U; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + if (FrameLength == 0U) + { + /* Set ETH HAL state to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_ERROR; + } + + /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ + if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) + { + /* OWN bit set */ + heth->State = HAL_ETH_STATE_BUSY_TX; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_ERROR; + } + + /* Get the number of needed Tx buffers for the current frame */ + if (FrameLength > ETH_TX_BUF_SIZE) + { + bufcount = FrameLength/ETH_TX_BUF_SIZE; + if (FrameLength % ETH_TX_BUF_SIZE) + { + bufcount++; + } + } + else + { + bufcount = 1U; + } + if (bufcount == 1U) + { + /* Set LAST and FIRST segment */ + heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS; + /* Set frame size */ + heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1); + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + heth->TxDesc->Status |= ETH_DMATXDESC_OWN; + /* Point to next descriptor */ + heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); + } + else + { + for (i=0U; i< bufcount; i++) + { + /* Clear FIRST and LAST segment bits */ + heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); + + if (i == 0U) + { + /* Setting the first segment bit */ + heth->TxDesc->Status |= ETH_DMATXDESC_FS; + } + + /* Program size */ + heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); + + if (i == (bufcount-1U)) + { + /* Setting the last segment bit */ + heth->TxDesc->Status |= ETH_DMATXDESC_LS; + size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE; + heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); + } + + /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ + heth->TxDesc->Status |= ETH_DMATXDESC_OWN; + /* point to next descriptor */ + heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); + } + } + + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + (heth->Instance)->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + (heth->Instance)->DMATPDR = 0U; + } + + /* Set ETH HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Checks for received frames. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) +{ + uint32_t framelength = 0U; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Check the ETH state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Check if segment is not owned by DMA */ + /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */ + if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)) + { + /* Check if last segment */ + if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) + { + /* increment segment count */ + (heth->RxFrameInfos).SegCount++; + + /* Check if last segment is first segment: one segment contains the frame */ + if ((heth->RxFrameInfos).SegCount == 1U) + { + (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; + } + + heth->RxFrameInfos.LSRxDesc = heth->RxDesc; + + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; + heth->RxFrameInfos.length = framelength; + + /* Get the address of the buffer start address */ + heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; + /* point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr); + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; + } + /* Check if first segment */ + else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) + { + (heth->RxFrameInfos).FSRxDesc = heth->RxDesc; + (heth->RxFrameInfos).LSRxDesc = NULL; + (heth->RxFrameInfos).SegCount = 1U; + /* Point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + } + /* Check if intermediate segment */ + else + { + (heth->RxFrameInfos).SegCount++; + /* Point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + } + } + + /* Set ETH HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_ERROR; +} + +/** + * @brief Gets the Received frame in interrupt mode. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) +{ + uint32_t descriptorscancounter = 0U; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set ETH HAL State to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Scan descriptors owned by CPU */ + while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB)) + { + /* Just for security */ + descriptorscancounter++; + + /* Check if first segment in frame */ + /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ + if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) + { + heth->RxFrameInfos.FSRxDesc = heth->RxDesc; + heth->RxFrameInfos.SegCount = 1U; + /* Point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + } + /* Check if intermediate segment */ + /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */ + else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET) + { + /* Increment segment count */ + (heth->RxFrameInfos.SegCount)++; + /* Point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr); + } + /* Should be last segment */ + else + { + /* Last segment */ + heth->RxFrameInfos.LSRxDesc = heth->RxDesc; + + /* Increment segment count */ + (heth->RxFrameInfos.SegCount)++; + + /* Check if last segment is first segment: one segment contains the frame */ + if ((heth->RxFrameInfos.SegCount) == 1U) + { + heth->RxFrameInfos.FSRxDesc = heth->RxDesc; + } + + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; + + /* Get the address of the buffer start address */ + heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; + + /* Point to next descriptor */ + heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; + } + } + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_ERROR; +} + +/** + * @brief This function handles ETH interrupt request. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + /* Frame received */ + if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) + { +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Receive complete callback*/ + heth->RxCpltCallback(heth); +#else + /* Receive complete callback */ + HAL_ETH_RxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the Eth DMA Rx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R); + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + } + /* Frame transmitted */ + else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) + { +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call resgistered Transfer complete callback*/ + heth->TxCpltCallback(heth); +#else + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the Eth DMA Tx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T); + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + } + + /* Clear the interrupt flags */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS); + + /* ETH DMA Error */ + if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS)) + { +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + heth->DMAErrorCallback(heth); +#else + /* Ethernet Error callback */ + HAL_ETH_ErrorCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the interrupt flags */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS); + + /* Set HAL State to Ready */ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet transfer error callbacks + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Reads a PHY register + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Basic Control Register, + * PHY_BSR: Transceiver Basic Status Register. + * More PHY register could be read depending on the used PHY + * @param RegValue PHY register value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) +{ + uint32_t tmpreg1 = 0U; + uint32_t tickstart = 0U; + + /* Check parameters */ + assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); + + /* Check the ETH peripheral state */ + if(heth->State == HAL_ETH_STATE_BUSY_RD) + { + return HAL_BUSY; + } + /* Set ETH HAL State to BUSY_RD */ + heth->State = HAL_ETH_STATE_BUSY_RD; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; + + /* Prepare the MII address register value */ + tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg1; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check for the Busy flag */ + while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > PHY_READ_TO) + { + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_TIMEOUT; + } + + tmpreg1 = heth->Instance->MACMIIAR; + } + + /* Get MACMIIDR value */ + *RegValue = (uint16_t)(heth->Instance->MACMIIDR); + + /* Set ETH HAL State to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Writes to a PHY register. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. + * This parameter can be one of the following values: + * PHY_BCR: Transceiver Control Register. + * More PHY register could be written depending on the used PHY + * @param RegValue the value to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) +{ + uint32_t tmpreg1 = 0U; + uint32_t tickstart = 0U; + + /* Check parameters */ + assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); + + /* Check the ETH peripheral state */ + if(heth->State == HAL_ETH_STATE_BUSY_WR) + { + return HAL_BUSY; + } + /* Set ETH HAL State to BUSY_WR */ + heth->State = HAL_ETH_STATE_BUSY_WR; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; + + /* Prepare the MII register address value */ + tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Give the value to the MII data register */ + heth->Instance->MACMIIDR = (uint16_t)RegValue; + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg1; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check for the Busy flag */ + while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + { + /* Check for the Timeout */ + if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) + { + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + return HAL_TIMEOUT; + } + + tmpreg1 = heth->Instance->MACMIIAR; + } + + /* Set ETH HAL State to READY */ + heth->State = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Enable MAC and DMA transmission and reception. + HAL_ETH_Start(); + (+) Disable MAC and DMA transmission and reception. + HAL_ETH_Stop(); + (+) Set the MAC configuration in runtime mode + HAL_ETH_ConfigMAC(); + (+) Set the DMA configuration in runtime mode + HAL_ETH_ConfigDMA(); + +@endverbatim + * @{ + */ + + /** + * @brief Enables Ethernet MAC and DMA reception/transmission + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) +{ + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Enable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionEnable(heth); + + /* Enable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionEnable(heth); + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + + /* Start DMA transmission */ + ETH_DMATransmissionEnable(heth); + + /* Start DMA reception */ + ETH_DMAReceptionEnable(heth); + + /* Set the ETH state to READY*/ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +{ + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State = HAL_ETH_STATE_BUSY; + + /* Stop DMA transmission */ + ETH_DMATransmissionDisable(heth); + + /* Stop DMA reception */ + ETH_DMAReceptionDisable(heth); + + /* Disable receive state machine of the MAC for reception from the MII */ + ETH_MACReceptionDisable(heth); + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + + /* Disable transmit state machine of the MAC for transmission on the MII */ + ETH_MACTransmissionDisable(heth); + + /* Set the ETH state*/ + heth->State = HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set ETH MAC Configuration. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf MAC Configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) +{ + uint32_t tmpreg1 = 0U; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State= HAL_ETH_STATE_BUSY; + + assert_param(IS_ETH_SPEED(heth->Init.Speed)); + assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); + + if (macconf != NULL) + { + /* Check the parameters */ + assert_param(IS_ETH_WATCHDOG(macconf->Watchdog)); + assert_param(IS_ETH_JABBER(macconf->Jabber)); + assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap)); + assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense)); + assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn)); + assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode)); + assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload)); + assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission)); + assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip)); + assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit)); + assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck)); + assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll)); + assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter)); + assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames)); + assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception)); + assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter)); + assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode)); + assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter)); + assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter)); + assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime)); + assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause)); + assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold)); + assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect)); + assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl)); + assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); + assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); + assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg1 = (heth->Instance)->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg1 &= ETH_MACCR_CLEAR_MASK; + + tmpreg1 |= (uint32_t)(macconf->Watchdog | + macconf->Jabber | + macconf->InterFrameGap | + macconf->CarrierSense | + (heth->Init).Speed | + macconf->ReceiveOwn | + macconf->LoopbackMode | + (heth->Init).DuplexMode | + macconf->ChecksumOffload | + macconf->RetryTransmission | + macconf->AutomaticPadCRCStrip | + macconf->BackOffLimit | + macconf->DeferralCheck); + + /* Write to ETHERNET MACCR */ + (heth->Instance)->MACCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Write to ETHERNET MACFFR */ + (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | + macconf->SourceAddrFilter | + macconf->PassControlFrames | + macconf->BroadcastFramesReception | + macconf->DestinationAddrFilter | + macconf->PromiscuousMode | + macconf->MulticastFramesFilter | + macconf->UnicastFramesFilter); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFFR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFFR = tmpreg1; + + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ + /* Write to ETHERNET MACHTHR */ + (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh; + + /* Write to ETHERNET MACHTLR */ + (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg1 = (heth->Instance)->MACFCR; + /* Clear xx bits */ + tmpreg1 &= ETH_MACFCR_CLEAR_MASK; + + tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | + macconf->ZeroQuantaPause | + macconf->PauseLowThreshold | + macconf->UnicastPauseFrameDetect | + macconf->ReceiveFlowControl | + macconf->TransmitFlowControl); + + /* Write to ETHERNET MACFCR */ + (heth->Instance)->MACFCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFCR = tmpreg1; + + /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ + (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | + macconf->VLANTagIdentifier); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACVLANTR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACVLANTR = tmpreg1; + } + else /* macconf == NULL : here we just configure Speed and Duplex mode */ + { + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg1 = (heth->Instance)->MACCR; + + /* Clear FES and DM bits */ + tmpreg1 &= ~(0x00004800U); + + tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); + + /* Write to ETHERNET MACCR */ + (heth->Instance)->MACCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + } + + /* Set the ETH state to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Sets ETH DMA Configuration. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf DMA Configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) +{ + uint32_t tmpreg1 = 0U; + + /* Process Locked */ + __HAL_LOCK(heth); + + /* Set the ETH peripheral state to BUSY */ + heth->State= HAL_ETH_STATE_BUSY; + + /* Check parameters */ + assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame)); + assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward)); + assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame)); + assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward)); + assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl)); + assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames)); + assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames)); + assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl)); + assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate)); + assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats)); + assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst)); + assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength)); + assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength)); + assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); + assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); + assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); + + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg1 = (heth->Instance)->DMAOMR; + /* Clear xx bits */ + tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; + + tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | + dmaconf->ReceiveStoreForward | + dmaconf->FlushReceivedFrame | + dmaconf->TransmitStoreForward | + dmaconf->TransmitThresholdControl | + dmaconf->ForwardErrorFrames | + dmaconf->ForwardUndersizedGoodFrames | + dmaconf->ReceiveThresholdControl | + dmaconf->SecondFrameOperate); + + /* Write to ETHERNET DMAOMR */ + (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMAOMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg1; + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | + dmaconf->FixedBurst | + dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + dmaconf->TxDMABurstLength | + dmaconf->EnhancedDescriptorFormat | + (dmaconf->DescriptorSkipLength << 2U) | + dmaconf->DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMABMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMABMR = tmpreg1; + + /* Set the ETH state to Ready */ + heth->State= HAL_ETH_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(heth); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * + @verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + (+) Get the ETH handle state: + HAL_ETH_GetState(); + + + @endverbatim + * @{ + */ + +/** + * @brief Return the ETH HAL state + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL state + */ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) +{ + /* Return ETH state */ + return heth->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup ETH_Private_Functions + * @{ + */ + +/** + * @brief Configures Ethernet MAC and DMA with default parameters. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param err Ethernet Init error + * @retval HAL status + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) +{ + ETH_MACInitTypeDef macinit; + ETH_DMAInitTypeDef dmainit; + uint32_t tmpreg1 = 0U; + + if (err != ETH_SUCCESS) /* Auto-negotiation failed */ + { + /* Set Ethernet duplex mode to Full-duplex */ + (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; + + /* Set Ethernet speed to 100M */ + (heth->Init).Speed = ETH_SPEED_100M; + } + + /* Ethernet MAC default initialization **************************************/ + macinit.Watchdog = ETH_WATCHDOG_ENABLE; + macinit.Jabber = ETH_JABBER_ENABLE; + macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; + macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; + macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; + macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; + if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) + { + macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; + } + else + { + macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; + } + macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; + macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; + macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; + macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; + macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; + macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; + macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; + macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; + macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; + macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; + macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; + macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; + macinit.HashTableHigh = 0x0U; + macinit.HashTableLow = 0x0U; + macinit.PauseTime = 0x0U; + macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; + macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; + macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; + macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; + macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; + macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; + macinit.VLANTagIdentifier = 0x0U; + + /*------------------------ ETHERNET MACCR Configuration --------------------*/ + /* Get the ETHERNET MACCR value */ + tmpreg1 = (heth->Instance)->MACCR; + /* Clear WD, PCE, PS, TE and RE bits */ + tmpreg1 &= ETH_MACCR_CLEAR_MASK; + /* Set the WD bit according to ETH Watchdog value */ + /* Set the JD: bit according to ETH Jabber value */ + /* Set the IFG bit according to ETH InterFrameGap value */ + /* Set the DCRS bit according to ETH CarrierSense value */ + /* Set the FES bit according to ETH Speed value */ + /* Set the DO bit according to ETH ReceiveOwn value */ + /* Set the LM bit according to ETH LoopbackMode value */ + /* Set the DM bit according to ETH Mode value */ + /* Set the IPCO bit according to ETH ChecksumOffload value */ + /* Set the DR bit according to ETH RetryTransmission value */ + /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ + /* Set the BL bit according to ETH BackOffLimit value */ + /* Set the DC bit according to ETH DeferralCheck value */ + tmpreg1 |= (uint32_t)(macinit.Watchdog | + macinit.Jabber | + macinit.InterFrameGap | + macinit.CarrierSense | + (heth->Init).Speed | + macinit.ReceiveOwn | + macinit.LoopbackMode | + (heth->Init).DuplexMode | + macinit.ChecksumOffload | + macinit.RetryTransmission | + macinit.AutomaticPadCRCStrip | + macinit.BackOffLimit | + macinit.DeferralCheck); + + /* Write to ETHERNET MACCR */ + (heth->Instance)->MACCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /*----------------------- ETHERNET MACFFR Configuration --------------------*/ + /* Set the RA bit according to ETH ReceiveAll value */ + /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ + /* Set the PCF bit according to ETH PassControlFrames value */ + /* Set the DBF bit according to ETH BroadcastFramesReception value */ + /* Set the DAIF bit according to ETH DestinationAddrFilter value */ + /* Set the PR bit according to ETH PromiscuousMode value */ + /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ + /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ + /* Write to ETHERNET MACFFR */ + (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | + macinit.SourceAddrFilter | + macinit.PassControlFrames | + macinit.BroadcastFramesReception | + macinit.DestinationAddrFilter | + macinit.PromiscuousMode | + macinit.MulticastFramesFilter | + macinit.UnicastFramesFilter); + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFFR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFFR = tmpreg1; + + /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ + /* Write to ETHERNET MACHTHR */ + (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh; + + /* Write to ETHERNET MACHTLR */ + (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow; + /*----------------------- ETHERNET MACFCR Configuration -------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg1 = (heth->Instance)->MACFCR; + /* Clear xx bits */ + tmpreg1 &= ETH_MACFCR_CLEAR_MASK; + + /* Set the PT bit according to ETH PauseTime value */ + /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ + /* Set the PLT bit according to ETH PauseLowThreshold value */ + /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ + /* Set the RFE bit according to ETH ReceiveFlowControl value */ + /* Set the TFE bit according to ETH TransmitFlowControl value */ + tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | + macinit.ZeroQuantaPause | + macinit.PauseLowThreshold | + macinit.UnicastPauseFrameDetect | + macinit.ReceiveFlowControl | + macinit.TransmitFlowControl); + + /* Write to ETHERNET MACFCR */ + (heth->Instance)->MACFCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFCR = tmpreg1; + + /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ + /* Set the ETV bit according to ETH VLANTagComparison value */ + /* Set the VL bit according to ETH VLANTagIdentifier value */ + (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | + macinit.VLANTagIdentifier); + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACVLANTR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACVLANTR = tmpreg1; + + /* Ethernet DMA default initialization ************************************/ + dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; + dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; + dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; + dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; + dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; + dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; + dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; + dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; + dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; + dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; + dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; + dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; + dmainit.DescriptorSkipLength = 0x0U; + dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; + + /* Get the ETHERNET DMAOMR value */ + tmpreg1 = (heth->Instance)->DMAOMR; + /* Clear xx bits */ + tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; + + /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ + /* Set the RSF bit according to ETH ReceiveStoreForward value */ + /* Set the DFF bit according to ETH FlushReceivedFrame value */ + /* Set the TSF bit according to ETH TransmitStoreForward value */ + /* Set the TTC bit according to ETH TransmitThresholdControl value */ + /* Set the FEF bit according to ETH ForwardErrorFrames value */ + /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ + /* Set the RTC bit according to ETH ReceiveThresholdControl value */ + /* Set the OSF bit according to ETH SecondFrameOperate value */ + tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | + dmainit.ReceiveStoreForward | + dmainit.FlushReceivedFrame | + dmainit.TransmitStoreForward | + dmainit.TransmitThresholdControl | + dmainit.ForwardErrorFrames | + dmainit.ForwardUndersizedGoodFrames | + dmainit.ReceiveThresholdControl | + dmainit.SecondFrameOperate); + + /* Write to ETHERNET DMAOMR */ + (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMAOMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg1; + + /*----------------------- ETHERNET DMABMR Configuration ------------------*/ + /* Set the AAL bit according to ETH AddressAlignedBeats value */ + /* Set the FB bit according to ETH FixedBurst value */ + /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ + /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ + /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ + /* Set the DSL bit according to ETH DesciptorSkipLength value */ + /* Set the PR and DA bits according to ETH DMAArbitration value */ + (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | + dmainit.FixedBurst | + dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ + dmainit.TxDMABurstLength | + dmainit.EnhancedDescriptorFormat | + (dmainit.DescriptorSkipLength << 2U) | + dmainit.DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMABMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMABMR = tmpreg1; + + if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) + { + /* Enable the Ethernet Rx Interrupt */ + __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R); + } + + /* Initialize MAC address in ethernet MAC */ + ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); +} + +/** + * @brief Configures the selected MAC address. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param MacAddr The MAC address to configure + * This parameter can be one of the following values: + * @arg ETH_MAC_Address0: MAC Address0 + * @arg ETH_MAC_Address1: MAC Address1 + * @arg ETH_MAC_Address2: MAC Address2 + * @arg ETH_MAC_Address3: MAC Address3 + * @param Addr Pointer to MAC address buffer data (6 bytes) + * @retval HAL status + */ +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg1; + + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + + /* Check the parameters */ + assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); + + /* Calculate the selected MAC address high register */ + tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; + /* Load the selected MAC address high register */ + (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; + /* Calculate the selected MAC address low register */ + tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; + + /* Load the selected MAC address low register */ + (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; +} + +/** + * @brief Enables the MAC transmission. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg1 = 0U; + + /* Enable the MAC transmission */ + (heth->Instance)->MACCR |= ETH_MACCR_TE; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; +} + +/** + * @brief Disables the MAC transmission. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg1 = 0U; + + /* Disable the MAC transmission */ + (heth->Instance)->MACCR &= ~ETH_MACCR_TE; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; +} + +/** + * @brief Enables the MAC reception. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg1 = 0U; + + /* Enable the MAC reception */ + (heth->Instance)->MACCR |= ETH_MACCR_RE; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; +} + +/** + * @brief Disables the MAC reception. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg1 = 0U; + + /* Disable the MAC reception */ + (heth->Instance)->MACCR &= ~ETH_MACCR_RE; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; +} + +/** + * @brief Enables the DMA transmission. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) +{ + /* Enable the DMA transmission */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; +} + +/** + * @brief Disables the DMA transmission. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) +{ + /* Disable the DMA transmission */ + (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; +} + +/** + * @brief Enables the DMA reception. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) +{ + /* Enable the DMA reception */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; +} + +/** + * @brief Disables the DMA reception. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) +{ + /* Disable the DMA reception */ + (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; +} + +/** + * @brief Clears the ETHERNET transmit FIFO. + * @param heth pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) +{ + __IO uint32_t tmpreg1 = 0U; + + /* Set the Flush Transmit FIFO bit */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMAOMR; + ETH_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg1; +} + +/** + * @brief This function provides delay (in milliseconds) based on CPU cycles method. + * @param mdelay specifies the delay time length, in milliseconds. + * @retval None + */ +static void ETH_Delay(uint32_t mdelay) +{ + __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); + do + { + __NOP(); + } + while (Delay --); +} + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) +{ + /* Init the ETH Callback settings */ + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ + heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */ +} +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ + STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#endif /* HAL_ETH_LEGACY_MODULE_ENABLED*/ +/** + * @} + */ + +/** + * @} + */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_eth_legacy.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_eth_legacy.h new file mode 100644 index 00000000000..ab84a468b0f --- /dev/null +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/Legacy/stm32f4xx_hal_eth_legacy.h @@ -0,0 +1,2209 @@ +/** + ****************************************************************************** + * @file stm32f4xx_hal_eth_legacy.h + * @author MCD Application Team + * @brief Header file of ETH HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F4xx_HAL_ETH_LEGACY_H +#define __STM32F4xx_HAL_ETH_LEGACY_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* Includes ------------------------------------------------------------------*/ +#include "stm32f4xx_hal_def.h" + +/** @addtogroup STM32F4xx_HAL_Driver + * @{ + */ + +/** @addtogroup ETH + * @{ + */ + +/** @addtogroup ETH_Private_Macros + * @{ + */ +#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) +#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ + ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) +#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ + ((SPEED) == ETH_SPEED_100M)) +#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ + ((MODE) == ETH_MODE_HALFDUPLEX)) +#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ + ((MODE) == ETH_RXINTERRUPT_MODE)) +#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ + ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) +#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ + ((MODE) == ETH_MEDIA_INTERFACE_RMII)) +#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ + ((CMD) == ETH_WATCHDOG_DISABLE)) +#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ + ((CMD) == ETH_JABBER_DISABLE)) +#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ + ((GAP) == ETH_INTERFRAMEGAP_40BIT)) +#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ + ((CMD) == ETH_CARRIERSENCE_DISABLE)) +#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ + ((CMD) == ETH_RECEIVEOWN_DISABLE)) +#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ + ((CMD) == ETH_LOOPBACKMODE_DISABLE)) +#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ + ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) +#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ + ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) +#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ + ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) +#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ + ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ + ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ + ((LIMIT) == ETH_BACKOFFLIMIT_1)) +#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ + ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) +#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ + ((CMD) == ETH_RECEIVEAll_DISABLE)) +#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ + ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ + ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) +#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ + ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ + ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) +#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ + ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) +#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ + ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) +#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ + ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) +#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ + ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ + ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ + ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) +#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ + ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ + ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) +#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) +#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ + ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) +#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ + ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ + ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ + ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) +#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ + ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) +#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ + ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) +#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ + ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) +#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ + ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) +#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) +#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ + ((ADDRESS) == ETH_MAC_ADDRESS1) || \ + ((ADDRESS) == ETH_MAC_ADDRESS2) || \ + ((ADDRESS) == ETH_MAC_ADDRESS3)) +#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ + ((ADDRESS) == ETH_MAC_ADDRESS2) || \ + ((ADDRESS) == ETH_MAC_ADDRESS3)) +#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ + ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) +#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ + ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) +#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ + ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) +#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ + ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) +#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ + ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) +#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ + ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) +#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ + ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) +#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ + ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) +#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ + ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) +#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ + ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ + ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ + ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) +#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ + ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) +#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ + ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) +#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ + ((CMD) == ETH_FIXEDBURST_DISABLE)) +#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ + ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) +#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ + ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) +#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) +#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ + ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ + ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ + ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ + ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) +#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ + ((FLAG) == ETH_DMATXDESC_IC) || \ + ((FLAG) == ETH_DMATXDESC_LS) || \ + ((FLAG) == ETH_DMATXDESC_FS) || \ + ((FLAG) == ETH_DMATXDESC_DC) || \ + ((FLAG) == ETH_DMATXDESC_DP) || \ + ((FLAG) == ETH_DMATXDESC_TTSE) || \ + ((FLAG) == ETH_DMATXDESC_TER) || \ + ((FLAG) == ETH_DMATXDESC_TCH) || \ + ((FLAG) == ETH_DMATXDESC_TTSS) || \ + ((FLAG) == ETH_DMATXDESC_IHE) || \ + ((FLAG) == ETH_DMATXDESC_ES) || \ + ((FLAG) == ETH_DMATXDESC_JT) || \ + ((FLAG) == ETH_DMATXDESC_FF) || \ + ((FLAG) == ETH_DMATXDESC_PCE) || \ + ((FLAG) == ETH_DMATXDESC_LCA) || \ + ((FLAG) == ETH_DMATXDESC_NC) || \ + ((FLAG) == ETH_DMATXDESC_LCO) || \ + ((FLAG) == ETH_DMATXDESC_EC) || \ + ((FLAG) == ETH_DMATXDESC_VF) || \ + ((FLAG) == ETH_DMATXDESC_CC) || \ + ((FLAG) == ETH_DMATXDESC_ED) || \ + ((FLAG) == ETH_DMATXDESC_UF) || \ + ((FLAG) == ETH_DMATXDESC_DB)) +#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ + ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) +#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ + ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ + ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ + ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) +#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) +#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ + ((FLAG) == ETH_DMARXDESC_AFM) || \ + ((FLAG) == ETH_DMARXDESC_ES) || \ + ((FLAG) == ETH_DMARXDESC_DE) || \ + ((FLAG) == ETH_DMARXDESC_SAF) || \ + ((FLAG) == ETH_DMARXDESC_LE) || \ + ((FLAG) == ETH_DMARXDESC_OE) || \ + ((FLAG) == ETH_DMARXDESC_VLAN) || \ + ((FLAG) == ETH_DMARXDESC_FS) || \ + ((FLAG) == ETH_DMARXDESC_LS) || \ + ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ + ((FLAG) == ETH_DMARXDESC_LC) || \ + ((FLAG) == ETH_DMARXDESC_FT) || \ + ((FLAG) == ETH_DMARXDESC_RWT) || \ + ((FLAG) == ETH_DMARXDESC_RE) || \ + ((FLAG) == ETH_DMARXDESC_DBE) || \ + ((FLAG) == ETH_DMARXDESC_CE) || \ + ((FLAG) == ETH_DMARXDESC_MAMPCE)) +#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ + ((BUFFER) == ETH_DMARXDESC_BUFFER2)) +#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ + ((FLAG) == ETH_PMT_FLAG_MPR)) +#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) +#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ + ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ + ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ + ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ + ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ + ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ + ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ + ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ + ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ + ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ + ((FLAG) == ETH_DMA_FLAG_T)) +#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) +#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ + ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ + ((IT) == ETH_MAC_IT_PMT)) +#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ + ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ + ((FLAG) == ETH_MAC_FLAG_PMT)) +#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) +#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ + ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ + ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ + ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ + ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ + ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ + ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ + ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ + ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) +#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ + ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) +#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ + ((IT) != 0x00U)) +#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ + ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ + ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) +#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ + ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) + +/** + * @} + */ + +/** @addtogroup ETH_Private_Defines + * @{ + */ +/* Delay to wait when writing to some Ethernet registers */ +#define ETH_REG_WRITE_DELAY 0x00000001U + +/* ETHERNET Errors */ +#define ETH_SUCCESS 0U +#define ETH_ERROR 1U + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U + +/* ETHERNET DMA Rx descriptors Frame length Shift */ +#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIAR register Mask */ +#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U + +/* ETHERNET MACCR register Mask */ +#define ETH_MACCR_CLEAR_MASK 0xFF20810FU + +/* ETHERNET MACFCR register Mask */ +#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U + +/* ETHERNET DMAOMR register Mask */ +#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8U + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U + /** + * @} + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup ETH_Exported_Types ETH Exported Types + * @{ + */ + +/** + * @brief HAL State structures definition + */ +typedef enum +{ + HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ + HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ + HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ + HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ + HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ + HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ + HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ + HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ + HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ + HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ +}HAL_ETH_StateTypeDef; + +/** + * @brief ETH Init Structure definition + */ + +typedef struct +{ + uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref ETH_AutoNegotiation */ + + uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. + This parameter can be a value of @ref ETH_Speed */ + + uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint16_t PhyAddress; /*!< Ethernet PHY address. + This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ + + uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ + + uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. + This parameter can be a value of @ref ETH_Rx_Mode */ + + uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. + This parameter can be a value of @ref ETH_Checksum_Mode */ + + uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. + This parameter can be a value of @ref ETH_Media_Interface */ + +} ETH_InitTypeDef; + + + /** + * @brief ETH MAC Configuration Structure definition + */ + +typedef struct +{ + uint32_t Watchdog; /*!< Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_Watchdog */ + + uint32_t Jabber; /*!< Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode. + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a collision occurs (Half-Duplex mode). + This parameter can be a value of @ref ETH_Retry_Transmission */ + + uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t BackOffLimit; /*!< Selects the BackOff limit value. + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ + + uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ + + uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ + + uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame. + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address). + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering. + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ + +} ETH_MACInitTypeDef; + +/** + * @brief ETH DMA Configuration Structure definition + */ + +typedef struct +{ + uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ + + uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. + This parameter can be a value of @ref ETH_Fixed_Burst */ + + uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. + This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ + + uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) + This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ + + uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. + This parameter can be a value of @ref ETH_DMA_Arbitration */ +} ETH_DMAInitTypeDef; + + +/** + * @brief ETH DMA Descriptors data structure definition + */ + +typedef struct +{ + __IO uint32_t Status; /*!< Status */ + + uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + + uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ + + uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ + + /*!< Enhanced ETHERNET DMA PTP Descriptors */ + uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ + + uint32_t Reserved1; /*!< Reserved */ + + uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ + + uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ + +} ETH_DMADescTypeDef; + +/** + * @brief Received Frame Informations structure definition + */ +typedef struct +{ + ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ + + ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ + + uint32_t SegCount; /*!< Segment count */ + + uint32_t length; /*!< Frame length */ + + uint32_t buffer; /*!< Frame buffer */ + +} ETH_DMARxFrameInfos; + +/** + * @brief ETH Handle Structure definition + */ + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +typedef struct __ETH_HandleTypeDef +#else +typedef struct +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ +{ + ETH_TypeDef *Instance; /*!< Register base address */ + + ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ + + uint32_t LinkStatus; /*!< Ethernet link status */ + + ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ + + ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ + + ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ + + __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ + + HAL_LockTypeDef Lock; /*!< ETH Lock */ + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + + void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */ + void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */ + void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< DMA Error Callback */ + void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */ + void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */ + +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +} ETH_HandleTypeDef; + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +/** + * @brief HAL ETH Callback ID enumeration definition + */ +typedef enum +{ + HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ + HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ + HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ + HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ + HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ + +}HAL_ETH_CallbackIDTypeDef; + +/** + * @brief HAL ETH Callback pointer definition + */ +typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */ + +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ETH_Exported_Constants ETH Exported Constants + * @{ + */ + +/** @defgroup ETH_Buffers_setting ETH Buffers setting + * @{ + */ +#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4U /*!< Ethernet CRC */ +#define ETH_EXTRA 2U /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ +#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ +#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ + + /* Ethernet driver receive buffers are organized in a chained linked-list, when + an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO + to the driver receive buffers memory. + + Depending on the size of the received ethernet packet and the size of + each ethernet driver receive buffer, the received packet can take one or more + ethernet driver receive buffer. + + In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE + and the total count of the driver receive buffers ETH_RXBUFNB. + + The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as + example, they can be reconfigured in the application layer to fit the application + needs */ + +/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet + packet */ +#ifndef ETH_RX_BUF_SIZE + #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ +#ifndef ETH_RXBUFNB + #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ +#endif + + + /* Ethernet driver transmit buffers are organized in a chained linked-list, when + an ethernet packet is transmitted, Tx-DMA will transfer the packet from the + driver transmit buffers memory to the TxFIFO. + + Depending on the size of the Ethernet packet to be transmitted and the size of + each ethernet driver transmit buffer, the packet to be transmitted can take + one or more ethernet driver transmit buffer. + + In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE + and the total count of the driver transmit buffers ETH_TXBUFNB. + + The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as + example, they can be reconfigured in the application layer to fit the application + needs */ + +/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet + packet */ +#ifndef ETH_TX_BUF_SIZE + #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE +#endif + +/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ +#ifndef ETH_TXBUFNB + #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ +#endif + + /** + * @} + */ + +/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor + * @{ + */ + +/* + DMA Tx Descriptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + ----------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of TDES0 register: DMA Tx descriptor status register + */ +#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ +#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ +#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ +#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ +#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ +#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ +#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ +#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ +#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ +#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ +#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ +#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ +#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ +#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ +#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ +#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ +#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ +#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ +#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ +#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ + +/** + * @brief Bit definition of TDES1 register + */ +#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ +#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TDES2 register + */ +#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TDES3 register + */ +#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ + + /*--------------------------------------------------------------------------------------------- + TDES6 | Transmit Time Stamp Low [31:0] | + ----------------------------------------------------------------------------------------------- + TDES7 | Transmit Time Stamp High [31:0] | + ----------------------------------------------------------------------------------------------*/ + +/* Bit definition of TDES6 register */ + #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ + +/* Bit definition of TDES7 register */ + #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ + +/** + * @} + */ +/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor + * @{ + */ + +/* + DMA Rx Descriptor + -------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of RDES0 register: DMA Rx descriptor status register + */ +#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ +#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ +#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ +#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ +#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ +#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ +#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ +#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ +#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ +#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ +#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/** + * @brief Bit definition of RDES1 register + */ +#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ +#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ +#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ +#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ +#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RDES2 register + */ +#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RDES3 register + */ +#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ + +/*--------------------------------------------------------------------------------------------------------------------- + RDES4 | Reserved[31:15] | Extended Status [14:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES5 | Reserved[31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES6 | Receive Time Stamp Low [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES7 | Receive Time Stamp High [31:0] | + --------------------------------------------------------------------------------------------------------------------*/ + +/* Bit definition of RDES4 register */ +#define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ +#define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ +#define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ + #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ + #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ + #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ + #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ + #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ + #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ + #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ +#define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ +#define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ +#define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ +#define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ +#define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ +#define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ + #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ + #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ + #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ + +/* Bit definition of RDES6 register */ +#define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ + +/* Bit definition of RDES7 register */ +#define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ +/** + * @} + */ + /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation + * @{ + */ +#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U +#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U + +/** + * @} + */ +/** @defgroup ETH_Speed ETH Speed + * @{ + */ +#define ETH_SPEED_10M 0x00000000U +#define ETH_SPEED_100M 0x00004000U + +/** + * @} + */ +/** @defgroup ETH_Duplex_Mode ETH Duplex Mode + * @{ + */ +#define ETH_MODE_FULLDUPLEX 0x00000800U +#define ETH_MODE_HALFDUPLEX 0x00000000U +/** + * @} + */ +/** @defgroup ETH_Rx_Mode ETH Rx Mode + * @{ + */ +#define ETH_RXPOLLING_MODE 0x00000000U +#define ETH_RXINTERRUPT_MODE 0x00000001U +/** + * @} + */ + +/** @defgroup ETH_Checksum_Mode ETH Checksum Mode + * @{ + */ +#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U +#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U +/** + * @} + */ + +/** @defgroup ETH_Media_Interface ETH Media Interface + * @{ + */ +#define ETH_MEDIA_INTERFACE_MII 0x00000000U +#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) +/** + * @} + */ + +/** @defgroup ETH_Watchdog ETH Watchdog + * @{ + */ +#define ETH_WATCHDOG_ENABLE 0x00000000U +#define ETH_WATCHDOG_DISABLE 0x00800000U +/** + * @} + */ + +/** @defgroup ETH_Jabber ETH Jabber + * @{ + */ +#define ETH_JABBER_ENABLE 0x00000000U +#define ETH_JABBER_DISABLE 0x00400000U +/** + * @} + */ + +/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap + * @{ + */ +#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ +#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ +#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ +#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ +#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ +#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ +#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ +#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ +/** + * @} + */ + +/** @defgroup ETH_Carrier_Sense ETH Carrier Sense + * @{ + */ +#define ETH_CARRIERSENCE_ENABLE 0x00000000U +#define ETH_CARRIERSENCE_DISABLE 0x00010000U +/** + * @} + */ + +/** @defgroup ETH_Receive_Own ETH Receive Own + * @{ + */ +#define ETH_RECEIVEOWN_ENABLE 0x00000000U +#define ETH_RECEIVEOWN_DISABLE 0x00002000U +/** + * @} + */ + +/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode + * @{ + */ +#define ETH_LOOPBACKMODE_ENABLE 0x00001000U +#define ETH_LOOPBACKMODE_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Checksum_Offload ETH Checksum Offload + * @{ + */ +#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U +#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Retry_Transmission ETH Retry Transmission + * @{ + */ +#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U +#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U +/** + * @} + */ + +/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip + * @{ + */ +#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U +#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit + * @{ + */ +#define ETH_BACKOFFLIMIT_10 0x00000000U +#define ETH_BACKOFFLIMIT_8 0x00000020U +#define ETH_BACKOFFLIMIT_4 0x00000040U +#define ETH_BACKOFFLIMIT_1 0x00000060U +/** + * @} + */ + +/** @defgroup ETH_Deferral_Check ETH Deferral Check + * @{ + */ +#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U +#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Receive_All ETH Receive All + * @{ + */ +#define ETH_RECEIVEALL_ENABLE 0x80000000U +#define ETH_RECEIVEAll_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter + * @{ + */ +#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U +#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U +#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames + * @{ + */ +#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ +#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ +/** + * @} + */ + +/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception + * @{ + */ +#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U +#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U +/** + * @} + */ + +/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter + * @{ + */ +#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U +#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U +/** + * @} + */ + +/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode + * @{ + */ +#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U +#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter + * @{ + */ +#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U +#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U +#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U +#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U +/** + * @} + */ + +/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter + * @{ + */ +#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U +#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U +#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause + * @{ + */ +#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U +#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U +/** + * @} + */ + +/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold + * @{ + */ +#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ +#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ +/** + * @} + */ + +/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect + * @{ + */ +#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U +#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control + * @{ + */ +#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U +#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control + * @{ + */ +#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U +#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison + * @{ + */ +#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U +#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses ETH MAC addresses + * @{ + */ +#define ETH_MAC_ADDRESS0 0x00000000U +#define ETH_MAC_ADDRESS1 0x00000008U +#define ETH_MAC_ADDRESS2 0x00000010U +#define ETH_MAC_ADDRESS3 0x00000018U +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA + * @{ + */ +#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U +#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U +/** + * @} + */ + +/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes + * @{ + */ +#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ +/** + * @} + */ + +/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame + * @{ + */ +#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U +#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U +/** + * @} + */ + +/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward + * @{ + */ +#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U +#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame + * @{ + */ +#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U +#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U +/** + * @} + */ + +/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward + * @{ + */ +#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U +#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control + * @{ + */ +#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ +/** + * @} + */ + +/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames + * @{ + */ +#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U +#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames + * @{ + */ +#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U +#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control + * @{ + */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ +/** + * @} + */ + +/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate + * @{ + */ +#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U +#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats + * @{ + */ +#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U +#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Fixed_Burst ETH Fixed Burst + * @{ + */ +#define ETH_FIXEDBURST_ENABLE 0x00010000U +#define ETH_FIXEDBURST_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length + * @{ + */ +#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ +/** + * @} + */ + +/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length + * @{ + */ +#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format + * @{ + */ +#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U +#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U +/** + * @} + */ + +/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration + * @{ + */ +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U +#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U +#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment + * @{ + */ +#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ +#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control + * @{ + */ +#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ +#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ +#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers + * @{ + */ +#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ +#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ +/** + * @} + */ + +/** @defgroup ETH_PMT_Flags ETH PMT Flags + * @{ + */ +#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ +/** + * @} + */ + +/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts + * @{ + */ +#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ +/** + * @} + */ + +/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts + * @{ + */ +#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ +/** + * @} + */ + +/** @defgroup ETH_MAC_Flags ETH MAC Flags + * @{ + */ +#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ +#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Flags ETH DMA Flags + * @{ + */ +#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ +#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ +#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ +#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ +#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ +#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ +/** + * @} + */ + +/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts + * @{ + */ +#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ +#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ +/** + * @} + */ + +/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts + * @{ + */ +#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ +#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ +#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ +#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ +#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ +#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ +#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ +#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ +#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ +#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ +/** + * @} + */ + +/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state + * @{ + */ +#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ +#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ +#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ +#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ +#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ + +/** + * @} + */ + + +/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state + * @{ + */ +#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ +#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ +#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ +#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ +#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ + +/** + * @} + */ + +/** @defgroup ETH_DMA_overflow ETH DMA overflow + * @{ + */ +#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ +/** + * @} + */ + +/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP + * @{ + */ +#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ETH_Exported_Macros ETH Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ + +/** @brief Reset ETH handle state + * @param __HANDLE__ specifies the ETH handle. + * @retval None + */ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) +#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag of TDES0 to check. + * @retval the ETH_DMATxDescFlag (SET or RESET). + */ +#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) + +/** + * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag of RDES0 to check. + * @retval the ETH_DMATxDescFlag (SET or RESET). + */ +#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) + +/** + * @brief Enables the specified DMA Rx Desc receive interrupt. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) + +/** + * @brief Disables the specified DMA Rx Desc receive interrupt. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) + +/** + * @brief Set the specified DMA Rx Desc Own bit. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) + +/** + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * @param __HANDLE__ ETH Handle + * @retval The Transmit descriptor collision counter value. + */ +#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) + +/** + * @brief Set the specified DMA Tx Desc Own bit. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) + +/** + * @brief Enables the specified DMA Tx Desc Transmit interrupt. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) + +/** + * @brief Disables the specified DMA Tx Desc Transmit interrupt. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) + +/** + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * @param __HANDLE__ ETH Handle + * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass + * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present + * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header + * @retval None + */ +#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) + +/** + * @brief Enables the DMA Tx Desc CRC. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) + +/** + * @brief Disables the DMA Tx Desc CRC. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) + +/** + * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) + +/** + * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) + +/** + * @brief Enables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval None + */ +#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be + * enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt + * @arg ETH_MAC_IT_PMT : PMT interrupt + * @retval None + */ +#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) + +/** + * @brief Initiate a Pause Control Frame (Full-duplex only). + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) + +/** + * @brief Checks whether the ETHERNET flow control busy bit is set or not. + * @param __HANDLE__ ETH Handle + * @retval The new state of flow control busy status bit (SET or RESET). + */ +#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) + +/** + * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) + +/** + * @brief Disables the MAC BackPressure operation activation (Half-duplex only). + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) + +/** + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag + * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag + * @arg ETH_MAC_FLAG_MMCR : MMC receive flag + * @arg ETH_MAC_FLAG_MMC : MMC flag + * @arg ETH_MAC_FLAG_PMT : PMT flag + * @retval The state of ETHERNET MAC flag. + */ +#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Enables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be + * enabled @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be + * disabled. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) + +/** + * @brief Clears the ETHERNET DMA IT pending bit. + * @param __HANDLE__ ETH Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. +* @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags + * @retval The new state of ETH_DMA_FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags + * @retval The new state of ETH_DMA_FLAG (SET or RESET). + */ +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) + +/** + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * @param __HANDLE__ ETH Handle + * @param __OVERFLOW__ specifies the DMA overflow flag to check. + * This parameter can be one of the following values: + * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter + * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter + * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). + */ +#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) + +/** + * @brief Set the DMA Receive status watchdog timer register value + * @param __HANDLE__ ETH Handle + * @param __VALUE__ DMA Receive status watchdog timer register value + * @retval None + */ +#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) + +/** + * @brief Enables any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) + +/** + * @brief Disables any unicast packet filtered by the MAC address + * recognition to be a wake-up frame. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) + +/** + * @brief Enables the MAC Wake-Up Frame Detection. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) + +/** + * @brief Disables the MAC Wake-Up Frame Detection. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) + +/** + * @brief Enables the MAC Magic Packet Detection. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) + +/** + * @brief Disables the MAC Magic Packet Detection. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) + +/** + * @brief Enables the MAC Power Down. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) + +/** + * @brief Disables the MAC Power Down. + * @param __HANDLE__ ETH Handle + * @retval None + */ +#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) + +/** + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * @param __HANDLE__ ETH Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset + * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPR : Magic Packet Received + * @retval The new state of ETHERNET PMT Flag (SET or RESET). + */ +#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) + +/** + * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ + (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) + +/** + * @brief Enables the MMC Counter Freeze. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) + +/** + * @brief Disables the MMC Counter Freeze. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) + +/** + * @brief Enables the MMC Reset On Read. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) + +/** + * @brief Disables the MMC Reset On Read. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) + +/** + * @brief Enables the MMC Counter Stop Rollover. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) + +/** + * @brief Disables the MMC Counter Stop Rollover. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) + +/** + * @brief Resets the MMC Counters. + * @param __HANDLE__ ETH Handle. + * @retval None + */ +#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) + +/** + * @brief Enables the specified ETHERNET MMC Rx interrupts. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) +/** + * @brief Disables the specified ETHERNET MMC Rx interrupts. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value + * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value + * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) +/** + * @brief Enables the specified ETHERNET MMC Tx interrupts. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET MMC Tx interrupts. + * @param __HANDLE__ ETH Handle. + * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value + * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value + * @retval None + */ +#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) + +/** + * @brief Enables the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Disables the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enable event on ETH External event line. + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Disable event on ETH External event line + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Get flag of the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Clear flag of the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enables rising edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP + +/** + * @brief Disables the rising edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enables falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Disables falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) + +/** + * @brief Enables rising/falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ + EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ + }while(0U) + +/** + * @brief Disables rising/falling edge trigger to the ETH External interrupt line. + * @retval None + */ +#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ + }while(0U) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP + +/** + * @} + */ +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup ETH_Exported_Functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ + +/** @addtogroup ETH_Exported_Functions_Group1 + * @{ + */ +HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); +HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ +/* IO operation functions ****************************************************/ + +/** @addtogroup ETH_Exported_Functions_Group2 + * @{ + */ +HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); +/* Communication with PHY functions*/ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); +/* Non-Blocking mode: Interrupt */ +HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); +/* Callback in non blocking modes (Interrupt) */ +void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ + +/** @addtogroup ETH_Exported_Functions_Group3 + * @{ + */ + +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ + +/** @addtogroup ETH_Exported_Functions_Group4 + * @{ + */ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ + STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F4xx_HAL_ETH_LEGACY_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal.c index 5fcf71afd90..9ba2ba7d880 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal.c @@ -5,6 +5,17 @@ * @brief HAL module driver. * This is the common part of the HAL initialization * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,17 +30,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -50,11 +50,11 @@ * @{ */ /** - * @brief STM32F4xx HAL Driver version number V1.7.12 + * @brief STM32F4xx HAL Driver version number V1.8.1 */ #define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */ -#define __STM32F4xx_HAL_VERSION_SUB2 (0x0CU) /*!< [15:8] sub2 version */ +#define __STM32F4xx_HAL_VERSION_SUB1 (0x08U) /*!< [23:16] sub1 version */ +#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */ #define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\ |(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\ @@ -612,4 +612,4 @@ void HAL_DisableMemorySwappingBank(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal.h index 209864d5302..f7eb847b3c1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -295,4 +294,4 @@ void HAL_DisableMemorySwappingBank(void); #endif /* __STM32F4xx_HAL_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.c index 37c6a9a905e..9ad943d8d0a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.c @@ -2,31 +2,42 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Converter (ADC) peripheral: * + Initialization and de-initialization functions - * + IO operation functions - * + State and errors functions - * + * + Peripheral Control functions + * + Peripheral State functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### ADC Peripheral features ##### ============================================================================== - [..] + [..] (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. - (#) Interrupt generation at the end of conversion, end of injected conversion, + (#) Interrupt generation at the end of conversion, end of injected conversion, and in case of analog watchdog or overrun events (#) Single and continuous conversion modes. (#) Scan mode for automatic conversion of channel 0 to channel x. (#) Data alignment with in-built data coherency. (#) Channel-wise programmable sampling time. - (#) External trigger option with configurable polarity for both regular and + (#) External trigger option with configurable polarity for both regular and injected conversion. (#) Dual/Triple mode (on devices with 2 ADCs or more). - (#) Configurable DMA data storage in Dual/Triple ADC mode. + (#) Configurable DMA data storage in Dual/Triple ADC mode. (#) Configurable delay between conversions in Dual/Triple interleaved mode. (#) ADC conversion type (refer to the datasheets). - (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at + (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at slower speed. (#) ADC input range: VREF(minus) = VIN = VREF(plus). (#) DMA request generation during regular channel conversion. @@ -39,8 +50,8 @@ (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() (##) ADC pins configuration (+++) Enable the clock for the ADC GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE() - (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() + __HAL_RCC_GPIOx_CLK_ENABLE() + (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() @@ -54,7 +65,7 @@ (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the two DMA Streams. The output stream should have higher priority than the input stream. - + *** Configuration of ADC, groups regular/injected, channels parameters *** ============================================================================== [..] @@ -62,64 +73,64 @@ and regular group parameters (conversion trigger, sequencer, ...) using function HAL_ADC_Init(). - (#) Configure the channels for regular group parameters (channel number, + (#) Configure the channels for regular group parameters (channel number, channel rank into sequencer, ..., into regular group) using function HAL_ADC_ConfigChannel(). - (#) Optionally, configure the injected group parameters (conversion trigger, + (#) Optionally, configure the injected group parameters (conversion trigger, sequencer, ..., of injected group) - and the channels for injected group parameters (channel number, + and the channels for injected group parameters (channel number, channel rank into sequencer, ..., into injected group) using function HAL_ADCEx_InjectedConfigChannel(). (#) Optionally, configure the analog watchdog parameters (channels monitored, thresholds, ...) using function HAL_ADC_AnalogWDGConfig(). - (#) Optionally, for devices with several ADC instances: configure the + (#) Optionally, for devices with several ADC instances: configure the multimode parameters using function HAL_ADCEx_MultiModeConfigChannel(). *** Execution of ADC conversions *** ============================================================================== - [..] + [..] (#) ADC driver can be used among three modes: polling, interruption, - transfer by DMA. + transfer by DMA. *** Polling mode IO operation *** ================================= - [..] - (+) Start the ADC peripheral using HAL_ADC_Start() + [..] + (+) Start the ADC peripheral using HAL_ADC_Start() (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage - user can specify the value of timeout according to his end application + user can specify the value of timeout according to his end application (+) To read the ADC converted values, use the HAL_ADC_GetValue() function. (+) Stop the ADC peripheral using HAL_ADC_Stop() - - *** Interrupt mode IO operation *** + + *** Interrupt mode IO operation *** =================================== - [..] - (+) Start the ADC peripheral using HAL_ADC_Start_IT() + [..] + (+) Start the ADC peripheral using HAL_ADC_Start_IT() (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine - (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADC_ConvCpltCallback - (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can + (+) At ADC end of conversion HAL_ADC_ConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ConvCpltCallback + (+) In case of ADC Error, HAL_ADC_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_ADC_ErrorCallback - (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() + (+) Stop the ADC peripheral using HAL_ADC_Stop_IT() - *** DMA mode IO operation *** + *** DMA mode IO operation *** ============================== - [..] - (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length - of data to be transferred at each end of conversion - (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADC_ConvCpltCallback - (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can + [..] + (+) Start the ADC peripheral using HAL_ADC_Start_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + (+) At The end of data transfer by HAL_ADC_ConvCpltCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADC_ConvCpltCallback + (+) In case of transfer Error, HAL_ADC_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_ADC_ErrorCallback (+) Stop the ADC peripheral using HAL_ADC_Stop_DMA() - + *** ADC HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in ADC HAL driver. - + (+) __HAL_ADC_ENABLE : Enable the ADC peripheral (+) __HAL_ADC_DISABLE : Disable the ADC peripheral (+) __HAL_ADC_ENABLE_IT: Enable the ADC end of conversion interrupt @@ -127,10 +138,10 @@ (+) __HAL_ADC_GET_IT_SOURCE: Check if the specified ADC interrupt source is enabled or disabled (+) __HAL_ADC_CLEAR_FLAG: Clear the ADC's pending flags (+) __HAL_ADC_GET_FLAG: Get the selected ADC's flag status - (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register - - [..] - (@) You can refer to the ADC HAL driver header file for more useful macros + (+) ADC_GET_RESOLUTION: Return resolution bits in CR1 register + + [..] + (@) You can refer to the ADC HAL driver header file for more useful macros *** Deinitialization of ADC *** ============================================================================== @@ -156,18 +167,18 @@ (#) Optionally, in case of usage of DMA: (++) Deinitialize the DMA using function HAL_DMA_DeInit(). - (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) + (++) Disable the NVIC for DMA using function HAL_NVIC_DisableIRQ(DMAx_Channelx_IRQn) *** Callback registration *** ============================================================================== [..] The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_ADC_RegisterCallback() + Use Functions HAL_ADC_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: + Function HAL_ADC_RegisterCallback() allows to register following callbacks: (+) ConvCpltCallback : ADC conversion complete callback (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback @@ -183,11 +194,11 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default + Use function HAL_ADC_UnRegisterCallback to reset a callback to the default weak function. [..] - @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ConvCpltCallback : ADC conversion complete callback @@ -203,27 +214,27 @@ (+) MspDeInitCallback : ADC Msp DeInit callback [..] - By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET + By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). + examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when + reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when these callbacks are null (not registered beforehand). [..] - If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() + If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, + in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. [..] Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() - or @ref HAL_ADC_Init() function. + using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit() + or HAL_ADC_Init() function. [..] When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or @@ -231,19 +242,7 @@ are set to the corresponding weak functions. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -255,10 +254,10 @@ /** @defgroup ADC ADC * @brief ADC driver modules * @{ - */ + */ #ifdef HAL_ADC_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -267,7 +266,7 @@ * @{ */ /* Private function prototypes -----------------------------------------------*/ -static void ADC_Init(ADC_HandleTypeDef* hadc); +static void ADC_Init(ADC_HandleTypeDef *hadc); static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); static void ADC_DMAError(DMA_HandleTypeDef *hdma); static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); @@ -279,46 +278,46 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); * @{ */ -/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. - (+) De-initialize the ADC. - + (+) Initialize and configure the ADC. + (+) De-initialize the ADC. + @endverbatim * @{ */ /** - * @brief Initializes the ADCx peripheral according to the specified parameters + * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct and initializes the ADC MSP. - * - * @note This function is used to configure the global features of the ADC ( + * + * @note This function is used to configure the global features of the ADC ( * ClockPrescaler, Resolution, Data Alignment and number of conversion), however, * the rest of the configuration parameters are specific to the regular * channels group (scan mode activation, continuous mode activation, - * External trigger source and edge, DMA continuous request after the + * External trigger source and edge, DMA continuous request after the * last transfer and End of conversion selection). - * + * * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. + * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); @@ -331,13 +330,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); } - - if(hadc->State == HAL_ADC_STATE_RESET) + + if (hadc->State == HAL_ADC_STATE_RESET) { #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Init the ADC Callback settings */ @@ -360,12 +359,12 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Initialize ADC error code */ ADC_CLEAR_ERRORCODE(hadc); - + /* Allocate lock resource and initialize it */ hadc->Lock = HAL_UNLOCKED; } - - /* Configuration of ADC parameters if previous preliminary actions are */ + + /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { @@ -373,13 +372,13 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_BUSY_INTERNAL); - + /* Set ADC parameters */ ADC_Init(hadc); - + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - + /* Set the ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, @@ -389,7 +388,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) { tmp_hal_status = HAL_ERROR; } - + /* Release Lock */ __HAL_UNLOCK(hadc); @@ -398,58 +397,58 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) } /** - * @brief Deinitializes the ADCx peripheral registers to their default reset values. + * @brief Deinitializes the ADCx peripheral registers to their default reset values. * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. + * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + /* Check ADC handle */ - if(hadc == NULL) + if (hadc == NULL) { return HAL_ERROR; } - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - + /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); - - /* Configuration of ADC parameters if previous preliminary actions are */ + + /* Configuration of ADC parameters if previous preliminary actions are */ /* correctly completed. */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } + if (hadc->MspDeInitCallback == NULL) + { + hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ + } - /* DeInit the low level hardware: RCC clock, NVIC */ - hadc->MspDeInitCallback(hadc); + /* DeInit the low level hardware: RCC clock, NVIC */ + hadc->MspDeInitCallback(hadc); #else - /* DeInit the low level hardware: RCC clock, NVIC */ - HAL_ADC_MspDeInit(hadc); + /* DeInit the low level hardware: RCC clock, NVIC */ + HAL_ADC_MspDeInit(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); - + /* Set ADC state */ hadc->State = HAL_ADC_STATE_RESET; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -657,31 +656,31 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca /** * @brief Initializes the ADC MSP. * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. + * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADC_MspInit could be implemented in the user file - */ + */ } /** * @brief DeInitializes the ADC MSP. * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. + * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_ADC_MspDeInit could be implemented in the user file - */ + */ } /** @@ -689,12 +688,12 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) */ /** @defgroup ADC_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions + * @brief IO operation functions * -@verbatim +@verbatim =============================================================================== ##### IO operation functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of regular channel. (+) Stop conversion of regular channel. @@ -702,8 +701,8 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) (+) Stop conversion of regular channel and disable interrupt. (+) Start conversion of regular channel and enable DMA transfer. (+) Stop conversion of regular channel and disable DMA transfer. - (+) Handle ADC interrupt request. - + (+) Handle ADC interrupt request. + @endverbatim * @{ */ @@ -714,37 +713,37 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; - + /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ - /* Check if ADC peripheral is disabled in order to enable it and wait during + /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); - + /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } - + /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -752,25 +751,25 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_REG_BUSY); - + /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - + /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); - } + } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ @@ -785,17 +784,17 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); - + /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { #if defined(ADC2) && defined(ADC3) - if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ - || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) { #endif /* ADC2 || ADC3 */ /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -807,10 +806,10 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } } @@ -822,45 +821,45 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } - + /* Return function status */ return HAL_OK; } /** * @brief Disables ADC and stop conversion of regular channels. - * - * @note Caution: This function will stop also injected channels. + * + * @note Caution: This function will stop also injected channels. * * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); - + /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return HAL_OK; } @@ -869,21 +868,21 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) * @brief Poll for regular conversion complete * @note ADC conversion flags EOS (end of sequence) and EOC (end of * conversion) are cleared by this function. - * @note This function cannot be used in a particular setup: ADC configured + * @note This function cannot be used in a particular setup: ADC configured * in DMA mode and polling for end of each conversion (ADC init * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). * In this case, DMA resets the flag EOC and polling cannot be - * performed on each conversion. Nevertheless, polling can still + * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence. * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart = 0U; - + /* Verification that ADC configuration is compliant with polling for */ /* each conversion: */ /* Particular case is ADC configured in DMA mode and ADC sequencer with */ @@ -891,69 +890,69 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* For code simplicity sake, this particular case is generalized to */ /* ADC configured in DMA mode and polling for end of each conversion. */ if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_EOCS) && - HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA) ) + HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_DMA)) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_ERROR; } - /* Get tick */ + /* Get tick */ tickstart = HAL_GetTick(); /* Check End of conversion flag */ - while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + while (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) { /* Check if timeout is disabled (set to infinite wait) */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) + if (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC))) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_TIMEOUT; } } } } - + /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); - + /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F4, there is no independent flag of end of sequence. */ /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) - { + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } - + /* Return ADC state */ return HAL_OK; } @@ -966,13 +965,13 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. * @arg ADC_OVR_EVENT: ADC Overrun event. - * @param Timeout Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) { uint32_t tickstart = 0U; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_EVENT_TYPE(EventType)); @@ -981,34 +980,34 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy tickstart = HAL_GetTick(); /* Check selected event flag */ - while(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + while (!(__HAL_ADC_GET_FLAG(hadc, EventType))) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc,EventType))) + if (!(__HAL_ADC_GET_FLAG(hadc, EventType))) { /* Update ADC state machine to timeout */ SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + return HAL_TIMEOUT; } } } } - + /* Analog watchdog (level out of window) event */ - if(EventType == ADC_AWD_EVENT) + if (EventType == ADC_AWD_EVENT) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - + /* Clear ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); } @@ -1019,11 +1018,11 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - + /* Clear ADC overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } - + /* Return ADC state */ return HAL_OK; } @@ -1035,37 +1034,37 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy * the configuration information for the specified ADC. * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; - + /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ - /* Check if ADC peripheral is disabled in order to enable it and wait during + /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); - + /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } - + /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -1073,19 +1072,19 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_REG_BUSY); - + /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - + /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { @@ -1106,20 +1105,20 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); - + /* Enable end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); - + /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { #if defined(ADC2) && defined(ADC3) - if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ - || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) { #endif /* ADC2 || ADC3 */ /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -1131,10 +1130,10 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } } @@ -1146,36 +1145,36 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } - + /* Return function status */ return HAL_OK; } /** * @brief Disables the interrupt and stop ADC conversion of regular channels. - * - * @note Caution: This function will stop also injected channels. + * + * @note Caution: This function will stop also injected channels. * * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) { /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); - + /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { - /* Disable ADC end of conversion interrupt for regular group */ + /* Disable ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR)); /* Set ADC state */ @@ -1183,82 +1182,85 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return HAL_OK; } /** - * @brief Handles ADC interrupt request + * @brief Handles ADC interrupt request * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) { uint32_t tmp1 = 0U, tmp2 = 0U; - + + uint32_t tmp_sr = hadc->Instance->SR; + uint32_t tmp_cr1 = hadc->Instance->CR1; + /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); - - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC); + + tmp1 = tmp_sr & ADC_FLAG_EOC; + tmp2 = tmp_cr1 & ADC_IT_EOC; /* Check End of conversion flag for regular channels */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) { /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); + SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); } - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F4, there is no independent flag of end of sequence. */ /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - + /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } - + /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); #else HAL_ADC_ConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC); } - - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); + + tmp1 = tmp_sr & ADC_FLAG_JEOC; + tmp2 = tmp_cr1 & ADC_IT_JEOC; /* Check End of conversion flag for injected channels */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) @@ -1271,132 +1273,132 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* by external trigger, scan sequence on going or by automatic injected */ /* conversion from group regular (same conditions as group regular */ /* interruption disabling above). */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && - (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE)))) { /* Disable ADC end of single conversion interrupt on group injected */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - + /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); + CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } - /* Conversion complete callback */ - /* Conversion complete callback */ + /* Conversion complete callback */ + /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->InjectedConvCpltCallback(hadc); + hadc->InjectedConvCpltCallback(hadc); #else - HAL_ADCEx_InjectedConvCpltCallback(hadc); + HAL_ADCEx_InjectedConvCpltCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC)); } - - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); + + tmp1 = tmp_sr & ADC_FLAG_AWD; + tmp2 = tmp_cr1 & ADC_IT_AWD; /* Check Analog watchdog flag */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { - if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) + if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD)) { /* Set ADC state */ SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - + /* Level out of window callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->LevelOutOfWindowCallback(hadc); #else HAL_ADC_LevelOutOfWindowCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Clear the ADC analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); } } - - tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR); - tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR); + + tmp1 = tmp_sr & ADC_FLAG_OVR; + tmp2 = tmp_cr1 & ADC_IT_OVR; /* Check Overrun flag */ - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Note: On STM32F4, ADC overrun can be set through other parameters */ /* refer to description of parameter "EOCSelection" for more */ /* details. */ - + /* Set ADC error code to overrun */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - + /* Clear ADC overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - - /* Error callback */ + + /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); + hadc->ErrorCallback(hadc); #else - HAL_ADC_ErrorCallback(hadc); + HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - + /* Clear the Overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); } } /** - * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral + * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param pData The destination Buffer address. * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; - + /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - + assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); + /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ - /* Check if ADC peripheral is disabled in order to enable it and wait during + /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); - + /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } - + /* Check ADC DMA Mode */ /* - disable the DMA Mode if it is already enabled */ - if((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA) + if ((hadc->Instance->CR2 & ADC_CR2_DMA) == ADC_CR2_DMA) { CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA); } - + /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -1404,19 +1406,19 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_REG_BUSY); - + /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - + /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { @@ -1427,7 +1429,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); + __HAL_UNLOCK(hadc); /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ @@ -1439,37 +1441,37 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - + /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ - + /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR); /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - + /* Enable ADC DMA mode */ hadc->Instance->CR2 |= ADC_CR2_DMA; - + /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - + /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { #if defined(ADC2) && defined(ADC3) - if((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ - || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) + if ((hadc->Instance == ADC1) || ((hadc->Instance == ADC2) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_0)) \ + || ((hadc->Instance == ADC3) && ((ADC->CCR & ADC_CCR_MULTI_Msk) < ADC_CCR_MULTI_4))) { #endif /* ADC2 || ADC3 */ /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -1481,10 +1483,10 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ - if((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) + if ((hadc->Instance == ADC1) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ - hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; + hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } } @@ -1496,43 +1498,43 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } - + /* Return function status */ return HAL_OK; } /** - * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral + * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); - + /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Disable the selected ADC DMA mode */ hadc->Instance->CR2 &= ~ADC_CR2_DMA; - + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* DMA transfer is on going) */ if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) { tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + /* Check if DMA channel effectively disabled */ if (tmp_hal_status != HAL_OK) { @@ -1540,19 +1542,19 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); } } - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -1563,19 +1565,19 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) * the configuration information for the specified ADC. * @retval Converted value */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) -{ - /* Return the selected ADC converted value */ +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc) +{ + /* Return the selected ADC converted value */ return hadc->Instance->DR; } /** - * @brief Regular conversion complete callback in non blocking mode + * @brief Regular conversion complete callback in non blocking mode * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -1585,12 +1587,12 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) } /** - * @brief Regular conversion half DMA transfer callback in non blocking mode + * @brief Regular conversion half DMA transfer callback in non blocking mode * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -1600,12 +1602,12 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) } /** - * @brief Analog watchdog callback in non blocking mode + * @brief Analog watchdog callback in non blocking mode * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -1616,8 +1618,8 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) /** * @brief Error ADC callback. - * @note In case of error due to overrun when using ADC with DMA transfer - * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): + * @note In case of error due to overrun when using ADC with DMA transfer + * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" @@ -1638,51 +1640,51 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) /** * @} */ - + /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions + * @brief Peripheral Control functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral Control functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: - (+) Configure regular channels. + (+) Configure regular channels. (+) Configure injected channels. (+) Configure multimode. (+) Configure the analog watch dog. - + @endverbatim * @{ */ - /** - * @brief Configures for the selected ADC regular channel its corresponding - * rank in the sequencer and its sample time. - * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param sConfig ADC configuration structure. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) +/** +* @brief Configures for the selected ADC regular channel its corresponding +* rank in the sequencer and its sample time. +* @param hadc pointer to a ADC_HandleTypeDef structure that contains +* the configuration information for the specified ADC. +* @param sConfig ADC configuration structure. +* @retval HAL status +*/ +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; - + /* Check the parameters */ assert_param(IS_ADC_CHANNEL(sConfig->Channel)); assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ if (sConfig->Channel > ADC_CHANNEL_9) { /* Clear the old sample time */ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel); - + /* Set the new sample time */ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel); } @@ -1690,17 +1692,17 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* Clear the old sample time */ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel); - + /* Set the new sample time */ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel); } - + /* For Rank 1 to 6 */ if (sConfig->Rank < 7U) { /* Clear the old SQx bits for the selected rank */ hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank); - + /* Set the SQx bits for the selected rank */ hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank); } @@ -1709,7 +1711,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* Clear the old SQx bits for the selected rank */ hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank); - + /* Set the SQx bits for the selected rank */ hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank); } @@ -1718,20 +1720,20 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf { /* Clear the old SQx bits for the selected rank */ hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank); - + /* Set the SQx bits for the selected rank */ hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank); } - /* Pointer to the common control register to which is belonging hadc */ - /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ - /* control register) */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); + /* Pointer to the common control register to which is belonging hadc */ + /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ + /* control register) */ + tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */ if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT)) { - /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/ + /* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/ if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT) { tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE; @@ -1739,8 +1741,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Enable the VBAT channel*/ tmpADC_Common->CCR |= ADC_CCR_VBATE; } - - /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or + + /* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or Channel_17 is selected for VREFINT enable TSVREFE */ if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT))) { @@ -1751,22 +1753,22 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf } /* Enable the Temperature sensor and VREFINT channel*/ tmpADC_Common->CCR |= ADC_CCR_TSVREFE; - + if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return HAL_OK; } @@ -1783,31 +1785,31 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf * effective timing of the new programmed threshold values. * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure + * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure * that contains the configuration information of ADC analog watchdog. - * @retval HAL status + * @retval HAL status */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) { -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT uint32_t tmp = 0U; -#endif /* USE_FULL_ASSERT */ - +#endif /* USE_FULL_ASSERT */ + /* Check the parameters */ assert_param(IS_ADC_ANALOG_WATCHDOG(AnalogWDGConfig->WatchdogMode)); assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); -#ifdef USE_FULL_ASSERT +#ifdef USE_FULL_ASSERT tmp = ADC_GET_RESOLUTION(hadc); assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->HighThreshold)); assert_param(IS_ADC_RANGE(tmp, AnalogWDGConfig->LowThreshold)); #endif /* USE_FULL_ASSERT */ - + /* Process locked */ __HAL_LOCK(hadc); - - if(AnalogWDGConfig->ITMode == ENABLE) + + if (AnalogWDGConfig->ITMode == ENABLE) { /* Enable the ADC Analog watchdog interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD); @@ -1817,28 +1819,28 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* Disable the ADC Analog watchdog interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD); } - + /* Clear AWDEN, JAWDEN and AWDSGL bits */ hadc->Instance->CR1 &= ~(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN | ADC_CR1_AWDEN); - + /* Set the analog watchdog enable mode */ hadc->Instance->CR1 |= AnalogWDGConfig->WatchdogMode; - + /* Set the high threshold */ hadc->Instance->HTR = AnalogWDGConfig->HighThreshold; - + /* Set the low threshold */ hadc->Instance->LTR = AnalogWDGConfig->LowThreshold; - + /* Clear the Analog watchdog channel select bits */ hadc->Instance->CR1 &= ~ADC_CR1_AWDCH; - + /* Set the Analog watchdog channel */ hadc->Instance->CR1 |= (uint32_t)((uint16_t)(AnalogWDGConfig->Channel)); - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return HAL_OK; } @@ -1848,28 +1850,28 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG */ /** @defgroup ADC_Exported_Functions_Group4 ADC Peripheral State functions - * @brief ADC Peripheral State functions + * @brief ADC Peripheral State functions * -@verbatim +@verbatim =============================================================================== ##### Peripheral State and errors functions ##### - =============================================================================== + =============================================================================== [..] This subsection provides functions allowing to (+) Check the ADC state (+) Check the ADC Error - + @endverbatim * @{ */ - + /** * @brief return the ADC state * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL state */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc) { /* Return ADC state */ return hadc->State; @@ -1895,49 +1897,49 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) */ /** - * @brief Initializes the ADCx peripheral according to the specified parameters - * in the ADC_InitStruct without initializing the ADC MSP. + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct without initializing the ADC MSP. * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. + * the configuration information for the specified ADC. * @retval None */ -static void ADC_Init(ADC_HandleTypeDef* hadc) +static void ADC_Init(ADC_HandleTypeDef *hadc) { ADC_Common_TypeDef *tmpADC_Common; - + /* Set ADC parameters */ /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */ /* control register) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - + /* Set the ADC clock prescaler */ tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE); tmpADC_Common->CCR |= hadc->Init.ClockPrescaler; - + /* Set ADC scan mode */ hadc->Instance->CR1 &= ~(ADC_CR1_SCAN); hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode); - + /* Set ADC resolution */ hadc->Instance->CR1 &= ~(ADC_CR1_RES); hadc->Instance->CR1 |= hadc->Init.Resolution; - + /* Set ADC data alignment */ hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN); hadc->Instance->CR2 |= hadc->Init.DataAlign; - + /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ - if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) { /* Select external trigger to start conversion */ hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv; - + /* Select external trigger polarity */ hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge; @@ -1948,18 +1950,18 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL); hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN); } - + /* Enable or disable ADC continuous conversion mode */ hadc->Instance->CR2 &= ~(ADC_CR2_CONT); hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode); - - if(hadc->Init.DiscontinuousConvMode != DISABLE) + + if (hadc->Init.DiscontinuousConvMode != DISABLE) { assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion)); - + /* Enable the selected ADC regular discontinuous mode */ hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN; - + /* Set the number of channels to be converted in discontinuous mode */ hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM); hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion); @@ -1969,63 +1971,63 @@ static void ADC_Init(ADC_HandleTypeDef* hadc) /* Disable the selected ADC regular discontinuous mode */ hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN); } - + /* Set ADC number of conversion */ hadc->Instance->SQR1 &= ~(ADC_SQR1_L); hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion); - + /* Enable or disable ADC DMA continuous request */ hadc->Instance->CR2 &= ~(ADC_CR2_DDS); hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests); - + /* Enable or disable ADC end of conversion selection */ hadc->Instance->CR2 &= ~(ADC_CR2_EOCS); hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection); } /** - * @brief DMA transfer complete callback. + * @brief DMA transfer complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) +static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F4, there is no independent flag of end of sequence. */ /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - + /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } - + /* Conversion complete callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvCpltCallback(hadc); @@ -2044,8 +2046,8 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) HAL_ADC_ErrorCallback(hadc); #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ } - else - { + else + { /* Call DMA error callback */ hadc->DMA_Handle->XferErrorCallback(hdma); } @@ -2053,15 +2055,15 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA half transfer complete callback. + * @brief DMA half transfer complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) +static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Half conversion callback */ + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Half conversion callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ConvHalfCpltCallback(hadc); #else @@ -2070,18 +2072,18 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA error callback + * @brief DMA error callback * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void ADC_DMAError(DMA_HandleTypeDef *hdma) +static void ADC_DMAError(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR_DMA; + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hadc->State = HAL_ADC_STATE_ERROR_DMA; /* Set ADC error code to DMA error */ hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - /* Error callback */ + /* Error callback */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) hadc->ErrorCallback(hadc); #else @@ -2100,10 +2102,9 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma) #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} - */ + */ /** * @} - */ + */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.h index a041e76965c..c79a073e913 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -22,7 +21,7 @@ #define __STM32F4xx_ADC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -37,15 +36,15 @@ /** @addtogroup ADC * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Types ADC Exported Types * @{ */ -/** - * @brief Structure definition of ADC and regular group initialization +/** + * @brief Structure definition of ADC and regular group initialization * @note Parameters of this structure are shared within 2 scopes: * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank. * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv. @@ -59,7 +58,7 @@ */ typedef struct { - uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for + uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for all the ADCs. This parameter can be a value of @ref ADC_ClockPrescaler */ uint32_t Resolution; /*!< Configures the ADC resolution. @@ -102,20 +101,20 @@ typedef struct If trigger is set to ADC_SOFTWARE_START, this parameter is discarded. This parameter can be a value of @ref ADC_External_trigger_edge_Regular */ FunctionalState DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached) - or in Continuous mode (DMA transfer unlimited, whatever number of conversions). - Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. - Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). - This parameter can be set to ENABLE or DISABLE. */ -}ADC_InitTypeDef; + or in Continuous mode (DMA transfer unlimited, whatever number of conversions). + Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. + Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). + This parameter can be set to ENABLE or DISABLE. */ +} ADC_InitTypeDef; -/** - * @brief Structure definition of ADC channel for regular group +/** + * @brief Structure definition of ADC channel for regular group * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state. * ADC can be either disabled or enabled without conversion on going on regular group. - */ -typedef struct + */ +typedef struct { uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group. This parameter can be a value of @ref ADC_channels */ @@ -131,31 +130,31 @@ typedef struct sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */ uint32_t Offset; /*!< Reserved for future use, can be set to 0 */ -}ADC_ChannelConfTypeDef; +} ADC_ChannelConfTypeDef; -/** - * @brief ADC Configuration multi-mode structure definition - */ +/** + * @brief ADC Configuration multi-mode structure definition + */ typedef struct { uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode. This parameter can be a value of @ref ADC_analog_watchdog_selection */ uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. - This parameter must be a 12-bit value. */ + This parameter must be a 12-bit value. */ uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. This parameter must be a 12-bit value. */ - uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. - This parameter has an effect only if watchdog mode is configured on single channel - This parameter can be a value of @ref ADC_channels */ + uint32_t Channel; /*!< Configures ADC channel for the analog watchdog. + This parameter has an effect only if watchdog mode is configured on single channel + This parameter can be a value of @ref ADC_channels */ FunctionalState ITMode; /*!< Specifies whether the analog watchdog is configured is interrupt mode or in polling mode. This parameter can be set to ENABLE or DISABLE */ uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */ -}ADC_AnalogWDGConfTypeDef; +} ADC_AnalogWDGConfTypeDef; -/** +/** * @brief HAL ADC state machine: ADC states definition (bitfields) - */ + */ /* States of ADC global scope */ #define HAL_ADC_STATE_RESET 0x00000000U /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY 0x00000001U /*!< ADC peripheral ready for use */ @@ -187,9 +186,9 @@ typedef struct #define HAL_ADC_STATE_MULTIMODE_SLAVE 0x00100000U /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */ -/** +/** * @brief ADC handle Structure definition - */ + */ #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) typedef struct __ADC_HandleTypeDef #else @@ -218,7 +217,7 @@ typedef struct void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -}ADC_HandleTypeDef; +} ADC_HandleTypeDef; #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /** @@ -269,18 +268,18 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler * @{ - */ + */ #define ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000U #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) /** * @} - */ + */ /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases * @{ - */ + */ #define ADC_TWOSAMPLINGDELAY_5CYCLES 0x00000000U #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) @@ -299,29 +298,29 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) /** * @} - */ + */ /** @defgroup ADC_Resolution ADC Resolution * @{ - */ + */ #define ADC_RESOLUTION_12B 0x00000000U #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0) #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1) #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES) /** * @} - */ + */ /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular * @{ - */ + */ #define ADC_EXTERNALTRIGCONVEDGE_NONE 0x00000000U #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0) #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1) #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN) /** * @} - */ + */ /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular * @{ @@ -347,20 +346,20 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1U) /** * @} - */ + */ /** @defgroup ADC_Data_align ADC Data Align * @{ - */ + */ #define ADC_DATAALIGN_RIGHT 0x00000000U #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN) /** * @} - */ + */ /** @defgroup ADC_channels ADC Common Channels * @{ - */ + */ #define ADC_CHANNEL_0 0x00000000U #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0) #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1) @@ -385,11 +384,11 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) /** * @} - */ + */ /** @defgroup ADC_sampling_times ADC Sampling Times * @{ - */ + */ #define ADC_SAMPLETIME_3CYCLES 0x00000000U #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0) #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1) @@ -400,21 +399,21 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10) /** * @} - */ + */ - /** @defgroup ADC_EOCSelection ADC EOC Selection +/** @defgroup ADC_EOCSelection ADC EOC Selection * @{ - */ + */ #define ADC_EOC_SEQ_CONV 0x00000000U #define ADC_EOC_SINGLE_CONV 0x00000001U #define ADC_EOC_SINGLE_SEQ_CONV 0x00000002U /*!< reserved for future use */ /** * @} - */ + */ /** @defgroup ADC_Event_type ADC Event Type * @{ - */ + */ #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) /** @@ -423,7 +422,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection * @{ - */ + */ #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN)) #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN)) @@ -433,22 +432,22 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_ANALOGWATCHDOG_NONE 0x00000000U /** * @} - */ - + */ + /** @defgroup ADC_interrupts_definition ADC Interrupts Definition * @{ - */ + */ #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE) #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE) #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE) #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE) /** * @} - */ - + */ + /** @defgroup ADC_flags_definition ADC Flags Definition * @{ - */ + */ #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD) #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC) #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC) @@ -457,11 +456,11 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR) /** * @} - */ + */ /** @defgroup ADC_channels_type ADC Channels Type * @{ - */ + */ #define ADC_ALL_CHANNELS 0x00000001U #define ADC_REGULAR_CHANNELS 0x00000002U /*!< reserved for future use */ #define ADC_INJECTED_CHANNELS 0x00000003U /*!< reserved for future use */ @@ -471,7 +470,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Macros ADC Exported Macros @@ -563,10 +562,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ /* Initialization/de-initialization functions ***********************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); +void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); +void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ @@ -581,25 +580,25 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca * @{ */ /* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); -void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); +void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); +void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); +void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); /** * @} @@ -609,8 +608,8 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions *************************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); /** * @} */ @@ -619,7 +618,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG * @{ */ /* Peripheral State functions ***************************************************/ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); +uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} @@ -698,7 +697,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) - + #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ @@ -782,7 +781,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Set ADC Regular channel sequence length. - * @param _NbrOfConversion_ Regular channel sequence length. + * @param _NbrOfConversion_ Regular channel sequence length. * @retval None */ #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U) @@ -790,7 +789,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. * @param _SAMPLETIME_ Sample time parameter. - * @param _CHANNELNB_ Channel number. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) @@ -798,7 +797,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. * @param _SAMPLETIME_ Sample time parameter. - * @param _CHANNELNB_ Channel number. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) @@ -806,7 +805,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Set the selected regular channel rank for rank between 1 and 6. * @param _CHANNELNB_ Channel number. - * @param _RANKNB_ Rank number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) @@ -814,7 +813,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Set the selected regular channel rank for rank between 7 and 12. * @param _CHANNELNB_ Channel number. - * @param _RANKNB_ Rank number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) @@ -822,7 +821,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @brief Set the selected regular channel rank for rank between 13 and 16. * @param _CHANNELNB_ Channel number. - * @param _RANKNB_ Rank number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) @@ -884,7 +883,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** * @} - */ + */ /** * @} @@ -897,4 +896,3 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); #endif /*__STM32F4xx_ADC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc_ex.c index c5489522a46..7db19937157 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc_ex.c @@ -6,6 +6,17 @@ * functionalities of the ADC extension peripheral: * + Extended features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -53,8 +64,8 @@ (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can - add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback - (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback + (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT() @@ -69,18 +80,6 @@ @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -93,12 +92,12 @@ /** @defgroup ADCEx ADCEx * @brief ADC Extended driver modules * @{ - */ + */ #ifdef HAL_ADC_MODULE_ENABLED - + /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @addtogroup ADCEx_Private_Functions @@ -107,7 +106,7 @@ /* Private function prototypes -----------------------------------------------*/ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma); static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma); -static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); +static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); /** * @} */ @@ -117,13 +116,13 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); * @{ */ -/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions * -@verbatim +@verbatim =============================================================================== ##### Extended features functions ##### - =============================================================================== + =============================================================================== [..] This section provides functions allowing to: (+) Start conversion of injected channel. (+) Stop conversion of injected channel. @@ -133,7 +132,7 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); (+) Get result of multimode conversion. (+) Configure injected channels. (+) Configure multimode. - + @endverbatim * @{ */ @@ -144,35 +143,35 @@ static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; uint32_t tmp1 = 0U, tmp2 = 0U; ADC_Common_TypeDef *tmpADC_Common; - + /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ - - /* Check if ADC peripheral is disabled in order to enable it and wait during + + /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); - + /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } - + /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ @@ -180,7 +179,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - + /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ @@ -190,12 +189,12 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); @@ -206,11 +205,11 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -220,7 +219,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) + if ((hadc->Instance == ADC1) && tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -235,7 +234,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } - + /* Return function status */ return HAL_OK; } @@ -247,35 +246,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) * * @retval HAL status. */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc) { __IO uint32_t counter = 0U; uint32_t tmp1 = 0U, tmp2 = 0U; ADC_Common_TypeDef *tmpADC_Common; - + /* Process locked */ __HAL_LOCK(hadc); - + /* Enable the ADC peripheral */ - - /* Check if ADC peripheral is disabled in order to enable it and wait during + + /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); - + /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } - + /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to injected group conversion results */ @@ -283,7 +282,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); - + /* Check if a regular conversion is ongoing */ /* Note: On this device, there is no ADC error code fields related to */ /* conversions on group injected only. In case of conversion on */ @@ -293,16 +292,16 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Clear injected group conversion flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - + /* Enable end of conversion interrupt for injected channels */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); @@ -310,13 +309,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ /* control register) */ tmpADC_Common = ADC_COMMON_REGISTER(hadc); - + /* Check if Multimode enabled */ - if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) + if (HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if(tmp1 && tmp2) + if (tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -326,7 +325,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) { tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); - if((hadc->Instance == ADC1) && tmp1 && tmp2) + if ((hadc->Instance == ADC1) && tmp1 && tmp2) { /* Enable the selected ADC software conversion for injected group */ hadc->Instance->CR2 |= ADC_CR2_JSWSTART; @@ -341,7 +340,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } - + /* Return function status */ return HAL_OK; } @@ -349,7 +348,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) /** * @brief Stop conversion of injected channels. Disable ADC peripheral if * no regular conversion is on going. - * @note If ADC must be disabled and if conversion is on going on + * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, @@ -358,31 +357,31 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) * @param hadc ADC handle * @retval None */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); - + /* Stop potential conversion and disable ADC peripheral */ /* Conditioned to: */ /* - No conversion on the other group (regular group) is intended to */ /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); - + /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, @@ -394,13 +393,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -409,28 +408,28 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) * @brief Poll for injected conversion complete * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) { uint32_t tickstart = 0U; - /* Get tick */ + /* Get tick */ tickstart = HAL_GetTick(); /* Check End of conversion flag */ - while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + while (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { /* New check to avoid false timeout detection in case of preemption */ - if(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) + if (!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) { - hadc->State= HAL_ADC_STATE_TIMEOUT; + hadc->State = HAL_ADC_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_TIMEOUT; @@ -438,44 +437,44 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u } } } - + /* Clear injected group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); - + /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); - + /* Determine whether any further conversion upcoming on group injected */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F4, there is no independent flag of end of sequence. */ /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && - (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && - (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && - (ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) + if (ADC_IS_SOFTWARE_START_INJECTED(hadc) && + (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) && + (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && + (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE)))) { /* Set ADC state */ CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); - + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) - { + { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } - + /* Return ADC state */ return HAL_OK; -} - +} + /** - * @brief Stop conversion of injected channels, disable interruption of + * @brief Stop conversion of injected channels, disable interruption of * end-of-conversion. Disable ADC peripheral if no regular conversion * is on going. - * @note If ADC must be disabled and if conversion is on going on + * @note If ADC must be disabled and if conversion is on going on * regular group, function HAL_ADC_Stop must be used to stop both * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, @@ -483,35 +482,35 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u * @param hadc ADC handle * @retval None */ -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); - + /* Stop potential conversion and disable ADC peripheral */ /* Conditioned to: */ /* - No conversion on the other group (regular group) is intended to */ /* continue (injected and regular groups stop conversion and ADC disable */ /* are common) */ - /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ - if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && - HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) + /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ + if (((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && + HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)) { /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); - + /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Disable ADC end of conversion interrupt for injected channels */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); - + /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, @@ -522,13 +521,13 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) { /* Update ADC state machine to error */ SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - + tmp_hal_status = HAL_ERROR; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } @@ -545,32 +544,32 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected * @retval None */ -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank) { __IO uint32_t tmp = 0U; - + /* Check the parameters */ assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); - + /* Clear injected group conversion flag to have similar behaviour as */ /* regular group: reading data register also clears end of conversion flag. */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); - - /* Return the selected ADC converted value */ - switch(InjectedRank) - { + + /* Return the selected ADC converted value */ + switch (InjectedRank) + { case ADC_INJECTED_RANK_4: { tmp = hadc->Instance->JDR4; - } + } break; - case ADC_INJECTED_RANK_3: - { + case ADC_INJECTED_RANK_3: + { tmp = hadc->Instance->JDR3; - } + } break; - case ADC_INJECTED_RANK_2: - { + case ADC_INJECTED_RANK_2: + { tmp = hadc->Instance->JDR2; } break; @@ -580,53 +579,53 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa } break; default: - break; + break; } return tmp; } /** * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral - * - * @note Caution: This function must be used only with the ADC master. + * + * @note Caution: This function must be used only with the ADC master. * * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. - * @param Length The length of data to be transferred from ADC peripheral to memory. + * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) { __IO uint32_t counter = 0U; ADC_Common_TypeDef *tmpADC_Common; - + /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - + /* Process locked */ __HAL_LOCK(hadc); - - /* Check if ADC peripheral is disabled in order to enable it and wait during + + /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ - if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) - { + if ((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) + { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); - + /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); - while(counter != 0U) + while (counter != 0U) { counter--; } } - + /* Start conversion if ADC is effectively enabled */ - if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ @@ -634,43 +633,43 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_REG_BUSY); - + /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { - ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); + ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } - + /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ - CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); + CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } - + /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); - + /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; - + /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; - + /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; - + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ - + /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); @@ -693,12 +692,12 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Disable the selected ADC EOC rising on each regular channel conversion */ tmpADC_Common->CCR &= ~ADC_CCR_DDS; } - + /* Enable the DMA Stream */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); - + /* if no external trigger present enable software conversion of regular channels */ - if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) + if ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; @@ -712,28 +711,28 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t /* Set ADC error code to ADC IP internal error */ SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); } - + /* Return function status */ return HAL_OK; } /** - * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral + * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_Common_TypeDef *tmpADC_Common; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - + /* Process locked */ __HAL_LOCK(hadc); - + /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ __HAL_ADC_DISABLE(hadc); @@ -744,39 +743,39 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* Check if ADC is effectively disabled */ - if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) + if (HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Disable the selected ADC DMA mode for multimode */ tmpADC_Common->CCR &= ~ADC_CCR_DDS; - + /* Disable the DMA channel (in case of DMA in circular mode or stop while */ /* DMA transfer is on going) */ tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - + /* Disable ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - + /* Set ADC state */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY); } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return tmp_hal_status; } /** - * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results + * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results * data in the selected multi mode. * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval The converted data value. */ -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc) { ADC_Common_TypeDef *tmpADC_Common; @@ -790,12 +789,12 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) } /** - * @brief Injected conversion complete callback in non blocking mode + * @brief Injected conversion complete callback in non blocking mode * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ -__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) +__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hadc); @@ -809,15 +808,15 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) * rank in the sequencer and its sample time. * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfigInjected ADC configuration structure for injected channel. + * @param sConfigInjected ADC configuration structure for injected channel. * @retval None */ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected) { - -#ifdef USE_FULL_ASSERT + +#ifdef USE_FULL_ASSERT uint32_t tmp = 0U; - + #endif /* USE_FULL_ASSERT */ ADC_Common_TypeDef *tmpADC_Common; @@ -836,20 +835,20 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); #endif /* USE_FULL_ASSERT */ - if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); } /* Process locked */ __HAL_LOCK(hadc); - + /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) { /* Clear the old sample time */ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); - + /* Set the new sample time */ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); } @@ -857,34 +856,34 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { /* Clear the old sample time */ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); - + /* Set the new sample time */ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); } - + /*---------------------------- ADCx JSQR Configuration -----------------*/ hadc->Instance->JSQR &= ~(ADC_JSQR_JL); hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); - + /* Rank configuration */ - + /* Clear the old SQx bits for the selected rank */ - hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); - + hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion); + /* Set the SQx bits for the selected rank */ - hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); + hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion); /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) - { + /* software start. */ + if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) + { /* Select external trigger to start conversion */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; - + /* Select external trigger polarity */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; @@ -893,9 +892,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I { /* Reset the external trigger */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); - hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); + hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); } - + if (sConfigInjected->AutoInjectedConv != DISABLE) { /* Enable the selected ADC automatic injected group conversion */ @@ -906,7 +905,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Disable the selected ADC automatic injected group conversion */ hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); } - + if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) { /* Enable the selected ADC injected discontinuous mode */ @@ -917,8 +916,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Disable the selected ADC injected discontinuous mode */ hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); } - - switch(sConfigInjected->InjectedRank) + + switch (sConfigInjected->InjectedRank) { case 1U: /* Set injected channel 1 offset */ @@ -945,7 +944,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Pointer to the common control register to which is belonging hadc */ /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ /* control register) */ - tmpADC_Common = ADC_COMMON_REGISTER(hadc); + tmpADC_Common = ADC_COMMON_REGISTER(hadc); /* if ADC1 Channel_18 is selected enable VBAT Channel */ if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) @@ -953,30 +952,30 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I /* Enable the VBAT channel*/ tmpADC_Common->CCR |= ADC_CCR_VBATE; } - + /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))) { /* Enable the TSVREFE channel*/ tmpADC_Common->CCR |= ADC_CCR_TSVREFE; } - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return HAL_OK; } /** - * @brief Configures the ADC multi-mode + * @brief Configures the ADC multi-mode * @param hadc pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains + * the configuration information for the specified ADC. + * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains * the configuration information for multimode. * @retval HAL status */ -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode) { ADC_Common_TypeDef *tmpADC_Common; @@ -985,7 +984,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ assert_param(IS_ADC_MODE(multimode->Mode)); assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); - + /* Process locked */ __HAL_LOCK(hadc); @@ -997,18 +996,18 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /* Set ADC mode */ tmpADC_Common->CCR &= ~(ADC_CCR_MULTI); tmpADC_Common->CCR |= multimode->Mode; - + /* Set the ADC DMA access mode */ tmpADC_Common->CCR &= ~(ADC_CCR_DMA); tmpADC_Common->CCR |= multimode->DMAAccessMode; - + /* Set delay between two sampling phases */ tmpADC_Common->CCR &= ~(ADC_CCR_DELAY); tmpADC_Common->CCR |= multimode->TwoSamplingDelay; - + /* Process unlocked */ __HAL_UNLOCK(hadc); - + /* Return function status */ return HAL_OK; } @@ -1018,48 +1017,48 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ */ /** - * @brief DMA transfer complete callback. + * @brief DMA transfer complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) +static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) { /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Update state machine on conversion status if not in error state */ if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) { /* Update ADC state machine */ SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - + /* Determine whether any further conversion upcoming on group regular */ /* by external trigger, continuous mode or scan sequence on going. */ /* Note: On STM32F4, there is no independent flag of end of sequence. */ /* The test of scan sequence on going is done either with scan */ /* sequence disabled or with end of conversion flag set to */ /* of end of sequence. */ - if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && - (hadc->Init.ContinuousConvMode == DISABLE) && - (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || - HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) + if (ADC_IS_SOFTWARE_START_REGULAR(hadc) && + (hadc->Init.ContinuousConvMode == DISABLE) && + (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || + HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS))) { /* Disable ADC end of single conversion interrupt on group regular */ /* Note: Overrun interrupt was enabled with EOC interrupt in */ /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ /* by overrun IRQ process below. */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - + /* Set ADC state */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); - + CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); + if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { SET_BIT(hadc->State, HAL_ADC_STATE_READY); } } - + /* Conversion complete callback */ HAL_ADC_ConvCpltCallback(hadc); } @@ -1071,31 +1070,31 @@ static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA half transfer complete callback. + * @brief DMA half transfer complete callback. * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) +static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Conversion complete callback */ - HAL_ADC_ConvHalfCpltCallback(hadc); + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Conversion complete callback */ + HAL_ADC_ConvHalfCpltCallback(hadc); } /** - * @brief DMA error callback + * @brief DMA error callback * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) +static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) { - ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hadc->State= HAL_ADC_STATE_ERROR_DMA; - /* Set ADC error code to DMA error */ - hadc->ErrorCode |= HAL_ADC_ERROR_DMA; - HAL_ADC_ErrorCallback(hadc); + ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + hadc->State = HAL_ADC_STATE_ERROR_DMA; + /* Set ADC error code to DMA error */ + hadc->ErrorCode |= HAL_ADC_ERROR_DMA; + HAL_ADC_ErrorCallback(hadc); } /** @@ -1105,10 +1104,9 @@ static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) #endif /* HAL_ADC_MODULE_ENABLED */ /** * @} - */ + */ /** * @} - */ + */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc_ex.h index b0cdd2abd35..8ce8484dda7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_adc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -22,7 +21,7 @@ #define __STM32F4xx_ADC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -34,14 +33,14 @@ /** @addtogroup ADCEx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup ADCEx_Exported_Types ADC Exported Types * @{ */ - -/** + +/** * @brief ADC Configuration injected Channel structure definition * @note Parameters of this structure are shared within 2 scopes: * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset @@ -53,7 +52,7 @@ * - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group. * - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group. */ -typedef struct +typedef struct { uint32_t InjectedChannel; /*!< Selection of ADC channel to configure This parameter can be a value of @ref ADC_channels @@ -77,17 +76,17 @@ typedef struct uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the injected group sequencer. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. This parameter must be a number between Min_Data = 1 and Max_Data = 4. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts). Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. This parameter can be set to ENABLE or DISABLE. Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group conversion after regular one - This parameter can be set to ENABLE or DISABLE. + This parameter can be set to ENABLE or DISABLE. Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START) Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. @@ -105,22 +104,22 @@ typedef struct uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected. If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. - Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to + Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on injected group can impact the configuration of other channels previously set. */ -}ADC_InjectionConfTypeDef; +} ADC_InjectionConfTypeDef; -/** - * @brief ADC Configuration multi-mode structure definition - */ +/** + * @brief ADC Configuration multi-mode structure definition + */ typedef struct { - uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. + uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. This parameter can be a value of @ref ADCEx_Common_mode */ uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ -}ADC_MultiModeTypeDef; +} ADC_MultiModeTypeDef; /** * @} @@ -133,7 +132,7 @@ typedef struct /** @defgroup ADCEx_Common_mode ADC Common Mode * @{ - */ + */ #define ADC_MODE_INDEPENDENT 0x00000000U #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0) #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1) @@ -149,33 +148,33 @@ typedef struct #define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)) /** * @} - */ + */ /** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode * @{ - */ + */ #define ADC_DMAACCESSMODE_DISABLED 0x00000000U /*!< DMA mode disabled */ #define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/ #define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/ #define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */ /** * @} - */ + */ /** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected * @{ - */ + */ #define ADC_EXTERNALTRIGINJECCONVEDGE_NONE 0x00000000U #define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0) #define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1) #define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN) /** * @} - */ + */ /** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected * @{ - */ + */ #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 0x00000000U #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0) #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1) @@ -195,11 +194,11 @@ typedef struct #define ADC_INJECTED_SOFTWARE_START ((uint32_t)ADC_CR2_JEXTSEL + 1U) /** * @} - */ + */ /** @defgroup ADCEx_injected_rank ADC Injected Rank * @{ - */ + */ #define ADC_INJECTED_RANK_1 0x00000001U #define ADC_INJECTED_RANK_2 0x00000002U #define ADC_INJECTED_RANK_3 0x00000003U @@ -220,18 +219,18 @@ typedef struct STM32F412Vx || STM32F412Rx || STM32F412Cx */ #if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */ #define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) #endif /* STM32F411xE || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} - */ + */ /** * @} - */ + */ /* Exported macro ------------------------------------------------------------*/ /** @defgroup ADC_Exported_Macros ADC Exported Macros @@ -243,9 +242,9 @@ typedef struct * @note Use case of this macro: * On devices STM32F42x and STM32F43x, ADC internal channels * Vbat and VrefInt share the same internal path, only - * one of them can be enabled.This macro is to be used when ADC - * channels Vbat and VrefInt are selected, and must be called - * before starting conversion of ADC channel VrefInt in order + * one of them can be enabled.This macro is to be used when ADC + * channels Vbat and VrefInt are selected, and must be called + * before starting conversion of ADC channel VrefInt in order * to disable ADC channel Vbat. * @retval None */ @@ -253,7 +252,7 @@ typedef struct #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ADCEx_Exported_Functions @@ -265,24 +264,24 @@ typedef struct */ /* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); -HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc); -uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc); -void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); +HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); +HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); +HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); +void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); /* Peripheral Control functions *************************************************/ -HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); -HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode); +HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); +HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); /** * @} - */ + */ /** * @} @@ -309,7 +308,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ #define IS_ADC_CHANNEL(CHANNEL) ((CHANNEL) <= ADC_CHANNEL_18) #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */ - + #if defined(STM32F411xE) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || \ defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || \ defined(STM32F469xx) || defined(STM32F479xx) @@ -361,7 +360,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @brief Set the selected injected Channel rank. * @param _CHANNELNB_ Channel number. - * @param _RANKNB_ Rank number. + * @param _RANKNB_ Rank number. * @param _JSQR_JL_ Sequence length. * @retval None */ @@ -393,7 +392,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** * @} - */ + */ /** * @} @@ -406,4 +405,3 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ #endif /*__STM32F4xx_ADC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_can.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_can.c index 86f6c7ceb00..b9bb57593ef 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_can.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_can.c @@ -12,6 +12,17 @@ * + Callbacks functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -131,9 +142,9 @@ The compilation define USE_HAL_CAN_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_CAN_RegisterCallback() to register an interrupt callback. + Use Function HAL_CAN_RegisterCallback() to register an interrupt callback. - Function @ref HAL_CAN_RegisterCallback() allows to register following callbacks: + Function HAL_CAN_RegisterCallback() allows to register following callbacks: (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. (+) TxMailbox1CompleteCallback : Tx Mailbox 1 Complete Callback. (+) TxMailbox2CompleteCallback : Tx Mailbox 2 Complete Callback. @@ -152,9 +163,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_CAN_UnRegisterCallback() to reset a callback to the default + Use function HAL_CAN_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_CAN_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxMailbox0CompleteCallback : Tx Mailbox 0 Complete Callback. @@ -173,13 +184,13 @@ (+) MspInitCallback : CAN MspInit. (+) MspDeInitCallback : CAN MspDeInit. - By default, after the @ref HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, + By default, after the HAL_CAN_Init() and when the state is HAL_CAN_STATE_RESET, all callbacks are set to the corresponding weak functions: - example @ref HAL_CAN_ErrorCallback(). + example HAL_CAN_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() only when + reset to the legacy weak function in the HAL_CAN_Init()/ HAL_CAN_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CAN_Init()/ @ref HAL_CAN_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CAN_Init()/ HAL_CAN_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_CAN_STATE_READY state only. @@ -187,8 +198,8 @@ in HAL_CAN_STATE_READY or HAL_CAN_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CAN_RegisterCallback() before calling @ref HAL_CAN_DeInit() - or @ref HAL_CAN_Init() function. + using HAL_CAN_RegisterCallback() before calling HAL_CAN_DeInit() + or HAL_CAN_Init() function. When The compilation define USE_HAL_CAN_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -196,17 +207,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -226,8 +226,8 @@ #ifdef HAL_CAN_MODULE_ENABLED #ifdef HAL_CAN_LEGACY_MODULE_ENABLED - #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" -#endif +#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -330,14 +330,14 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) } #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ - /* Exit from sleep mode */ - CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); + /* Request initialisation */ + SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); /* Get tick */ tickstart = HAL_GetTick(); - /* Check Sleep mode leave acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) + /* Wait initialisation acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { @@ -351,14 +351,14 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan) } } - /* Request initialisation */ - SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ); + /* Exit from sleep mode */ + CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait initialisation acknowledge */ - while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U) + /* Check Sleep mode leave acknowledge */ + while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U) { if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE) { @@ -537,25 +537,26 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan) * the configuration information for CAN module * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)) +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)) { HAL_StatusTypeDef status = HAL_OK; @@ -675,24 +676,24 @@ HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Call /** * @brief Unregister a CAN CallBack. - * CAN callabck is redirected to the weak predefined callback + * CAN callback is redirected to the weak predefined callback * @param hcan pointer to a CAN_HandleTypeDef structure that contains * the configuration information for CAN module * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: - * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CALLBACK_CB_ID Tx Mailbox 0 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CALLBACK_CB_ID Tx Mailbox 1 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CALLBACK_CB_ID Tx Mailbox 2 Complete callback ID - * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CALLBACK_CB_ID Tx Mailbox 0 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CALLBACK_CB_ID Tx Mailbox 1 Abort callback ID - * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CALLBACK_CB_ID Tx Mailbox 2 Abort callback ID - * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CALLBACK_CB_ID Rx Fifo 0 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO0_FULL_CALLBACK_CB_ID Rx Fifo 0 full callback ID - * @arg @ref HAL_CAN_RX_FIFO1_MSGPENDING_CALLBACK_CB_ID Rx Fifo 1 message pending callback ID - * @arg @ref HAL_CAN_RX_FIFO1_FULL_CALLBACK_CB_ID Rx Fifo 1 full callback ID - * @arg @ref HAL_CAN_SLEEP_CALLBACK_CB_ID Sleep callback ID - * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CALLBACK_CB_ID Wake Up from Rx message callback ID - * @arg @ref HAL_CAN_ERROR_CALLBACK_CB_ID Error callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID Tx Mailbox 0 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID Tx Mailbox 1 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID Tx Mailbox 2 Complete callback ID + * @arg @ref HAL_CAN_TX_MAILBOX0_ABORT_CB_ID Tx Mailbox 0 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX1_ABORT_CB_ID Tx Mailbox 1 Abort callback ID + * @arg @ref HAL_CAN_TX_MAILBOX2_ABORT_CB_ID Tx Mailbox 2 Abort callback ID + * @arg @ref HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID Rx Fifo 0 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO0_FULL_CB_ID Rx Fifo 0 full callback ID + * @arg @ref HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID Rx Fifo 1 message pending callback ID + * @arg @ref HAL_CAN_RX_FIFO1_FULL_CB_ID Rx Fifo 1 full callback ID + * @arg @ref HAL_CAN_SLEEP_CB_ID Sleep callback ID + * @arg @ref HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID Wake Up from Rx message callback ID + * @arg @ref HAL_CAN_ERROR_CB_ID Error callback ID * @arg @ref HAL_CAN_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_CAN_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status @@ -835,7 +836,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca * contains the filter configuration information. * @retval None */ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig) +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig) { uint32_t filternbrbitpos; CAN_TypeDef *can_ip = hcan->Instance; @@ -1216,7 +1217,7 @@ HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan) * - 0 : Sleep mode is not active. * - 1 : Sleep mode is active. */ -uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan) { uint32_t status = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1247,7 +1248,8 @@ uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan) * This parameter can be a value of @arg CAN_Tx_Mailboxes. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox) +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox) { uint32_t transmitmailbox; HAL_CAN_StateTypeDef state = hcan->State; @@ -1404,7 +1406,7 @@ HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMai * the configuration information for the specified CAN. * @retval Number of free Tx Mailboxes. */ -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan) { uint32_t freelevel = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1447,7 +1449,7 @@ uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan) * - 1 : Pending transmission request on at least one of the selected * Tx Mailbox. */ -uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes) { uint32_t status = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -1479,7 +1481,7 @@ uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxe * This parameter can be one value of @arg CAN_Tx_Mailboxes. * @retval Timestamp of message sent from Tx Mailbox. */ -uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox) { uint32_t timestamp = 0U; uint32_t transmitmailbox; @@ -1513,7 +1515,8 @@ uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox) * @param aData array where the payload of the Rx frame will be stored. * @retval HAL status */ -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]) { HAL_CAN_StateTypeDef state = hcan->State; @@ -1554,7 +1557,8 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, } else { - pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; + pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & + hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos; } pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR); pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos; @@ -1603,7 +1607,7 @@ HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, * This parameter can be a value of @arg CAN_receive_FIFO_number. * @retval Number of messages available in Rx FIFO. */ -uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo) +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo) { uint32_t filllevel = 0U; HAL_CAN_StateTypeDef state = hcan->State; @@ -2371,7 +2375,7 @@ __weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan) * the configuration information for the specified CAN. * @retval HAL state */ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan) { HAL_CAN_StateTypeDef state = hcan->State; @@ -2406,7 +2410,7 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan) * the configuration information for the specified CAN. * @retval CAN Error Code */ -uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan) +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan) { /* Return CAN error code */ return hcan->ErrorCode; @@ -2460,5 +2464,3 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_can.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_can.h index 062abd69250..cf4557b545b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_can.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_can.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -103,21 +102,25 @@ typedef struct { uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number, according to the mode (MSBs for a 32-bit configuration, first one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number, according to the mode (LSBs for a 32-bit configuration, second one for a 16-bit configuration). - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0xFFFF. */ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter. This parameter can be a value of @ref CAN_filter_FIFO */ @@ -295,11 +298,11 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to #define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */ #define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */ #define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 0 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 1 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 2 transmit failure due to arbitration lost */ -#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ +#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 2 transmit failure due to transmit error */ #define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */ #define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */ #define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */ @@ -330,7 +333,8 @@ typedef void (*pCAN_CallbackTypeDef)(CAN_HandleTypeDef *hcan); /*!< pointer to #define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */ #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ -#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ +#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with + silent mode */ /** * @} */ @@ -645,7 +649,8 @@ void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan); #if USE_HAL_CAN_REGISTER_CALLBACKS == 1 /* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, void (* pCallback)(CAN_HandleTypeDef *_hcan)); +HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID, + void (* pCallback)(CAN_HandleTypeDef *_hcan)); HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID); #endif /* (USE_HAL_CAN_REGISTER_CALLBACKS) */ @@ -659,7 +664,7 @@ HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_Ca */ /* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig); +HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig); /** * @} @@ -675,14 +680,16 @@ HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan); -HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox); +uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan); +HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader, + const uint8_t aData[], uint32_t *pTxMailbox); HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); -uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); -uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox); -HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); -uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo); +uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes); +uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox); +HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, + CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]); +uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo); /** * @} @@ -730,8 +737,8 @@ void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan); -uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); +HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan); +uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan); HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); /** @@ -807,7 +814,8 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); #define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 )) -#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2)) +#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | \ + CAN_TX_MAILBOX2)) #define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU) #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) #define IS_CAN_DLC(DLC) ((DLC) <= 8U) @@ -843,6 +851,3 @@ HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan); #endif #endif /* STM32F4xx_HAL_CAN_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.c index 7420907a694..3ef9e3f4323 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.c @@ -11,6 +11,17 @@ * + Peripheral Control function * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -47,10 +58,10 @@ The compilation define USE_HAL_CEC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback() + Use Functions HAL_CEC_RegisterCallback() or HAL_CEC_RegisterXXXCallback() to register an interrupt callback. - Function @ref HAL_CEC_RegisterCallback() allows to register following callbacks: + Function HAL_CEC_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Transfer completed callback. (+) ErrorCallback : callback for error detection. (+) MspInitCallback : CEC MspInit. @@ -59,11 +70,11 @@ and a pointer to the user callback function. For specific callback HAL_CEC_RxCpltCallback use dedicated register callbacks - @ref HAL_CEC_RegisterRxCpltCallback(). + HAL_CEC_RegisterRxCpltCallback(). - Use function @ref HAL_CEC_UnRegisterCallback() to reset a callback to the default + Use function HAL_CEC_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_CEC_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Transfer completed callback. @@ -72,15 +83,15 @@ (+) MspDeInitCallback : CEC MspDeInit. For callback HAL_CEC_RxCpltCallback use dedicated unregister callback : - @ref HAL_CEC_UnRegisterRxCpltCallback(). + HAL_CEC_UnRegisterRxCpltCallback(). - By default, after the @ref HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET + By default, after the HAL_CEC_Init() and when the state is HAL_CEC_STATE_RESET all callbacks are set to the corresponding weak functions : - examples @ref HAL_CEC_TxCpltCallback() , @ref HAL_CEC_RxCpltCallback(). + examples HAL_CEC_TxCpltCallback() , HAL_CEC_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CEC_Init()/ @ref HAL_CEC_DeInit() only when + reset to the legacy weak function in the HAL_CEC_Init()/ HAL_CEC_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CEC_Init() / @ref HAL_CEC_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CEC_Init() / HAL_CEC_DeInit() keep and use the user MspInit/MspDeInit functions (registered beforehand) Callbacks can be registered/unregistered in HAL_CEC_STATE_READY state only. @@ -88,25 +99,14 @@ in HAL_CEC_STATE_READY or HAL_CEC_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CEC_RegisterCallback() before calling @ref HAL_CEC_DeInit() - or @ref HAL_CEC_Init() function. + using HAL_CEC_RegisterCallback() before calling HAL_CEC_DeInit() + or HAL_CEC_Init() function. When the compilation define USE_HAL_CEC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -497,7 +497,7 @@ HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_Call /** * @brief Unregister an CEC Callback - * CEC callabck is redirected to the weak predefined callback + * CEC callback is redirected to the weak predefined callback * @param hcec uart handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -694,9 +694,9 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec) * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, - uint8_t *pData, uint32_t Size) + const uint8_t *pData, uint32_t Size) { - /* if the IP isn't already busy and if there is no previous transmission + /* if the peripheral isn't already busy and if there is no previous transmission already pending due to arbitration lost */ if (hcec->gState == HAL_CEC_STATE_READY) { @@ -749,7 +749,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator * @param hcec CEC handle * @retval Frame size */ -uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) +uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec) { return hcec->RxXferSize; } @@ -775,13 +775,13 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) { /* save interrupts register for further error or interrupts handling purposes */ - uint32_t reg; - reg = hcec->Instance->ISR; + uint32_t itflag; + itflag = hcec->Instance->ISR; /* ----------------------------Arbitration Lost Management----------------------------------*/ /* CEC TX arbitration error interrupt occurred --------------------------------------*/ - if ((reg & CEC_FLAG_ARBLST) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_ARBLST)) { hcec->ErrorCode = HAL_CEC_ERROR_ARBLST; __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); @@ -789,7 +789,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* ----------------------------Rx Management----------------------------------*/ /* CEC RX byte received interrupt ---------------------------------------------------*/ - if ((reg & CEC_FLAG_RXBR) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXBR)) { /* reception is starting */ hcec->RxState = HAL_CEC_STATE_BUSY_RX; @@ -801,7 +801,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) } /* CEC RX end received interrupt ---------------------------------------------------*/ - if ((reg & CEC_FLAG_RXEND) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_RXEND)) { /* clear IT */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXEND); @@ -820,7 +820,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) /* ----------------------------Tx Management----------------------------------*/ /* CEC TX byte request interrupt ------------------------------------------------*/ - if ((reg & CEC_FLAG_TXBR) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXBR)) { --hcec->TxXferCount; if (hcec->TxXferCount == 0U) @@ -829,14 +829,14 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) __HAL_CEC_LAST_BYTE_TX_SET(hcec); } /* In all cases transmit the byte */ - hcec->Instance->TXDR = *hcec->pTxBuffPtr; + hcec->Instance->TXDR = (uint8_t)*hcec->pTxBuffPtr; hcec->pTxBuffPtr++; /* clear Tx-Byte request flag */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXBR); } /* CEC TX end interrupt ------------------------------------------------*/ - if ((reg & CEC_FLAG_TXEND) != 0U) + if (HAL_IS_BIT_SET(itflag, CEC_FLAG_TXEND)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXEND); @@ -854,21 +854,21 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) } /* ----------------------------Rx/Tx Error Management----------------------------------*/ - if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | CEC_ISR_TXERR | - CEC_ISR_TXACKE)) != 0U) + if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE | CEC_ISR_TXUDR | + CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U) { - hcec->ErrorCode = reg; + hcec->ErrorCode = itflag; __HAL_CEC_CLEAR_FLAG(hcec, HAL_CEC_ERROR_RXOVR | HAL_CEC_ERROR_BRE | CEC_FLAG_LBPE | CEC_FLAG_SBPE | HAL_CEC_ERROR_RXACKE | HAL_CEC_ERROR_TXUDR | HAL_CEC_ERROR_TXERR | HAL_CEC_ERROR_TXACKE); - if ((reg & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) + if ((itflag & (CEC_ISR_RXOVR | CEC_ISR_BRE | CEC_ISR_SBPE | CEC_ISR_LBPE | CEC_ISR_RXACKE)) != 0U) { hcec->Init.RxBuffer -= hcec->RxXferSize; hcec->RxXferSize = 0U; hcec->RxState = HAL_CEC_STATE_READY; } - else if (((reg & CEC_ISR_ARBLST) == 0U) && ((reg & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) + else if (((itflag & CEC_ISR_ARBLST) == 0U) && ((itflag & (CEC_ISR_TXUDR | CEC_ISR_TXERR | CEC_ISR_TXACKE)) != 0U)) { /* Set the CEC state ready to be able to start again the process */ hcec->gState = HAL_CEC_STATE_READY; @@ -957,7 +957,7 @@ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) * the configuration information for the specified CEC module. * @retval HAL state */ -HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) +HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec) { uint32_t temp1, temp2; temp1 = hcec->gState; @@ -972,7 +972,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec) * the configuration information for the specified CEC. * @retval CEC Error Code */ -uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) +uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec) { return hcec->ErrorCode; } @@ -994,4 +994,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.h index f371a9cf136..7738946662f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cec.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -105,7 +104,7 @@ typedef struct uint16_t OwnAddress; /*!< Own addresses configuration This parameter can be a value of @ref CEC_OWN_ADDRESS */ - uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */ + uint8_t *RxBuffer; /*!< CEC Rx buffer pointer */ } CEC_InitTypeDef; @@ -121,14 +120,14 @@ typedef struct * b6 Error information * 0 : No Error * 1 : Error - * b5 IP initialization status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized. HAL CEC Init function already called) + * b5 CEC peripheral initialization status + * 0 : Reset (peripheral not initialized) + * 1 : Init done (peripheral initialized. HAL CEC Init function already called) * b4-b3 (not used) * xx : Should be set to 00 * b2 Intrinsic process state * 0 : Ready - * 1 : Busy (IP busy with some configuration or internal operations) + * 1 : Busy (peripheral busy with some configuration or internal operations) * b1 (not used) * x : Should be set to 0 * b0 Tx state @@ -138,9 +137,9 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initialization status - * 0 : Reset (IP not initialized) - * 1 : Init done (IP initialized) + * b5 CEC peripheral initialization status + * 0 : Reset (peripheral not initialized) + * 1 : Init done (peripheral initialized) * b4-b2 (not used) * xxx : Should be set to 000 * b1 Rx state @@ -164,7 +163,7 @@ typedef struct CEC_InitTypeDef Init; /*!< CEC communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ @@ -661,8 +660,8 @@ HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); */ /* I/O operation functions ***************************************************/ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress, - uint8_t *pData, uint32_t Size); -uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); + const uint8_t *pData, uint32_t Size); +uint32_t HAL_CEC_GetLastReceivedFrameSize(const CEC_HandleTypeDef *hcec); void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer); void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); @@ -676,8 +675,8 @@ void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); * @{ */ /* Peripheral State functions ************************************************/ -HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); -uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); +HAL_CEC_StateTypeDef HAL_CEC_GetState(const CEC_HandleTypeDef *hcec); +uint32_t HAL_CEC_GetError(const CEC_HandleTypeDef *hcec); /** * @} */ @@ -791,4 +790,3 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); #endif /* STM32F4xxHAL_CEC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cortex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cortex.c index 2efb98640c4..98515c5002f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cortex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cortex.c @@ -68,14 +68,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -502,4 +500,3 @@ __weak void HAL_SYSTICK_Callback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cortex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cortex.h index 95218cfbbc3..fdc96b529af 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cortex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -407,4 +405,3 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #endif /* __STM32F4xx_HAL_CORTEX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.c index 18fc4bd6bd6..2e86b2b6a29 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -29,17 +40,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -69,8 +69,8 @@ */ /** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. - * + * @brief Initialization and Configuration functions. + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -197,8 +197,8 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) */ /** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions - * @brief management functions. - * + * @brief management functions. + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -285,8 +285,8 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t */ /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions - * @brief Peripheral State functions. - * + * @brief Peripheral State functions. + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -326,5 +326,3 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.h index bbd58a581ae..41edbe381c3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_crc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -180,5 +179,3 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); #endif #endif /* STM32F4xx_HAL_CRC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c index 23fb46ed0a2..c439c2cf891 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.c @@ -11,6 +11,17 @@ * + CRYP IRQ handler management * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -148,10 +159,10 @@ The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() + Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() to register an interrupt callback. - Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: + Function HAL_CRYP_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. (+) OutCpltCallback : Output FIFO transfer completed callback. (+) ErrorCallback : callback for error detection. @@ -160,9 +171,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default + Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) InCpltCallback : Input FIFO transfer completed callback. @@ -171,13 +182,13 @@ (+) MspInitCallback : CRYP MspInit. (+) MspDeInitCallback : CRYP MspDeInit. - By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET + By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET all callbacks are set to the corresponding weak functions : - examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback(). + examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the @ref HAL_CRYP_Init()/ @ref HAL_CRYP_DeInit() only when + reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit() + if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit() keep and use the user MspInit/MspDeInit functions (registered beforehand) Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only. @@ -185,8 +196,8 @@ in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit() - or @ref HAL_CRYP_Init() function. + using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit() + or HAL_CRYP_Init() function. When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -241,17 +252,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2533,15 +2533,17 @@ static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); #else /* CRYP */ @@ -2780,7 +2782,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -2822,7 +2825,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); /* Turn back to ALGOMODE of the configuration */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); @@ -2867,15 +2871,17 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp) /* Enable CRYP */ __HAL_CRYP_ENABLE(hcryp); - /* Write the input block in the IN FIFO */ - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + /* Increment the pointer before writing the input block in the IN FIFO to make sure that + when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value + and it is ready for the next operation. */ hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; - hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); hcryp->CrypInCount++; + hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U)); #else /* CRYP */ @@ -2961,7 +2967,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF Flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -3005,7 +3012,8 @@ static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); /* Turn back to ALGOMODE of the configuration */ MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm); @@ -3943,7 +3951,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ @@ -3980,7 +3989,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4218,7 +4228,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ @@ -4255,7 +4266,8 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -4855,7 +4867,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); /* Select header phase */ CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); @@ -5016,7 +5029,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); + } + while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN); #else /* AES */ @@ -5062,7 +5076,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5107,7 +5122,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } @@ -5144,7 +5160,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } @@ -5178,7 +5195,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } @@ -5247,7 +5265,8 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -5545,16 +5564,16 @@ static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount); hcryp->CrypInCount++; if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U)) - { - /* Call Input transfer complete callback */ + { + /* Call Input transfer complete callback */ #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1) - /*Call registered Input complete callback*/ - hcryp->InCpltCallback(hcryp); + /*Call registered Input complete callback*/ + hcryp->InCpltCallback(hcryp); #else - /*Call legacy weak Input complete callback*/ - HAL_CRYP_InCpltCallback(hcryp); + /*Call legacy weak Input complete callback*/ + HAL_CRYP_InCpltCallback(hcryp); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ - } + } } else /* Last block of payload < 128bit*/ { @@ -5922,7 +5941,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry { headersize_in_bytes = hcryp->Init.HeaderSize; } - + if (headersize_in_bytes != 0U) { @@ -5966,7 +5985,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } } else @@ -6001,7 +6021,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Last block optionally pad the data with zeros*/ for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) @@ -6051,7 +6072,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM)); } /* Wait until the complete message has been processed */ count = CRYP_TIMEOUT_GCMCCMHEADERPHASE; @@ -6071,7 +6093,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); + } + while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY)); #else /* AES */ @@ -6119,7 +6142,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -6158,13 +6182,14 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); } /* Last block optionally pad the data with zeros*/ - for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes /4U) % 4U)); loopcounter++) + for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++) { hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount); hcryp->CrypHeaderCount++ ; @@ -6211,7 +6236,8 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry __HAL_UNLOCK(hcryp); return HAL_ERROR; } - } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); + } + while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)); /* Clear CCF flag */ __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR); @@ -6329,10 +6355,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) loopcounter++; hcryp->CrypHeaderCount++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DIN = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DIN = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } @@ -6463,10 +6489,10 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) loopcounter++; hcryp->CrypHeaderCount++; /* Pad the data with zeros to have a complete block */ - while (loopcounter < 4U) - { - hcryp->Instance->DINR = 0x0U; - loopcounter++; + while (loopcounter < 4U) + { + hcryp->Instance->DINR = 0x0U; + loopcounter++; hcryp->CrypHeaderCount++; } } @@ -7130,4 +7156,3 @@ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t T * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.h index 8596fe7d21e..960e1c794ce 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -682,4 +681,3 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); #endif /* __STM32F4xx_HAL_CRYP_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c index b3af317f02e..3a828473b55 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.c @@ -7,6 +7,17 @@ * functionalities of CRYP extension peripheral: * + Extended AES processing functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -20,17 +31,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -678,4 +678,3 @@ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.h index 251e94b1daa..dd12742e069 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_cryp_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -141,4 +140,3 @@ void HAL_CRYPEx_DisableAutoKeyDerivation(CRYP_HandleTypeDef *hcryp); #endif /* __STM32F4xx_HAL_CRYP_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.c index b4aa37d5aa4..9023e3e784d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.c @@ -11,6 +11,17 @@ * + Peripheral State and Errors functions * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### DAC Peripheral features ##### @@ -141,7 +152,7 @@ The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, + Use Functions HAL_DAC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -156,7 +167,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default + Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. @@ -171,12 +182,12 @@ (+) All Callbacks This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET + By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init - and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit + reset to the legacy weak (surcharged) functions in the HAL_DAC_Init + and HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -184,8 +195,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit - or @ref HAL_DAC_Init function. + using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit + or HAL_DAC_Init function. When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -205,17 +216,6 @@ (@) You can refer to the DAC HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -522,7 +522,7 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel) HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment) { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpreg = 0U; /* Check the parameters */ @@ -895,23 +895,23 @@ __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) */ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel) { - uint32_t tmp = 0U; + uint32_t result = 0; /* Check the parameters */ assert_param(IS_DAC_CHANNEL(Channel)); if (Channel == DAC_CHANNEL_1) { - tmp = hdac->Instance->DOR1; + result = hdac->Instance->DOR1; } #if defined(DAC_CHANNEL2_SUPPORT) else { - tmp = hdac->Instance->DOR2; + result = hdac->Instance->DOR2; } #endif /* DAC_CHANNEL2_SUPPORT */ /* Returns the DAC channel data output register value */ - return tmp; + return result; } /** @@ -1339,4 +1339,3 @@ void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.h index a1f49eae9e8..a79ca73a170 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -79,19 +78,19 @@ typedef struct __IO uint32_t ErrorCode; /*!< DAC Error code */ #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); #if defined(DAC_CHANNEL2_SUPPORT) - void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac); - void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac); + void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); + void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); #endif /* DAC_CHANNEL2_SUPPORT */ - void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac); - void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac); + void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); + void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ } DAC_HandleTypeDef; @@ -479,4 +478,3 @@ void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); #endif /* STM32F4xx_HAL_DAC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac_ex.c index 50ff2b85e27..343dd98682e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac_ex.c @@ -7,6 +7,17 @@ * functionalities of the DAC peripheral. * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -28,17 +39,6 @@ (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * ****************************************************************************** */ @@ -152,7 +152,6 @@ HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac) /* Return function status */ return HAL_OK; } - #endif /* DAC_CHANNEL2_SUPPORT */ /** @@ -494,4 +493,3 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac_ex.h index 03159d4fe5f..db109902975 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dac_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -204,4 +203,3 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); #endif /* STM32F4xx_HAL_DAC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.c index d3b10fc7ca2..d117c0e7405 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.c @@ -9,7 +9,17 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State and Error functions - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -62,9 +72,9 @@ The compilation define USE_HAL_DCMI_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use functions @ref HAL_DCMI_RegisterCallback() to register a user callback. + Use functions HAL_DCMI_RegisterCallback() to register a user callback. - Function @ref HAL_DCMI_RegisterCallback() allows to register following callbacks: + Function HAL_DCMI_RegisterCallback() allows to register following callbacks: (+) FrameEventCallback : DCMI Frame Event. (+) VsyncEventCallback : DCMI Vsync Event. (+) LineEventCallback : DCMI Line Event. @@ -74,9 +84,9 @@ This function takes as parameters the HAL peripheral handle, the callback ID and a pointer to the user callback function. - Use function @ref HAL_DCMI_UnRegisterCallback() to reset a callback to the default + Use function HAL_DCMI_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_DCMI_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the callback ID. This function allows to reset following callbacks: (+) FrameEventCallback : DCMI Frame Event. @@ -86,13 +96,13 @@ (+) MspInitCallback : DCMI MspInit. (+) MspDeInitCallback : DCMI MspDeInit. - By default, after the @ref HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET + By default, after the HAL_DCMI_Init and if the state is HAL_DCMI_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples @ref FrameEventCallback(), @ref HAL_DCMI_ErrorCallback(). + examples FrameEventCallback(), HAL_DCMI_ErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_DCMI_Init - and @ref HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_DCMI_Init and @ref HAL_DCMI_DeInit + reset to the legacy weak (surcharged) functions in the HAL_DCMI_Init + and HAL_DCMI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_DCMI_Init and HAL_DCMI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Callbacks can be registered/unregistered in READY state only. @@ -100,8 +110,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_DCMI_RegisterCallback before calling @ref HAL_DCMI_DeInit - or @ref HAL_DCMI_Init function. + using HAL_DCMI_RegisterCallback before calling HAL_DCMI_DeInit + or HAL_DCMI_Init function. When the compilation define USE_HAL_DCMI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -109,17 +119,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1160,5 +1159,3 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.h index 2a9edb6c47f..b7e82dc5e4e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -563,5 +561,3 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi); #endif #endif /* __STM32F4xx_HAL_DCMI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi_ex.c index b21454c90d9..bbc64c6aaba 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi_ex.c @@ -7,6 +7,16 @@ * functionalities of DCMI extension peripheral: * + Extension features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + ****************************************************************************** @verbatim ============================================================================== ##### DCMI peripheral extension features ##### @@ -23,17 +33,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -181,5 +180,3 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi_ex.h index 9bc942dea81..b4f181c9d7b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dcmi_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -208,5 +206,3 @@ typedef struct #endif #endif /* __STM32F4xx_HAL_DCMI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_def.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_def.h index 975f70bd4b2..1df0d7d0749 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_def.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_def.h @@ -7,13 +7,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -55,7 +54,9 @@ typedef enum /* Exported macro ------------------------------------------------------------*/ +#if !defined(UNUSED) #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ #define HAL_MAX_DELAY 0xFFFFFFFFU @@ -208,4 +209,4 @@ typedef enum #endif /* ___STM32F4xx_HAL_DEF */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dfsdm.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dfsdm.c index c57ebebf7ff..63126be3057 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dfsdm.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dfsdm.c @@ -2,7 +2,7 @@ ****************************************************************************** * @file stm32f4xx_hal_dfsdm.c * @author MCD Application Team - * @brief This file provides firmware functions to manage the following + * @brief This file provides firmware functions to manage the following * functionalities of the Digital Filter for Sigma-Delta Modulators * (DFSDM) peripherals: * + Initialization and configuration of channels and filters @@ -15,7 +15,18 @@ * + Extremes detector feature * + Clock absence detector feature * + Break generation on analog watchdog or short-circuit event - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -32,7 +43,7 @@ (++) If interrupt mode is used, enable and configure DFSDMz_FLT0 global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). (#) Configure the output clock, input, serial interface, analog watchdog, - offset and data right bit shift parameters for this channel using the + offset and data right bit shift parameters for this channel using the HAL_DFSDM_ChannelInit() function. *** Channel clock absence detector *** @@ -46,36 +57,36 @@ clock absence is detected. (#) Stop clock absence detector using HAL_DFSDM_ChannelCkabStop() or HAL_DFSDM_ChannelCkabStop_IT(). - (#) Please note that the same mode (polling or interrupt) has to be used + (#) Please note that the same mode (polling or interrupt) has to be used for all channels because the channels are sharing the same interrupt. (#) Please note also that in interrupt mode, if clock absence detector is stopped for one channel, interrupt will be disabled for all channels. *** Channel short circuit detector *** ====================================== - [..] + [..] (#) Start short circuit detector using HAL_DFSDM_ChannelScdStart() or or HAL_DFSDM_ChannelScdStart_IT(). (#) In polling mode, use HAL_DFSDM_ChannelPollForScd() to detect short circuit. - (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if + (#) In interrupt mode, HAL_DFSDM_ChannelScdCallback() will be called if short circuit is detected. (#) Stop short circuit detector using HAL_DFSDM_ChannelScdStop() or or HAL_DFSDM_ChannelScdStop_IT(). - (#) Please note that the same mode (polling or interrupt) has to be used + (#) Please note that the same mode (polling or interrupt) has to be used for all channels because the channels are sharing the same interrupt. (#) Please note also that in interrupt mode, if short circuit detector is stopped for one channel, interrupt will be disabled for all channels. *** Channel analog watchdog value *** ===================================== - [..] + [..] (#) Get analog watchdog filter value of a channel using HAL_DFSDM_ChannelGetAwdValue(). *** Channel offset value *** ===================================== - [..] + [..] (#) Modify offset value of a channel using HAL_DFSDM_ChannelModifyOffset(). *** Filter initialization *** @@ -94,21 +105,21 @@ *** Filter regular channel conversion *** ========================================= - [..] + [..] (#) Select regular channel and enable/disable continuous mode using HAL_DFSDM_FilterConfigRegChannel(). (#) Start regular conversion using HAL_DFSDM_FilterRegularStart(), HAL_DFSDM_FilterRegularStart_IT(), HAL_DFSDM_FilterRegularStart_DMA() or HAL_DFSDM_FilterRegularMsbStart_DMA(). - (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect + (#) In polling mode, use HAL_DFSDM_FilterPollForRegConversion() to detect the end of regular conversion. (#) In interrupt mode, HAL_DFSDM_FilterRegConvCpltCallback() will be called at the end of regular conversion. - (#) Get value of regular conversion and corresponding channel using + (#) Get value of regular conversion and corresponding channel using HAL_DFSDM_FilterGetRegularValue(). - (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and + (#) In DMA mode, HAL_DFSDM_FilterRegConvHalfCpltCallback() and HAL_DFSDM_FilterRegConvCpltCallback() will be called respectively at the - half transfer and at the transfer complete. Please note that + half transfer and at the transfer complete. Please note that HAL_DFSDM_FilterRegConvHalfCpltCallback() will be called only in DMA circular mode. (#) Stop regular conversion using HAL_DFSDM_FilterRegularStop(), @@ -121,15 +132,15 @@ (#) Start injected conversion using HAL_DFSDM_FilterInjectedStart(), HAL_DFSDM_FilterInjectedStart_IT(), HAL_DFSDM_FilterInjectedStart_DMA() or HAL_DFSDM_FilterInjectedMsbStart_DMA(). - (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect + (#) In polling mode, use HAL_DFSDM_FilterPollForInjConversion() to detect the end of injected conversion. (#) In interrupt mode, HAL_DFSDM_FilterInjConvCpltCallback() will be called at the end of injected conversion. - (#) Get value of injected conversion and corresponding channel using + (#) Get value of injected conversion and corresponding channel using HAL_DFSDM_FilterGetInjectedValue(). - (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and + (#) In DMA mode, HAL_DFSDM_FilterInjConvHalfCpltCallback() and HAL_DFSDM_FilterInjConvCpltCallback() will be called respectively at the - half transfer and at the transfer complete. Please note that + half transfer and at the transfer complete. Please note that HAL_DFSDM_FilterInjConvCpltCallback() will be called only in DMA circular mode. (#) Stop injected conversion using HAL_DFSDM_FilterInjectedStop(), @@ -190,7 +201,7 @@ and a pointer to the user callback function. [..] - For specific DFSDM filter analog watchdog callback use dedicated register callback: + For specific DFSDM filter analog watchdog callback use dedicated register callback: HAL_DFSDM_Filter_RegisterAwdCallback(). [..] @@ -226,11 +237,11 @@ HAL_DFSDM_Filter_UnRegisterAwdCallback(). [..] - By default, after the call of init function and if the state is RESET - all callbacks are reset to the corresponding legacy weak functions: + By default, after the call of init function and if the state is RESET + all callbacks are reset to the corresponding legacy weak functions: examples HAL_DFSDM_ChannelScdCallback(), HAL_DFSDM_FilterErrorCallback(). Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak functions in the init and de-init only when these + reset to the legacy weak functions in the init and de-init only when these callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null, the init and de-init keep and use the user MspInit/MspDeInit callbacks (registered beforehand) @@ -240,28 +251,17 @@ Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the init/de-init. - In that case first register the MspInit/MspDeInit user callbacks using + In that case first register the MspInit/MspDeInit user callbacks using HAL_DFSDM_Channel_RegisterCallback() or HAL_DFSDM_Filter_RegisterCallback() before calling init or de-init function. [..] When The compilation define USE_HAL_DFSDM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available + not defined, the callback registering feature is not available and weak callbacks are used. @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -275,7 +275,7 @@ /** @defgroup DFSDM DFSDM * @brief DFSDM HAL driver module * @{ - */ + */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -296,7 +296,7 @@ /** * @} */ -/** @addtogroup DFSDM_Private_Macros +/** @addtogroup DFSDM_Private_Macros * @{ */ @@ -324,7 +324,7 @@ DFSDM_Channel_HandleTypeDef* a_dfsdm2ChannelHandle[DFSDM2_CHANNEL_NUMBER] = {NUL * @{ */ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels); -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance); +static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance); static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter); @@ -345,7 +345,7 @@ static void DFSDM_DMAError(DMA_HandleTypeDef *hdma); */ /** @defgroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions - * @brief Channel initialization and de-initialization functions + * @brief Channel initialization and de-initialization functions * @verbatim ============================================================================== @@ -371,7 +371,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan DFSDM_Channel_HandleTypeDef **channelHandleTable; DFSDM_Channel_TypeDef* channel0Instance; #endif /* defined(DFSDM2_Channel0) */ - + /* Check DFSDM Channel handle */ if(hdfsdm_channel == NULL) { @@ -390,7 +390,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan assert_param(IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(hdfsdm_channel->Init.Awd.Oversampling)); assert_param(IS_DFSDM_CHANNEL_OFFSET(hdfsdm_channel->Init.Offset)); assert_param(IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(hdfsdm_channel->Init.RightBitShift)); - + #if defined(DFSDM2_Channel0) /* Get channel counter, channel handle table and channel 0 instance */ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) @@ -405,13 +405,13 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan channelHandleTable = a_dfsdm2ChannelHandle; channel0Instance = DFSDM2_Channel0; } - + /* Check that channel has not been already initialized */ if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) { return HAL_ERROR; } - + #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) /* Reset callback pointers to the weak predefined callbacks */ hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback; @@ -427,10 +427,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /* Call MSP init function */ HAL_DFSDM_ChannelMspInit(hdfsdm_channel); #endif - + /* Update the channel counter */ (*channelCounterPtr)++; - + /* Configure output serial clock and enable global DFSDM interface only for first channel */ if(*channelCounterPtr == 1U) { @@ -438,59 +438,59 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /* Set the output serial clock source */ channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); channel0Instance->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; - + /* Reset clock divider */ channel0Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE) { assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); /* Set the output clock divider */ - channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) << + channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) << DFSDM_CHCFGR1_CKOUTDIV_Pos); } - + /* enable the DFSDM global interface */ channel0Instance->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; } - + /* Set channel input parameters */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | DFSDM_CHCFGR1_CHINSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | - hdfsdm_channel->Init.Input.DataPacking | + hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | + hdfsdm_channel->Init.Input.DataPacking | hdfsdm_channel->Init.Input.Pins); - + /* Set serial interface parameters */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | + hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | hdfsdm_channel->Init.SerialInterface.SpiClock); - + /* Set analog watchdog parameters */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); - hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | + hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos)); /* Set channel offset and right bit shift */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); - hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | + hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); /* Enable DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; - + /* Set DFSDM Channel to ready state */ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY; /* Store channel handle in DFSDM channel handle table */ channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel; - + #else /* Check that channel has not been already initialized */ if(a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] != NULL) { return HAL_ERROR; } - + #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) /* Reset callback pointers to the weak predefined callbacks */ hdfsdm_channel->CkabCallback = HAL_DFSDM_ChannelCkabCallback; @@ -506,10 +506,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /* Call MSP init function */ HAL_DFSDM_ChannelMspInit(hdfsdm_channel); #endif - + /* Update the channel counter */ v_dfsdm1ChannelCounter++; - + /* Configure output serial clock and enable global DFSDM interface only for first channel */ if(v_dfsdm1ChannelCounter == 1U) { @@ -517,53 +517,53 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan /* Set the output serial clock source */ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTSRC); DFSDM1_Channel0->CHCFGR1 |= hdfsdm_channel->Init.OutputClock.Selection; - + /* Reset clock divider */ DFSDM1_Channel0->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKOUTDIV); if(hdfsdm_channel->Init.OutputClock.Activation == ENABLE) { assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider)); /* Set the output clock divider */ - DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) << + DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) << DFSDM_CHCFGR1_CKOUTDIV_Pos); } - + /* enable the DFSDM global interface */ DFSDM1_Channel0->CHCFGR1 |= DFSDM_CHCFGR1_DFSDMEN; } - + /* Set channel input parameters */ - hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | + hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_DATPACK | DFSDM_CHCFGR1_DATMPX | DFSDM_CHCFGR1_CHINSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | - hdfsdm_channel->Init.Input.DataPacking | + hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.Input.Multiplexer | + hdfsdm_channel->Init.Input.DataPacking | hdfsdm_channel->Init.Input.Pins); - + /* Set serial interface parameters */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SITP | DFSDM_CHCFGR1_SPICKSEL); - hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | + hdfsdm_channel->Instance->CHCFGR1 |= (hdfsdm_channel->Init.SerialInterface.Type | hdfsdm_channel->Init.SerialInterface.SpiClock); - + /* Set analog watchdog parameters */ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR); - hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | + hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder | ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos)); /* Set channel offset and right bit shift */ hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS); - hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | + hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) | (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos)); /* Enable DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN; - + /* Set DFSDM Channel to ready state */ hdfsdm_channel->State = HAL_DFSDM_CHANNEL_STATE_READY; /* Store channel handle in DFSDM channel handle table */ a_dfsdm1ChannelHandle[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] = hdfsdm_channel; #endif /* DFSDM2_Channel0 */ - + return HAL_OK; } @@ -573,13 +573,13 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_chan * @retval HAL status. */ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) -{ +{ #if defined(DFSDM2_Channel0) __IO uint32_t* channelCounterPtr; DFSDM_Channel_HandleTypeDef **channelHandleTable; DFSDM_Channel_TypeDef* channel0Instance; #endif /* defined(DFSDM2_Channel0) */ - + /* Check DFSDM Channel handle */ if(hdfsdm_channel == NULL) { @@ -588,7 +588,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + #if defined(DFSDM2_Channel0) /* Get channel counter, channel handle table and channel 0 instance */ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) @@ -603,7 +603,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch channelHandleTable = a_dfsdm2ChannelHandle; channel0Instance = DFSDM2_Channel0; } - + /* Check that channel has not been already deinitialized */ if(channelHandleTable[DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance)] == NULL) { @@ -612,10 +612,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /* Disable the DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN); - + /* Update the channel counter */ (*channelCounterPtr)--; - + /* Disable global DFSDM at deinit of last channel */ if(*channelCounterPtr == 0U) { @@ -647,10 +647,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_ch /* Disable the DFSDM channel */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CHEN); - + /* Update the channel counter */ v_dfsdm1ChannelCounter--; - + /* Disable global DFSDM at deinit of last channel */ if(v_dfsdm1ChannelCounter == 0U) { @@ -868,7 +868,7 @@ HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeD * @note Same mode has to be used for all channels. * @note If clock is not available on this channel during 5 seconds, * clock absence detection will not be activated and function - * will return HAL_TIMEOUT error. + * will return HAL_TIMEOUT error. * @param hdfsdm_channel DFSDM channel handle. * @retval HAL status */ @@ -884,7 +884,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { @@ -902,7 +902,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm else { filter0Instance = DFSDM2_Filter0; - } + } /* Get channel number from channel instance */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); @@ -942,7 +942,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm break; } } -#endif /* DFSDM2_Channel0 */ +#endif /* DFSDM2_Channel0 */ if(status == HAL_OK) { @@ -960,7 +960,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; @@ -968,7 +968,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs #if defined(DFSDM2_Channel0) DFSDM_Filter_TypeDef* filter0Instance; #endif /* defined(DFSDM2_Channel0) */ - + /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); @@ -981,7 +981,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs else { #if defined(DFSDM2_Channel0) - + /* Get channel counter, channel handle table and channel 0 instance */ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) { @@ -994,7 +994,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs /* Get channel number from channel instance */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - + /* Get timeout */ tickstart = HAL_GetTick(); @@ -1011,13 +1011,13 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs } } } - + /* Clear clock absence detection flag */ - filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); -#else + filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); +#else /* Get channel number from channel instance */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - + /* Get timeout */ tickstart = HAL_GetTick(); @@ -1034,10 +1034,10 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfs } } } - + /* Clear clock absence detection flag */ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); -#endif /* defined(DFSDM2_Channel0) */ +#endif /* defined(DFSDM2_Channel0) */ /* Return function status */ return HAL_OK; } @@ -1058,7 +1058,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { @@ -1077,7 +1077,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ else { filter0Instance = DFSDM2_Filter0; - } + } /* Stop clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); @@ -1089,16 +1089,16 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_ #else /* Stop clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); - + /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); -#endif /* DFSDM2_Channel0 */ +#endif /* DFSDM2_Channel0 */ } /* Return function status */ return status; } - + /** * @brief This function allows to start clock absence detection in interrupt mode. * @note Same mode has to be used for all channels. @@ -1119,7 +1119,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { @@ -1168,7 +1168,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf /* Start clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; } -#else +#else /* Get channel number from channel instance */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); @@ -1198,14 +1198,14 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdf hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CKABEN; } -#endif /* defined(DFSDM2_Channel0) */ +#endif /* defined(DFSDM2_Channel0) */ } /* Return function status */ return status; } /** - * @brief Clock absence detection callback. + * @brief Clock absence detection callback. * @param hdfsdm_channel DFSDM channel handle. * @retval None */ @@ -1234,7 +1234,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { @@ -1253,7 +1253,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs else { filter0Instance = DFSDM2_Filter0; - } + } /* Stop clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); @@ -1263,12 +1263,12 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfs filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); /* Disable clock absence detection interrupt */ - filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); + filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE); #else /* Stop clock absence detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_CKABEN); - + /* Clear clock absence flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel)); @@ -1302,7 +1302,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); - + /* Check DFSDM channel state */ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { @@ -1315,7 +1315,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ Threshold); - + /* Start short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; } @@ -1329,7 +1329,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_ * @param Timeout Timeout value in milliseconds. * @retval HAL status */ -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout) { uint32_t tickstart; @@ -1337,7 +1337,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd #if defined(DFSDM2_Channel0) DFSDM_Filter_TypeDef* filter0Instance; #endif /* defined(DFSDM2_Channel0) */ - + /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); @@ -1379,7 +1379,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd } } } - + /* Clear short circuit detection flag */ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); @@ -1403,7 +1403,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsd /* Clear short circuit detection flag */ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); -#endif /* DFSDM2_Channel0 */ +#endif /* DFSDM2_Channel0 */ /* Return function status */ return HAL_OK; @@ -1421,11 +1421,11 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c uint32_t channel; #if defined(DFSDM2_Channel0) DFSDM_Filter_TypeDef* filter0Instance; -#endif /* defined(DFSDM2_Channel0) */ +#endif /* defined(DFSDM2_Channel0) */ /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { @@ -1439,7 +1439,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_c /* Clear short circuit detection flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); - + #if defined(DFSDM2_Channel0) /* Get channel counter, channel handle table and channel 0 instance */ if(IS_DFSDM1_CHANNEL_INSTANCE(hdfsdm_channel->Instance)) @@ -1477,13 +1477,13 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs HAL_StatusTypeDef status = HAL_OK; #if defined(DFSDM2_Channel0) DFSDM_Filter_TypeDef* filter0Instance; -#endif /* defined(DFSDM2_Channel0) */ - +#endif /* defined(DFSDM2_Channel0) */ + /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); assert_param(IS_DFSDM_CHANNEL_SCD_THRESHOLD(Threshold)); assert_param(IS_DFSDM_BREAK_SIGNALS(BreakSignal)); - + /* Check DFSDM channel state */ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { @@ -1513,7 +1513,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT); hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \ Threshold); - + /* Start short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_SCDEN; } @@ -1522,7 +1522,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs } /** - * @brief Short circuit detection callback. + * @brief Short circuit detection callback. * @param hdfsdm_channel DFSDM channel handle. * @retval None */ @@ -1551,7 +1551,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); - + /* Check DFSDM channel state */ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { @@ -1562,7 +1562,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd { /* Stop short circuit detection */ hdfsdm_channel->Instance->CHCFGR1 &= ~(DFSDM_CHCFGR1_SCDEN); - + /* Clear short circuit detection flag */ channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance); #if defined(DFSDM2_Channel0) @@ -1596,7 +1596,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsd * @param hdfsdm_channel DFSDM channel handle. * @retval Channel analog watchdog value. */ -int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { return (int16_t) hdfsdm_channel->Instance->CHWDATAR; } @@ -1616,7 +1616,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf /* Check parameters */ assert_param(IS_DFSDM_CHANNEL_ALL_INSTANCE(hdfsdm_channel->Instance)); assert_param(IS_DFSDM_CHANNEL_OFFSET(Offset)); - + /* Check DFSDM channel state */ if(hdfsdm_channel->State != HAL_DFSDM_CHANNEL_STATE_READY) { @@ -1655,7 +1655,7 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdf * @param hdfsdm_channel DFSDM channel handle. * @retval DFSDM channel state. */ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel) +HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel) { /* Return DFSDM channel handle state */ return hdfsdm_channel->State; @@ -1666,7 +1666,7 @@ HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTyp */ /** @defgroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions - * @brief Filter initialization and de-initialization functions + * @brief Filter initialization and de-initialization functions * @verbatim ============================================================================== @@ -1706,27 +1706,27 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter assert_param(IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(hdfsdm_filter->Init.FilterParam.IntOversampling)); /* Check parameters compatibility */ - if((hdfsdm_filter->Instance == DFSDM1_Filter0) && - ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || + if((hdfsdm_filter->Instance == DFSDM1_Filter0) && + ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) { return HAL_ERROR; } -#if defined (DFSDM2_Channel0) - if((hdfsdm_filter->Instance == DFSDM2_Filter0) && - ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || +#if defined (DFSDM2_Channel0) + if((hdfsdm_filter->Instance == DFSDM2_Filter0) && + ((hdfsdm_filter->Init.RegularParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER) || (hdfsdm_filter->Init.InjectedParam.Trigger == DFSDM_FILTER_SYNC_TRIGGER))) { return HAL_ERROR; - } + } #endif /* DFSDM2_Channel0 */ - + /* Initialize DFSDM filter variables with default values */ hdfsdm_filter->RegularContMode = DFSDM_CONTINUOUS_CONV_OFF; hdfsdm_filter->InjectedChannelsNbr = 1U; hdfsdm_filter->InjConvRemaining = 1U; hdfsdm_filter->ErrorCode = DFSDM_FILTER_ERROR_NONE; - + #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) /* Reset callback pointers to the weak predefined callbacks */ hdfsdm_filter->AwdCallback = HAL_DFSDM_FilterAwdCallback; @@ -1793,7 +1793,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter { hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_JDMAEN); } - + /* Set filter parameters */ hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR); hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder | @@ -1805,13 +1805,13 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter hdfsdm_filter->InjectedTrigger = hdfsdm_filter->Init.InjectedParam.Trigger; hdfsdm_filter->ExtTriggerEdge = hdfsdm_filter->Init.InjectedParam.ExtTriggerEdge; hdfsdm_filter->InjectedScanMode = hdfsdm_filter->Init.InjectedParam.ScanMode; - + /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; /* Set DFSDM filter to ready state */ hdfsdm_filter->State = HAL_DFSDM_FILTER_STATE_READY; - + return HAL_OK; } @@ -1830,10 +1830,10 @@ HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filt /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - + /* Disable the DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - + /* Call MSP deinit function */ #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) if(hdfsdm_filter->MspDeInitCallback == NULL) @@ -2147,14 +2147,14 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h uint32_t ContinuousMode) { HAL_StatusTypeDef status = HAL_OK; - + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(IS_DFSDM_REGULAR_CHANNEL(Channel)); assert_param(IS_DFSDM_CONTINUOUS_MODE(ContinuousMode)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) { /* Configure channel and continuous mode for regular conversion */ @@ -2170,7 +2170,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *h } /* Store continuous mode information */ hdfsdm_filter->RegularContMode = ContinuousMode; - } + } else { status = HAL_ERROR; @@ -2195,9 +2195,9 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); - + /* Check DFSDM filter state */ - if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && + if((hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_RESET) && (hdfsdm_filter->State != HAL_DFSDM_FILTER_STATE_ERROR)) { /* Configure channel for injected conversion */ @@ -2252,7 +2252,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to start regular conversion in polling mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -2304,7 +2304,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDe else { /* Get timeout */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); /* Wait end of regular conversion */ while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_REOCF) != DFSDM_FLTISR_REOCF) @@ -2376,7 +2376,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm /** * @brief This function allows to start regular conversion in interrupt mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -2394,7 +2394,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hd { /* Enable interrupts for regular conversions */ hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); - + /* Start regular conversion */ DFSDM_RegConvStart(hdfsdm_filter); } @@ -2430,7 +2430,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf { /* Disable interrupts for regular conversions */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_REOCIE | DFSDM_FLTCR2_ROVRIE); - + /* Stop regular conversion */ DFSDM_RegConvStop(hdfsdm_filter); } @@ -2440,7 +2440,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdf /** * @brief This function allows to start regular conversion in DMA mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * Please note that data on buffer will contain signed regular conversion * value on 24 most significant bits and corresponding channel on 3 least @@ -2492,7 +2492,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ DFSDM_DMARegularHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)&hdfsdm_filter->Instance->FLTRDATAR, \ (uint32_t) pData, Length) != HAL_OK) @@ -2518,7 +2518,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *h /** * @brief This function allows to start regular conversion in DMA mode and to get * only the 16 most significant bits of conversion. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if injected conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of regular conversion. @@ -2569,7 +2569,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef hdfsdm_filter->hdmaReg->XferErrorCallback = DFSDM_DMAError; hdfsdm_filter->hdmaReg->XferHalfCpltCallback = (hdfsdm_filter->hdmaReg->Init.Mode == DMA_CIRCULAR) ?\ DFSDM_DMARegularHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaReg, (uint32_t)(&hdfsdm_filter->Instance->FLTRDATAR) + 2U, \ (uint32_t) pData, Length) != HAL_OK) @@ -2637,19 +2637,19 @@ HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hd * @param Channel Corresponding channel of regular conversion. * @retval Regular conversion value */ -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; int32_t value = 0; - + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(Channel != NULL); /* Get value of data register for regular channel */ reg = hdfsdm_filter->Instance->FLTRDATAR; - + /* Extract channel and regular conversion value */ *Channel = (reg & DFSDM_FLTRDATAR_RDATACH); value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos); @@ -2660,7 +2660,7 @@ int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filte /** * @brief This function allows to start injected conversion in polling mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -2712,7 +2712,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe else { /* Get timeout */ - tickstart = HAL_GetTick(); + tickstart = HAL_GetTick(); /* Wait end of injected conversions */ while((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_JEOCF) != DFSDM_FLTISR_JEOCF) @@ -2752,7 +2752,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDe hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) ? \ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_REG; } - + /* end of injected sequence, reset the value */ hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ hdfsdm_filter->InjectedChannelsNbr : 1U; @@ -2794,7 +2794,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd /** * @brief This function allows to start injected conversion in interrupt mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * @param hdfsdm_filter DFSDM filter handle. * @retval HAL status @@ -2812,7 +2812,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *h { /* Enable interrupts for injected conversions */ hdfsdm_filter->Instance->FLTCR2 |= (DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); - + /* Start injected conversion */ DFSDM_InjConvStart(hdfsdm_filter); } @@ -2848,7 +2848,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd { /* Disable interrupts for injected conversions */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_JEOCIE | DFSDM_FLTCR2_JOVRIE); - + /* Stop injected conversion */ DFSDM_InjConvStop(hdfsdm_filter); } @@ -2858,7 +2858,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hd /** * @brief This function allows to start injected conversion in DMA mode. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * Please note that data on buffer will contain signed injected conversion * value on 24 most significant bits and corresponding channel on 3 least @@ -2908,7 +2908,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef * hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ DFSDM_DMAInjectedHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)&hdfsdm_filter->Instance->FLTJDATAR, \ (uint32_t) pData, Length) != HAL_OK) @@ -2934,7 +2934,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef * /** * @brief This function allows to start injected conversion in DMA mode and to get * only the 16 most significant bits of conversion. - * @note This function should be called only when DFSDM filter instance is + * @note This function should be called only when DFSDM filter instance is * in idle state or if regular conversion is ongoing. * Please note that data on buffer will contain signed 16 most significant * bits of injected conversion. @@ -2983,7 +2983,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDe hdfsdm_filter->hdmaInj->XferErrorCallback = DFSDM_DMAError; hdfsdm_filter->hdmaInj->XferHalfCpltCallback = (hdfsdm_filter->hdmaInj->Init.Mode == DMA_CIRCULAR) ?\ DFSDM_DMAInjectedHalfConvCplt : NULL; - + /* Start DMA in interrupt mode */ if(HAL_DMA_Start_IT(hdfsdm_filter->hdmaInj, (uint32_t)(&hdfsdm_filter->Instance->FLTJDATAR) + 2U, \ (uint32_t) pData, Length) != HAL_OK) @@ -3051,19 +3051,19 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *h * @param Channel Corresponding channel of injected conversion. * @retval Injected conversion value */ -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; int32_t value = 0; - + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(Channel != NULL); /* Get value of data register for injected channel */ reg = hdfsdm_filter->Instance->FLTJDATAR; - + /* Extract channel and injected conversion value */ *Channel = (reg & DFSDM_FLTJDATAR_JDATACH); value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos); @@ -3079,7 +3079,7 @@ int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filt * @retval HAL status */ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef *awdParam) + const DFSDM_Filter_AwdParamTypeDef *awdParam) { HAL_StatusTypeDef status = HAL_OK; @@ -3091,7 +3091,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfs assert_param(IS_DFSDM_FILTER_AWD_THRESHOLD(awdParam->LowThreshold)); assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->HighBreakSignal)); assert_param(IS_DFSDM_BREAK_SIGNALS(awdParam->LowBreakSignal)); - + /* Check DFSDM filter state */ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) @@ -3133,7 +3133,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_ /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - + /* Check DFSDM filter state */ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) @@ -3148,7 +3148,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_ /* Clear all analog watchdog flags */ hdfsdm_filter->Instance->FLTAWCFR = (DFSDM_FLTAWCFR_CLRAWHTF | DFSDM_FLTAWCFR_CLRAWLTF); - + /* Reset thresholds and break signals */ hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH); hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL); @@ -3175,7 +3175,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(IS_DFSDM_INJECTED_CHANNEL(Channel)); - + /* Check DFSDM filter state */ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) @@ -3187,7 +3187,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_fi { /* Set channels for extreme detector */ hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH); - hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); + hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos); } /* Return function status */ return status; @@ -3206,7 +3206,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); - + /* Check DFSDM filter state */ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_RESET) || \ (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_ERROR)) @@ -3221,7 +3221,7 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil /* Clear extreme detector values */ reg1 = hdfsdm_filter->Instance->FLTEXMAX; - reg2 = hdfsdm_filter->Instance->FLTEXMIN; + reg2 = hdfsdm_filter->Instance->FLTEXMIN; UNUSED(reg1); /* To avoid GCC warning */ UNUSED(reg2); /* To avoid GCC warning */ } @@ -3236,19 +3236,19 @@ HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_fil * @retval Extreme detector maximum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; int32_t value = 0; - + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(Channel != NULL); /* Get value of extreme detector maximum register */ reg = hdfsdm_filter->Instance->FLTEXMAX; - + /* Extract channel and extreme detector maximum value */ *Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH); value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos); @@ -3264,19 +3264,19 @@ int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter * @retval Extreme detector minimum value * This value is between Min_Data = -8388608 and Max_Data = 8388607. */ -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, +int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel) { uint32_t reg = 0U; int32_t value = 0; - + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); assert_param(Channel != NULL); /* Get value of extreme detector minimum register */ reg = hdfsdm_filter->Instance->FLTEXMIN; - + /* Extract channel and extreme detector minimum value */ *Channel = (reg & DFSDM_FLTEXMIN_EXMINCH); value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos); @@ -3291,17 +3291,17 @@ int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter * @retval Conversion time value * @note To get time in second, this value has to be divided by DFSDM clock frequency. */ -uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { uint32_t reg = 0U; uint32_t value = 0U; - + /* Check parameters */ assert_param(IS_DFSDM_FILTER_ALL_INSTANCE(hdfsdm_filter->Instance)); /* Get value of conversion timer register */ reg = hdfsdm_filter->Instance->FLTCNVTIMR; - + /* Extract conversion time value */ value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos); @@ -3410,7 +3410,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) uint32_t reg = 0U; uint32_t threshold = 0U; uint32_t channel = 0U; - + /* Get channel and threshold */ reg = hdfsdm_filter->Instance->FLTAWSR; threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD; @@ -3442,7 +3442,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { uint32_t reg = 0U; uint32_t channel = 0U; - + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); while(channel < DFSDM1_CHANNEL_NUMBER) @@ -3468,7 +3468,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) reg = reg >> 1U; } } -#if defined (DFSDM2_Channel0) +#if defined (DFSDM2_Channel0) /* Check if clock absence occurs */ else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) != 0U) && \ @@ -3476,7 +3476,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { uint32_t reg = 0U; uint32_t channel = 0U; - + reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos); while(channel < DFSDM2_CHANNEL_NUMBER) @@ -3502,7 +3502,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) reg = reg >> 1U; } } -#endif /* DFSDM2_Channel0 */ +#endif /* DFSDM2_Channel0 */ /* Check if short circuit detection occurs */ else if((hdfsdm_filter->Instance == DFSDM1_Filter0) && \ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \ @@ -3510,7 +3510,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { uint32_t reg = 0U; uint32_t channel = 0U; - + /* Get channel */ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); while((reg & 1U) == 0U) @@ -3518,7 +3518,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) channel++; reg = reg >> 1U; } - + /* Clear short circuit detection flag */ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); @@ -3529,7 +3529,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]); #endif } -#if defined (DFSDM2_Channel0) +#if defined (DFSDM2_Channel0) /* Check if short circuit detection occurs */ else if((hdfsdm_filter->Instance == DFSDM2_Filter0) && \ ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) != 0U) && \ @@ -3537,7 +3537,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { uint32_t reg = 0U; uint32_t channel = 0U; - + /* Get channel */ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos); while((reg & 1U) == 0U) @@ -3545,7 +3545,7 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) channel++; reg = reg >> 1U; } - + /* Clear short circuit detection flag */ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_Pos + channel)); @@ -3556,11 +3556,11 @@ void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) HAL_DFSDM_ChannelScdCallback(a_dfsdm2ChannelHandle[channel]); #endif } -#endif /* DFSDM2_Channel0 */ +#endif /* DFSDM2_Channel0 */ } /** - * @brief Regular conversion complete callback. + * @brief Regular conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetRegularValue. * @param hdfsdm_filter DFSDM filter handle. @@ -3576,7 +3576,7 @@ __weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs } /** - * @brief Half regular conversion complete callback. + * @brief Half regular conversion complete callback. * @param hdfsdm_filter DFSDM filter handle. * @retval None */ @@ -3590,7 +3590,7 @@ __weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * } /** - * @brief Injected conversion complete callback. + * @brief Injected conversion complete callback. * @note In interrupt mode, user has to read conversion value in this function * using HAL_DFSDM_FilterGetInjectedValue. * @param hdfsdm_filter DFSDM filter handle. @@ -3606,7 +3606,7 @@ __weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfs } /** - * @brief Half injected conversion complete callback. + * @brief Half injected conversion complete callback. * @param hdfsdm_filter DFSDM filter handle. * @retval None */ @@ -3620,7 +3620,7 @@ __weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef * } /** - * @brief Filter analog watchdog callback. + * @brief Filter analog watchdog callback. * @param hdfsdm_filter DFSDM filter handle. * @param Channel Corresponding channel. * @param Threshold Low or high threshold has been reached. @@ -3633,14 +3633,14 @@ __weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filte UNUSED(hdfsdm_filter); UNUSED(Channel); UNUSED(Threshold); - + /* NOTE : This function should not be modified, when the callback is needed, the HAL_DFSDM_FilterAwdCallback could be implemented in the user file. */ } /** - * @brief Error callback. + * @brief Error callback. * @param hdfsdm_filter DFSDM filter handle. * @retval None */ @@ -3676,7 +3676,7 @@ __weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_fil * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter state. */ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { /* Return DFSDM filter handle state */ return hdfsdm_filter->State; @@ -3687,7 +3687,7 @@ HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDe * @param hdfsdm_filter DFSDM filter handle. * @retval DFSDM filter error code. */ -uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) +uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter) { return hdfsdm_filter->ErrorCode; } @@ -3711,13 +3711,13 @@ uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter) #if defined(SYSCFG_MCHDLYCR_BSCKSEL) /** * @brief Select the DFSDM2 as clock source for the bitstream clock. - * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called - * before HAL_DFSDM_BitstreamClock_Start() + * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called + * before HAL_DFSDM_BitstreamClock_Start() */ void HAL_DFSDM_BitstreamClock_Start(void) { - uint32_t tmp = 0; - + uint32_t tmp = 0; + tmp = SYSCFG->MCHDLYCR; tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL)); @@ -3726,14 +3726,14 @@ void HAL_DFSDM_BitstreamClock_Start(void) /** * @brief Stop the DFSDM2 as clock source for the bitstream clock. - * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called - * before HAL_DFSDM_BitstreamClock_Stop() + * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called + * before HAL_DFSDM_BitstreamClock_Stop() * @retval None */ void HAL_DFSDM_BitstreamClock_Stop(void) { - uint32_t tmp = 0U; - + uint32_t tmp = 0U; + tmp = SYSCFG->MCHDLYCR; tmp = (tmp &(~SYSCFG_MCHDLYCR_BSCKSEL)); @@ -3744,16 +3744,16 @@ void HAL_DFSDM_BitstreamClock_Stop(void) * @brief Disable Delay Clock for DFSDM1/2. * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2. * HAL_MCHDLY_CLOCK_DFSDM1. - * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called - * before HAL_DFSDM_DisableDelayClock() + * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called + * before HAL_DFSDM_DisableDelayClock() * @retval None */ void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY) { - uint32_t tmp = 0U; - + uint32_t tmp = 0U; + assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY)); - + tmp = SYSCFG->MCHDLYCR; if(MCHDLY == HAL_MCHDLY_CLOCK_DFSDM2) { @@ -3771,13 +3771,13 @@ void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY) * @brief Enable Delay Clock for DFSDM1/2. * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2. * HAL_MCHDLY_CLOCK_DFSDM1. - * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called - * before HAL_DFSDM_EnableDelayClock() + * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called + * before HAL_DFSDM_EnableDelayClock() * @retval None */ void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY) { - uint32_t tmp = 0U; + uint32_t tmp = 0U; assert_param(IS_DFSDM_DELAY_CLOCK(MCHDLY)); @@ -3797,17 +3797,17 @@ void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY) */ void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source) { - uint32_t tmp = 0U; - + uint32_t tmp = 0U; + assert_param(IS_DFSDM_CLOCKIN_SELECTION(source)); tmp = SYSCFG->MCHDLYCR; - + if((source == HAL_DFSDM2_CKIN_PAD) || (source == HAL_DFSDM2_CKIN_DM)) { tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CFG); - - if(source == HAL_DFSDM2_CKIN_PAD) + + if(source == HAL_DFSDM2_CKIN_PAD) { source = 0x000000U; } @@ -3823,23 +3823,23 @@ void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source) /** * @brief Select the source for CKOut signals for DFSDM1/2. * @param source: DFSDM2_CKOUT_DFSDM2. - * DFSDM2_CKOUT_M27. + * DFSDM2_CKOUT_M27. * DFSDM1_CKOUT_DFSDM1. * DFSDM1_CKOUT_M27. * @retval None */ void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source) { - uint32_t tmp = 0U; - + uint32_t tmp = 0U; + assert_param(IS_DFSDM_CLOCKOUT_SELECTION(source)); - + tmp = SYSCFG->MCHDLYCR; if((source == HAL_DFSDM2_CKOUT_DFSDM2) || (source == HAL_DFSDM2_CKOUT_M27)) { tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CKOSEL); - + if(source == HAL_DFSDM2_CKOUT_DFSDM2) { source = 0x000U; @@ -3856,19 +3856,19 @@ void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source) /** * @brief Select the source for DataIn0 signals for DFSDM1/2. * @param source DATAIN0_DFSDM2_PAD. - * DATAIN0_DFSDM2_DATAIN1. + * DATAIN0_DFSDM2_DATAIN1. * DATAIN0_DFSDM1_PAD. - * DATAIN0_DFSDM1_DATAIN1. + * DATAIN0_DFSDM1_DATAIN1. * @retval None */ void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source) { - uint32_t tmp = 0U; + uint32_t tmp = 0U; assert_param(IS_DFSDM_DATAIN0_SRC_SELECTION(source)); tmp = SYSCFG->MCHDLYCR; - + if((source == HAL_DATAIN0_DFSDM2_PAD)|| (source == HAL_DATAIN0_DFSDM2_DATAIN1)) { tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D0SEL); @@ -3887,26 +3887,26 @@ void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source) /** * @brief Select the source for DataIn2 signals for DFSDM1/2. * @param source DATAIN2_DFSDM2_PAD. - * DATAIN2_DFSDM2_DATAIN3. + * DATAIN2_DFSDM2_DATAIN3. * DATAIN2_DFSDM1_PAD. * DATAIN2_DFSDM1_DATAIN3. * @retval None */ void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source) { - uint32_t tmp = 0U; + uint32_t tmp = 0U; assert_param(IS_DFSDM_DATAIN2_SRC_SELECTION(source)); tmp = SYSCFG->MCHDLYCR; - + if((source == HAL_DATAIN2_DFSDM2_PAD)|| (source == HAL_DATAIN2_DFSDM2_DATAIN3)) { tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D2SEL); if (source == HAL_DATAIN2_DFSDM2_PAD) { source = 0x0000U; - } + } } else { @@ -3923,7 +3923,7 @@ void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source) */ void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source) { - uint32_t tmp = 0U; + uint32_t tmp = 0U; assert_param(IS_DFSDM_DATAIN4_SRC_SELECTION(source)); @@ -3941,20 +3941,20 @@ void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source) */ void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source) { - uint32_t tmp = 0U; + uint32_t tmp = 0U; assert_param(IS_DFSDM_DATAIN6_SRC_SELECTION(source)); tmp = SYSCFG->MCHDLYCR; - + tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2D6SEL); SYSCFG->MCHDLYCR = (source|tmp); } /** - * @brief Configure the distribution of the bitstream clock gated from TIM4_OC - * for DFSDM1 or TIM3_OC for DFSDM2 + * @brief Configure the distribution of the bitstream clock gated from TIM4_OC + * for DFSDM1 or TIM3_OC for DFSDM2 * @param source DFSDM1_CLKIN0_TIM4OC2 * DFSDM1_CLKIN2_TIM4OC2 * DFSDM1_CLKIN1_TIM4OC1 @@ -3971,7 +3971,7 @@ void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source) */ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source) { - uint32_t tmp = 0U; + uint32_t tmp = 0U; assert_param(IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(source)); @@ -3992,7 +3992,7 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source) else if ((source == HAL_DFSDM2_CLKIN1_TIM3OC3) || (source == HAL_DFSDM2_CLKIN5_TIM3OC3)) { tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK15SEL); - + }else if ((source == HAL_DFSDM2_CLKIN2_TIM3OC2) || (source == HAL_DFSDM2_CLKIN6_TIM3OC2)) { tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK26SEL); @@ -4001,36 +4001,36 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source) { tmp = (tmp & ~SYSCFG_MCHDLYCR_DFSDM2CK37SEL); } - + if((source == HAL_DFSDM1_CLKIN0_TIM4OC2) ||(source == HAL_DFSDM1_CLKIN1_TIM4OC1)|| (source == HAL_DFSDM2_CLKIN0_TIM3OC4) ||(source == HAL_DFSDM2_CLKIN1_TIM3OC3)|| (source == HAL_DFSDM2_CLKIN2_TIM3OC2) ||(source == HAL_DFSDM2_CLKIN3_TIM3OC1)) { source = 0x0000U; } - + SYSCFG->MCHDLYCR = (source|tmp); } /** - * @brief Configure multi channel delay block: Use DFSDM2 audio clock source as input + * @brief Configure multi channel delay block: Use DFSDM2 audio clock source as input * clock for DFSDM1 and DFSDM2 filters to Synchronize DFSDMx filters. * Set the path of the DFSDM2 clock output (dfsdm2_ckout) to the * DFSDM1/2 CkInx and data inputs channels by configuring following MCHDLY muxes * or demuxes: M1, M2, M3, M4, M5, M6, M7, M8, DM1, DM2, DM3, DM4, DM5, DM6, * M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 based on the - * contains of the DFSDM_MultiChannelConfigTypeDef structure + * contains of the DFSDM_MultiChannelConfigTypeDef structure * @param mchdlystruct Structure of multi channel configuration * @retval None - * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called + * @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called * before HAL_DFSDM_ConfigMultiChannelDelay() * @note The HAL_DFSDM_ConfigMultiChannelDelay() function clears the SYSCFG-MCHDLYCR - * register before setting the new configuration. + * register before setting the new configuration. */ void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct) -{ - uint32_t mchdlyreg = 0U; - +{ + uint32_t mchdlyreg = 0U; + assert_param(IS_DFSDM_DFSDM1_CLKOUT(mchdlystruct->DFSDM1ClockOut)); assert_param(IS_DFSDM_DFSDM2_CLKOUT(mchdlystruct->DFSDM2ClockOut)); assert_param(IS_DFSDM_DFSDM1_CLKIN(mchdlystruct->DFSDM1ClockIn)); @@ -4039,7 +4039,7 @@ void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlyst assert_param(IS_DFSDM_DFSDM2_BIT_CLK(mchdlystruct->DFSDM2BitClkDistribution)); assert_param(IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(mchdlystruct->DFSDM1DataDistribution)); assert_param(IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(mchdlystruct->DFSDM2DataDistribution)); - + mchdlyreg = (SYSCFG->MCHDLYCR & 0x80103U); SYSCFG->MCHDLYCR = (mchdlyreg |(mchdlystruct->DFSDM1ClockOut)|(mchdlystruct->DFSDM2ClockOut)| @@ -4063,11 +4063,11 @@ void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlyst */ /** - * @brief DMA half transfer complete callback for regular conversion. + * @brief DMA half transfer complete callback for regular conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; @@ -4081,11 +4081,11 @@ static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA transfer complete callback for regular conversion. + * @brief DMA transfer complete callback for regular conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; @@ -4099,11 +4099,11 @@ static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA half transfer complete callback for injected conversion. + * @brief DMA half transfer complete callback for injected conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; @@ -4117,11 +4117,11 @@ static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA transfer complete callback for injected conversion. + * @brief DMA transfer complete callback for injected conversion. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) +static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; @@ -4135,11 +4135,11 @@ static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma) } /** - * @brief DMA error callback. + * @brief DMA error callback. * @param hdma DMA handle. * @retval None */ -static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) +static void DFSDM_DMAError(DMA_HandleTypeDef *hdma) { /* Get DFSDM filter handle */ DFSDM_Filter_HandleTypeDef* hdfsdm_filter = (DFSDM_Filter_HandleTypeDef*) ((DMA_HandleTypeDef*)hdma)->Parent; @@ -4164,7 +4164,7 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) { uint32_t nbChannels = 0U; uint32_t tmp; - + /* Get the number of channels from bitfield */ tmp = (uint32_t) (Channels & DFSDM_LSB_MASK); while(tmp != 0U) @@ -4183,10 +4183,10 @@ static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels) * @param Instance DFSDM channel instance. * @retval Channel number. */ -static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance) +static uint32_t DFSDM_GetChannelFromInstance(const DFSDM_Channel_TypeDef *Instance) { uint32_t channel; - + /* Get channel from instance */ #if defined(DFSDM2_Channel0) if((Instance == DFSDM1_Channel0) || (Instance == DFSDM2_Channel0)) @@ -4261,13 +4261,13 @@ static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { /* Disable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - + /* Set RSYNC bit in DFSDM_FLTCR1 register */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_RSYNC; /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - + /* If injected conversion was in progress, restart it */ if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_INJ) { @@ -4303,7 +4303,7 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - + /* If injected conversion was in progress, restart it */ if(hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) { @@ -4315,7 +4315,7 @@ static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) hdfsdm_filter->InjConvRemaining = (hdfsdm_filter->InjectedScanMode == ENABLE) ? \ hdfsdm_filter->InjectedChannelsNbr : 1U; } - + /* Update DFSDM filter state */ hdfsdm_filter->State = (hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG) ? \ HAL_DFSDM_FILTER_STATE_READY : HAL_DFSDM_FILTER_STATE_INJ; @@ -4338,7 +4338,7 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) { /* Disable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 &= ~(DFSDM_FLTCR1_DFEN); - + if(hdfsdm_filter->InjectedTrigger == DFSDM_FILTER_SYNC_TRIGGER) { /* Set JSYNC bit in DFSDM_FLTCR1 register */ @@ -4349,7 +4349,7 @@ static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /* Set JEXTEN[1:0] bits in DFSDM_FLTCR1 register */ hdfsdm_filter->Instance->FLTCR1 |= hdfsdm_filter->ExtTriggerEdge; } - + /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; @@ -4392,7 +4392,7 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) } /* Enable DFSDM filter */ hdfsdm_filter->Instance->FLTCR1 |= DFSDM_FLTCR1_DFEN; - + /* If regular conversion was in progress, restart it */ if((hdfsdm_filter->State == HAL_DFSDM_FILTER_STATE_REG_INJ) && \ (hdfsdm_filter->RegularTrigger == DFSDM_FILTER_SW_TRIGGER)) @@ -4421,5 +4421,3 @@ static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dfsdm.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dfsdm.h index 09c6551e603..2b0f1937d09 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dfsdm.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dfsdm.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -35,16 +34,16 @@ /** @addtogroup DFSDM * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /** @defgroup DFSDM_Exported_Types DFSDM Exported Types * @{ */ -/** - * @brief HAL DFSDM Channel states definition - */ +/** + * @brief HAL DFSDM Channel states definition + */ typedef enum { HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ @@ -52,21 +51,21 @@ typedef enum HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ }HAL_DFSDM_Channel_StateTypeDef; -/** - * @brief DFSDM channel output clock structure definition - */ +/** + * @brief DFSDM channel output clock structure definition + */ typedef struct { FunctionalState Activation; /*!< Output clock enable/disable */ uint32_t Selection; /*!< Output clock is system clock or audio clock. - This parameter can be a value of @ref DFSDM_Channel_OuputClock */ + This parameter can be a value of @ref DFSDM_Channel_OutputClock */ uint32_t Divider; /*!< Output clock divider. This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ }DFSDM_Channel_OutputClockTypeDef; -/** - * @brief DFSDM channel input structure definition - */ +/** + * @brief DFSDM channel input structure definition + */ typedef struct { uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. @@ -77,9 +76,9 @@ typedef struct This parameter can be a value of @ref DFSDM_Channel_InputPins */ }DFSDM_Channel_InputTypeDef; -/** - * @brief DFSDM channel serial interface structure definition - */ +/** + * @brief DFSDM channel serial interface structure definition + */ typedef struct { uint32_t Type; /*!< SPI or Manchester modes. @@ -88,9 +87,9 @@ typedef struct This parameter can be a value of @ref DFSDM_Channel_SpiClock */ }DFSDM_Channel_SerialInterfaceTypeDef; -/** - * @brief DFSDM channel analog watchdog structure definition - */ +/** + * @brief DFSDM channel analog watchdog structure definition + */ typedef struct { uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. @@ -99,9 +98,9 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ }DFSDM_Channel_AwdTypeDef; -/** - * @brief DFSDM channel init structure definition - */ +/** + * @brief DFSDM channel init structure definition + */ typedef struct { DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ @@ -114,14 +113,14 @@ typedef struct This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ }DFSDM_Channel_InitTypeDef; -/** - * @brief DFSDM channel handle structure definition - */ +/** + * @brief DFSDM channel handle structure definition + */ #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) typedef struct __DFSDM_Channel_HandleTypeDef #else typedef struct -#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ +#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ { DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ @@ -151,9 +150,9 @@ typedef enum */ typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); #endif -/** - * @brief HAL DFSDM Filter states definition - */ +/** + * @brief HAL DFSDM Filter states definition + */ typedef enum { HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ @@ -164,9 +163,9 @@ typedef enum HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ }HAL_DFSDM_Filter_StateTypeDef; -/** - * @brief DFSDM filter regular conversion parameters structure definition - */ +/** + * @brief DFSDM filter regular conversion parameters structure definition + */ typedef struct { uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. @@ -175,9 +174,9 @@ typedef struct FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ }DFSDM_Filter_RegularParamTypeDef; -/** - * @brief DFSDM filter injected conversion parameters structure definition - */ +/** + * @brief DFSDM filter injected conversion parameters structure definition + */ typedef struct { uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. @@ -190,9 +189,9 @@ typedef struct This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ }DFSDM_Filter_InjectedParamTypeDef; -/** - * @brief DFSDM filter parameters structure definition - */ +/** + * @brief DFSDM filter parameters structure definition + */ typedef struct { uint32_t SincOrder; /*!< Sinc filter order. @@ -203,9 +202,9 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ }DFSDM_Filter_FilterParamTypeDef; -/** - * @brief DFSDM filter init structure definition - */ +/** + * @brief DFSDM filter init structure definition + */ typedef struct { DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ @@ -213,9 +212,9 @@ typedef struct DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ }DFSDM_Filter_InitTypeDef; -/** - * @brief DFSDM filter handle structure definition - */ +/** + * @brief DFSDM filter handle structure definition + */ #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) typedef struct __DFSDM_Filter_HandleTypeDef #else @@ -234,7 +233,7 @@ typedef struct uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ uint32_t InjConvRemaining; /*!< Injected conversions remaining */ HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ - uint32_t ErrorCode; /*!< DFSDM filter error code */ + uint32_t ErrorCode; /*!< DFSDM filter error code */ #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ @@ -248,9 +247,9 @@ typedef struct #endif }DFSDM_Filter_HandleTypeDef; -/** - * @brief DFSDM filter analog watchdog parameters structure definition - */ +/** + * @brief DFSDM filter analog watchdog parameters structure definition + */ typedef struct { uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. @@ -291,11 +290,11 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf /** * @} - */ -#if defined(SYSCFG_MCHDLYCR_BSCKSEL) -/** - * @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices - */ + */ +#if defined(SYSCFG_MCHDLYCR_BSCKSEL) +/** + * @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices + */ typedef struct { uint32_t DFSDM1ClockIn; /*!< Source selection for DFSDM1_Ckin. @@ -307,15 +306,15 @@ typedef struct uint32_t DFSDM2ClockOut; /*!< Source selection for DFSDM2_Ckout. This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/ uint32_t DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2. - This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION - @note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2 + This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION + @note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2 @note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */ uint32_t DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4. - This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION - @note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4 - @note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5 - @note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6 - @note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */ + This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION + @note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4 + @note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5 + @note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6 + @note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */ uint32_t DFSDM1DataDistribution; /*!< Source selection for DatIn0 and DatIn2 of DFSDM1. This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */ uint32_t DFSDM2DataDistribution; /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2. @@ -324,8 +323,8 @@ typedef struct #endif /* SYSCFG_MCHDLYCR_BSCKSEL */ /** * @} - */ - + */ + /* End of exported types -----------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ @@ -333,11 +332,11 @@ typedef struct * @{ */ -/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection +/** @defgroup DFSDM_Channel_OutputClock DFSDM channel output clock selection * @{ */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ -#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for output clock is system clock */ +#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for output clock is audio clock */ /** * @} */ @@ -416,7 +415,7 @@ typedef struct /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger * @{ */ -#if defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F413xx) || defined(STM32F423xx) /* Trigger for stm32f413xx and STM32f423xx devices */ #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For All DFSDM1/2 filters */ #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For All DFSDM1/2 filters */ @@ -443,7 +442,7 @@ typedef struct /** * @} */ - + /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge * @{ */ @@ -478,7 +477,7 @@ typedef struct /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code * @{ - */ + */ #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ @@ -511,7 +510,7 @@ typedef struct - in 16-bit MSB the channel number is set e.g. for channel 3 definition: - the channel mask is 0x00000008 (bit 3 is set) - - the channel number 3 is 0x00030000 + - the channel number 3 is 0x00030000 --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */ #define DFSDM_CHANNEL_0 0x00000001U #define DFSDM_CHANNEL_1 0x00010002U @@ -546,25 +545,25 @@ typedef struct #if defined(SYSCFG_MCHDLYCR_BSCKSEL) /** @defgroup DFSDM_1_CLOCKOUT_SELECTION DFSDM1 ClockOut Selection * @{ - */ + */ #define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U #define DFSDM1_CKOUT_DFSDM1 0x00000000U /** * @} - */ - + */ + /** @defgroup DFSDM_2_CLOCKOUT_SELECTION DFSDM2 ClockOut Selection * @{ - */ + */ #define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U -#define DFSDM2_CKOUT_DFSDM2 0x00000000U +#define DFSDM2_CKOUT_DFSDM2 0x00000000U /** * @} - */ + */ /** @defgroup DFSDM_1_CLOCKIN_SELECTION DFSDM1 ClockIn Selection * @{ - */ + */ #define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U #define DFSDM1_CKIN_PAD 0x00000000U /** @@ -573,16 +572,16 @@ typedef struct /** @defgroup DFSDM_2_CLOCKIN_SELECTION DFSDM2 ClockIn Selection * @{ - */ + */ #define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U #define DFSDM2_CKIN_PAD 0x00000000U /** * @} */ -/** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution +/** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution * @{ - */ + */ #define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */ #define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */ #define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */ @@ -590,14 +589,14 @@ typedef struct /** * @} */ - -/** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution + +/** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution * @{ */ -#define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */ -#define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */ -#define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */ -#define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */ +#define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */ +#define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */ +#define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */ +#define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */ #define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */ #define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */ #define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */ @@ -606,9 +605,9 @@ typedef struct * @} */ -/** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution +/** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution * @{ - */ + */ #define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U #define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL #define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U @@ -616,8 +615,8 @@ typedef struct /** * @} */ - -/** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution + +/** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution * @{ */ #define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U @@ -625,13 +624,13 @@ typedef struct #define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U #define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL #define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U -#define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL -#define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U -#define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL +#define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL +#define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U +#define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL /** * @} */ - + /** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable * @{ */ @@ -651,7 +650,7 @@ typedef struct /** * @} */ - + /** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection * @{ */ @@ -683,8 +682,8 @@ typedef struct #define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL /** * @} - */ - + */ + /** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4 * @{ */ @@ -692,8 +691,8 @@ typedef struct #define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL /** * @} - */ - + */ + /** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6 * @{ */ @@ -701,7 +700,7 @@ typedef struct #define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL /** * @} - */ + */ /** @defgroup DFSDM1_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN * @{ @@ -712,8 +711,8 @@ typedef struct #define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /** * @} - */ - + */ + /** @defgroup DFSDM2_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN * @{ */ @@ -727,12 +726,12 @@ typedef struct #define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /** * @} - */ - + */ + #endif /* SYSCFG_MCHDLYCR_BSCKSEL*/ /** * @} - */ + */ /* End of exported constants -------------------------------------------------*/ /* Exported macros -----------------------------------------------------------*/ @@ -812,11 +811,11 @@ HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfs HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); -int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +int16_t HAL_DFSDM_ChannelGetAwdValue(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); -HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); @@ -828,7 +827,7 @@ void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); * @{ */ /* Channel state function *****************************************************/ -HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); +HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(const DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /** * @} */ @@ -888,16 +887,16 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, - DFSDM_Filter_AwdParamTypeDef* awdParam); + const DFSDM_Filter_AwdParamTypeDef* awdParam); HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); -uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +int32_t HAL_DFSDM_FilterGetRegularValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetInjectedValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetExdMaxValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +int32_t HAL_DFSDM_FilterGetExdMinValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); +uint32_t HAL_DFSDM_FilterGetConvTimeValue(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); @@ -918,8 +917,8 @@ void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); * @{ */ /* Filter state functions *****************************************************/ -HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); -uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); +uint32_t HAL_DFSDM_FilterGetError(const DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /** * @} */ @@ -995,7 +994,7 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) #define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \ - ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1)) + ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1)) #else #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ @@ -1046,18 +1045,18 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); ((INSTANCE) == DFSDM1_Channel2) || \ ((INSTANCE) == DFSDM1_Channel3)) #define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \ - ((INSTANCE) == DFSDM1_Filter1)) + ((INSTANCE) == DFSDM1_Filter1)) #endif /* DFSDM2_Channel0 */ #if defined(SYSCFG_MCHDLYCR_BSCKSEL) #define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \ ((SELECTION) == HAL_DFSDM2_CKIN_DM) || \ ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \ - ((SELECTION) == HAL_DFSDM1_CKIN_DM)) + ((SELECTION) == HAL_DFSDM1_CKIN_DM)) #define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \ ((SELECTION) == HAL_DFSDM2_CKOUT_M27) || \ ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \ - ((SELECTION) == HAL_DFSDM1_CKOUT_M27)) + ((SELECTION) == HAL_DFSDM1_CKOUT_M27)) #define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) || \ ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \ ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) || \ @@ -1085,16 +1084,16 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); #define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) || \ ((CLKOUT) == DFSDM1_CKOUT_DFSDM1)) #define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) || \ - ((CLKOUT) == DFSDM2_CKOUT_DFSDM2)) + ((CLKOUT) == DFSDM2_CKOUT_DFSDM2)) #define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) || \ - ((CLKIN) == DFSDM1_CKIN_PAD)) + ((CLKIN) == DFSDM1_CKIN_PAD)) #define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) || \ ((CLKIN) == DFSDM2_CKIN_PAD)) #define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) || \ ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) || \ ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) || \ ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) || \ - ((CLK) <= 0x30U)) + ((CLK) <= 0x30U)) #define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) || \ ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) || \ @@ -1104,14 +1103,14 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) || \ ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) || \ ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \ - ((CLK) <= 0x1E000U)) + ((CLK) <= 0x1E000U)) #define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \ ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \ ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \ ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \ - ((DISTRIBUTION) <= 0xCU)) - + ((DISTRIBUTION) <= 0xCU)) + #define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \ ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \ ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \ @@ -1120,16 +1119,16 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \ ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \ ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \ - ((DISTRIBUTION) <= 0x1D00U)) + ((DISTRIBUTION) <= 0x1D00U)) #endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */ /** * @} - */ + */ /* End of private macros -----------------------------------------------------*/ /** * @} - */ + */ /** * @} @@ -1140,5 +1139,3 @@ void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); #endif #endif /* __STM32F4xx_HAL_DFSDM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.c index 69d848f3dc1..3dbb47766e3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.c @@ -83,13 +83,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -199,12 +198,12 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } - - /* Allocate lock resource */ - __HAL_UNLOCK(hdma); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; + + /* Allocate lock resource */ + __HAL_UNLOCK(hdma); /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); @@ -550,12 +549,12 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_TIMEOUT; } } @@ -563,11 +562,11 @@ HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state*/ hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } return HAL_OK; } @@ -602,7 +601,7 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param CompleteLevel Specifies the DMA level complete. - * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. + * @note The polling mode is kept in this version for legacy. it is recommended to use the IT model instead. * This model could be used for debug purpose. * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). * @param Timeout Timeout duration. @@ -657,13 +656,13 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_TIMEOUT; } } @@ -708,12 +707,12 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Clear the half transfer and transfer complete flags */ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State= HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + return HAL_ERROR; } } @@ -724,10 +723,10 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level /* Clear the half transfer and transfer complete flags */ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; + hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hdma); - - hdma->State = HAL_DMA_STATE_READY; } else { @@ -863,12 +862,12 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Clear all interrupt flags at correct offset within the register */ regs->IFCR = 0x3FU << hdma->StreamIndex; - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + if(hdma->XferAbortCallback != NULL) { hdma->XferAbortCallback(hdma); @@ -905,11 +904,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Disable the transfer complete interrupt */ hdma->Instance->CR &= ~(DMA_IT_TC); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } if(hdma->XferCpltCallback != NULL) @@ -940,11 +939,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) } while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); } if(hdma->XferErrorCallback != NULL) @@ -959,9 +958,9 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * @brief Register callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifer + * @param CallbackID User Callback identifier * a DMA_HandleTypeDef structure as parameter. - * @param pCallback pointer to private callbacsk function which has pointer to + * @param pCallback pointer to private callback function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ @@ -1002,6 +1001,8 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call break; default: + /* Return error status */ + status = HAL_ERROR; break; } } @@ -1021,7 +1022,7 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call * @brief UnRegister callbacks * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param CallbackID User Callback identifer + * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. * @retval HAL status */ @@ -1302,4 +1303,3 @@ static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.h index 90dd292cc0a..7ff3836b65b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -801,4 +800,3 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #endif /* __STM32F4xx_HAL_DMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma2d.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma2d.c index d76d29697de..4cfac40613d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma2d.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -147,17 +158,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -2124,5 +2124,3 @@ static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_ */ #endif /* DMA2D */ #endif /* HAL_DMA2D_MODULE_ENABLED */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma2d.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma2d.h index 158ed67d0e3..896714137be 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma2d.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -279,15 +278,6 @@ typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointe * @} */ -/** @defgroup DMA2D_Aliases DMA2D API Aliases - * @{ - */ -#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort - for compatibility with legacy code */ -/** - * @} - */ - #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) /** * @brief HAL DMA2D common Callback ID enumeration definition @@ -646,6 +636,3 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); #endif #endif /* STM32F4xx_HAL_DMA2D_H */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.c index 6e073768347..7167e77e344 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.c @@ -25,13 +25,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -312,4 +311,3 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.h index 2e60aff2ffe..9858c741047 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dma_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -101,4 +100,3 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre #endif /*__STM32F4xx_HAL_DMA_EX_H*/ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.c index da57a8fa69d..2ae7faa2395 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -140,17 +151,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -200,12 +200,14 @@ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32 uint32_t Data1); static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, - uint32_t ChannelID, - uint32_t Mode, - uint32_t Param1, - uint32_t Param2); - + uint32_t ChannelID, + uint32_t Mode, + uint32_t Param1, + uint32_t Param2); /* Private functions ---------------------------------------------------------*/ +/** @defgroup DSI_Private_Functions DSI Private Functions + * @{ + */ /** * @brief Generic DSI packet header configuration * @param DSIx Pointer to DSI register base @@ -255,10 +257,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, tickstart = HAL_GetTick(); /* Wait for Command FIFO Empty */ - while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) + while ((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) { /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -271,6 +273,10 @@ static HAL_StatusTypeDef DSI_ShortWrite(DSI_HandleTypeDef *hdsi, return HAL_OK; } +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ /** @addtogroup DSI_Exported_Functions * @{ @@ -365,11 +371,17 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI /* Set the PLL division factors */ hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); - hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << 2U) | ((PLLInit->PLLIDF) << 11U) | ((PLLInit->PLLODF) << 16U)); + hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV) << DSI_WRPCR_PLL_NDIV_Pos) | \ + ((PLLInit->PLLIDF) << DSI_WRPCR_PLL_IDF_Pos) | \ + ((PLLInit->PLLODF) << DSI_WRPCR_PLL_ODF_Pos)); /* Enable the DSI PLL */ __HAL_DSI_PLL_ENABLE(hdsi); + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + /* Get tick */ tickstart = HAL_GetTick(); @@ -419,7 +431,7 @@ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLI hdsi->Instance->IER[1U] = 0U; hdsi->ErrorMsk = 0U; - /* Initialise the error code */ + /* Initialize the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; /* Initialize the DSI state*/ @@ -473,7 +485,7 @@ HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) HAL_DSI_MspDeInit(hdsi); #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ - /* Initialise the error code */ + /* Initialize the error code */ hdsi->ErrorCode = HAL_DSI_ERROR_NONE; /* Initialize the DSI state*/ @@ -698,7 +710,7 @@ HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Call /** * @brief Unregister a DSI Callback - * DSI callabck is redirected to the weak predefined callback + * DSI callback is redirected to the weak predefined callback * @param hdsi dsi handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -733,11 +745,11 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca break; case HAL_DSI_MSPINIT_CB_ID : - hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */ break; case HAL_DSI_MSPDEINIT_CB_ID : - hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */ break; default : @@ -753,11 +765,11 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca switch (CallbackID) { case HAL_DSI_MSPINIT_CB_ID : - hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ + hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legacy weak MspInit Callback */ break; case HAL_DSI_MSPDEINIT_CB_ID : - hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ + hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legacy weak MspDeInit Callback */ break; default : @@ -808,7 +820,8 @@ HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_Ca */ void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) { - uint32_t ErrorStatus0, ErrorStatus1; + uint32_t ErrorStatus0; + uint32_t ErrorStatus1; /* Tearing Effect Interrupt management ***************************************/ if (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U) @@ -1365,7 +1378,8 @@ HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerT High-Speed transmission. To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed to Low-Power and from Low-Power to High-Speed. - This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). + This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration + Register (DSI_CLTCR). But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. @@ -1587,7 +1601,7 @@ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, /* Process locked */ __HAL_LOCK(hdsi); - status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2); + status = DSI_ShortWrite(hdsi, ChannelID, Mode, Param1, Param2); /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -1616,7 +1630,9 @@ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, uint32_t Param1, uint8_t *ParametersTable) { - uint32_t uicounter, nbBytes, count; + uint32_t uicounter; + uint32_t nbBytes; + uint32_t count; uint32_t tickstart; uint32_t fifoword; uint8_t *pparams = ParametersTable; @@ -1721,7 +1737,7 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, { /* set max return packet size */ if (DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize) & 0xFFU), - (((datasize) >> 8U) & 0xFFU)) != HAL_OK) + (((datasize) >> 8U) & 0xFFU)) != HAL_OK) { /* Process Unlocked */ __HAL_UNLOCK(hdsi); @@ -1782,6 +1798,21 @@ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, return HAL_TIMEOUT; } + + /* Software workaround to avoid HAL_TIMEOUT when a DSI read command is */ + /* issued to the panel and the read data is not captured by the DSI Host */ + /* which returns Packet Size Error. */ + /* Need to ensure that the Read command has finished before checking PSE */ + if ((hdsi->Instance->GPSR & DSI_GPSR_RCB) == 0U) + { + if ((hdsi->Instance->ISR[1U] & DSI_ISR1_PSE) == DSI_ISR1_PSE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } } /* Process unlocked */ @@ -1804,6 +1835,85 @@ HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify the initial status of the DSI Host */ + + /* Verify that the clock lane and the digital section of the D-PHY are enabled */ + if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that the D-PHY PLL and the reference bias are enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no ULPS exit or request on data lanes */ + if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no Transmission trigger */ + if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Verify that D-PHY PLL is locked */ + tickstart = HAL_GetTick(); + + while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + /* ULPS Request on Data Lanes */ hdsi->Instance->PUCR |= DSI_PUCR_URDL; @@ -1867,6 +1977,58 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify that all active lanes are in ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + + /* Turn on the DSI PLL */ + __HAL_DSI_PLL_ENABLE(hdsi); + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Exit ULPS on Data Lanes */ hdsi->Instance->PUCR |= DSI_PUCR_UEDL; @@ -1916,6 +2078,61 @@ HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) /* De-assert the ULPM requests and the ULPM exit bits */ hdsi->Instance->PUCR = 0U; + /* Verify that D-PHY PLL is enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that D-PHY PLL is locked */ + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -1936,6 +2153,86 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify the initial status of the DSI Host */ + + /* Verify that the clock lane and the digital section of the D-PHY are enabled */ + if ((hdsi->Instance->PCTLR & (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) != (DSI_PCTLR_CKE | DSI_PCTLR_DEN)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that the D-PHY PLL and the reference bias are enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no ULPS exit or request on both data and clock lanes */ + if ((hdsi->Instance->PUCR & (DSI_PUCR_UEDL | DSI_PUCR_URDL | DSI_PUCR_UECL | DSI_PUCR_URCL)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that there are no Transmission trigger */ + if ((hdsi->Instance->PTTCR & DSI_PTTCR_TX_TRIG) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Verify that D-PHY PLL is locked */ + tickstart = HAL_GetTick(); + + while ((__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U)) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ + DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + /* Clock lane configuration: no more HS request */ hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; @@ -1948,7 +2245,7 @@ HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) /* Get tick */ tickstart = HAL_GetTick(); - /* Wait until all active lanes exit ULPM */ + /* Wait until all active lanes enter ULPM */ if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) { while ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U) @@ -2008,9 +2305,44 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /* Process locked */ __HAL_LOCK(hdsi); + /* Verify that all active lanes are in ULPM */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | \ + DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_RUE0 | DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_UAN1 | \ + DSI_PSR_PSS1 | DSI_PSR_UANC | DSI_PSR_PSSC | DSI_PSR_PD)) != 0U) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_ERROR; + } + /* Turn on the DSI PLL */ __HAL_DSI_PLL_ENABLE(hdsi); + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + /* Get tick */ tickstart = HAL_GetTick(); @@ -2077,12 +2409,68 @@ HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) /* De-assert the ULPM requests and the ULPM exit bits */ hdsi->Instance->PUCR = 0U; - /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ + /* Switch the lane byte clock source in the RCC from system PLL to D-PHY */ __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); /* Restore clock lane configuration to HS */ hdsi->Instance->CLCR |= DSI_CLCR_DPCC; + /* Verify that D-PHY PLL is enabled */ + if ((hdsi->Instance->WRPCR & DSI_WRPCR_PLLEN) != DSI_WRPCR_PLLEN) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that all active lanes are in Stop state */ + if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) + { + if ((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | \ + DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_PSS0 | DSI_PSR_PSS1 | DSI_PSR_UAN1)) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + } + else + { + /* Process unlocked */ + __HAL_UNLOCK(hdsi); + return HAL_ERROR; + } + + /* Verify that D-PHY PLL is locked */ + /* Requires min of 400us delay before reading the PLLLS flag */ + /* 1ms delay is inserted that is the minimum HAL delay granularity */ + HAL_Delay(1); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for the lock of the PLL */ + while (__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > DSI_TIMEOUT_VALUE) + { + /* Process Unlocked */ + __HAL_UNLOCK(hdsi); + + return HAL_TIMEOUT; + } + } + /* Process unlocked */ __HAL_UNLOCK(hdsi); @@ -2727,5 +3115,3 @@ uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.h index 716dea17daf..6da96681c3f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_dsi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -40,6 +39,9 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup DSI_Exported_Types DSI Exported Types + * @{ + */ /** * @brief DSI Init Structure definition */ @@ -61,14 +63,14 @@ typedef struct */ typedef struct { - uint32_t PLLNDIV; /*!< PLL Loop Division Factor - This parameter must be a value between 10 and 125 */ + uint32_t PLLNDIV; /*!< PLL Loop Division Factor + This parameter must be a value between 10 and 125 */ - uint32_t PLLIDF; /*!< PLL Input Division Factor - This parameter can be any value of @ref DSI_PLL_IDF */ + uint32_t PLLIDF; /*!< PLL Input Division Factor + This parameter can be any value of @ref DSI_PLL_IDF */ - uint32_t PLLODF; /*!< PLL Output Division Factor - This parameter can be any value of @ref DSI_PLL_ODF */ + uint32_t PLLODF; /*!< PLL Output Division Factor + This parameter can be any value of @ref DSI_PLL_ODF */ } DSI_PLLInitTypeDef; @@ -346,6 +348,9 @@ typedef enum typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ /** @defgroup DSI_Exported_Constants DSI Exported Constants @@ -700,8 +705,8 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE -#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ - DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ +#define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ + DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ DSI_FLOW_CONTROL_EOTP_TX) /** * @} @@ -841,18 +846,18 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @{ */ #define HAL_DSI_ERROR_NONE 0U -#define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ -#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ -#define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ -#define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ -#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ -#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ -#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ -#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ -#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ -#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ +#define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */ +#define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ +#define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */ +#define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */ +#define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ +#define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ +#define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ +#define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ +#define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ +#define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) -#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ +#define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ /** * @} @@ -912,6 +917,7 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @} */ + /** * @} */ @@ -955,11 +961,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ - /* Delay after an DSI Host disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + /* Delay after an DSI Host disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -968,11 +974,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI warpper enabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -981,11 +987,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - /* Delay after an DSI warpper disabling*/ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + /* Delay after an DSI warpper disabling*/ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -994,11 +1000,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - /* Delay after an DSI PLL enabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL enabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -1007,11 +1013,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - /* Delay after an DSI PLL disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + /* Delay after an DSI PLL disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -1033,11 +1039,11 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to * @retval None. */ #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ - __IO uint32_t tmpreg = 0x00U; \ - CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ - /* Delay after an DSI regulator disabling */ \ - tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ - UNUSED(tmpreg); \ + __IO uint32_t tmpreg = 0x00U; \ + CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + /* Delay after an DSI regulator disabling */ \ + tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ + UNUSED(tmpreg); \ } while(0U) /** @@ -1121,23 +1127,41 @@ typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to /** @defgroup DSI_Exported_Functions DSI Exported Functions * @{ */ +/** @defgroup DSI_Group1 Initialization and Configuration functions + * @brief Initialization and Configuration functions + * @{ + */ HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); - -void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); -void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); -void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); -void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); - +HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, pDSI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup DSI_Group2 IO operation functions + * @brief IO operation functions + * @{ + */ +void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); +void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); +void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); +/** + * @} + */ +/** @defgroup DSI_Group3 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); @@ -1190,40 +1214,28 @@ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, Functional HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); -uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); -HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); -HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} */ -/* Private types -------------------------------------------------------------*/ -/** @defgroup DSI_Private_Types DSI Private Types +/** @defgroup DSI_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * @{ */ +uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); +HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); /** * @} */ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup DSI_Private_Defines DSI Private Defines - * @{ - */ - /** * @} */ +/* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/** @defgroup DSI_Private_Variables DSI Private Variables - * @{ - */ - -/** - * @} - */ - /* Private constants ---------------------------------------------------------*/ /** @defgroup DSI_Private_Constants DSI Private Constants * @{ @@ -1249,45 +1261,73 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); ((ODF) == DSI_PLL_OUT_DIV2) || \ ((ODF) == DSI_PLL_OUT_DIV4) || \ ((ODF) == DSI_PLL_OUT_DIV8)) -#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) -#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) +#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\ + || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) +#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\ + || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) -#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) -#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) -#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) -#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) +#define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\ + || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) +#define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\ + || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) +#define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\ + || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) +#define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\ + || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ ((VideoModeType) == DSI_VID_MODE_BURST)) -#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) +#define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\ + || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) -#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) +#define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\ + || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) -#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) +#define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\ + || ((LPVActive) == DSI_LP_VACT_ENABLE)) #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) -#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) -#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) +#define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\ + || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) +#define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\ + || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) -#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) -#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) -#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) -#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) -#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) -#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) -#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) -#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) -#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) -#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) -#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) -#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) -#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) -#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) -#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) -#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) -#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) +#define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\ + || ((TEPolarity) == DSI_TE_FALLING_EDGE)) +#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\ + || ((AutomaticRefresh) == DSI_AR_ENABLE)) +#define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\ + || ((VSPolarity) == DSI_VSYNC_RISING)) +#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\ + || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\ + || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) +#define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\ + || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) +#define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\ + || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) +#define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\ + || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) +#define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\ + || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) +#define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\ + || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) +#define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\ + || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) +#define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\ + || ((LP_GLW) == DSI_LP_GLW_ENABLE)) +#define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\ + || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) +#define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\ + || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) +#define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\ + || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) +#define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\ + || ((LP_DLW) == DSI_LP_DLW_ENABLE)) +#define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\ + || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ @@ -1299,10 +1339,14 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) -#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) +#define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \ + ((CommDelay) == DSI_SLEW_RATE_LPTX) || \ + ((CommDelay) == DSI_HS_DELAY)) #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) -#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) -#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) +#define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\ + || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) +#define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \ + ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ ((Timing) == DSI_TLPX_CLK ) || \ ((Timing) == DSI_THS_EXIT ) || \ @@ -1317,24 +1361,6 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); * @} */ -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes - * @{ - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup DSI_Private_Functions DSI Private Functions - * @{ - */ - -/** - * @} - */ - /** * @} */ @@ -1349,5 +1375,3 @@ HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); #endif #endif /* STM32F4xx_HAL_DSI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.c index 1e36f989520..50d95b882a8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.c @@ -3,102 +3,159 @@ * @file stm32f4xx_hal_eth.c * @author MCD Application Team * @brief ETH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: - * + Initialization and de-initialization functions + * + Initialization and deinitialization functions * + IO operation functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + [..] + The ETH HAL driver can be used as follows: + (#)Declare a ETH_HandleTypeDef handle structure, for example: ETH_HandleTypeDef heth; - + (#)Fill parameters of Init structure in heth handle - - (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) + + (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...) (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API: - (##) Enable the Ethernet interface clock using - (+++) __HAL_RCC_ETHMAC_CLK_ENABLE(); - (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE(); - (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE(); - + (##) Enable the Ethernet interface clock using + (+++) __HAL_RCC_ETH1MAC_CLK_ENABLE() + (+++) __HAL_RCC_ETH1TX_CLK_ENABLE() + (+++) __HAL_RCC_ETH1RX_CLK_ENABLE() + (##) Initialize the related GPIO clocks - (##) Configure Ethernet pin-out - (##) Configure Ethernet NVIC interrupt (IT mode) - - (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers: - (##) HAL_ETH_DMATxDescListInit(); for Transmission process - (##) HAL_ETH_DMARxDescListInit(); for Reception process + (##) Configure Ethernet pinout + (##) Configure Ethernet NVIC interrupt (in Interrupt mode) + + (#) Ethernet data reception is asynchronous, so call the following API + to start the listening mode: + (##) HAL_ETH_Start(): + This API starts the MAC and DMA transmission and reception process, + without enabling end of transfer interrupts, in this mode user + has to poll for data reception by calling HAL_ETH_ReadData() + (##) HAL_ETH_Start_IT(): + This API starts the MAC and DMA transmission and reception process, + end of transfer interrupts are enabled in this mode, + HAL_ETH_RxCpltCallback() will be executed when an Ethernet packet is received + + (#) When data is received user can call the following API to get received data: + (##) HAL_ETH_ReadData(): Read a received packet + + (#) For transmission path, two APIs are available: + (##) HAL_ETH_Transmit(): Transmit an ETH frame in blocking mode + (##) HAL_ETH_Transmit_IT(): Transmit an ETH frame in interrupt mode, + HAL_ETH_TxCpltCallback() will be executed when end of transfer occur + + (#) Communication with an external PHY device: + (##) HAL_ETH_ReadPHYRegister(): Read a register from an external PHY + (##) HAL_ETH_WritePHYRegister(): Write data to an external RHY register - (#)Enable MAC and DMA transmission and reception: - (##) HAL_ETH_Start(); + (#) Configure the Ethernet MAC after ETH peripheral initialization + (##) HAL_ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef + (##) HAL_ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef - (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer - the frame to MAC TX FIFO: - (##) HAL_ETH_TransmitFrame(); + (#) Configure the Ethernet DMA after ETH peripheral initialization + (##) HAL_ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef + (##) HAL_ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef - (#)Poll for a received frame in ETH RX DMA Descriptors and get received - frame parameters - (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop) + (#) Configure the Ethernet PTP after ETH peripheral initialization + (##) Define HAL_ETH_USE_PTP to use PTP APIs. + (##) HAL_ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef + (##) HAL_ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef + (##) HAL_ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers + (##) HAL_ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers + (##) HAL_ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers + (##) HAL_ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission + (##) HAL_ETH_PTP_GetTxTimestamp(): Get transmission timestamp + (##) HAL_ETH_PTP_GetRxTimestamp(): Get reception timestamp - (#) Get a received frame when an ETH RX interrupt occurs: - (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only) + -@- The ARP offload feature is not supported in this driver. - (#) Communicate with external PHY device: - (##) Read a specific register from the PHY - HAL_ETH_ReadPHYRegister(); - (##) Write data to a specific RHY register: - HAL_ETH_WritePHYRegister(); + -@- The PTP offload feature is not supported in this driver. - (#) Configure the Ethernet MAC after ETH peripheral initialization - HAL_ETH_ConfigMAC(); all MAC parameters should be filled. - - (#) Configure the Ethernet DMA after ETH peripheral initialization - HAL_ETH_ConfigDMA(); all DMA parameters should be filled. - - -@- The PTP protocol and the DMA descriptors ring mode are not supported - in this driver -*** Callback registration *** + *** Callback registration *** ============================================= The compilation define USE_HAL_ETH_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_ETH_RegisterCallback() to register an interrupt callback. + Use Function HAL_ETH_RegisterCallback() to register an interrupt callback. - Function @ref HAL_ETH_RegisterCallback() allows to register following callbacks: + Function HAL_ETH_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. - (+) DMAErrorCallback : DMA Error Callback. + (+) ErrorCallback : Error Callback. + (+) PMTCallback : Power Management Callback + (+) EEECallback : EEE Callback. + (+) WakeUpCallback : Wake UP Callback (+) MspInitCallback : MspInit Callback. (+) MspDeInitCallback: MspDeInit Callback. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_ETH_UnRegisterCallback() to reset a callback to the default + For specific callbacks RxAllocateCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterRxAllocateCallback(). + + For specific callbacks RxLinkCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterRxLinkCallback(). + + For specific callbacks TxFreeCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterTxFreeCallback(). + + For specific callbacks TxPtpCallback use dedicated register callbacks: + respectively HAL_ETH_RegisterTxPtpCallback(). + + Use function HAL_ETH_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_ETH_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. - (+) DMAErrorCallback : DMA Error Callback. + (+) ErrorCallback : Error Callback. + (+) PMTCallback : Power Management Callback + (+) EEECallback : EEE Callback. + (+) WakeUpCallback : Wake UP Callback (+) MspInitCallback : MspInit Callback. (+) MspDeInitCallback: MspDeInit Callback. + For specific callbacks RxAllocateCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterRxAllocateCallback(). + + For specific callbacks RxLinkCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterRxLinkCallback(). + + For specific callbacks TxFreeCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterTxFreeCallback(). + + For specific callbacks TxPtpCallback use dedicated unregister callbacks: + respectively HAL_ETH_UnRegisterTxPtpCallback(). + By default, after the HAL_ETH_Init and when the state is HAL_ETH_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_ETH_TxCpltCallback(), @ref HAL_ETH_RxCpltCallback(). + examples HAL_ETH_TxCpltCallback(), HAL_ETH_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak function in the HAL_ETH_Init/ @ref HAL_ETH_DeInit only when + reset to the legacy weak function in the HAL_ETH_Init/ HAL_ETH_DeInit only when these callbacks are null (not registered beforehand). - if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ @ref HAL_ETH_DeInit + if not, MspInit or MspDeInit are not null, the HAL_ETH_Init/ HAL_ETH_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in HAL_ETH_STATE_READY state only. @@ -106,7 +163,7 @@ in HAL_ETH_STATE_READY or HAL_ETH_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_ETH_RegisterCallback() before calling @ref HAL_ETH_DeInit + using HAL_ETH_RegisterCallback() before calling HAL_ETH_DeInit or HAL_ETH_Init function. When The compilation define USE_HAL_ETH_REGISTER_CALLBACKS is set to 0 or @@ -115,17 +172,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -134,533 +180,274 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#ifdef HAL_ETH_MODULE_ENABLED -/** @defgroup ETH ETH +#if defined(ETH) + +/** @defgroup ETH ETH * @brief ETH HAL module driver * @{ */ -#ifdef HAL_ETH_MODULE_ENABLED - -#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/** @defgroup ETH_Private_Constants ETH Private Constants +/** @addtogroup ETH_Private_Constants ETH Private Constants * @{ */ -#define ETH_TIMEOUT_SWRESET 500U -#define ETH_TIMEOUT_LINKED_STATE 5000U -#define ETH_TIMEOUT_AUTONEGO_COMPLETED 5000U +#define ETH_MACCR_MASK 0xFFFB7F7CU +#define ETH_MACECR_MASK 0x3F077FFFU +#define ETH_MACFFR_MASK 0x800007FFU +#define ETH_MACWTR_MASK 0x0000010FU +#define ETH_MACTFCR_MASK 0xFFFF00F2U +#define ETH_MACRFCR_MASK 0x00000003U +#define ETH_MTLTQOMR_MASK 0x00000072U +#define ETH_MTLRQOMR_MASK 0x0000007BU + +#define ETH_DMAMR_MASK 0x00007802U +#define ETH_DMASBMR_MASK 0x0000D001U +#define ETH_DMACCR_MASK 0x00013FFFU +#define ETH_DMACTCR_MASK 0x003F1010U +#define ETH_DMACRCR_MASK 0x803F0000U +#define ETH_MACPMTCSR_MASK (ETH_MACPMTCSR_PD | ETH_MACPMTCSR_WFE | \ + ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU) + +/* Timeout values */ +#define ETH_SWRESET_TIMEOUT 500U +#define ETH_MDIO_BUS_TIMEOUT 1000U + +#define ETH_DMARXDESC_ERRORS_MASK ((uint32_t)(ETH_DMARXDESC_DBE | ETH_DMARXDESC_RE | \ + ETH_DMARXDESC_OE | ETH_DMARXDESC_RWT |\ + ETH_DMARXDESC_LC | ETH_DMARXDESC_CE |\ + ETH_DMARXDESC_DE | ETH_DMARXDESC_IPV4HCE)) + +#define ETH_MAC_US_TICK 1000000U + +#define ETH_MACTSCR_MASK 0x0087FF2FU + +#define ETH_PTPTSHR_VALUE 0xFFFFFFFFU +#define ETH_PTPTSLR_VALUE 0xBB9ACA00U + +/* Ethernet MACMIIAR register Mask */ +#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U + +/* Delay to wait when writing to some Ethernet registers */ +#define ETH_REG_WRITE_DELAY 0x00000001U + +/* ETHERNET MACCR register Mask */ +#define ETH_MACCR_CLEAR_MASK 0xFF20810FU + +/* ETHERNET MACFCR register Mask */ +#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U + +/* ETHERNET DMAOMR register Mask */ +#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U + +/* ETHERNET MAC address offsets */ +#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ + +/* ETHERNET DMA Rx descriptors Frame length Shift */ +#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Macros ETH Private Macros + * @{ + */ +/* Helper macros for TX descriptor handling */ +#define INCR_TX_DESC_INDEX(inx, offset) do {\ + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\ + } while (0) + +/* Helper macros for RX descriptor handling */ +#define INCR_RX_DESC_INDEX(inx, offset) do {\ + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\ + } while (0) /** * @} */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup ETH_Private_Functions ETH Private Functions +/** @defgroup ETH_Private_Functions ETH Private Functions * @{ */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err); -static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); -static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth); -static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth); -static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth); -static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth); -static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth); -static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth); -static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth); -static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth); +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth); +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth); +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth); +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode); +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth); static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth); -static void ETH_Delay(uint32_t mdelay); +static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr); + #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - /** * @} */ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ /** @defgroup ETH_Exported_Functions ETH Exported Functions * @{ */ -/** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions + * @brief Initialization and Configuration functions * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the Ethernet peripheral - (+) De-initialize the Ethernet peripheral +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the ETH peripheral: - @endverbatim + (+) User must Implement HAL_ETH_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO and NVIC ). + + (+) Call the function HAL_ETH_Init() to configure the selected device with + the selected configuration: + (++) MAC address + (++) Media interface (MII or RMII) + (++) Rx DMA Descriptors Tab + (++) Tx DMA Descriptors Tab + (++) Length of Rx Buffers + + (+) Call the function HAL_ETH_DeInit() to restore the default configuration + of the selected ETH peripheral. + +@endverbatim * @{ */ /** - * @brief Initializes the Ethernet MAC and DMA according to default - * parameters. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Initialize the Ethernet peripheral registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) { - uint32_t tmpreg1 = 0U, phyreg = 0U; - uint32_t hclk = 60000000U; - uint32_t tickstart = 0U; - uint32_t err = ETH_SUCCESS; - - /* Check the ETH peripheral state */ - if(heth == NULL) + uint32_t tickstart; + + if (heth == NULL) { return HAL_ERROR; } - - /* Check parameters */ - assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation)); - assert_param(IS_ETH_RX_MODE(heth->Init.RxMode)); - assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode)); - assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface)); - - if(heth->State == HAL_ETH_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - heth->Lock = HAL_UNLOCKED; + if (heth->gState == HAL_ETH_STATE_RESET) + { + heth->gState = HAL_ETH_STATE_BUSY; + #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + ETH_InitCallbacksToDefault(heth); - if(heth->MspInitCallback == NULL) + if (heth->MspInitCallback == NULL) { - /* Init the low level hardware : GPIO, CLOCK, NVIC. */ heth->MspInitCallback = HAL_ETH_MspInit; } - heth->MspInitCallback(heth); + /* Init the low level hardware */ + heth->MspInitCallback(heth); #else /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ } - - /* Enable SYSCFG Clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); - + /* Select MII or RMII Mode*/ SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL); SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface; - + /* Dummy read to sync SYSCFG with ETH */ + (void)SYSCFG->PMC; + /* Ethernet Software reset */ /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ /* After reset all the registers holds their respective reset values */ - (heth->Instance)->DMABMR |= ETH_DMABMR_SR; - + SET_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR); + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait for software reset */ - while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) - { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET) - { - heth->State= HAL_ETH_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are - not available, please check your external PHY or the IO configuration */ - return HAL_TIMEOUT; - } - } - - /*-------------------------------- MAC Initialization ----------------------*/ - /* Get the ETHERNET MACMIIAR value */ - tmpreg1 = (heth->Instance)->MACMIIAR; - /* Clear CSR Clock Range CR[2:0] bits */ - tmpreg1 &= ETH_MACMIIAR_CR_MASK; - - /* Get hclk frequency value */ - hclk = HAL_RCC_GetHCLKFreq(); - - /* Set CR bits depending on hclk value */ - if((hclk >= 20000000U)&&(hclk < 35000000U)) - { - /* CSR Clock Range between 20-35 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16; - } - else if((hclk >= 35000000U)&&(hclk < 60000000U)) - { - /* CSR Clock Range between 35-60 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26; - } - else if((hclk >= 60000000U)&&(hclk < 100000000U)) - { - /* CSR Clock Range between 60-100 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42; - } - else if((hclk >= 100000000U)&&(hclk < 150000000U)) - { - /* CSR Clock Range between 100-150 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62; - } - else /* ((hclk >= 150000000)&&(hclk <= 183000000)) */ - { - /* CSR Clock Range between 150-183 MHz */ - tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102; - } - - /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ - (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1; - - /*-------------------- PHY initialization and configuration ----------------*/ - /* Put the PHY in reset mode */ - if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Delay to assure PHY reset */ - HAL_Delay(PHY_RESET_DELAY); - - if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE) + while (READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_SR) > 0U) { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* We wait for linked status */ - do - { - HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS)); - - - /* Enable Auto-Negotiation */ - if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until the auto-negotiation will be completed */ - do - { - HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg); - - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE)); - - /* Read the result of the auto-negotiation */ - if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */ - if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET) - { - /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - } - else + if (((HAL_GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) { - /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */ - (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX; - } - /* Configure the MAC with the speed fixed by the auto-negotiation process */ - if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS) - { - /* Set Ethernet speed to 10M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_10M; - } - else - { - /* Set Ethernet speed to 100M following the auto-negotiation */ - (heth->Init).Speed = ETH_SPEED_100M; + /* Set Error Code */ + heth->ErrorCode = HAL_ETH_ERROR_TIMEOUT; + /* Set State as Error */ + heth->gState = HAL_ETH_STATE_ERROR; + /* Return Error */ + return HAL_ERROR; } } - else /* AutoNegotiation Disable */ - { - /* Check parameters */ - assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - - /* Set MAC Speed and Duplex Mode */ - if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3U) | - (uint16_t)((heth->Init).Speed >> 1U))) != HAL_OK) - { - /* In case of write timeout */ - err = ETH_ERROR; - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set the ETH peripheral state to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return HAL_ERROR */ - return HAL_ERROR; - } - - /* Delay to assure PHY configuration */ - HAL_Delay(PHY_CONFIG_DELAY); - } - - /* Config MAC and DMA */ - ETH_MACDMAConfig(heth, err); - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Return function status */ + + + /*------------------ MAC, MTL and DMA default Configuration ----------------*/ + ETH_MACDMAConfig(heth); + + + /*------------------ DMA Tx Descriptors Configuration ----------------------*/ + ETH_DMATxDescListInit(heth); + + /*------------------ DMA Rx Descriptors Configuration ----------------------*/ + ETH_DMARxDescListInit(heth); + + /*--------------------- ETHERNET MAC Address Configuration ------------------*/ + ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); + + heth->ErrorCode = HAL_ETH_ERROR_NONE; + heth->gState = HAL_ETH_STATE_READY; + return HAL_OK; } /** - * @brief De-Initializes the ETH peripheral. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief DeInitializes the ETH peripheral. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth) { /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - + heth->gState = HAL_ETH_STATE_BUSY; + #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - if(heth->MspDeInitCallback == NULL) + + if (heth->MspDeInitCallback == NULL) { heth->MspDeInitCallback = HAL_ETH_MspDeInit; } - /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + /* DeInit the low level hardware */ heth->MspDeInitCallback(heth); #else + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspDeInit(heth); -#endif - - /* Set ETH HAL state to Disabled */ - heth->State= HAL_ETH_STATE_RESET; - /* Release Lock */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} +#endif /* (USE_HAL_ETH_REGISTER_CALLBACKS) */ -/** - * @brief Initializes the DMA Tx descriptors in chain mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMATxDescTab Pointer to the first Tx desc list - * @param TxBuff Pointer to the first TxBuffer list - * @param TxBuffCount Number of the used Tx desc in the list - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) -{ - uint32_t i = 0U; - ETH_DMADescTypeDef *dmatxdesc; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */ - heth->TxDesc = DMATxDescTab; - - /* Fill each DMATxDesc descriptor with the right values */ - for(i=0U; i < TxBuffCount; i++) - { - /* Get the pointer on the ith member of the Tx Desc list */ - dmatxdesc = DMATxDescTab + i; - - /* Set Second Address Chained bit */ - dmatxdesc->Status = ETH_DMATXDESC_TCH; - - /* Set Buffer1 address pointer */ - dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]); - - if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) - { - /* Set the DMA Tx descriptors checksum insertion */ - dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL; - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (TxBuffCount-1U)) - { - /* Set next descriptor address register with next descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1U); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab; - } - } - - /* Set Transmit Descriptor List Address Register */ - (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab; - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; -} + /* Set ETH HAL state to Disabled */ + heth->gState = HAL_ETH_STATE_RESET; -/** - * @brief Initializes the DMA Rx descriptors in chain mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param DMARxDescTab Pointer to the first Rx desc list - * @param RxBuff Pointer to the first RxBuffer list - * @param RxBuffCount Number of the used Rx desc in the list - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) -{ - uint32_t i = 0U; - ETH_DMADescTypeDef *DMARxDesc; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */ - heth->RxDesc = DMARxDescTab; - - /* Fill each DMARxDesc descriptor with the right values */ - for(i=0U; i < RxBuffCount; i++) - { - /* Get the pointer on the ith member of the Rx Desc list */ - DMARxDesc = DMARxDescTab+i; - - /* Set Own bit of the Rx descriptor Status */ - DMARxDesc->Status = ETH_DMARXDESC_OWN; - - /* Set Buffer1 size and Second Address Chained bit */ - DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; - - /* Set Buffer1 address pointer */ - DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]); - - if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) - { - /* Enable Ethernet DMA Rx Descriptor interrupt */ - DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC; - } - - /* Initialize the next descriptor with the Next Descriptor Polling Enable */ - if(i < (RxBuffCount-1U)) - { - /* Set next descriptor address register with next descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1U); - } - else - { - /* For last descriptor, set next descriptor address register equal to the first descriptor base address */ - DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); - } - } - - /* Set Receive Descriptor List Address Register */ - (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab; - - /* Set ETH HAL State to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - /* Return function status */ return HAL_OK; } /** * @brief Initializes the ETH MSP. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -675,7 +462,7 @@ __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) /** * @brief DeInitializes ETH MSP. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -697,80 +484,96 @@ __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) * This parameter can be one of the following values: * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID + * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID + * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, + pETH_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + return HAL_ERROR; } - /* Process locked */ - __HAL_LOCK(heth); - if(heth->State == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_READY) { switch (CallbackID) { - case HAL_ETH_TX_COMPLETE_CB_ID : - heth->TxCpltCallback = pCallback; - break; - - case HAL_ETH_RX_COMPLETE_CB_ID : - heth->RxCpltCallback = pCallback; - break; - - case HAL_ETH_DMA_ERROR_CB_ID : - heth->DMAErrorCallback = pCallback; - break; - - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = pCallback; + break; + + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = pCallback; + break; + + case HAL_ETH_ERROR_CB_ID : + heth->ErrorCallback = pCallback; + break; + + case HAL_ETH_PMT_CB_ID : + heth->PMTCallback = pCallback; + break; + + + case HAL_ETH_WAKEUP_CB_ID : + heth->WakeUpCallback = pCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(heth->State == HAL_ETH_STATE_RESET) + else if (heth->gState == HAL_ETH_STATE_RESET) { switch (CallbackID) { - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = pCallback; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = pCallback; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = pCallback; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(heth); - return status; } @@ -782,7 +585,9 @@ HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Call * This parameter can be one of the following values: * @arg @ref HAL_ETH_TX_COMPLETE_CB_ID Tx Complete Callback ID * @arg @ref HAL_ETH_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_ETH_DMA_ERROR_CB_ID DMA Error Callback ID + * @arg @ref HAL_ETH_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_ETH_PMT_CB_ID Power Management Callback ID + * @arg @ref HAL_ETH_WAKEUP_CB_ID Wake UP Callback ID * @arg @ref HAL_ETH_MSPINIT_CB_ID MspInit callback ID * @arg @ref HAL_ETH_MSPDEINIT_CB_ID MspDeInit callback ID * @retval status @@ -791,66 +596,75 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca { HAL_StatusTypeDef status = HAL_OK; - /* Process locked */ - __HAL_LOCK(heth); - - if(heth->State == HAL_ETH_STATE_READY) + if (heth->gState == HAL_ETH_STATE_READY) { switch (CallbackID) { - case HAL_ETH_TX_COMPLETE_CB_ID : - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; - break; + case HAL_ETH_TX_COMPLETE_CB_ID : + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; + break; - case HAL_ETH_RX_COMPLETE_CB_ID : - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; - break; + case HAL_ETH_RX_COMPLETE_CB_ID : + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; + break; - case HAL_ETH_DMA_ERROR_CB_ID : - heth->DMAErrorCallback = HAL_ETH_ErrorCallback; - break; + case HAL_ETH_ERROR_CB_ID : + heth->ErrorCallback = HAL_ETH_ErrorCallback; + break; - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = HAL_ETH_MspInit; - break; + case HAL_ETH_PMT_CB_ID : + heth->PMTCallback = HAL_ETH_PMTCallback; + break; + + + case HAL_ETH_WAKEUP_CB_ID : + heth->WakeUpCallback = HAL_ETH_WakeUpCallback; + break; + + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; - default : - /* Return error status */ - status = HAL_ERROR; - break; + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(heth->State == HAL_ETH_STATE_RESET) + else if (heth->gState == HAL_ETH_STATE_RESET) { switch (CallbackID) { - case HAL_ETH_MSPINIT_CB_ID : - heth->MspInitCallback = HAL_ETH_MspInit; - break; - - case HAL_ETH_MSPDEINIT_CB_ID : - heth->MspDeInitCallback = HAL_ETH_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_ETH_MSPINIT_CB_ID : + heth->MspInitCallback = HAL_ETH_MspInit; + break; + + case HAL_ETH_MSPDEINIT_CB_ID : + heth->MspDeInitCallback = HAL_ETH_MspDeInit; + break; + + default : + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; + /* Return error status */ + status = HAL_ERROR; + break; } } else { + /* Update the error code */ + heth->ErrorCode |= HAL_ETH_ERROR_INVALID_CALLBACK; /* Return error status */ status = HAL_ERROR; } - /* Release Lock */ - __HAL_UNLOCK(heth); - return status; } #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ @@ -859,1199 +673,2224 @@ HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_Ca * @} */ -/** @defgroup ETH_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief ETH Transmit and Receive functions * - @verbatim +@verbatim ============================================================================== - ##### IO operation functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Transmit a frame - HAL_ETH_TransmitFrame(); - (+) Receive a frame - HAL_ETH_GetReceivedFrame(); - HAL_ETH_GetReceivedFrame_IT(); - (+) Read from an External PHY register - HAL_ETH_ReadPHYRegister(); - (+) Write to an External PHY register - HAL_ETH_WritePHYRegister(); + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the ETH + data transfer. - @endverbatim - +@endverbatim * @{ */ /** - * @brief Sends an Ethernet frame. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Enables Ethernet MAC and DMA reception and transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param FrameLength Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) { - uint32_t bufcount = 0U, size = 0U, i = 0U; - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - if (FrameLength == 0U) - { - /* Set ETH HAL state to READY */ - heth->State = HAL_ETH_STATE_READY; - - return HAL_ERROR; - } - - /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */ - if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET) - { - /* OWN bit set */ - heth->State = HAL_ETH_STATE_BUSY_TX; - - return HAL_ERROR; - } - - /* Get the number of needed Tx buffers for the current frame */ - if (FrameLength > ETH_TX_BUF_SIZE) - { - bufcount = FrameLength/ETH_TX_BUF_SIZE; - if (FrameLength % ETH_TX_BUF_SIZE) - { - bufcount++; - } - } - else - { - bufcount = 1U; - } - if (bufcount == 1U) + uint32_t tmpreg1; + + if (heth->gState == HAL_ETH_STATE_READY) { - /* Set LAST and FIRST segment */ - heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS; - /* Set frame size */ - heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1); - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - heth->TxDesc->Status |= ETH_DMATXDESC_OWN; - /* Point to next descriptor */ - heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); + heth->gState = HAL_ETH_STATE_BUSY; + + /* Set nombre of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + + /* Enable the DMA transmission */ + SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); + + /* Enable the DMA reception */ + SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); + + heth->gState = HAL_ETH_STATE_STARTED; + + return HAL_OK; } else { - for (i=0U; i< bufcount; i++) - { - /* Clear FIRST and LAST segment bits */ - heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); - - if (i == 0U) - { - /* Setting the first segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_FS; - } - - /* Program size */ - heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1); - - if (i == (bufcount-1U)) - { - /* Setting the last segment bit */ - heth->TxDesc->Status |= ETH_DMATXDESC_LS; - size = FrameLength - (bufcount-1U)*ETH_TX_BUF_SIZE; - heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1); - } - - /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */ - heth->TxDesc->Status |= ETH_DMATXDESC_OWN; - /* point to next descriptor */ - heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr); - } - } - - /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ - if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) - { - /* Clear TBUS ETHERNET DMA flag */ - (heth->Instance)->DMASR = ETH_DMASR_TBUS; - /* Resume DMA transmission*/ - (heth->Instance)->DMATPDR = 0U; + return HAL_ERROR; } - - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; } /** - * @brief Checks for received frames. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth) +HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth) { - uint32_t framelength = 0U; - - /* Check the ETH state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Check if segment is not owned by DMA */ - /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET)) + uint32_t tmpreg1; + + if (heth->gState == HAL_ETH_STATE_READY) { - /* Check if last segment */ - if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) - { - /* increment segment count */ - (heth->RxFrameInfos).SegCount++; - - /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos).SegCount == 1U) - { - (heth->RxFrameInfos).FSRxDesc =heth->RxDesc; - } - - heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; - heth->RxFrameInfos.length = framelength; - - /* Get the address of the buffer start address */ - heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - /* point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; - } - /* Check if first segment */ - else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) - { - (heth->RxFrameInfos).FSRxDesc = heth->RxDesc; - (heth->RxFrameInfos).LSRxDesc = NULL; - (heth->RxFrameInfos).SegCount = 1U; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - /* Check if intermediate segment */ - else - { - (heth->RxFrameInfos).SegCount++; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - } - - /* Set ETH HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_ERROR; -} + heth->gState = HAL_ETH_STATE_BUSY; -/** - * @brief Gets the Received frame in interrupt mode. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth) -{ - uint32_t descriptorscancounter = 0U; - - /* Set ETH HAL State to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Scan descriptors owned by CPU */ - while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB)) - { - /* Just for security */ - descriptorscancounter++; - - /* Check if first segment in frame */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */ - if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS) - { - heth->RxFrameInfos.FSRxDesc = heth->RxDesc; - heth->RxFrameInfos.SegCount = 1U; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - } - /* Check if intermediate segment */ - /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */ - else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET) - { - /* Increment segment count */ - (heth->RxFrameInfos.SegCount)++; - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr); - } - /* Should be last segment */ - else - { - /* Last segment */ - heth->RxFrameInfos.LSRxDesc = heth->RxDesc; - - /* Increment segment count */ - (heth->RxFrameInfos.SegCount)++; - - /* Check if last segment is first segment: one segment contains the frame */ - if ((heth->RxFrameInfos.SegCount) == 1U) - { - heth->RxFrameInfos.FSRxDesc = heth->RxDesc; + /* save IT mode to ETH Handle */ + heth->RxDescList.ItMode = 1U; + /* Disable MMC Interrupts */ + SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM); + + /* Disable Rx MMC Interrupts */ + SET_BIT(heth->Instance->MMCRIMR, ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | \ + ETH_MMCRIMR_RFCEM); + + /* Disable Tx MMC Interrupts */ + SET_BIT(heth->Instance->MMCTIMR, ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | \ + ETH_MMCTIMR_TGFSCM); + + /* Set nombre of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + + /* Enable the MAC transmission */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /* Enable the MAC reception */ + SET_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + + /* Enable the DMA transmission */ + SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); + + /* Enable the DMA reception */ + SET_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); + + /* Enable ETH DMA interrupts: + - Tx complete interrupt + - Rx complete interrupt + - Fatal bus interrupt + */ + __HAL_ETH_DMA_ENABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE | + ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE)); + + heth->gState = HAL_ETH_STATE_STARTED; + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) +{ + uint32_t tmpreg1; + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + /* Disable the DMA transmission */ + CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); + + /* Disable the DMA reception */ + CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); + + /* Disable the MAC reception */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + + /* Disable the MAC transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + heth->gState = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmarxdesc; + uint32_t descindex; + uint32_t tmpreg1; + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = HAL_ETH_STATE_BUSY; + + __HAL_ETH_DMA_DISABLE_IT(heth, (ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE | + ETH_DMAIER_FBEIE | ETH_DMAIER_AISE | ETH_DMAIER_RBUIE)); + + /* Disable the DMA transmission */ + CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_ST); + + /* Disable the DMA reception */ + CLEAR_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_SR); + + /* Disable the MAC reception */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_RE); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /* Flush Transmit FIFO */ + ETH_FlushTransmitFIFO(heth); + + /* Disable the MAC transmission */ + CLEAR_BIT(heth->Instance->MACCR, ETH_MACCR_TE); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /* Clear IOC bit to all Rx descriptors */ + for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) + { + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex]; + SET_BIT(dmarxdesc->DESC1, ETH_DMARXDESC_DIC); + } + + heth->RxDescList.ItMode = 0U; + + heth->gState = HAL_ETH_STATE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sends an Ethernet Packet in polling mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @param Timeout: timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout) +{ + uint32_t tickstart; + ETH_DMADescTypeDef *dmatxdesc; + + if (pTxConfig == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != HAL_ETH_ERROR_NONE) + { + /* Set the ETH error code */ + heth->ErrorCode |= HAL_ETH_ERROR_BUSY; + return HAL_ERROR; + } + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc]; + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + WRITE_REG(heth->Instance->DMATPDR, (uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); + + tickstart = HAL_GetTick(); + + /* Wait for data to be transmitted or timeout occurred */ + while ((dmatxdesc->DESC0 & ETH_DMATXDESC_OWN) != (uint32_t)RESET) + { + if ((heth->Instance->DMASR & ETH_DMASR_FBES) != (uint32_t)RESET) + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + heth->DMAErrorCode = heth->Instance->DMASR; + /* Return function status */ + return HAL_ERROR; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + heth->ErrorCode |= HAL_ETH_ERROR_TIMEOUT; + /* Clear TX descriptor so that we can proceed */ + dmatxdesc->DESC0 = (ETH_DMATXDESC_FS | ETH_DMATXDESC_LS); + return HAL_ERROR; + } + } + } + + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sends an Ethernet Packet in interrupt mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig) +{ + if (pTxConfig == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_STARTED) + { + /* Save the packet pointer to release. */ + heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData; + + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != HAL_ETH_ERROR_NONE) + { + heth->ErrorCode |= HAL_ETH_ERROR_BUSY; + return HAL_ERROR; + } + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + /* Clear TBUS ETHERNET DMA flag */ + (heth->Instance)->DMASR = ETH_DMASR_TBUS; + /* Resume DMA transmission*/ + (heth->Instance)->DMATPDR = 0U; + } + + return HAL_OK; + + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Read a received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pAppBuff: Pointer to an application buffer to receive the packet. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) +{ + uint32_t descidx; + ETH_DMADescTypeDef *dmarxdesc; + uint32_t desccnt = 0U; + uint32_t desccntmax; + uint32_t bufflength; + uint8_t rxdataready = 0U; + + + if (pAppBuff == NULL) + { + heth->ErrorCode |= HAL_ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState != HAL_ETH_STATE_STARTED) + { + return HAL_ERROR; + } + + descidx = heth->RxDescList.RxDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt; + + /* Check if descriptor is not owned by DMA */ + while ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (desccnt < desccntmax) + && (rxdataready == 0U)) + { + if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET) + { + /* Get timestamp high */ + heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC6; + /* Get timestamp low */ + heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC7; + } + if ((READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) || (heth->RxDescList.pRxStart != NULL)) + { + /* Check first descriptor */ + if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_FS) != (uint32_t)RESET) + { + heth->RxDescList.RxDescCnt = 0; + heth->RxDescList.RxDataLength = 0; + } + + /* Check if last descriptor */ + bufflength = heth->Init.RxBuffLen; + if (READ_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_LS) != (uint32_t)RESET) + { + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + bufflength = ((dmarxdesc->DESC0 & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; + + /* Save Last descriptor index */ + heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC0; + + /* Packet ready */ + rxdataready = 1; + } + + /* Link data */ + WRITE_REG(dmarxdesc->BackupAddr0, dmarxdesc->DESC2); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Link callback*/ + heth->rxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, bufflength); +#else + /* Link callback */ + HAL_ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + heth->RxDescList.RxDescCnt++; + heth->RxDescList.RxDataLength += bufflength; + + /* Clear buffer pointer */ + dmarxdesc->BackupAddr0 = 0; + } + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccnt++; + } + + heth->RxDescList.RxBuildDescCnt += desccnt; + if ((heth->RxDescList.RxBuildDescCnt) != 0U) + { + /* Update Descriptors */ + ETH_UpdateDescriptor(heth); + } + + heth->RxDescList.RxDescIdx = descidx; + + if (rxdataready == 1U) + { + /* Return received packet */ + *pAppBuff = heth->RxDescList.pRxStart; + /* Reset first element */ + heth->RxDescList.pRxStart = NULL; + + return HAL_OK; + } + + /* Packet not ready */ + return HAL_ERROR; +} + +/** + * @brief This function gives back Rx Desc of the last received Packet + * to the DMA, so ETH DMA will be able to use these descriptors + * to receive next Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) +{ + uint32_t descidx; + uint32_t desccount; + ETH_DMADescTypeDef *dmarxdesc; + uint8_t *buff = NULL; + uint8_t allocStatus = 1U; + + descidx = heth->RxDescList.RxBuildDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount = heth->RxDescList.RxBuildDescCnt; + + while ((desccount > 0U) && (allocStatus != 0U)) + { + /* Check if a buffer's attached the descriptor */ + if (READ_REG(dmarxdesc->BackupAddr0) == 0U) + { + /* Get a new buffer. */ +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Allocate callback*/ + heth->rxAllocateCallback(&buff); +#else + /* Allocate callback */ + HAL_ETH_RxAllocateCallback(&buff); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + if (buff == NULL) + { + allocStatus = 0U; + } + else + { + WRITE_REG(dmarxdesc->BackupAddr0, (uint32_t)buff); + WRITE_REG(dmarxdesc->DESC2, (uint32_t)buff); + } + } + + if (allocStatus != 0U) + { + if (heth->RxDescList.ItMode == 0U) + { + WRITE_REG(dmarxdesc->DESC1, ETH_DMARXDESC_DIC | ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH); + } + else + { + WRITE_REG(dmarxdesc->DESC1, ETH_RX_BUF_SIZE | ETH_DMARXDESC_RCH); + } + + /* Before transferring the ownership to DMA, make sure that the RX descriptors bits writing + is fully performed. + The __DMB() instruction is added to avoid any potential compiler optimization that + may lead to abnormal behavior. */ + __DMB(); + + SET_BIT(dmarxdesc->DESC0, ETH_DMARXDESC_OWN); + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount--; + } + } + + if (heth->RxDescList.RxBuildDescCnt != desccount) + { + /* Set the Tail pointer address */ + WRITE_REG(heth->Instance->DMARPDR, 0); + + heth->RxDescList.RxBuildDescIdx = descidx; + heth->RxDescList.RxBuildDescCnt = desccount; + } +} + +/** + * @brief Register the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxAllocateCallback: pointer to function to alloc buffer + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback) +{ + if (rxAllocateCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to allocate buffer */ + heth->rxAllocateCallback = rxAllocateCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; + + return HAL_OK; +} + +/** + * @brief Rx Allocate callback. + * @param buff: pointer to allocated buffer + * @retval None + */ +__weak void HAL_ETH_RxAllocateCallback(uint8_t **buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxAllocateCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Link callback. + * @param pStart: pointer to packet start + * @param pStart: pointer to packet end + * @param buff: pointer to received data + * @param Length: received data length + * @retval None + */ +__weak void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(pStart); + UNUSED(pEnd); + UNUSED(buff); + UNUSED(Length); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxLinkCallback could be implemented in the user file + */ +} + +/** + * @brief Set the Rx link data function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxLinkCallback: pointer to function to link data + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback) +{ + if (rxLinkCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to link data */ + heth->rxLinkCallback = rxLinkCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Rx link callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxLinkCallback = HAL_ETH_RxLinkCallback; + + return HAL_OK; +} + +/** + * @brief Get the error state of the last received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pErrorCode: pointer to uint32_t to hold the error code + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode) +{ + /* Get error bits. */ + *pErrorCode = READ_BIT(heth->RxDescList.pRxLastRxDesc, ETH_DMARXDESC_ERRORS_MASK); + + return HAL_OK; +} + +/** + * @brief Set the Tx free function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txFreeCallback: pointer to function to release the packet + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback) +{ + if (txFreeCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + + /* Set function to free transmmitted packet */ + heth->txFreeCallback = txFreeCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx free callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txFreeCallback = HAL_ETH_TxFreeCallback; + + return HAL_OK; +} + +/** + * @brief Tx Free callback. + * @param buff: pointer to buffer to free + * @retval None + */ +__weak void HAL_ETH_TxFreeCallback(uint32_t *buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxFreeCallback could be implemented in the user file + */ +} + +/** + * @brief Release transmitted Tx packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t numOfBuf = dmatxdesclist->BuffersInUse; + uint32_t idx = dmatxdesclist->releaseIndex; + uint8_t pktTxStatus = 1U; + uint8_t pktInUse; +#ifdef HAL_ETH_USE_PTP + ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp; +#endif /* HAL_ETH_USE_PTP */ + + /* Loop through buffers in use. */ + while ((numOfBuf != 0U) && (pktTxStatus != 0U)) + { + pktInUse = 1U; + numOfBuf--; + /* If no packet, just examine the next packet. */ + if (dmatxdesclist->PacketAddress[idx] == NULL) + { + /* No packet in use, skip to next. */ + idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + pktInUse = 0U; + } + + if (pktInUse != 0U) + { + /* Determine if the packet has been transmitted. */ + if ((heth->Init.TxDesc[idx].DESC0 & ETH_DMATXDESC_OWN) == 0U) + { +#ifdef HAL_ETH_USE_PTP + /* Get timestamp low */ + timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC6; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC7; +#endif /* HAL_ETH_USE_PTP */ + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered callbacks*/ +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + heth->txPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + heth->txFreeCallback(dmatxdesclist->PacketAddress[idx]); +#else + /* Call callbacks */ +#ifdef HAL_ETH_USE_PTP + /* Handle Ptp */ + HAL_ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); +#endif /* HAL_ETH_USE_PTP */ + /* Release the packet. */ + HAL_ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + /* Clear the entry in the in-use array. */ + dmatxdesclist->PacketAddress[idx] = NULL; + + /* Update the transmit relesae index and number of buffers in use. */ + idx = (idx + 1U) & (ETH_TX_DESC_CNT - 1U); + dmatxdesclist->BuffersInUse = numOfBuf; + dmatxdesclist->releaseIndex = idx; + } + else + { + /* Get out of the loop! */ + pktTxStatus = 0U; + } + } + } + return HAL_OK; +} + +#ifdef HAL_ETH_USE_PTP +/** + * @brief Set the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + uint32_t tmpTSCR; + ETH_TimeTypeDef time; + + if (ptpconfig == NULL) + { + return HAL_ERROR; + } + + tmpTSCR = ptpconfig->Timestamp | + ((uint32_t)ptpconfig->TimestampUpdate << ETH_PTPTSCR_TSFCU_Pos) | + ((uint32_t)ptpconfig->TimestampAll << ETH_PTPTSCR_TSSARFE_Pos) | + ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_PTPTSCR_TSSSR_Pos) | + ((uint32_t)ptpconfig->TimestampV2 << ETH_PTPTSCR_TSPTPPSV2E_Pos) | + ((uint32_t)ptpconfig->TimestampEthernet << ETH_PTPTSCR_TSSPTPOEFE_Pos) | + ((uint32_t)ptpconfig->TimestampIPv6 << ETH_PTPTSCR_TSSIPV6FE_Pos) | + ((uint32_t)ptpconfig->TimestampIPv4 << ETH_PTPTSCR_TSSIPV4FE_Pos) | + ((uint32_t)ptpconfig->TimestampEvent << ETH_PTPTSCR_TSSEME_Pos) | + ((uint32_t)ptpconfig->TimestampMaster << ETH_PTPTSCR_TSSMRME_Pos) | + ((uint32_t)ptpconfig->TimestampFilter << ETH_PTPTSCR_TSPFFMAE_Pos) | + ((uint32_t)ptpconfig->TimestampClockType << ETH_PTPTSCR_TSCNT_Pos); + + /* Write to MACTSCR */ + MODIFY_REG(heth->Instance->PTPTSCR, ETH_MACTSCR_MASK, tmpTSCR); + + /* Enable Timestamp */ + SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSE); + WRITE_REG(heth->Instance->PTPSSIR, ptpconfig->TimestampSubsecondInc); + WRITE_REG(heth->Instance->PTPTSAR, ptpconfig->TimestampAddend); + + /* Enable Timestamp */ + if (ptpconfig->TimestampAddendUpdate == ENABLE) + { + SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSARU); + while ((heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU) != 0) {} + } + + /* Enable Update mode */ + if (ptpconfig->TimestampUpdateMode == ENABLE) + { + SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSFCU); + } + + /* Initialize Time */ + time.Seconds = 0; + time.NanoSeconds = 0; + HAL_ETH_PTP_SetTime(heth, &time); + + /* Ptp Init */ + SET_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSTI); + + /* Set PTP Configuration done */ + heth->IsPtpConfigured = HAL_ETH_PTP_CONFIGURATED; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Get the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + if (ptpconfig == NULL) + { + return HAL_ERROR; + } + ptpconfig->Timestamp = READ_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSE); + ptpconfig->TimestampUpdate = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSFCU) >> ETH_PTPTSCR_TSFCU_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampAll = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSARFE) >> ETH_PTPTSCR_TSSARFE_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampRolloverMode = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSSR) >> ETH_PTPTSCR_TSSSR_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampV2 = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSPTPPSV2E) >> ETH_PTPTSCR_TSPTPPSV2E_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampEthernet = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSPTPOEFE) >> ETH_PTPTSCR_TSSPTPOEFE_Pos) > 0U) + ? ENABLE : DISABLE; + ptpconfig->TimestampIPv6 = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSIPV6FE) >> ETH_PTPTSCR_TSSIPV6FE_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampIPv4 = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSIPV4FE) >> ETH_PTPTSCR_TSSIPV4FE_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampEvent = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSEME) >> ETH_PTPTSCR_TSSEME_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampMaster = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSSMRME) >> ETH_PTPTSCR_TSSMRME_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampFilter = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSPFFMAE) >> ETH_PTPTSCR_TSPFFMAE_Pos) > 0U) ? ENABLE : DISABLE; + ptpconfig->TimestampClockType = ((READ_BIT(heth->Instance->PTPTSCR, + ETH_PTPTSCR_TSCNT) >> ETH_PTPTSCR_TSCNT_Pos) > 0U) ? ENABLE : DISABLE; + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Set Seconds and Nanoseconds for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param heth: pointer to a ETH_TimeTypeDef structure that contains + * time to set + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Set Seconds */ + heth->Instance->PTPTSHUR = time->Seconds; + + /* Set NanoSeconds */ + heth->Instance->PTPTSLUR = time->NanoSeconds; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get Seconds and Nanoseconds for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param heth: pointer to a ETH_TimeTypeDef structure that contains + * time to get + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get Seconds */ + time->Seconds = heth->Instance->PTPTSHR; + + /* Get NanoSeconds */ + time->NanoSeconds = heth->Instance->PTPTSLR; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Update time for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timeupdate: pointer to a ETH_TIMEUPDATETypeDef structure that contains + * the time update information + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + if (ptpoffsettype == HAL_ETH_PTP_NEGATIVE_UPDATE) + { + /* Set Seconds update */ + heth->Instance->PTPTSHUR = ETH_PTPTSHR_VALUE - timeoffset->Seconds + 1U; + + if (READ_BIT(heth->Instance->PTPTSCR, ETH_PTPTSCR_TSSSR) == ETH_PTPTSCR_TSSSR) + { + /* Set nanoSeconds update */ + heth->Instance->PTPTSLUR = ETH_PTPTSLR_VALUE - timeoffset->NanoSeconds; + } + else + { + heth->Instance->PTPTSLUR = ETH_PTPTSHR_VALUE - timeoffset->NanoSeconds + 1U; + } + } + else + { + /* Set Seconds update */ + heth->Instance->PTPTSHUR = timeoffset->Seconds; + /* Set nanoSeconds update */ + heth->Instance->PTPTSLUR = timeoffset->NanoSeconds; + } + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Insert Timestamp in transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txtimestampconf: Enable or Disable timestamp in transmission + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Enable Time Stamp transmission */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TTSE); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get transmission timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * transmission timestamp + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t idx = dmatxdesclist->releaseIndex; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx]; + + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = dmatxdesc->DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = dmatxdesc->DESC1; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Get receive timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * receive timestamp + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + if (heth->IsPtpConfigured == HAL_ETH_PTP_CONFIGURATED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh; + + /* Return function status */ + return HAL_OK; + } + else + { + /* Return function status */ + return HAL_ERROR; + } +} + +/** + * @brief Register the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txPtpCallback: Function to handle Ptp transmission + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback) +{ + if (txPtpCallback == NULL) + { + /* No buffer to save */ + return HAL_ERROR; + } + /* Set Function to handle Tx Ptp */ + heth->txPtpCallback = txPtpCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txPtpCallback = HAL_ETH_TxPtpCallback; + + return HAL_OK; +} + +/** + * @brief Tx Ptp callback. + * @param buff: pointer to application buffer + * @retval None + */ +__weak void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxPtpCallback could be implemented in the user file + */ +} +#endif /* HAL_ETH_USE_PTP */ + +/** + * @brief This function handles ETH interrupt request. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + /* Packet received */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_RS)) + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_RIE)) + { + /* Clear the Eth DMA Rx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_RS | ETH_DMASR_NIS); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Receive complete callback*/ + heth->RxCpltCallback(heth); +#else + /* Receive complete callback */ + HAL_ETH_RxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } + + /* Packet transmitted */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_TS)) + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_TIE)) + { + /* Clear the Eth DMA Tx IT pending bits */ + __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMASR_TS | ETH_DMASR_NIS); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /*Call registered Transmit complete callback*/ + heth->TxCpltCallback(heth); +#else + /* Transfer complete callback */ + HAL_ETH_TxCpltCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } + } + + + /* ETH DMA Error */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_AIS)) + { + if (__HAL_ETH_DMA_GET_IT_SOURCE(heth, ETH_DMAIER_AISE)) + { + heth->ErrorCode |= HAL_ETH_ERROR_DMA; + + /* if fatal bus error occurred */ + if (__HAL_ETH_DMA_GET_IT(heth, ETH_DMASR_FBES)) + { + /* Get DMA error code */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_FBES | ETH_DMASR_TPS | ETH_DMASR_RPS)); + + /* Disable all interrupts */ + __HAL_ETH_DMA_DISABLE_IT(heth, ETH_DMAIER_NISE | ETH_DMAIER_AISE); + + /* Set HAL state to ERROR */ + heth->gState = HAL_ETH_STATE_ERROR; + } + else + { + /* Get DMA error status */ + heth->DMAErrorCode = READ_BIT(heth->Instance->DMASR, (ETH_DMASR_ETS | ETH_DMASR_RWTS | + ETH_DMASR_RBUS | ETH_DMASR_AIS)); + + /* Clear the interrupt summary flag */ + __HAL_ETH_DMA_CLEAR_IT(heth, (ETH_DMASR_ETS | ETH_DMASR_RWTS | + ETH_DMASR_RBUS | ETH_DMASR_AIS)); } - - /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ - heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4U; - - /* Get the address of the buffer start address */ - heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr; - - /* Point to next descriptor */ - heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered Error callback*/ + heth->ErrorCallback(heth); +#else + /* Ethernet DMA Error callback */ + HAL_ETH_ErrorCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + } + } + + + /* ETH PMT IT */ + if (__HAL_ETH_MAC_GET_IT(heth, ETH_MAC_PMT_IT)) + { + /* Get MAC Wake-up source and clear the status register pending bit */ + heth->MACWakeUpEvent = READ_BIT(heth->Instance->MACPMTCSR, (ETH_MACPMTCSR_WFR | ETH_MACPMTCSR_MPR)); + +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered PMT callback*/ + heth->PMTCallback(heth); +#else + /* Ethernet PMT callback */ + HAL_ETH_PMTCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + + heth->MACWakeUpEvent = (uint32_t)(0x0U); + } + + + /* check ETH WAKEUP exti flag */ + if (__HAL_ETH_WAKEUP_EXTI_GET_FLAG(ETH_WAKEUP_EXTI_LINE) != (uint32_t)RESET) + { + /* Clear ETH WAKEUP Exti pending bit */ + __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); +#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) + /* Call registered WakeUp callback*/ + heth->WakeUpCallback(heth); +#else + /* ETH WAKEUP callback */ + HAL_ETH_WakeUpCallback(heth); +#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ + } +} + +/** + * @brief Tx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_RxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet transfer error callbacks + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet Power Management module IT callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_PMTCallback could be implemented in the user file + */ +} + + +/** + * @brief ETH WAKEUP interrupt callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +__weak void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_ETH_WakeUpCallback could be implemented in the user file + */ +} + +/** + * @brief Read a PHY register + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYAddr: PHY port address, must be a value from 0 to 31 + * @param PHYReg: PHY register address, must be a value from 0 to 31 + * @param pRegValue: parameter to hold read value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue) +{ + uint32_t tmpreg1; + uint32_t tickstart; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; + + /* Prepare the MII address register value */ + tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg1; + + + tickstart = HAL_GetTick(); + + /* Check for the Busy flag */ + while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > PHY_READ_TO) + { + return HAL_ERROR; + } + + tmpreg1 = heth->Instance->MACMIIAR; + } + + /* Get MACMIIDR value */ + *pRegValue = (uint16_t)(heth->Instance->MACMIIDR); + + return HAL_OK; +} + + +/** + * @brief Writes to a PHY register. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYAddr: PHY port address, must be a value from 0 to 31 + * @param PHYReg: PHY register address, must be a value from 0 to 31 + * @param RegValue: the value to write + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue) +{ + uint32_t tmpreg1; + uint32_t tickstart; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg1 = heth->Instance->MACMIIAR; + + /* Keep only the CSR Clock Range CR[2:0] bits value */ + tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; + + /* Prepare the MII register address value */ + tmpreg1 |= ((PHYAddr << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ + tmpreg1 |= (((uint32_t)PHYReg << 6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ + tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ + tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ + + /* Give the value to the MII data register */ + heth->Instance->MACMIIDR = (uint16_t)RegValue; + + /* Write the result value into the MII Address register */ + heth->Instance->MACMIIAR = tmpreg1; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check for the Busy flag */ + while ((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > PHY_WRITE_TO) + { + return HAL_ERROR; } + + tmpreg1 = heth->Instance->MACMIIAR; + } + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions + * @brief ETH control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the ETH + peripheral. + +@endverbatim + * @{ + */ +/** + * @brief Get the configuration of the MAC and MTL subsystems. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold + * the configuration of the MAC. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + if (macconf == NULL) + { + return HAL_ERROR; + } + + /* Get MAC parameters */ + macconf->DeferralCheck = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_DC) >> 4) > 0U) ? ENABLE : DISABLE; + macconf->BackOffLimit = READ_BIT(heth->Instance->MACCR, ETH_MACCR_BL); + macconf->RetryTransmission = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_RD) >> 9) == 0U) ? ENABLE : DISABLE; + macconf->CarrierSenseDuringTransmit = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_CSD) >> 16) > 0U) + ? ENABLE : DISABLE; + macconf->ReceiveOwn = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_ROD) >> 13) == 0U) ? ENABLE : DISABLE; + macconf->LoopbackMode = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_LM) >> 12) > 0U) ? ENABLE : DISABLE; + macconf->DuplexMode = READ_BIT(heth->Instance->MACCR, ETH_MACCR_DM); + macconf->Speed = READ_BIT(heth->Instance->MACCR, ETH_MACCR_FES); + macconf->Jabber = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_JD) >> 22) == 0U) ? ENABLE : DISABLE; + macconf->Watchdog = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_WD) >> 23) == 0U) ? ENABLE : DISABLE; + macconf->AutomaticPadCRCStrip = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_APCS) >> 7) > 0U) ? ENABLE : DISABLE; + macconf->InterPacketGapVal = READ_BIT(heth->Instance->MACCR, ETH_MACCR_IFG); + macconf->ChecksumOffload = ((READ_BIT(heth->Instance->MACCR, ETH_MACCR_IPCO) >> 10U) > 0U) ? ENABLE : DISABLE; + + + macconf->TransmitFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_TFCE) >> 1) > 0U) ? ENABLE : DISABLE; + macconf->ZeroQuantaPause = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_ZQPD) >> 7) == 0U) ? ENABLE : DISABLE; + macconf->PauseLowThreshold = READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PLT); + macconf->PauseTime = (READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_PT) >> 16); + macconf->ReceiveFlowControl = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_RFCE) >> 2U) > 0U) ? ENABLE : DISABLE; + macconf->UnicastPausePacketDetect = ((READ_BIT(heth->Instance->MACFCR, ETH_MACFCR_UPFD) >> 3U) > 0U) + ? ENABLE : DISABLE; + + return HAL_OK; +} + +/** + * @brief Get the configuration of the DMA. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold + * the configuration of the ETH DMA. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + if (dmaconf == NULL) + { + return HAL_ERROR; } - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_ERROR; + dmaconf->DMAArbitration = READ_BIT(heth->Instance->DMABMR, + (ETH_DMAARBITRATION_RXPRIORTX | ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1)); + dmaconf->AddressAlignedBeats = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_AAB) >> 25U) > 0U) ? ENABLE : DISABLE; + dmaconf->BurstMode = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_FB | ETH_DMABMR_MB); + dmaconf->RxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_RDP); + dmaconf->TxDMABurstLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_PBL); + dmaconf->EnhancedDescriptorFormat = ((READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_EDE) >> 7) > 0U) ? ENABLE : DISABLE; + dmaconf->DescriptorSkipLength = READ_BIT(heth->Instance->DMABMR, ETH_DMABMR_DSL) >> 2; + + dmaconf->DropTCPIPChecksumErrorFrame = ((READ_BIT(heth->Instance->DMAOMR, + ETH_DMAOMR_DTCEFD) >> 26) > 0U) ? DISABLE : ENABLE; + dmaconf->ReceiveStoreForward = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RSF) >> 25) > 0U) ? ENABLE : DISABLE; + dmaconf->FlushRxPacket = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_FTF) >> 20) > 0U) ? DISABLE : ENABLE; + dmaconf->TransmitStoreForward = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_TSF) >> 21) > 0U) ? ENABLE : DISABLE; + dmaconf->TransmitThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_TTC); + dmaconf->ForwardErrorFrames = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_FEF) >> 7) > 0U) ? ENABLE : DISABLE; + dmaconf->ForwardUndersizedGoodFrames = ((READ_BIT(heth->Instance->DMAOMR, + ETH_DMAOMR_FUGF) >> 6) > 0U) ? ENABLE : DISABLE; + dmaconf->ReceiveThresholdControl = READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_RTC); + dmaconf->SecondFrameOperate = ((READ_BIT(heth->Instance->DMAOMR, ETH_DMAOMR_OSF) >> 2) > 0U) ? ENABLE : DISABLE; + return HAL_OK; } /** - * @brief This function handles ETH interrupt request. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Set the MAC configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that contains + * the configuration of the MAC. * @retval HAL status */ -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth) +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) { - /* Frame received */ - if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R)) + if (macconf == NULL) { -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /*Call registered Receive complete callback*/ - heth->RxCpltCallback(heth); -#else - /* Receive complete callback */ - HAL_ETH_RxCpltCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the Eth DMA Rx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - + return HAL_ERROR; } - /* Frame transmitted */ - else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T)) - { -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - /* Call resgistered Transfer complete callback*/ - heth->TxCpltCallback(heth); -#else - /* Transfer complete callback */ - HAL_ETH_TxCpltCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - /* Clear the Eth DMA Tx IT pending bits */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T); + if (heth->gState == HAL_ETH_STATE_READY) + { + ETH_SetMACConfig(heth, macconf); - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); + return HAL_OK; } - - /* Clear the interrupt flags */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS); - - /* ETH DMA Error */ - if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS)) + else { -#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) - heth->DMAErrorCallback(heth); -#else - /* Ethernet Error callback */ - HAL_ETH_ErrorCallback(heth); -#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ - - /* Clear the interrupt flags */ - __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS); - - /* Set HAL State to Ready */ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); + return HAL_ERROR; } } /** - * @brief Tx Transfer completed callbacks. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Set the ETH DMA configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @retval None + * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold + * the configuration of the ETH DMA. + * @retval HAL status */ -__weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + if (dmaconf == NULL) + { + return HAL_ERROR; + } + + if (heth->gState == HAL_ETH_STATE_READY) + { + ETH_SetDMAConfig(heth, dmaconf); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } } /** - * @brief Rx Transfer completed callbacks. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Configures the Clock range of ETH MDIO interface. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ -__weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + uint32_t hclk; + uint32_t tmpreg; + + /* Get the ETHERNET MACMIIAR value */ + tmpreg = (heth->Instance)->MACMIIAR; + /* Clear CSR Clock Range CR[2:0] bits */ + tmpreg &= ETH_MACMIIAR_CR_MASK; + + /* Get hclk frequency value */ + hclk = HAL_RCC_GetHCLKFreq(); + + /* Set CR bits depending on hclk value */ + if ((hclk >= 20000000U) && (hclk < 35000000U)) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div16; + } + else if ((hclk >= 35000000U) && (hclk < 60000000U)) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div26; + } + else if ((hclk >= 60000000U) && (hclk < 100000000U)) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div42; + } + else if ((hclk >= 100000000U) && (hclk < 150000000U)) + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div62; + } + else /* ((hclk >= 150000000)&&(hclk <= 183000000))*/ + { + /* CSR Clock Range between 150-183 MHz */ + tmpreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; + } + + /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */ + (heth->Instance)->MACMIIAR = (uint32_t)tmpreg; } /** - * @brief Ethernet transfer error callbacks - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Set the ETH MAC (L2) Filters configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @retval None + * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains + * the configuration of the ETH MAC filters. + * @retval HAL status */ -__weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth) +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) { - /* Prevent unused argument(s) compilation warning */ - UNUSED(heth); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_ETH_TxCpltCallback could be implemented in the user file - */ + uint32_t filterconfig; + uint32_t tmpreg1; + + if (pFilterConfig == NULL) + { + return HAL_ERROR; + } + + filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode | + ((uint32_t)pFilterConfig->HashUnicast << 1) | + ((uint32_t)pFilterConfig->HashMulticast << 2) | + ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | + ((uint32_t)pFilterConfig->PassAllMulticast << 4) | + ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | + ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | + ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | + ((uint32_t)pFilterConfig->ReceiveAllMode << 31) | + pFilterConfig->ControlPacketsFilter); + + MODIFY_REG(heth->Instance->MACFFR, ETH_MACFFR_MASK, filterconfig); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFFR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFFR = tmpreg1; + + return HAL_OK; } /** - * @brief Reads a PHY register - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Basic Control Register, - * PHY_BSR: Transceiver Basic Status Register. - * More PHY register could be read depending on the used PHY - * @param RegValue PHY register value + * @brief Get the ETH MAC (L2) Filters configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold + * the configuration of the ETH MAC filters. * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) { - uint32_t tmpreg1 = 0U; - uint32_t tickstart = 0U; - - /* Check parameters */ - assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - - /* Check the ETH peripheral state */ - if(heth->State == HAL_ETH_STATE_BUSY_RD) - { - return HAL_BUSY; - } - /* Set ETH HAL State to BUSY_RD */ - heth->State = HAL_ETH_STATE_BUSY_RD; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg1 = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII address register value */ - tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */ - tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg1; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check for the Busy flag */ - while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + if (pFilterConfig == NULL) { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > PHY_READ_TO) - { - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - tmpreg1 = heth->Instance->MACMIIAR; + return HAL_ERROR; } - - /* Get MACMIIDR value */ - *RegValue = (uint16_t)(heth->Instance->MACMIIDR); - - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ + + pFilterConfig->PromiscuousMode = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PM)) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HashUnicast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HU) >> 1) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HashMulticast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HM) >> 2) > 0U) ? ENABLE : DISABLE; + pFilterConfig->DestAddrInverseFiltering = ((READ_BIT(heth->Instance->MACFFR, + ETH_MACFFR_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; + pFilterConfig->PassAllMulticast = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PAM) >> 4) > 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_BFD) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->ControlPacketsFilter = READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_PCF); + pFilterConfig->SrcAddrInverseFiltering = ((READ_BIT(heth->Instance->MACFFR, + ETH_MACFFR_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; + pFilterConfig->SrcAddrFiltering = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_SAF) >> 9) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HachOrPerfectFilter = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_HPF) >> 10) > 0U) + ? ENABLE : DISABLE; + pFilterConfig->ReceiveAllMode = ((READ_BIT(heth->Instance->MACFFR, ETH_MACFFR_RA) >> 31) > 0U) ? ENABLE : DISABLE; + return HAL_OK; } /** - * @brief Writes to a PHY register. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @param PHYReg PHY register address, is the index of one of the 32 PHY register. - * This parameter can be one of the following values: - * PHY_BCR: Transceiver Control Register. - * More PHY register could be written depending on the used PHY - * @param RegValue the value to write + * @brief Set the source MAC Address to be matched. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param AddrNbr: The MAC address to configure + * This parameter must be a value of the following: + * ETH_MAC_ADDRESS1 + * ETH_MAC_ADDRESS2 + * ETH_MAC_ADDRESS3 + * @param pMACAddr: Pointer to MAC address buffer data (6 bytes) * @retval HAL status */ -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr) { - uint32_t tmpreg1 = 0U; - uint32_t tickstart = 0U; - - /* Check parameters */ - assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress)); - - /* Check the ETH peripheral state */ - if(heth->State == HAL_ETH_STATE_BUSY_WR) - { - return HAL_BUSY; - } - /* Set ETH HAL State to BUSY_WR */ - heth->State = HAL_ETH_STATE_BUSY_WR; - - /* Get the ETHERNET MACMIIAR value */ - tmpreg1 = heth->Instance->MACMIIAR; - - /* Keep only the CSR Clock Range CR[2:0] bits value */ - tmpreg1 &= ~ETH_MACMIIAR_CR_MASK; - - /* Prepare the MII register address value */ - tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11U) & ETH_MACMIIAR_PA); /* Set the PHY device address */ - tmpreg1 |=(((uint32_t)PHYReg<<6U) & ETH_MACMIIAR_MR); /* Set the PHY register address */ - tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */ - tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */ - - /* Give the value to the MII data register */ - heth->Instance->MACMIIDR = (uint16_t)RegValue; - - /* Write the result value into the MII Address register */ - heth->Instance->MACMIIAR = tmpreg1; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Check for the Busy flag */ - while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB) + uint32_t macaddrlr; + uint32_t macaddrhr; + + if (pMACAddr == NULL) { - /* Check for the Timeout */ - if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO) - { - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - return HAL_TIMEOUT; - } - - tmpreg1 = heth->Instance->MACMIIAR; + return HAL_ERROR; } - - /* Set ETH HAL State to READY */ - heth->State = HAL_ETH_STATE_READY; - - /* Return function status */ - return HAL_OK; + + /* Get mac addr high reg offset */ + macaddrhr = ((uint32_t) &(heth->Instance->MACA0HR) + AddrNbr); + /* Get mac addr low reg offset */ + macaddrlr = ((uint32_t) &(heth->Instance->MACA0LR) + AddrNbr); + + /* Set MAC addr bits 32 to 47 */ + (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]); + /* Set MAC addr bits 0 to 31 */ + (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) | + ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]); + + /* Enable address and set source address bit */ + (*(__IO uint32_t *)macaddrhr) |= (ETH_MACA1HR_AE | ETH_MACA1HR_SA); + + return HAL_OK; } /** - * @} + * @brief Set the ETH Hash Table Value. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pHashTable: pointer to a table of two 32 bit values, that contains + * the 64 bits of the hash table. + * @retval HAL status */ +HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable) +{ + uint32_t tmpreg1; + if (pHashTable == NULL) + { + return HAL_ERROR; + } -/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Enable MAC and DMA transmission and reception. - HAL_ETH_Start(); - (+) Disable MAC and DMA transmission and reception. - HAL_ETH_Stop(); - (+) Set the MAC configuration in runtime mode - HAL_ETH_ConfigMAC(); - (+) Set the DMA configuration in runtime mode - HAL_ETH_ConfigDMA(); + heth->Instance->MACHTHR = pHashTable[0]; -@endverbatim - * @{ - */ + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACHTHR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACHTHR = tmpreg1; - /** - * @brief Enables Ethernet MAC and DMA reception/transmission - * @param heth pointer to a ETH_HandleTypeDef structure that contains + heth->Instance->MACHTLR = pHashTable[1]; + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACHTLR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACHTLR = tmpreg1; + + return HAL_OK; +} + +/** + * @brief Set the VLAN Identifier for Rx packets + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @retval HAL status + * @param ComparisonBits: 12 or 16 bit comparison mode + must be a value of @ref ETH_VLAN_Tag_Comparison + * @param VLANIdentifier: VLAN Identifier value + * @retval None */ -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth) -{ - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Enable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionEnable(heth); - - /* Enable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionEnable(heth); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Start DMA transmission */ - ETH_DMATransmissionEnable(heth); - - /* Start DMA reception */ - ETH_DMAReceptionEnable(heth); - - /* Set the ETH state to READY*/ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; +void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier) +{ + uint32_t tmpreg1; + MODIFY_REG(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTI, VLANIdentifier); + if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT) + { + CLEAR_BIT(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTC); + } + else + { + SET_BIT(heth->Instance->MACVLANTR, ETH_MACVLANTR_VLANTC); + } + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACVLANTR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACVLANTR = tmpreg1; } /** - * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Enters the Power down mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @retval HAL status + * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure + * that contains the Power Down configuration + * @retval None. */ -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth) -{ - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State = HAL_ETH_STATE_BUSY; - - /* Stop DMA transmission */ - ETH_DMATransmissionDisable(heth); - - /* Stop DMA reception */ - ETH_DMAReceptionDisable(heth); - - /* Disable receive state machine of the MAC for reception from the MII */ - ETH_MACReceptionDisable(heth); - - /* Flush Transmit FIFO */ - ETH_FlushTransmitFIFO(heth); - - /* Disable transmit state machine of the MAC for transmission on the MII */ - ETH_MACTransmissionDisable(heth); - - /* Set the ETH state*/ - heth->State = HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig) +{ + uint32_t powerdownconfig; + + powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << ETH_MACPMTCSR_MPE_Pos) | + ((uint32_t)pPowerDownConfig->WakeUpPacket << ETH_MACPMTCSR_WFE_Pos) | + ((uint32_t)pPowerDownConfig->GlobalUnicast << ETH_MACPMTCSR_GU_Pos) | + ETH_MACPMTCSR_PD); + + MODIFY_REG(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_MASK, powerdownconfig); } /** - * @brief Set ETH MAC Configuration. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Exits from the Power down mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param macconf MAC Configuration structure - * @retval HAL status + * @retval None. */ -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) +void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth) { - uint32_t tmpreg1 = 0U; - - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State= HAL_ETH_STATE_BUSY; - - assert_param(IS_ETH_SPEED(heth->Init.Speed)); - assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode)); - - if (macconf != NULL) - { - /* Check the parameters */ - assert_param(IS_ETH_WATCHDOG(macconf->Watchdog)); - assert_param(IS_ETH_JABBER(macconf->Jabber)); - assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap)); - assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense)); - assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn)); - assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode)); - assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload)); - assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission)); - assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip)); - assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit)); - assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck)); - assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll)); - assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter)); - assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames)); - assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception)); - assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter)); - assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode)); - assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter)); - assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter)); - assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime)); - assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause)); - assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold)); - assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect)); - assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl)); - assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl)); - assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison)); - assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier)); - - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg1 = (heth->Instance)->MACCR; - /* Clear WD, PCE, PS, TE and RE bits */ - tmpreg1 &= ETH_MACCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)(macconf->Watchdog | - macconf->Jabber | - macconf->InterFrameGap | - macconf->CarrierSense | - (heth->Init).Speed | - macconf->ReceiveOwn | - macconf->LoopbackMode | - (heth->Init).DuplexMode | - macconf->ChecksumOffload | - macconf->RetryTransmission | - macconf->AutomaticPadCRCStrip | - macconf->BackOffLimit | - macconf->DeferralCheck); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg1; - + uint32_t tmpreg1; + + /* clear wake up sources */ + CLEAR_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_WFE | ETH_MACPMTCSR_MPE | ETH_MACPMTCSR_GU); + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACPMTCSR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACPMTCSR = tmpreg1; + + if (READ_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_PD) != 0U) + { + /* Exit power down mode */ + CLEAR_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_PD); + /* Wait until the write operation will be taken into account : at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll | - macconf->SourceAddrFilter | - macconf->PassControlFrames | - macconf->BroadcastFramesReception | - macconf->DestinationAddrFilter | - macconf->PromiscuousMode | - macconf->MulticastFramesFilter | - macconf->UnicastFramesFilter); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFFR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg1; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/ - /* Write to ETHERNET MACHTHR */ - (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration --------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg1 = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - - tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | - macconf->ZeroQuantaPause | - macconf->PauseLowThreshold | - macconf->UnicastPauseFrameDetect | - macconf->ReceiveFlowControl | - macconf->TransmitFlowControl); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg1; - - /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/ - (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison | - macconf->VLANTagIdentifier); - - /* Wait until the write operation will be taken into account : - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACVLANTR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg1; - } - else /* macconf == NULL : here we just configure Speed and Duplex mode */ - { - /*------------------------ ETHERNET MACCR Configuration --------------------*/ - /* Get the ETHERNET MACCR value */ - tmpreg1 = (heth->Instance)->MACCR; - - /* Clear FES and DM bits */ - tmpreg1 &= ~(0x00004800U); - - tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode); - - /* Write to ETHERNET MACCR */ - (heth->Instance)->MACCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; + tmpreg1 = (heth->Instance)->MACPMTCSR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; + (heth->Instance)->MACPMTCSR = tmpreg1; } - - /* Set the ETH state to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; + + /* Disable PMT interrupt */ + SET_BIT(heth->Instance->MACIMR, ETH_MACIMR_PMTIM); } /** - * @brief Sets ETH DMA Configuration. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Set the WakeUp filter. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param dmaconf DMA Configuration structure - * @retval HAL status + * @param pFilter: pointer to filter registers values + * @param Count: number of filter registers, must be from 1 to 8. + * @retval None. */ -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) +HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count) { - uint32_t tmpreg1 = 0U; + uint32_t regindex; - /* Process Locked */ - __HAL_LOCK(heth); - - /* Set the ETH peripheral state to BUSY */ - heth->State= HAL_ETH_STATE_BUSY; - - /* Check parameters */ - assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame)); - assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward)); - assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame)); - assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward)); - assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl)); - assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames)); - assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames)); - assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl)); - assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate)); - assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats)); - assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst)); - assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength)); - assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength)); - assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat)); - assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength)); - assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration)); - - /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ - /* Get the ETHERNET DMAOMR value */ - tmpreg1 = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; + if (pFilter == NULL) + { + return HAL_ERROR; + } - tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame | - dmaconf->ReceiveStoreForward | - dmaconf->FlushReceivedFrame | - dmaconf->TransmitStoreForward | - dmaconf->TransmitThresholdControl | - dmaconf->ForwardErrorFrames | - dmaconf->ForwardUndersizedGoodFrames | - dmaconf->ReceiveThresholdControl | - dmaconf->SecondFrameOperate); + /* Reset Filter Pointer */ + SET_BIT(heth->Instance->MACPMTCSR, ETH_MACPMTCSR_WFFRPR); - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; + /* Wake up packet filter config */ + for (regindex = 0; regindex < Count; regindex++) + { + /* Write filter regs */ + WRITE_REG(heth->Instance->MACRWUFFR, pFilter[regindex]); + } - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg1; + return HAL_OK; +} - /*----------------------- ETHERNET DMABMR Configuration --------------------*/ - (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats | - dmaconf->FixedBurst | - dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmaconf->TxDMABurstLength | - dmaconf->EnhancedDescriptorFormat | - (dmaconf->DescriptorSkipLength << 2U) | - dmaconf->DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMABMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg1; - - /* Set the ETH state to Ready */ - heth->State= HAL_ETH_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(heth); - - /* Return function status */ - return HAL_OK; +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief ETH State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + ETH communication process, return Peripheral Errors occurred during communication + process + + +@endverbatim + * @{ + */ + +/** + * @brief Returns the ETH state. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL state + */ +HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) +{ + return heth->gState; } /** - * @} + * @brief Returns the ETH error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH Error Code */ +uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth) +{ + return heth->ErrorCode; +} -/** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * - @verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - (+) Get the ETH handle state: - HAL_ETH_GetState(); - +/** + * @brief Returns the ETH DMA error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH DMA Error Code + */ +uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth) +{ + return heth->DMAErrorCode; +} - @endverbatim - * @{ +/** + * @brief Returns the ETH MAC error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval ETH MAC Error Code */ +uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth) +{ + return heth->MACErrorCode; +} /** - * @brief Return the ETH HAL state - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Returns the ETH MAC WakeUp event source + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @retval HAL state + * @retval ETH MAC WakeUp event source */ -HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth) -{ - /* Return ETH state */ - return heth->State; +uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth) +{ + return heth->MACWakeUpEvent; } /** * @} */ - + /** * @} */ - -/** @addtogroup ETH_Private_Functions + +/** @addtogroup ETH_Private_Functions ETH Private Functions * @{ */ /** - * @brief Configures Ethernet MAC and DMA with default parameters. + * @brief Clears the ETHERNET transmit FIFO. * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param err Ethernet Init error - * @retval HAL status + * @retval None */ -static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) +static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) { - ETH_MACInitTypeDef macinit; - ETH_DMAInitTypeDef dmainit; - uint32_t tmpreg1 = 0U; - - if (err != ETH_SUCCESS) /* Auto-negotiation failed */ - { - /* Set Ethernet duplex mode to Full-duplex */ - (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX; - - /* Set Ethernet speed to 100M */ - (heth->Init).Speed = ETH_SPEED_100M; - } - - /* Ethernet MAC default initialization **************************************/ - macinit.Watchdog = ETH_WATCHDOG_ENABLE; - macinit.Jabber = ETH_JABBER_ENABLE; - macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT; - macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE; - macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE; - macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE; - if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE) - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE; - } - else - { - macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE; - } - macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE; - macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE; - macinit.BackOffLimit = ETH_BACKOFFLIMIT_10; - macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE; - macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE; - macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE; - macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL; - macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE; - macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL; - macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE; - macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT; - macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT; - macinit.HashTableHigh = 0x0U; - macinit.HashTableLow = 0x0U; - macinit.PauseTime = 0x0U; - macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE; - macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; - macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE; - macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE; - macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE; - macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT; - macinit.VLANTagIdentifier = 0x0U; - + __IO uint32_t tmpreg = 0; + + /* Set the Flush Transmit FIFO bit */ + (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg = (heth->Instance)->DMAOMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg; +} + +static void ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + uint32_t tmpreg1; + /*------------------------ ETHERNET MACCR Configuration --------------------*/ /* Get the ETHERNET MACCR value */ tmpreg1 = (heth->Instance)->MACCR; /* Clear WD, PCE, PS, TE and RE bits */ tmpreg1 &= ETH_MACCR_CLEAR_MASK; - /* Set the WD bit according to ETH Watchdog value */ - /* Set the JD: bit according to ETH Jabber value */ - /* Set the IFG bit according to ETH InterFrameGap value */ - /* Set the DCRS bit according to ETH CarrierSense value */ - /* Set the FES bit according to ETH Speed value */ - /* Set the DO bit according to ETH ReceiveOwn value */ - /* Set the LM bit according to ETH LoopbackMode value */ - /* Set the DM bit according to ETH Mode value */ - /* Set the IPCO bit according to ETH ChecksumOffload value */ - /* Set the DR bit according to ETH RetryTransmission value */ - /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */ - /* Set the BL bit according to ETH BackOffLimit value */ - /* Set the DC bit according to ETH DeferralCheck value */ - tmpreg1 |= (uint32_t)(macinit.Watchdog | - macinit.Jabber | - macinit.InterFrameGap | - macinit.CarrierSense | - (heth->Init).Speed | - macinit.ReceiveOwn | - macinit.LoopbackMode | - (heth->Init).DuplexMode | - macinit.ChecksumOffload | - macinit.RetryTransmission | - macinit.AutomaticPadCRCStrip | - macinit.BackOffLimit | - macinit.DeferralCheck); - + + tmpreg1 |= (uint32_t)(((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 23U) | + ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 22U) | + (uint32_t)macconf->InterPacketGapVal | + ((uint32_t)macconf->CarrierSenseDuringTransmit << 16U) | + macconf->Speed | + ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 13U) | + ((uint32_t)macconf->LoopbackMode << 12U) | + macconf->DuplexMode | + ((uint32_t)macconf->ChecksumOffload << 10U) | + ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 9U) | + ((uint32_t)macconf->AutomaticPadCRCStrip << 7U) | + macconf->BackOffLimit | + ((uint32_t)macconf->DeferralCheck << 4U)); + /* Write to ETHERNET MACCR */ (heth->Instance)->MACCR = (uint32_t)tmpreg1; - + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACCR = tmpreg1; + + /*----------------------- ETHERNET MACFCR Configuration --------------------*/ + + /* Get the ETHERNET MACFCR value */ + tmpreg1 = (heth->Instance)->MACFCR; + /* Clear xx bits */ + tmpreg1 &= ETH_MACFCR_CLEAR_MASK; + + tmpreg1 |= (uint32_t)((macconf->PauseTime << 16U) | + ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7U) | + macconf->PauseLowThreshold | + ((uint32_t)((macconf->UnicastPausePacketDetect == ENABLE) ? 1U : 0U) << 3U) | + ((uint32_t)((macconf->ReceiveFlowControl == ENABLE) ? 1U : 0U) << 2U) | + ((uint32_t)((macconf->TransmitFlowControl == ENABLE) ? 1U : 0U) << 1U)); + + /* Write to ETHERNET MACFCR */ + (heth->Instance)->MACFCR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account : + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->MACFCR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->MACFCR = tmpreg1; +} + +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + uint32_t tmpreg1; + + /*----------------------- ETHERNET DMAOMR Configuration --------------------*/ + /* Get the ETHERNET DMAOMR value */ + tmpreg1 = (heth->Instance)->DMAOMR; + /* Clear xx bits */ + tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; + + tmpreg1 |= (uint32_t)(((uint32_t)((dmaconf->DropTCPIPChecksumErrorFrame == DISABLE) ? 1U : 0U) << 26U) | + ((uint32_t)dmaconf->ReceiveStoreForward << 25U) | + ((uint32_t)((dmaconf->FlushRxPacket == DISABLE) ? 1U : 0U) << 20U) | + ((uint32_t)dmaconf->TransmitStoreForward << 21U) | + dmaconf->TransmitThresholdControl | + ((uint32_t)dmaconf->ForwardErrorFrames << 7U) | + ((uint32_t)dmaconf->ForwardUndersizedGoodFrames << 6U) | + dmaconf->ReceiveThresholdControl | + ((uint32_t)dmaconf->SecondFrameOperate << 2U)); + + /* Write to ETHERNET DMAOMR */ + (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; + + /* Wait until the write operation will be taken into account: + at least four TX_CLK/RX_CLK clock cycles */ + tmpreg1 = (heth->Instance)->DMAOMR; + HAL_Delay(ETH_REG_WRITE_DELAY); + (heth->Instance)->DMAOMR = tmpreg1; + + /*----------------------- ETHERNET DMABMR Configuration --------------------*/ + (heth->Instance)->DMABMR = (uint32_t)(((uint32_t)dmaconf->AddressAlignedBeats << 25U) | + dmaconf->BurstMode | + dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or + Rx it is applied for the other */ + dmaconf->TxDMABurstLength | + ((uint32_t)dmaconf->EnhancedDescriptorFormat << 7U) | + (dmaconf->DescriptorSkipLength << 2U) | + dmaconf->DMAArbitration | + ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ + /* Wait until the write operation will be taken into account: at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; + tmpreg1 = (heth->Instance)->DMABMR; HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; - - /*----------------------- ETHERNET MACFFR Configuration --------------------*/ - /* Set the RA bit according to ETH ReceiveAll value */ - /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */ - /* Set the PCF bit according to ETH PassControlFrames value */ - /* Set the DBF bit according to ETH BroadcastFramesReception value */ - /* Set the DAIF bit according to ETH DestinationAddrFilter value */ - /* Set the PR bit according to ETH PromiscuousMode value */ - /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */ - /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */ - /* Write to ETHERNET MACFFR */ - (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll | - macinit.SourceAddrFilter | - macinit.PassControlFrames | - macinit.BroadcastFramesReception | - macinit.DestinationAddrFilter | - macinit.PromiscuousMode | - macinit.MulticastFramesFilter | - macinit.UnicastFramesFilter); - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFFR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFFR = tmpreg1; - - /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/ - /* Write to ETHERNET MACHTHR */ - (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh; - - /* Write to ETHERNET MACHTLR */ - (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow; - /*----------------------- ETHERNET MACFCR Configuration -------------------*/ - - /* Get the ETHERNET MACFCR value */ - tmpreg1 = (heth->Instance)->MACFCR; - /* Clear xx bits */ - tmpreg1 &= ETH_MACFCR_CLEAR_MASK; - - /* Set the PT bit according to ETH PauseTime value */ - /* Set the DZPQ bit according to ETH ZeroQuantaPause value */ - /* Set the PLT bit according to ETH PauseLowThreshold value */ - /* Set the UP bit according to ETH UnicastPauseFrameDetect value */ - /* Set the RFE bit according to ETH ReceiveFlowControl value */ - /* Set the TFE bit according to ETH TransmitFlowControl value */ - tmpreg1 |= (uint32_t)((macinit.PauseTime << 16U) | - macinit.ZeroQuantaPause | - macinit.PauseLowThreshold | - macinit.UnicastPauseFrameDetect | - macinit.ReceiveFlowControl | - macinit.TransmitFlowControl); - - /* Write to ETHERNET MACFCR */ - (heth->Instance)->MACFCR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACFCR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACFCR = tmpreg1; - - /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/ - /* Set the ETV bit according to ETH VLANTagComparison value */ - /* Set the VL bit according to ETH VLANTagIdentifier value */ - (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison | - macinit.VLANTagIdentifier); - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACVLANTR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACVLANTR = tmpreg1; - - /* Ethernet DMA default initialization ************************************/ - dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE; - dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE; - dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE; - dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE; - dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; - dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE; - dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE; - dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; - dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE; - dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE; - dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE; - dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; - dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; - dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE; - dmainit.DescriptorSkipLength = 0x0U; - dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; - - /* Get the ETHERNET DMAOMR value */ - tmpreg1 = (heth->Instance)->DMAOMR; - /* Clear xx bits */ - tmpreg1 &= ETH_DMAOMR_CLEAR_MASK; - - /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */ - /* Set the RSF bit according to ETH ReceiveStoreForward value */ - /* Set the DFF bit according to ETH FlushReceivedFrame value */ - /* Set the TSF bit according to ETH TransmitStoreForward value */ - /* Set the TTC bit according to ETH TransmitThresholdControl value */ - /* Set the FEF bit according to ETH ForwardErrorFrames value */ - /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */ - /* Set the RTC bit according to ETH ReceiveThresholdControl value */ - /* Set the OSF bit according to ETH SecondFrameOperate value */ - tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame | - dmainit.ReceiveStoreForward | - dmainit.FlushReceivedFrame | - dmainit.TransmitStoreForward | - dmainit.TransmitThresholdControl | - dmainit.ForwardErrorFrames | - dmainit.ForwardUndersizedGoodFrames | - dmainit.ReceiveThresholdControl | - dmainit.SecondFrameOperate); - - /* Write to ETHERNET DMAOMR */ - (heth->Instance)->DMAOMR = (uint32_t)tmpreg1; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMAOMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg1; - - /*----------------------- ETHERNET DMABMR Configuration ------------------*/ - /* Set the AAL bit according to ETH AddressAlignedBeats value */ - /* Set the FB bit according to ETH FixedBurst value */ - /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */ - /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */ - /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/ - /* Set the DSL bit according to ETH DesciptorSkipLength value */ - /* Set the PR and DA bits according to ETH DMAArbitration value */ - (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats | - dmainit.FixedBurst | - dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */ - dmainit.TxDMABurstLength | - dmainit.EnhancedDescriptorFormat | - (dmainit.DescriptorSkipLength << 2U) | - dmainit.DMAArbitration | - ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */ - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMABMR; - HAL_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMABMR = tmpreg1; - - if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE) - { - /* Enable the Ethernet Rx Interrupt */ - __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R); - } - - /* Initialize MAC address in ethernet MAC */ - ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr); + (heth->Instance)->DMABMR = tmpreg1; +} + +/** + * @brief Configures Ethernet MAC and DMA with default parameters. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL status + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) +{ + ETH_MACConfigTypeDef macDefaultConf; + ETH_DMAConfigTypeDef dmaDefaultConf; + + /*--------------- ETHERNET MAC registers default Configuration --------------*/ + macDefaultConf.Watchdog = ENABLE; + macDefaultConf.Jabber = ENABLE; + macDefaultConf.InterPacketGapVal = ETH_INTERFRAMEGAP_96BIT; + macDefaultConf.CarrierSenseDuringTransmit = DISABLE; + macDefaultConf.ReceiveOwn = ENABLE; + macDefaultConf.LoopbackMode = DISABLE; + macDefaultConf.ChecksumOffload = ENABLE; + macDefaultConf.RetryTransmission = DISABLE; + macDefaultConf.AutomaticPadCRCStrip = DISABLE; + macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; + macDefaultConf.DeferralCheck = DISABLE; + macDefaultConf.PauseTime = 0x0U; + macDefaultConf.ZeroQuantaPause = DISABLE; + macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4; + macDefaultConf.ReceiveFlowControl = DISABLE; + macDefaultConf.TransmitFlowControl = DISABLE; + macDefaultConf.Speed = ETH_SPEED_100M; + macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; + macDefaultConf.UnicastPausePacketDetect = DISABLE; + + /* MAC default configuration */ + ETH_SetMACConfig(heth, &macDefaultConf); + + /*--------------- ETHERNET DMA registers default Configuration --------------*/ + dmaDefaultConf.DropTCPIPChecksumErrorFrame = ENABLE; + dmaDefaultConf.ReceiveStoreForward = ENABLE; + dmaDefaultConf.FlushRxPacket = ENABLE; + dmaDefaultConf.TransmitStoreForward = ENABLE; + dmaDefaultConf.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES; + dmaDefaultConf.ForwardErrorFrames = DISABLE; + dmaDefaultConf.ForwardUndersizedGoodFrames = DISABLE; + dmaDefaultConf.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES; + dmaDefaultConf.SecondFrameOperate = ENABLE; + dmaDefaultConf.AddressAlignedBeats = ENABLE; + dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; + dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + dmaDefaultConf.EnhancedDescriptorFormat = ENABLE; + dmaDefaultConf.DescriptorSkipLength = 0x0U; + dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1; + + /* DMA default configuration */ + ETH_SetDMAConfig(heth, &dmaDefaultConf); } /** @@ -2060,8 +2899,8 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) * the configuration information for ETHERNET module * @param MacAddr The MAC address to configure * This parameter can be one of the following values: - * @arg ETH_MAC_Address0: MAC Address0 - * @arg ETH_MAC_Address1: MAC Address1 + * @arg ETH_MAC_Address0: MAC Address0 + * @arg ETH_MAC_Address1: MAC Address1 * @arg ETH_MAC_Address2: MAC Address2 * @arg ETH_MAC_Address3: MAC Address3 * @param Addr Pointer to MAC address buffer data (6 bytes) @@ -2070,194 +2909,296 @@ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) { uint32_t tmpreg1; - + /* Prevent unused argument(s) compilation warning */ UNUSED(heth); - /* Check the parameters */ - assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr)); - /* Calculate the selected MAC address high register */ tmpreg1 = ((uint32_t)Addr[5U] << 8U) | (uint32_t)Addr[4U]; /* Load the selected MAC address high register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1; /* Calculate the selected MAC address low register */ tmpreg1 = ((uint32_t)Addr[3U] << 24U) | ((uint32_t)Addr[2U] << 16U) | ((uint32_t)Addr[1U] << 8U) | Addr[0U]; - + /* Load the selected MAC address low register */ (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1; } /** - * @brief Enables the MAC transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module + * @brief Initializes the DMA Tx descriptors. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module * @retval None */ -static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; - - /* Enable the MAC transmission */ - (heth->Instance)->MACCR |= ETH_MACCR_TE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmatxdesc; + uint32_t i; -/** - * @brief Disables the MAC transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; - - /* Disable the MAC transmission */ - (heth->Instance)->MACCR &= ~ETH_MACCR_TE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) + { + dmatxdesc = heth->Init.TxDesc + i; -/** - * @brief Enables the MAC reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; - - /* Enable the MAC reception */ - (heth->Instance)->MACCR |= ETH_MACCR_RE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} + WRITE_REG(dmatxdesc->DESC0, 0x0); + WRITE_REG(dmatxdesc->DESC1, 0x0); + WRITE_REG(dmatxdesc->DESC2, 0x0); + WRITE_REG(dmatxdesc->DESC3, 0x0); -/** - * @brief Disables the MAC reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth) -{ - __IO uint32_t tmpreg1 = 0U; - - /* Disable the MAC reception */ - (heth->Instance)->MACCR &= ~ETH_MACCR_RE; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->MACCR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->MACCR = tmpreg1; -} + WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); -/** - * @brief Enables the DMA transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth) -{ - /* Enable the DMA transmission */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST; -} + /* Set Second Address Chained bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_TCH); -/** - * @brief Disables the DMA transmission. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth) -{ - /* Disable the DMA transmission */ - (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST; -} + if (i < ((uint32_t)ETH_TX_DESC_CNT - 1U)) + { + WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc + i + 1U)); + } + else + { + WRITE_REG(dmatxdesc->DESC3, (uint32_t)(heth->Init.TxDesc)); + } -/** - * @brief Enables the DMA reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth) -{ - /* Enable the DMA reception */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR; -} + /* Set the DMA Tx descriptors checksum insertion */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL); + } -/** - * @brief Disables the DMA reception. - * @param heth pointer to a ETH_HandleTypeDef structure that contains - * the configuration information for ETHERNET module - * @retval None - */ -static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth) -{ - /* Disable the DMA reception */ - (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR; + heth->TxDescList.CurTxDesc = 0; + + /* Set Transmit Descriptor List Address */ + WRITE_REG(heth->Instance->DMATDLAR, (uint32_t) heth->Init.TxDesc); } /** - * @brief Clears the ETHERNET transmit FIFO. - * @param heth pointer to a ETH_HandleTypeDef structure that contains + * @brief Initializes the DMA Rx descriptors in chain mode. + * called by HAL_ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ -static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth) +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) { - __IO uint32_t tmpreg1 = 0U; - - /* Set the Flush Transmit FIFO bit */ - (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF; - - /* Wait until the write operation will be taken into account: - at least four TX_CLK/RX_CLK clock cycles */ - tmpreg1 = (heth->Instance)->DMAOMR; - ETH_Delay(ETH_REG_WRITE_DELAY); - (heth->Instance)->DMAOMR = tmpreg1; + ETH_DMADescTypeDef *dmarxdesc; + uint32_t i; + + for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) + { + dmarxdesc = heth->Init.RxDesc + i; + + WRITE_REG(dmarxdesc->DESC0, 0x0); + WRITE_REG(dmarxdesc->DESC1, 0x0); + WRITE_REG(dmarxdesc->DESC2, 0x0); + WRITE_REG(dmarxdesc->DESC3, 0x0); + WRITE_REG(dmarxdesc->BackupAddr0, 0x0); + WRITE_REG(dmarxdesc->BackupAddr1, 0x0); + + /* Set Own bit of the Rx descriptor Status */ + dmarxdesc->DESC0 = ETH_DMARXDESC_OWN; + + /* Set Buffer1 size and Second Address Chained bit */ + dmarxdesc->DESC1 = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE; + + /* Enable Ethernet DMA Rx Descriptor interrupt */ + dmarxdesc->DESC1 &= ~ETH_DMARXDESC_DIC; + + /* Set Rx descritors addresses */ + WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); + + if (i < ((uint32_t)ETH_RX_DESC_CNT - 1U)) + { + WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc + i + 1U)); + } + else + { + WRITE_REG(dmarxdesc->DESC3, (uint32_t)(heth->Init.RxDesc)); + } + } + + WRITE_REG(heth->RxDescList.RxDescIdx, 0); + WRITE_REG(heth->RxDescList.RxDescCnt, 0); + WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0); + WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0); + WRITE_REG(heth->RxDescList.ItMode, 0); + + /* Set Receive Descriptor List Address */ + WRITE_REG(heth->Instance->DMARDLAR, (uint32_t) heth->Init.RxDesc); } /** - * @brief This function provides delay (in milliseconds) based on CPU cycles method. - * @param mdelay specifies the delay time length, in milliseconds. - * @retval None + * @brief Prepare Tx DMA descriptor before transmission. + * called by HAL_ETH_Transmit_IT and HAL_ETH_Transmit_IT() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Tx packet configuration + * @param ItMode: Enable or disable Tx EOT interrept + * @retval Status */ -static void ETH_Delay(uint32_t mdelay) +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t ItMode) { - __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U); - do + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + uint32_t firstdescidx = dmatxdesclist->CurTxDesc; + uint32_t idx; + uint32_t descnbr = 0; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; + uint32_t bd_count = 0; + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + { + return HAL_ETH_ERROR_BUSY; + } + + + descnbr += 1U; + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); + + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC1, ETH_DMATXDESC_TBS1, txbuffer->len); + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != 0U) + { + MODIFY_REG(dmatxdesc->DESC0, ETH_DMATXDESC_CIC, pTxConfig->ChecksumCtrl); + } + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != 0U) + { + MODIFY_REG(dmatxdesc->DESC0, ETH_CRC_PAD_DISABLE, pTxConfig->CRCPadCtrl); + } + + + if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_VLANTAG) != 0U) + { + /* Set Vlan Type */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_VF); + } + + /* Mark it as First Descriptor */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS); + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* set OWN bit of FIRST descriptor */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); + + /* only if the packet is split into more than one descriptors > 1 */ + while (txbuffer->next != NULL) + { + /* Clear the LD bit of previous descriptor */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS); + if (ItMode != ((uint32_t)RESET)) + { + /* Set Interrupt on completion bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + } + else + { + /* Clear Interrupt on completion bit */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + } + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + /* Clear the FD bit of new Descriptor */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_FS); + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((READ_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN) == ETH_DMATXDESC_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + { + descidx = firstdescidx; + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + /* clear previous desc own bit */ + for (idx = 0; idx < descnbr; idx ++) + { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); + + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + } + + return HAL_ETH_ERROR_BUSY; + } + + descnbr += 1U; + + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC2, (uint32_t)txbuffer->buffer); + + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC1, ETH_DMATXDESC_TBS1, txbuffer->len); + + bd_count += 1U; + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set Own bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_OWN); + } + + if (ItMode != ((uint32_t)RESET)) { - __NOP(); - } - while (Delay --); + /* Set Interrupt on completion bit */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + } + else + { + /* Clear Interrupt on completion bit */ + CLEAR_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_IC); + } + + /* Mark it as LAST descriptor */ + SET_BIT(dmatxdesc->DESC0, ETH_DMATXDESC_LS); + /* Save the current packet address to expose it to the application */ + dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; + + dmatxdesclist->CurTxDesc = descidx; + + /* disable the interrupt */ + __disable_irq(); + + dmatxdesclist->BuffersInUse += bd_count + 1U; + + /* Enable interrupts back */ + __enable_irq(); + + + /* Return function status */ + return HAL_ETH_ERROR_NONE; } #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) { /* Init the ETH Callback settings */ - heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ - heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ - heth->DMAErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak DMAErrorCallback */ + heth->TxCpltCallback = HAL_ETH_TxCpltCallback; /* Legacy weak TxCpltCallback */ + heth->RxCpltCallback = HAL_ETH_RxCpltCallback; /* Legacy weak RxCpltCallback */ + heth->ErrorCallback = HAL_ETH_ErrorCallback; /* Legacy weak ErrorCallback */ + heth->PMTCallback = HAL_ETH_PMTCallback; /* Legacy weak PMTCallback */ + heth->WakeUpCallback = HAL_ETH_WakeUpCallback; /* Legacy weak WakeUpCallback */ + heth->rxLinkCallback = HAL_ETH_RxLinkCallback; /* Legacy weak RxLinkCallback */ + heth->txFreeCallback = HAL_ETH_TxFreeCallback; /* Legacy weak TxFreeCallback */ +#ifdef HAL_ETH_USE_PTP + heth->txPtpCallback = HAL_ETH_TxPtpCallback; /* Legacy weak TxPtpCallback */ +#endif /* HAL_ETH_USE_PTP */ + heth->rxAllocateCallback = HAL_ETH_RxAllocateCallback; /* Legacy weak RxAllocateCallback */ } #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ @@ -2265,15 +3206,15 @@ static void ETH_InitCallbacksToDefault(ETH_HandleTypeDef *heth) * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ - STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ -#endif /* HAL_ETH_MODULE_ENABLED */ /** * @} */ +#endif /* ETH */ + +#endif /* HAL_ETH_MODULE_ENABLED */ + /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.h index a0b0ad32078..ba5a09bbc88 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_eth.h @@ -6,641 +6,586 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_ETH_H -#define __STM32F4xx_HAL_ETH_H +#ifndef STM32F4xx_HAL_ETH_H +#define STM32F4xx_HAL_ETH_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ - defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" +#if defined(ETH) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ /** @addtogroup ETH * @{ - */ - -/** @addtogroup ETH_Private_Macros - * @{ - */ -#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) -#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ - ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) -#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ - ((SPEED) == ETH_SPEED_100M)) -#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ - ((MODE) == ETH_MODE_HALFDUPLEX)) -#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ - ((MODE) == ETH_RXINTERRUPT_MODE)) -#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ - ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) -#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ - ((MODE) == ETH_MEDIA_INTERFACE_RMII)) -#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ - ((CMD) == ETH_WATCHDOG_DISABLE)) -#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ - ((CMD) == ETH_JABBER_DISABLE)) -#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ - ((GAP) == ETH_INTERFRAMEGAP_40BIT)) -#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ - ((CMD) == ETH_CARRIERSENCE_DISABLE)) -#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ - ((CMD) == ETH_RECEIVEOWN_DISABLE)) -#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ - ((CMD) == ETH_LOOPBACKMODE_DISABLE)) -#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ - ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) -#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ - ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) -#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ - ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) -#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ - ((LIMIT) == ETH_BACKOFFLIMIT_1)) -#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ - ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) -#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ - ((CMD) == ETH_RECEIVEAll_DISABLE)) -#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ - ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) -#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ - ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) -#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ - ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) -#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ - ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) -#define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ - ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) -#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ - ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) -#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ - ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) -#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) -#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ - ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) -#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ - ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) -#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ - ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) -#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) -#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ - ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) -#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ - ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) -#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) -#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ - ((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ - ((ADDRESS) == ETH_MAC_ADDRESS2) || \ - ((ADDRESS) == ETH_MAC_ADDRESS3)) -#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ - ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) -#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ - ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) -#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ - ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) -#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) -#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ - ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) -#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ - ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) -#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ - ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) -#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) -#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ - ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) -#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ - ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) -#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ - ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) -#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ - ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) -#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ - ((CMD) == ETH_FIXEDBURST_DISABLE)) -#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ - ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) -#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) -#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ - ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ - ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) -#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ - ((FLAG) == ETH_DMATXDESC_IC) || \ - ((FLAG) == ETH_DMATXDESC_LS) || \ - ((FLAG) == ETH_DMATXDESC_FS) || \ - ((FLAG) == ETH_DMATXDESC_DC) || \ - ((FLAG) == ETH_DMATXDESC_DP) || \ - ((FLAG) == ETH_DMATXDESC_TTSE) || \ - ((FLAG) == ETH_DMATXDESC_TER) || \ - ((FLAG) == ETH_DMATXDESC_TCH) || \ - ((FLAG) == ETH_DMATXDESC_TTSS) || \ - ((FLAG) == ETH_DMATXDESC_IHE) || \ - ((FLAG) == ETH_DMATXDESC_ES) || \ - ((FLAG) == ETH_DMATXDESC_JT) || \ - ((FLAG) == ETH_DMATXDESC_FF) || \ - ((FLAG) == ETH_DMATXDESC_PCE) || \ - ((FLAG) == ETH_DMATXDESC_LCA) || \ - ((FLAG) == ETH_DMATXDESC_NC) || \ - ((FLAG) == ETH_DMATXDESC_LCO) || \ - ((FLAG) == ETH_DMATXDESC_EC) || \ - ((FLAG) == ETH_DMATXDESC_VF) || \ - ((FLAG) == ETH_DMATXDESC_CC) || \ - ((FLAG) == ETH_DMATXDESC_ED) || \ - ((FLAG) == ETH_DMATXDESC_UF) || \ - ((FLAG) == ETH_DMATXDESC_DB)) -#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ - ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) -#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ - ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) -#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) -#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ - ((FLAG) == ETH_DMARXDESC_AFM) || \ - ((FLAG) == ETH_DMARXDESC_ES) || \ - ((FLAG) == ETH_DMARXDESC_DE) || \ - ((FLAG) == ETH_DMARXDESC_SAF) || \ - ((FLAG) == ETH_DMARXDESC_LE) || \ - ((FLAG) == ETH_DMARXDESC_OE) || \ - ((FLAG) == ETH_DMARXDESC_VLAN) || \ - ((FLAG) == ETH_DMARXDESC_FS) || \ - ((FLAG) == ETH_DMARXDESC_LS) || \ - ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ - ((FLAG) == ETH_DMARXDESC_LC) || \ - ((FLAG) == ETH_DMARXDESC_FT) || \ - ((FLAG) == ETH_DMARXDESC_RWT) || \ - ((FLAG) == ETH_DMARXDESC_RE) || \ - ((FLAG) == ETH_DMARXDESC_DBE) || \ - ((FLAG) == ETH_DMARXDESC_CE) || \ - ((FLAG) == ETH_DMARXDESC_MAMPCE)) -#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ - ((BUFFER) == ETH_DMARXDESC_BUFFER2)) -#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ - ((FLAG) == ETH_PMT_FLAG_MPR)) -#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) -#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ - ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ - ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ - ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ - ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ - ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ - ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ - ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ - ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ - ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ - ((FLAG) == ETH_DMA_FLAG_T)) -#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) -#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ - ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ - ((IT) == ETH_MAC_IT_PMT)) -#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ - ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ - ((FLAG) == ETH_MAC_FLAG_PMT)) -#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) -#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ - ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ - ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ - ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ - ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ - ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ - ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ - ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ - ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) -#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ - ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) -#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ - ((IT) != 0x00U)) -#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ - ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ - ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) -#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ - ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) - -/** - * @} - */ - -/** @addtogroup ETH_Private_Defines - * @{ - */ -/* Delay to wait when writing to some Ethernet registers */ -#define ETH_REG_WRITE_DELAY 0x00000001U - -/* ETHERNET Errors */ -#define ETH_SUCCESS 0U -#define ETH_ERROR 1U - -/* ETHERNET DMA Tx descriptors Collision Count Shift */ -#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U - -/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ -#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U - -/* ETHERNET DMA Rx descriptors Frame Length Shift */ -#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U - -/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ -#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U - -/* ETHERNET DMA Rx descriptors Frame length Shift */ -#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U - -/* ETHERNET MAC address offsets */ -#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ -#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ - -/* ETHERNET MACMIIAR register Mask */ -#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U - -/* ETHERNET MACCR register Mask */ -#define ETH_MACCR_CLEAR_MASK 0xFF20810FU - -/* ETHERNET MACFCR register Mask */ -#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U - -/* ETHERNET DMAOMR register Mask */ -#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U - -/* ETHERNET Remote Wake-up frame register length */ -#define ETH_WAKEUP_REGISTER_LENGTH 8U - -/* ETHERNET Missed frames counter Shift */ -#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U - /** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ + */ + +/* Exported types ------------------------------------------------------------*/ +#ifndef ETH_TX_DESC_CNT +#define ETH_TX_DESC_CNT 4U +#endif /* ETH_TX_DESC_CNT */ + +#ifndef ETH_RX_DESC_CNT +#define ETH_RX_DESC_CNT 4U +#endif /* ETH_RX_DESC_CNT */ + + +/*********************** Descriptors struct def section ************************/ /** @defgroup ETH_Exported_Types ETH Exported Types * @{ */ -/** - * @brief HAL State structures definition - */ -typedef enum +/** + * @brief ETH DMA Descriptor structure definition + */ +typedef struct +{ + __IO uint32_t DESC0; + __IO uint32_t DESC1; + __IO uint32_t DESC2; + __IO uint32_t DESC3; + __IO uint32_t DESC4; + __IO uint32_t DESC5; + __IO uint32_t DESC6; + __IO uint32_t DESC7; + uint32_t BackupAddr0; /* used to store rx buffer 1 address */ + uint32_t BackupAddr1; /* used to store rx buffer 2 address */ +} ETH_DMADescTypeDef; +/** + * + */ + +/** + * @brief ETH Buffers List structure definition + */ +typedef struct __ETH_BufferTypeDef { - HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ - HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ - HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ - HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ - HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ - HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ - HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -}HAL_ETH_StateTypeDef; - -/** - * @brief ETH Init Structure definition + uint8_t *buffer; /*State = HAL_ETH_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else -#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) +#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \ + } while(0) #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ -/** - * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag of TDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag of RDES0 to check. - * @retval the ETH_DMATxDescFlag (SET or RESET). - */ -#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) - -/** - * @brief Enables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) - -/** - * @brief Disables the specified DMA Rx Desc receive interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) - -/** - * @brief Set the specified DMA Rx Desc Own bit. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) - -/** - * @brief Returns the specified ETHERNET DMA Tx Desc collision count. - * @param __HANDLE__ ETH Handle - * @retval The Transmit descriptor collision counter value. - */ -#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) - -/** - * @brief Set the specified DMA Tx Desc Own bit. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) - -/** - * @brief Enables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) - -/** - * @brief Disables the specified DMA Tx Desc Transmit interrupt. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) - -/** - * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. - * @param __HANDLE__ ETH Handle - * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. - * This parameter can be one of the following values: - * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass - * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present - * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) - -/** - * @brief Enables the DMA Tx Desc CRC. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) - -/** - * @brief Disables the DMA Tx Desc CRC. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) - -/** - * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) - -/** - * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) - -/** - * @brief Enables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) - -/** - * @brief Disables the specified ETHERNET MAC interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be - * enabled or disabled. - * This parameter can be any combination of the following values: - * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt - * @arg ETH_MAC_IT_PMT : PMT interrupt - * @retval None - */ -#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) - -/** - * @brief Initiate a Pause Control Frame (Full-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Checks whether the ETHERNET flow control busy bit is set or not. - * @param __HANDLE__ ETH Handle - * @retval The new state of flow control busy status bit (SET or RESET). - */ -#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) - -/** - * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) - -/** - * @brief Disables the MAC BackPressure operation activation (Half-duplex only). - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) - /** - * @brief Checks whether the specified ETHERNET MAC flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag - * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag - * @arg ETH_MAC_FLAG_MMCR : MMC receive flag - * @arg ETH_MAC_FLAG_MMC : MMC flag - * @arg ETH_MAC_FLAG_PMT : PMT flag - * @retval The state of ETHERNET MAC flag. - */ -#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) - -/** * @brief Enables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be * enabled @ref ETH_DMA_Interrupts * @retval None */ -#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) +#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \ + |= (__INTERRUPT__)) /** * @brief Disables the specified ETHERNET DMA interrupts. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be * disabled. @ref ETH_DMA_Interrupts * @retval None */ -#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) - -/** - * @brief Clears the ETHERNET DMA IT pending bit. - * @param __HANDLE__ ETH Handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts - * @retval None - */ -#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. -* @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags - * @retval The new state of ETH_DMA_FLAG (SET or RESET). - */ -#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) - -/** - * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. - * @param __HANDLE__ ETH Handle - * @param __OVERFLOW__ specifies the DMA overflow flag to check. - * This parameter can be one of the following values: - * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter - * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter - * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). - */ -#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) - -/** - * @brief Set the DMA Receive status watchdog timer register value - * @param __HANDLE__ ETH Handle - * @param __VALUE__ DMA Receive status watchdog timer register value - * @retval None - */ -#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) - -/** - * @brief Enables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) - -/** - * @brief Disables any unicast packet filtered by the MAC address - * recognition to be a wake-up frame. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) - -/** - * @brief Enables the MAC Wake-Up Frame Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) - -/** - * @brief Disables the MAC Wake-Up Frame Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Magic Packet Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) - -/** - * @brief Disables the MAC Magic Packet Detection. - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) - -/** - * @brief Enables the MAC Power Down. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) - -/** - * @brief Disables the MAC Power Down. - * @param __HANDLE__ ETH Handle - * @retval None - */ -#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) - -/** - * @brief Checks whether the specified ETHERNET PMT flag is set or not. - * @param __HANDLE__ ETH Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset - * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received - * @arg ETH_PMT_FLAG_MPR : Magic Packet Received - * @retval The new state of ETHERNET PMT Flag (SET or RESET). - */ -#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) - -/** - * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) - -/** - * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) - * @param __HANDLE__ ETH Handle. - * @retval None - */ -#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ - (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) +#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \ + &= ~(__INTERRUPT__)) /** - * @brief Enables the MMC Counter Freeze. - * @param __HANDLE__ ETH Handle. - * @retval None + * @brief Gets the ETHERNET DMA IT source enabled or disabled. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The ETH DMA IT Source enabled or disabled */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) +#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMAIER &\ + (__INTERRUPT__)) == (__INTERRUPT__)) /** - * @brief Disables the MMC Counter Freeze. - * @param __HANDLE__ ETH Handle. - * @retval None + * @brief Gets the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The state of ETH DMA IT (SET or RESET) */ -#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) +#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMASR &\ + (__INTERRUPT__)) == (__INTERRUPT__)) /** - * @brief Enables the MMC Reset On Read. - * @param __HANDLE__ ETH Handle. + * @brief Clears the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts * @retval None */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) +#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR = (__INTERRUPT__)) /** - * @brief Disables the MMC Reset On Read. - * @param __HANDLE__ ETH Handle. - * @retval None + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of ETH DMA FLAG (SET or RESET). */ -#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) +#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &\ + ( __FLAG__)) == ( __FLAG__)) /** - * @brief Enables the MMC Counter Stop Rollover. - * @param __HANDLE__ ETH Handle. - * @retval None + * @brief Clears the specified ETHERNET DMA flag. + * @param __HANDLE__: ETH Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of ETH DMA FLAG (SET or RESET). */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) +#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__)) /** - * @brief Disables the MMC Counter Stop Rollover. - * @param __HANDLE__ ETH Handle. + * @brief Enables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts * @retval None */ -#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) +#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \ + |= (__INTERRUPT__)) /** - * @brief Resets the MMC Counters. - * @param __HANDLE__ ETH Handle. + * @brief Disables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : ETH Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts * @retval None */ -#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) +#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER \ + &= ~(__INTERRUPT__)) /** - * @brief Enables the specified ETHERNET MMC Rx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) -/** - * @brief Disables the specified ETHERNET MMC Rx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value - * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value - * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) -/** - * @brief Enables the specified ETHERNET MMC Tx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * @param __HANDLE__: ETH Handle + * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts + * @retval The state of ETH MAC IT (SET or RESET). */ -#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) +#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACSR &\ + ( __INTERRUPT__)) == ( __INTERRUPT__)) -/** - * @brief Disables the specified ETHERNET MMC Tx interrupts. - * @param __HANDLE__ ETH Handle. - * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. - * This parameter can be one of the following values: - * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value - * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value - * @retval None - */ -#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) +/*!< External interrupt line 19 Connected to the ETH wakeup EXTI Line */ +#define ETH_WAKEUP_EXTI_LINE 0x00080000U /** - * @brief Enables the ETH External interrupt line. - * @retval None + * @brief Enable the ETH WAKEUP Exti Line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR |= (__EXTI_LINE__)) /** - * @brief Disables the ETH External interrupt line. - * @retval None + * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval EXTI ETH WAKEUP Line Status. */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) /** - * @brief Enable event on ETH External event line. + * @brief Clear the ETH WAKEUP Exti flag. + * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE * @retval None. */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) -/** - * @brief Disable event on ETH External event line - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) /** - * @brief Get flag of the ETH External interrupt line. + * @brief enable rising edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR &= ~(__EXTI_LINE__)); \ + (EXTI->RTSR |= (__EXTI_LINE__)) /** - * @brief Clear flag of the ETH External interrupt line. + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR &= ~(__EXTI_LINE__));\ + (EXTI->FTSR |= (__EXTI_LINE__)) /** - * @brief Enables rising edge trigger to the ETH External interrupt line. + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP - -/** - * @brief Disables the rising edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) - -/** - * @brief Enables falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR |= (__EXTI_LINE__));\ + (EXTI->FTSR |= (__EXTI_LINE__)) /** - * @brief Disables falling edge trigger to the ETH External interrupt line. + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE * @retval None */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) +#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) -/** - * @brief Enables rising/falling edge trigger to the ETH External interrupt line. - * @retval None - */ -#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ - EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ - }while(0U) +#define __HAL_ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->PTPTSCR) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->PTPTSCR |= (__FLAG__)) /** - * @brief Disables rising/falling edge trigger to the ETH External interrupt line. - * @retval None + * @} */ -#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ - }while(0U) -/** - * @brief Generate a Software interrupt on selected EXTI line. - * @retval None. - */ -#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP -/** - * @} - */ /* Exported functions --------------------------------------------------------*/ /** @addtogroup ETH_Exported_Functions * @{ */ -/* Initialization and de-initialization functions ****************************/ - /** @addtogroup ETH_Exported_Functions_Group1 * @{ */ +/* Initialization and de initialization functions **********************************/ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); -void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); -HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); +void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); + /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, + pETH_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ /** * @} */ -/* IO operation functions ****************************************************/ /** @addtogroup ETH_Exported_Functions_Group2 * @{ */ -HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); -/* Communication with PHY functions*/ -HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); -HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); -void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); -/* Callback in non blocking modes (Interrupt) */ -void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); -void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); +/* IO operation functions *******************************************************/ +HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth); + +HAL_StatusTypeDef HAL_ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff); +HAL_StatusTypeDef HAL_ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_GetRxDataErrorCode(ETH_HandleTypeDef *heth, uint32_t *pErrorCode); +HAL_StatusTypeDef HAL_ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); + +#ifdef HAL_ETH_USE_PTP +HAL_StatusTypeDef HAL_ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +HAL_StatusTypeDef HAL_ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +HAL_StatusTypeDef HAL_ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +HAL_StatusTypeDef HAL_ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +HAL_StatusTypeDef HAL_ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset); +HAL_StatusTypeDef HAL_ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +HAL_StatusTypeDef HAL_ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback); +HAL_StatusTypeDef HAL_ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); +#endif /* HAL_ETH_USE_PTP */ + +HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout); +HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig); + +HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue); +HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue); + +void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); +void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth); +void HAL_ETH_RxAllocateCallback(uint8_t **buff); +void HAL_ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length); +void HAL_ETH_TxFreeCallback(uint32_t *buff); +void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp); /** * @} */ -/* Peripheral Control functions **********************************************/ - /** @addtogroup ETH_Exported_Functions_Group3 * @{ */ +/* Peripheral Control functions **********************************************/ +/* MAC & DMA Configuration APIs **********************************************/ +HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); + +/* MAC VLAN Processing APIs ************************************************/ +void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, + uint32_t VLANIdentifier); + +/* MAC L2 Packet Filtering APIs **********************************************/ +HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); +HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr); + +/* MAC Power Down APIs *****************************************************/ +void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig); +void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); +HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); -HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); -HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); -HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); /** * @} - */ - -/* Peripheral State functions ************************************************/ + */ /** @addtogroup ETH_Exported_Functions_Group4 * @{ */ +/* Peripheral State functions **************************************************/ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth); +uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth); /** * @} */ @@ -2200,14 +2133,12 @@ HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ - STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ - +#endif /* ETH */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_ETH_H */ +#endif /* STM32F4xx_HAL_ETH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.c index 7cf3e092bf8..0804555468b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### EXTI Peripheral features ##### @@ -69,18 +80,6 @@ (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -276,6 +275,10 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT pExtiConfig->Mode |= EXTI_MODE_EVENT; } + /* Get default Trigger and GPIOSel configuration */ + pExtiConfig->Trigger = EXTI_TRIGGER_NONE; + pExtiConfig->GPIOSel = 0x00u; + /* 2] Get trigger for configurable lines : rising */ if ((pExtiConfig->Line & EXTI_CONFIG) != 0x00u) { @@ -284,10 +287,6 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT { pExtiConfig->Trigger = EXTI_TRIGGER_RISING; } - else - { - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - } /* Get falling configuration */ /* Check if configuration of selected line is enable */ @@ -302,18 +301,8 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT assert_param(IS_EXTI_GPIO_PIN(linepos)); regval = SYSCFG->EXTICR[linepos >> 2u]; - pExtiConfig->GPIOSel = ((regval << (SYSCFG_EXTICR1_EXTI1_Pos * (3uL - (linepos & 0x03u)))) >> 24); + pExtiConfig->GPIOSel = (regval >> (SYSCFG_EXTICR1_EXTI1_Pos * (linepos & 0x03u))) & SYSCFG_EXTICR1_EXTI0; } - else - { - pExtiConfig->GPIOSel = 0x00u; - } - } - else - { - /* No Trigger selected */ - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; } return HAL_OK; @@ -556,4 +545,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.h index 857011236b0..b18a2287a1f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_exti.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2018 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2018 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause * ****************************************************************************** */ @@ -365,4 +364,3 @@ void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); #endif /* STM32f4xx_HAL_EXTI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash.c index 69b47a6eca7..2830da07e9f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash.c @@ -63,14 +63,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -775,4 +773,3 @@ static void FLASH_SetErrorCode(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash.h index b817f63b760..26d789effde 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -425,4 +423,3 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #endif /* __STM32F4xx_HAL_FLASH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ex.c index 4e2a8dcec73..d99eacec3a8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ex.c @@ -3,62 +3,60 @@ * @file stm32f4xx_hal_flash_ex.c * @author MCD Application Team * @brief Extended FLASH HAL module driver. - * This file provides firmware functions to manage the following + * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: * + Extended programming operations functions - * + * @verbatim ============================================================================== ##### Flash Extension features ##### ============================================================================== - - [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and - STM32F429xx/439xx devices contains the following additional features - + + [..] Comparing to other previous devices, the FLASH interface for STM32F427xx/437xx and + STM32F429xx/439xx devices contains the following additional features + (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write capability (RWW) - (+) Dual bank memory organization + (+) Dual bank memory organization (+) PCROP protection for all banks - + ##### How to use this driver ##### ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx + [..] This driver provides functions to configure and program the FLASH memory + of all STM32F427xx/437xx, STM32F429xx/439xx, STM32F469xx/479xx and STM32F446xx devices. It includes - (#) FLASH Memory Erase functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and + (#) FLASH Memory Erase functions: + (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and HAL_FLASH_Lock() functions (++) Erase function: Erase sector, erase all sectors (++) There are two modes of erase : (+++) Polling Mode using HAL_FLASHEx_Erase() (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() - + (#) Option Bytes Programming functions: Use HAL_FLASHEx_OBProgram() to : (++) Set/Reset the write protection (++) Set the Read protection Level (++) Set the BOR level (++) Program the user Option Bytes - (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to : + (#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to : (++) Extended space (bank 2) erase function (++) Full FLASH space (2 Mo) erase (bank 1 and bank 2) (++) Dual Boot activation (++) Write protection configuration for bank 2 (++) PCROP protection configuration and control for both banks - + @endverbatim ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -78,17 +76,17 @@ /* Private define ------------------------------------------------------------*/ /** @addtogroup FLASHEx_Private_Constants * @{ - */ + */ #define FLASH_TIMEOUT_VALUE 50000U /* 50 s */ /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @addtogroup FLASHEx_Private_Variables * @{ - */ + */ extern FLASH_ProcessTypeDef pFlash; /** * @} @@ -118,7 +116,7 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector); #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx STM32F413xx || STM32F423xx */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks); static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig); @@ -135,35 +133,35 @@ extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); */ /** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions - * @brief Extended IO operation functions + * @brief Extended IO operation functions * -@verbatim +@verbatim =============================================================================== ##### Extended programming operation functions ##### - =============================================================================== + =============================================================================== [..] - This subsection provides a set of functions allowing to manage the Extension FLASH + This subsection provides a set of functions allowing to manage the Extension FLASH programming operations. @endverbatim * @{ */ /** - * @brief Perform a mass erase or erase the specified FLASH memory sectors + * @brief Perform a mass erase or erase the specified FLASH memory sectors * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. - * + * * @param[out] SectorError pointer to variable that - * contains the configuration information on faulty sector in case of error + * contains the configuration information on faulty sector in case of error * (0xFFFFFFFFU means that all the sectors have been correctly erased) - * + * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError) { HAL_StatusTypeDef status = HAL_ERROR; uint32_t index = 0U; - + /* Process Locked */ __HAL_LOCK(&pFlash); @@ -173,19 +171,19 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { /*Initialization of SectorError variable*/ *SectorError = 0xFFFFFFFFU; - - if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /*Mass erase to be done*/ FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* if the erase operation is completed, disable the MER Bit */ FLASH->CR &= (~FLASH_MER_BIT); } @@ -195,17 +193,17 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector)); /* Erase by sector by sector to be done*/ - for(index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) + for (index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++) { FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - + /* If the erase operation is completed, disable the SER and SNB Bits */ CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB)); - if(status != HAL_OK) + if (status != HAL_OK) { /* In case of error, stop erase procedure and return the faulty sector*/ *SectorError = index; @@ -214,7 +212,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t } } /* Flush the caches to be sure of the data consistency */ - FLASH_FlushCaches(); + FLASH_FlushCaches(); } /* Process Unlocked */ @@ -227,7 +225,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. - * + * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) @@ -242,15 +240,15 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) /* Enable End of FLASH Operation interrupt */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - + /* Enable Error source interrupt */ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR| FLASH_FLAG_PGSERR); - - if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) + + /* Clear pending flags (if any) */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | \ + FLASH_FLAG_PGAERR | FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR); + + if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE) { /*Mass erase to be done*/ pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE; @@ -280,13 +278,13 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) * @brief Program option bytes * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. - * + * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) { HAL_StatusTypeDef status = HAL_ERROR; - + /* Process Locked */ __HAL_LOCK(&pFlash); @@ -294,10 +292,10 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); /*Write protection configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + if ((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) { assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if(pOBInit->WRPState == OB_WRPSTATE_ENABLE) + if (pOBInit->WRPState == OB_WRPSTATE_ENABLE) { /*Enable of Write protection on the selected Sector*/ status = FLASH_OB_EnableWRP(pOBInit->WRPSector, pOBInit->Banks); @@ -310,21 +308,21 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) } /*Read protection configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + if ((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) { status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); } /*USER configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + if ((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) { - status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW, - pOBInit->USERConfig&OB_STOP_NO_RST, - pOBInit->USERConfig&OB_STDBY_NO_RST); + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NO_RST, + pOBInit->USERConfig & OB_STDBY_NO_RST); } /*BOR Level configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + if ((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) { status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); } @@ -339,7 +337,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) * @brief Get the Option byte configuration * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. - * + * * @retval None */ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) @@ -368,22 +366,22 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) * @brief Program option bytes * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that * contains the configuration information for the programming. - * + * * @retval HAL Status */ -HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) +HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) { HAL_StatusTypeDef status = HAL_ERROR; - + /* Check the parameters */ assert_param(IS_OBEX(pAdvOBInit->OptionType)); /*Program PCROP option byte*/ - if(((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) + if (((pAdvOBInit->OptionType) & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) { /* Check the parameters */ assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); - if((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE) + if ((pAdvOBInit->PCROPState) == OB_PCROP_STATE_ENABLE) { /*Enable of Write protection on the selected Sector*/ #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ @@ -408,10 +406,10 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO STM32F413xx || STM32F423xx */ } } - + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /*Program BOOT config option byte*/ - if(((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) + if (((pAdvOBInit->OptionType) & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) { status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); } @@ -424,7 +422,7 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO * @brief Get the OBEX byte configuration * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that * contains the configuration information for the programming. - * + * * @retval None */ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) @@ -448,15 +446,15 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) } /** - * @brief Select the Protection Mode - * - * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted - * Global Read Out Protection modification (from level1 to level0) - * @note Once SPRMOD bit is active unprotection of a protected sector is not possible + * @brief Select the Protection Mode + * + * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted + * Global Read Out Protection modification (from level1 to level0) + * @note Once SPRMOD bit is active unprotection of a protected sector is not possible * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices. - * + * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) @@ -464,36 +462,36 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) uint8_t optiontmp = 0xFF; /* Mask SPRMOD bit */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); - + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + /* Update Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp); - + *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_SELECTED | optiontmp); + return HAL_OK; } /** - * @brief Deselect the Protection Mode - * - * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted - * Global Read Out Protection modification (from level1 to level0) - * @note Once SPRMOD bit is active unprotection of a protected sector is not possible + * @brief Deselect the Protection Mode + * + * @note After PCROP activated Option Byte modification NOT POSSIBLE! excepted + * Global Read Out Protection modification (from level1 to level0) + * @note Once SPRMOD bit is active unprotection of a protected sector is not possible * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F401xx/STM32F411xx/STM32F446xx/ * STM32F469xx/STM32F479xx/STM32F412xx/STM32F413xx devices. - * + * * @retval HAL Status */ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) { uint8_t optiontmp = 0xFF; - + /* Mask SPRMOD bit */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); - + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE3_ADDRESS) & (uint8_t)0x7F); + /* Update Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp); - + *(__IO uint8_t *)OPTCR_BYTE3_ADDRESS = (uint8_t)(OB_PCROP_DESELECTED | optiontmp); + return HAL_OK; } #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F401xC || STM32F401xE || STM32F410xx ||\ @@ -503,11 +501,11 @@ HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** * @brief Returns the FLASH Write Protection Option Bytes value for Bank 2 - * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices. + * @note This function can be used only for STM32F42xxx/STM32F43xxx/STM32F469xx/STM32F479xx devices. * @retval The FLASH Write Protection Option Bytes value */ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) -{ +{ /* Return the FLASH write protection Register value */ return (*(__IO uint16_t *)(OPTCR1_BYTE2_ADDRESS)); } @@ -516,21 +514,21 @@ uint16_t HAL_FLASHEx_OB_GetBank2WRP(void) /** * @} */ - + #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) /** - * @brief Full erase of FLASH memory sectors - * @param VoltageRange The device voltage range which defines the erase parallelism. + * @brief Full erase of FLASH memory sectors + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, * the operation will be done by half word (16-bit) * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) - * + * * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased @@ -548,12 +546,12 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /* if the previous operation is completed, proceed to erase all sectors */ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); - if(Banks == FLASH_BANK_BOTH) + if (Banks == FLASH_BANK_BOTH) { /* bank1 & bank2 will be erased*/ FLASH->CR |= FLASH_MER_BIT; } - else if(Banks == FLASH_BANK_1) + else if (Banks == FLASH_BANK_1) { /*Only bank1 will be erased*/ FLASH->CR |= FLASH_CR_MER1; @@ -563,24 +561,24 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /*Only bank2 will be erased*/ FLASH->CR |= FLASH_CR_MER2; } - FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U); + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U); } /** * @brief Erase the specified FLASH memory sector * @param Sector FLASH sector to erase - * The value of this parameter depend on device used within the same series - * @param VoltageRange The device voltage range which defines the erase parallelism. + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, * the operation will be done by half word (16-bit) * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) - * + * * @retval None */ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) @@ -590,16 +588,16 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) /* Check the parameters */ assert_param(IS_FLASH_SECTOR(Sector)); assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + + if (VoltageRange == FLASH_VOLTAGE_RANGE_1) { - tmp_psize = FLASH_PSIZE_BYTE; + tmp_psize = FLASH_PSIZE_BYTE; } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + else if (VoltageRange == FLASH_VOLTAGE_RANGE_2) { tmp_psize = FLASH_PSIZE_HALF_WORD; } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + else if (VoltageRange == FLASH_VOLTAGE_RANGE_3) { tmp_psize = FLASH_PSIZE_WORD; } @@ -609,7 +607,7 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) } /* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */ - if(Sector > FLASH_SECTOR_11) + if (Sector > FLASH_SECTOR_11) { Sector += 4U; } @@ -624,11 +622,11 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) /** * @brief Enable the write protection of the desired bank1 or bank 2 sectors * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 @@ -641,53 +639,53 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) * @arg FLASH_BANK_2: WRP on all sectors of bank2 * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 * - * @retval HAL FLASH State + * @retval HAL FLASH State */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_OB_WRP_SECTOR(WRPSector)); assert_param(IS_FLASH_BANK(Banks)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || - (WRPSector < OB_WRP_SECTOR_12)) + if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || + (WRPSector < OB_WRP_SECTOR_12)) { - if(WRPSector == OB_WRP_SECTOR_All) - { - /*Write protection on all sector of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~(WRPSector>>12)); - } - else - { - /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector); - } + if (WRPSector == OB_WRP_SECTOR_All) + { + /*Write protection on all sector of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~(WRPSector >> 12)); + } + else + { + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector); + } } - else + else { /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12)); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12)); } /*Write protection on all sector of BANK2*/ - if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) + if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector>>12)); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~(WRPSector >> 12)); } } - + } return status; } @@ -695,11 +693,11 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) /** * @brief Disable the write protection of the desired bank1 or bank 2 sectors * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23 @@ -712,53 +710,53 @@ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) * @arg FLASH_BANK_2: Bank2 to be erased * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased * - * @retval HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_OB_WRP_SECTOR(WRPSector)); assert_param(IS_FLASH_BANK(Banks)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - if(((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || - (WRPSector < OB_WRP_SECTOR_12)) + if (((WRPSector == OB_WRP_SECTOR_All) && ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH))) || + (WRPSector < OB_WRP_SECTOR_12)) { - if(WRPSector == OB_WRP_SECTOR_All) - { - /*Write protection on all sector of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); - } - else - { - /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; - } + if (WRPSector == OB_WRP_SECTOR_All) + { + /*Write protection on all sector of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); + } + else + { + /*Write protection done on sectors of BANK1*/ + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; + } } - else + else { /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); } /*Write protection on all sector of BANK2*/ - if((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) + if ((WRPSector == OB_WRP_SECTOR_All) && (Banks == FLASH_BANK_BOTH)) { /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector>>12); + + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)(WRPSector >> 12); } } - + } return status; @@ -766,9 +764,9 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) /** * @brief Configure the Dual Bank Boot. - * + * * @note This function can be used only for STM32F42xxx/43xxx devices. - * + * * @param BootConfig specifies the Dual Bank Boot Option byte. * This parameter can be one of the following values: * @arg OB_Dual_BootEnabled: Dual Bank Boot Enable @@ -782,77 +780,77 @@ static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t BootConfig) /* Check the parameters */ assert_param(IS_OB_BOOT(BootConfig)); - /* Wait for last operation to be completed */ + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) - { + if (status == HAL_OK) + { /* Set Dual Bank Boot */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BFB2); *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= BootConfig; } - + return status; } /** - * @brief Enable the read/write protection (PCROP) of the desired + * @brief Enable the read/write protection (PCROP) of the desired * sectors of Bank 1 and/or Bank 2. * @note This function can be used only for STM32F42xxx/43xxx devices. * @param SectorBank1 Specifies the sector(s) to be read/write protected or unprotected for bank1. * This parameter can be one of the following values: * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11 - * @arg OB_PCROP_SECTOR__All + * @arg OB_PCROP_SECTOR__All * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2. * This parameter can be one of the following values: * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23 - * @arg OB_PCROP_SECTOR__All + * @arg OB_PCROP_SECTOR__All * @param Banks Enable PCROP protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * @arg FLASH_BANK_2: WRP on all sectors of bank2 * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 * - * @retval HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) { HAL_StatusTypeDef status = HAL_OK; - + assert_param(IS_FLASH_BANK(Banks)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) + if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) { assert_param(IS_OB_PCROP(SectorBank1)); /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)SectorBank1; } - else + else { assert_param(IS_OB_PCROP(SectorBank2)); /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; } /*Write protection on all sector of BANK2*/ - if(Banks == FLASH_BANK_BOTH) + if (Banks == FLASH_BANK_BOTH) { assert_param(IS_OB_PCROP(SectorBank2)); /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { + + if (status == HAL_OK) + { /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS |= (uint16_t)SectorBank2; } } - + } return status; @@ -860,66 +858,66 @@ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t SectorBank1, uint32_t Sec /** - * @brief Disable the read/write protection (PCROP) of the desired + * @brief Disable the read/write protection (PCROP) of the desired * sectors of Bank 1 and/or Bank 2. * @note This function can be used only for STM32F42xxx/43xxx devices. * @param SectorBank1 specifies the sector(s) to be read/write protected or unprotected for bank1. * This parameter can be one of the following values: * @arg OB_PCROP: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_11 - * @arg OB_PCROP_SECTOR__All + * @arg OB_PCROP_SECTOR__All * @param SectorBank2 Specifies the sector(s) to be read/write protected or unprotected for bank2. * This parameter can be one of the following values: * @arg OB_PCROP: A value between OB_PCROP_SECTOR_12 and OB_PCROP_SECTOR_23 - * @arg OB_PCROP_SECTOR__All + * @arg OB_PCROP_SECTOR__All * @param Banks Disable PCROP protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * @arg FLASH_BANK_2: WRP on all sectors of bank2 * @arg FLASH_BANK_BOTH: WRP on all sectors of bank1 & bank2 * - * @retval HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t SectorBank2, uint32_t Banks) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_FLASH_BANK(Banks)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) + if (status == HAL_OK) { - if((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) + if ((Banks == FLASH_BANK_1) || (Banks == FLASH_BANK_BOTH)) { assert_param(IS_OB_PCROP(SectorBank1)); /*Write protection done on sectors of BANK1*/ - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~SectorBank1); } - else + else { /*Write protection done on sectors of BANK2*/ assert_param(IS_OB_PCROP(SectorBank2)); - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); } /*Write protection on all sector of BANK2*/ - if(Banks == FLASH_BANK_BOTH) + if (Banks == FLASH_BANK_BOTH) { assert_param(IS_OB_PCROP(SectorBank2)); - /* Wait for last operation to be completed */ + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { + + if (status == HAL_OK) + { /*Write protection done on sectors of BANK2*/ - *(__IO uint16_t*)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); + *(__IO uint16_t *)OPTCR1_BYTE2_ADDRESS &= (~SectorBank2); } } - + } - + return status; } @@ -933,17 +931,17 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t SectorBank1, uint32_t Se defined(STM32F423xx) /** * @brief Mass erase of FLASH memory - * @param VoltageRange The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, * the operation will be done by half word (16-bit) * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) - * + * * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased @@ -955,28 +953,28 @@ static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks) /* Check the parameters */ assert_param(IS_VOLTAGERANGE(VoltageRange)); assert_param(IS_FLASH_BANK(Banks)); - + /* If the previous operation is completed, proceed to erase all sectors */ CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE); FLASH->CR |= FLASH_CR_MER; - FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8U); + FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U); } /** * @brief Erase the specified FLASH memory sector * @param Sector FLASH sector to erase - * The value of this parameter depend on device used within the same series - * @param VoltageRange The device voltage range which defines the erase parallelism. + * The value of this parameter depend on device used within the same series + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: - * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, - * the operation will be done by byte (8-bit) + * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, + * the operation will be done by byte (8-bit) * @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V, * the operation will be done by half word (16-bit) * @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V, * the operation will be done by word (32-bit) - * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, + * @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) - * + * * @retval None */ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) @@ -986,16 +984,16 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) /* Check the parameters */ assert_param(IS_FLASH_SECTOR(Sector)); assert_param(IS_VOLTAGERANGE(VoltageRange)); - - if(VoltageRange == FLASH_VOLTAGE_RANGE_1) + + if (VoltageRange == FLASH_VOLTAGE_RANGE_1) { - tmp_psize = FLASH_PSIZE_BYTE; + tmp_psize = FLASH_PSIZE_BYTE; } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_2) + else if (VoltageRange == FLASH_VOLTAGE_RANGE_2) { tmp_psize = FLASH_PSIZE_HALF_WORD; } - else if(VoltageRange == FLASH_VOLTAGE_RANGE_3) + else if (VoltageRange == FLASH_VOLTAGE_RANGE_3) { tmp_psize = FLASH_PSIZE_WORD; } @@ -1015,72 +1013,72 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange) /** * @brief Enable the write protection of the desired bank 1 sectors * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * * @param WRPSector specifies the sector(s) to be write protected. - * The value of this parameter depend on device used within the same series - * + * The value of this parameter depend on device used within the same series + * * @param Banks Enable write protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * - * @retval HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector, uint32_t Banks) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_OB_WRP_SECTOR(WRPSector)); assert_param(IS_FLASH_BANK(Banks)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~WRPSector); + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~WRPSector); } - + return status; } /** * @brief Disable the write protection of the desired bank 1 sectors * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase the flash sector i if CortexM4 - * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 - * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). - * + * @note When the memory read protection level is selected (RDP level = 1), + * it is not possible to program or erase the flash sector i if CortexM4 + * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 + * @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1). + * * @param WRPSector specifies the sector(s) to be write protected. - * The value of this parameter depend on device used within the same series - * + * The value of this parameter depend on device used within the same series + * * @param Banks Enable write protection on all the sectors for the specific bank * This parameter can be one of the following values: * @arg FLASH_BANK_1: WRP on all sectors of bank1 * - * @retval HAL Status + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_OB_WRP_SECTOR(WRPSector)); assert_param(IS_FLASH_BANK(Banks)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)WRPSector; } - + return status; } #endif /* STM32F40xxx || STM32F41xxx || STM32F401xx || STM32F410xx || STM32F411xE || STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx @@ -1095,24 +1093,24 @@ static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector, uint32_t Banks) * @param Sector specifies the sector(s) to be read/write protected or unprotected. * This parameter can be one of the following values: * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 - * @arg OB_PCROP_Sector_All - * @retval HAL Status + * @arg OB_PCROP_Sector_All + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_OB_PCROP(Sector)); - - /* Wait for last operation to be completed */ + + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector; + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS |= (uint16_t)Sector; } - + return status; } @@ -1123,24 +1121,24 @@ static HAL_StatusTypeDef FLASH_OB_EnablePCROP(uint32_t Sector) * @param Sector specifies the sector(s) to be read/write protected or unprotected. * This parameter can be one of the following values: * @arg OB_PCROP: A value between OB_PCROP_Sector0 and OB_PCROP_Sector5 - * @arg OB_PCROP_Sector_All - * @retval HAL Status + * @arg OB_PCROP_Sector_All + * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) -{ +{ HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_OB_PCROP(Sector)); - - /* Wait for last operation to be completed */ + + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) - { - *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~Sector); + if (status == HAL_OK) + { + *(__IO uint16_t *)OPTCR_BYTE2_ADDRESS &= (~Sector); } - + return status; } @@ -1154,31 +1152,31 @@ static HAL_StatusTypeDef FLASH_OB_DisablePCROP(uint32_t Sector) * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Read protection of the memory * @arg OB_RDP_LEVEL_2: Full chip protection - * + * * @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0 - * + * * @retval HAL Status */ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level) { HAL_StatusTypeDef status = HAL_OK; - + /* Check the parameters */ assert_param(IS_OB_RDP_LEVEL(Level)); - + /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - if(status == HAL_OK) - { - *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level; + if (status == HAL_OK) + { + *(__IO uint8_t *)OPTCR_BYTE1_ADDRESS = Level; } - + return status; } /** - * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. * @param Iwdg Selects the IWDG mode * This parameter can be one of the following values: * @arg OB_IWDG_SW: Software IWDG selected @@ -1205,21 +1203,21 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t Iwdg, uint8_t Stop, uint8_t /* Wait for last operation to be completed */ status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE); - - if(status == HAL_OK) - { + + if (status == HAL_OK) + { /* Mask OPTLOCK, OPTSTRT, BOR_LEV and BFB2 bits */ - optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); + optiontmp = (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x1F); /* Update User Option Byte */ - *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp))); + *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = Iwdg | (uint8_t)(Stdby | (uint8_t)(Stop | ((uint8_t)optiontmp))); } - - return status; + + return status; } /** - * @brief Set the BOR Level. + * @brief Set the BOR Level. * @param Level specifies the Option Bytes BOR Reset Level. * This parameter can be one of the following values: * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V @@ -1236,9 +1234,9 @@ static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) /* Set the BOR Level */ *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV); *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= Level; - + return HAL_OK; - + } /** @@ -1274,15 +1272,15 @@ static uint8_t FLASH_OB_GetRDP(void) { uint8_t readstatus = OB_RDP_LEVEL_0; - if (*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2) + if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_2) { readstatus = OB_RDP_LEVEL_2; } - else if (*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0) + else if (*(__IO uint8_t *)(OPTCR_BYTE1_ADDRESS) == (uint8_t)OB_RDP_LEVEL_0) { readstatus = OB_RDP_LEVEL_0; } - else + else { readstatus = OB_RDP_LEVEL_1; } @@ -1296,7 +1294,7 @@ static uint8_t FLASH_OB_GetRDP(void) * - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V * - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V * - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V - * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V + * - OB_BOR_OFF : Supply voltage ranges from 1.62 to 2.1 V */ static uint8_t FLASH_OB_GetBOR(void) { @@ -1311,7 +1309,7 @@ static uint8_t FLASH_OB_GetBOR(void) void FLASH_FlushCaches(void) { /* Flush instruction cache */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN)!= RESET) + if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET) { /* Disable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_DISABLE(); @@ -1320,9 +1318,9 @@ void FLASH_FlushCaches(void) /* Enable instruction cache */ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE(); } - + /* Flush data cache */ - if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) + if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET) { /* Disable data cache */ __HAL_FLASH_DATA_CACHE_DISABLE(); @@ -1336,7 +1334,7 @@ void FLASH_FlushCaches(void) /** * @} */ - + #endif /* HAL_FLASH_MODULE_ENABLED */ /** @@ -1347,4 +1345,3 @@ void FLASH_FlushCaches(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ex.h index 4dbad673233..1cf8c458243 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -1063,4 +1061,3 @@ void FLASH_FlushCaches(void); #endif /* __STM32F4xx_HAL_FLASH_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ramfunc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ramfunc.c index 12db458b576..952595b82f0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ramfunc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ramfunc.c @@ -34,14 +34,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -172,4 +170,3 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ramfunc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ramfunc.h index 9fab0c98c56..05917ecc9d2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ramfunc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_flash_ramfunc.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -76,4 +74,3 @@ __RAM_FUNC HAL_StatusTypeDef HAL_FLASHEx_DisableFlashSleepMode(void); #endif /* __STM32F4xx_FLASH_RAMFUNC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c.c index 0f10310c730..4b425460a37 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,7 +30,7 @@ (#) Declare a FMPI2C_HandleTypeDef handle structure, for example: FMPI2C_HandleTypeDef hfmpi2c; - (#)Initialize the FMPI2C low level resources by implementing the @ref HAL_FMPI2C_MspInit() API: + (#)Initialize the FMPI2C low level resources by implementing the HAL_FMPI2C_MspInit() API: (##) Enable the FMPI2Cx interface clock (##) FMPI2C pins configuration (+++) Enable the clock for the FMPI2C GPIOs @@ -28,7 +39,8 @@ (+++) Configure the FMPI2Cx interrupt priority (+++) Enable the NVIC FMPI2C IRQ Channel (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Declare a DMA_HandleTypeDef handle structure for + the transmit or receive stream (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx stream @@ -39,49 +51,49 @@ (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure. - (#) Initialize the FMPI2C registers by calling the @ref HAL_FMPI2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_FMPI2C_MspInit(&hfmpi2c) API. + (#) Initialize the FMPI2C registers by calling the HAL_FMPI2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_FMPI2C_MspInit(&hfmpi2c) API. - (#) To check if target device is ready for communication, use the function @ref HAL_FMPI2C_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_FMPI2C_IsDeviceReady() (#) For FMPI2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_FMPI2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using @ref HAL_FMPI2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_FMPI2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_FMPI2C_Slave_Receive() + (+) Transmit in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_FMPI2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_FMPI2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_FMPI2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_FMPI2C_Mem_Read() + (+) Write an amount of data in blocking mode to a specific memory address using HAL_FMPI2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_FMPI2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Receive_IT() - (+) At reception end of transfer, @ref HAL_FMPI2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Receive_IT() - (+) At reception end of transfer, @ref HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback() - (+) Abort a master FMPI2C process communication with Interrupt using @ref HAL_FMPI2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_FMPI2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_AbortCpltCallback() - (+) Discard a slave FMPI2C process communication using @ref __HAL_FMPI2C_GENERATE_NACK() macro. + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_FMPI2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() + (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() + (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. @@ -92,120 +104,135 @@ when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref FMPI2C_XFEROPTIONS and are listed below: - (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode + (+) Option field values are defined through FMPI2C_XFEROPTIONS and are listed below: + (++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in + no sequential mode (++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition - (++) FMPI2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like @ref HAL_FMPI2C_Master_Seq_Transmit_IT() then @ref HAL_FMPI2C_Master_Seq_Transmit_IT() - or @ref HAL_FMPI2C_Master_Seq_Transmit_DMA() then @ref HAL_FMPI2C_Master_Seq_Transmit_DMA()) + (++) FMPI2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with + start condition, address and data to transfer without a final stop condition, + an then permit a call the same master sequential interface several times + (like HAL_FMPI2C_Master_Seq_Transmit_IT() then HAL_FMPI2C_Master_Seq_Transmit_IT() + or HAL_FMPI2C_Master_Seq_Transmit_DMA() then HAL_FMPI2C_Master_Seq_Transmit_DMA()) (++) FMPI2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and without a final stop condition in both cases (++) FMPI2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to transfer + and with new data to transfer if the direction change or manage only the new data to + transfer if no direction change and with a final stop condition in both cases - (++) FMPI2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential - interface several times (link with option FMPI2C_FIRST_AND_NEXT_FRAME). - Usage can, transfer several bytes one by one using HAL_FMPI2C_Master_Seq_Transmit_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME) - or HAL_FMPI2C_Master_Seq_Receive_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME) - or HAL_FMPI2C_Master_Seq_Transmit_DMA(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME) - or HAL_FMPI2C_Master_Seq_Receive_DMA(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME). - Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit + (++) FMPI2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition + after several call of the same master sequential interface several times + (link with option FMPI2C_FIRST_AND_NEXT_FRAME). + Usage can, transfer several bytes one by one using + HAL_FMPI2C_Master_Seq_Transmit_IT + or HAL_FMPI2C_Master_Seq_Receive_IT + or HAL_FMPI2C_Master_Seq_Transmit_DMA + or HAL_FMPI2C_Master_Seq_Receive_DMA + with option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME. + Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or + Receive sequence permit to call the opposite interface Receive or Transmit without stopping the communication and so generate a restart condition. - (++) FMPI2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential + (++) FMPI2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after + each call of the same master sequential interface. - Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_FMPI2C_Master_Seq_Transmit_IT(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME) - or HAL_FMPI2C_Master_Seq_Receive_IT(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME) - or HAL_FMPI2C_Master_Seq_Transmit_DMA(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME) - or HAL_FMPI2C_Master_Seq_Receive_DMA(option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME). - Then usage of this option FMPI2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. + Usage can, transfer several bytes one by one with a restart with slave address between + each bytes using + HAL_FMPI2C_Master_Seq_Transmit_IT + or HAL_FMPI2C_Master_Seq_Receive_IT + or HAL_FMPI2C_Master_Seq_Transmit_DMA + or HAL_FMPI2C_Master_Seq_Receive_DMA + with option FMPI2C_FIRST_FRAME then FMPI2C_OTHER_FRAME. + Then usage of this option FMPI2C_OTHER_AND_LAST_FRAME at the last frame to help automatic + generation of STOP condition. (+) Different sequential FMPI2C interfaces are listed below: - (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Seq_Transmit_IT() - or using @ref HAL_FMPI2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterTxCpltCallback() - (++) Sequential receive in master FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Master_Seq_Receive_IT() - or using @ref HAL_FMPI2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_FMPI2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA FMPI2C process communication with Interrupt using @ref HAL_FMPI2C_Master_Abort_IT() - (+++) End of abort process, @ref HAL_FMPI2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave FMPI2C mode using @ref HAL_FMPI2C_EnableListen_IT() @ref HAL_FMPI2C_DisableListen_IT() - (+++) When address slave FMPI2C match, @ref HAL_FMPI2C_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end @ref HAL_FMPI2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ListenCpltCallback() - (++) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Seq_Transmit_IT() - or using @ref HAL_FMPI2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveTxCpltCallback() - (++) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using @ref HAL_FMPI2C_Slave_Seq_Receive_IT() - or using @ref HAL_FMPI2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveRxCpltCallback() - (++) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback() - (++) Discard a slave FMPI2C process communication using @ref __HAL_FMPI2C_GENERATE_NACK() macro. + (++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using + HAL_FMPI2C_Master_Seq_Transmit_IT() or using HAL_FMPI2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() + (++) Sequential receive in master FMPI2C mode an amount of data in non-blocking mode using + HAL_FMPI2C_Master_Seq_Receive_IT() or using HAL_FMPI2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() + (+++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave FMPI2C mode using HAL_FMPI2C_EnableListen_IT() + HAL_FMPI2C_DisableListen_IT() + (+++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction request by master + (Write/Read). + (+++) At Listen mode end HAL_FMPI2C_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ListenCpltCallback() + (++) Sequential transmit in slave FMPI2C mode an amount of data in non-blocking mode using + HAL_FMPI2C_Slave_Seq_Transmit_IT() or using HAL_FMPI2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and + users can add their own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() + (++) Sequential receive in slave FMPI2C mode an amount of data in non-blocking mode using + HAL_FMPI2C_Slave_Seq_Receive_IT() or using HAL_FMPI2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (++) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - @ref HAL_FMPI2C_Mem_Write_IT() - (+) At Memory end of write transfer, @ref HAL_FMPI2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MemTxCpltCallback() + HAL_FMPI2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - @ref HAL_FMPI2C_Mem_Read_IT() - (+) At Memory end of read transfer, @ref HAL_FMPI2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback() + HAL_FMPI2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_FMPI2C_Master_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_FMPI2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterTxCpltCallback() + HAL_FMPI2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_FMPI2C_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_FMPI2C_Master_Receive_DMA() - (+) At reception end of transfer, @ref HAL_FMPI2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MasterRxCpltCallback() + HAL_FMPI2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_FMPI2C_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_FMPI2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_FMPI2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveTxCpltCallback() + HAL_FMPI2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_FMPI2C_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_FMPI2C_Slave_Receive_DMA() - (+) At reception end of transfer, @ref HAL_FMPI2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback() - (+) Abort a master FMPI2C process communication with Interrupt using @ref HAL_FMPI2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_FMPI2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_AbortCpltCallback() - (+) Discard a slave FMPI2C process communication using @ref __HAL_FMPI2C_GENERATE_NACK() macro. + HAL_FMPI2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_FMPI2C_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ErrorCallback() + (+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT() + (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback() + (+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro. This action will inform Master to generate a Stop condition to discard the communication. *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - @ref HAL_FMPI2C_Mem_Write_DMA() - (+) At Memory end of write transfer, @ref HAL_FMPI2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MemTxCpltCallback() + HAL_FMPI2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_FMPI2C_MemTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - @ref HAL_FMPI2C_Mem_Read_DMA() - (+) At Memory end of read transfer, @ref HAL_FMPI2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_FMPI2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPI2C_ErrorCallback() + HAL_FMPI2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_FMPI2C_MemRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPI2C_ErrorCallback() *** FMPI2C HAL driver macros list *** @@ -213,23 +240,23 @@ [..] Below the list of most used macros in FMPI2C HAL driver. - (+) @ref __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral - (+) @ref __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral - (+) @ref __HAL_FMPI2C_GENERATE_NACK: Generate a Non-Acknowledge FMPI2C peripheral in Slave mode - (+) @ref __HAL_FMPI2C_GET_FLAG: Check whether the specified FMPI2C flag is set or not - (+) @ref __HAL_FMPI2C_CLEAR_FLAG: Clear the specified FMPI2C pending flag - (+) @ref __HAL_FMPI2C_ENABLE_IT: Enable the specified FMPI2C interrupt - (+) @ref __HAL_FMPI2C_DISABLE_IT: Disable the specified FMPI2C interrupt + (+) __HAL_FMPI2C_ENABLE: Enable the FMPI2C peripheral + (+) __HAL_FMPI2C_DISABLE: Disable the FMPI2C peripheral + (+) __HAL_FMPI2C_GENERATE_NACK: Generate a Non-Acknowledge FMPI2C peripheral in Slave mode + (+) __HAL_FMPI2C_GET_FLAG: Check whether the specified FMPI2C flag is set or not + (+) __HAL_FMPI2C_CLEAR_FLAG: Clear the specified FMPI2C pending flag + (+) __HAL_FMPI2C_ENABLE_IT: Enable the specified FMPI2C interrupt + (+) __HAL_FMPI2C_DISABLE_IT: Disable the specified FMPI2C interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_FMPI2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_FMPI2C_RegisterCallback() or @ref HAL_FMPI2C_RegisterAddrCallback() + Use Functions HAL_FMPI2C_RegisterCallback() or HAL_FMPI2C_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_FMPI2C_RegisterCallback() allows to register following callbacks: + Function HAL_FMPI2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -244,11 +271,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_FMPI2C_RegisterAddrCallback(). + For specific callback AddrCallback use dedicated register callbacks : HAL_FMPI2C_RegisterAddrCallback(). [..] - Use function @ref HAL_FMPI2C_UnRegisterCallback to reset a callback to the default + Use function HAL_FMPI2C_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_FMPI2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_FMPI2C_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -263,24 +290,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_FMPI2C_UnRegisterAddrCallback(). + For callback AddrCallback use dedicated register callbacks : HAL_FMPI2C_UnRegisterAddrCallback(). [..] - By default, after the @ref HAL_FMPI2C_Init() and when the state is @ref HAL_FMPI2C_STATE_RESET + By default, after the HAL_FMPI2C_Init() and when the state is HAL_FMPI2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_FMPI2C_MasterTxCpltCallback(), @ref HAL_FMPI2C_MasterRxCpltCallback(). + examples HAL_FMPI2C_MasterTxCpltCallback(), HAL_FMPI2C_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_FMPI2C_Init()/ @ref HAL_FMPI2C_DeInit() only when + reset to the legacy weak functions in the HAL_FMPI2C_Init()/ HAL_FMPI2C_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_FMPI2C_Init()/ @ref HAL_FMPI2C_DeInit() + If MspInit or MspDeInit are not null, the HAL_FMPI2C_Init()/ HAL_FMPI2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_FMPI2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_FMPI2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_FMPI2C_STATE_READY or @ref HAL_FMPI2C_STATE_RESET state, + in HAL_FMPI2C_STATE_READY or HAL_FMPI2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_FMPI2C_RegisterCallback() before calling @ref HAL_FMPI2C_DeInit() - or @ref HAL_FMPI2C_Init() function. + using HAL_FMPI2C_RegisterCallback() before calling HAL_FMPI2C_DeInit() + or HAL_FMPI2C_Init() function. [..] When the compilation flag USE_HAL_FMPI2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -290,18 +317,6 @@ (@) You can refer to the FMPI2C HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -337,28 +352,48 @@ #define FMPI2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ #define MAX_NBYTE_SIZE 255U -#define SlaveAddr_SHIFT 7U -#define SlaveAddr_MSK 0x06U +#define SLAVE_ADDR_SHIFT 7U +#define SLAVE_ADDR_MSK 0x06U /* Private define for @ref PreviousState usage */ -#define FMPI2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_FMPI2C_STATE_BUSY_TX | (uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ -#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) /*!< Default Value */ -#define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | (uint32_t)HAL_FMPI2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_FMPI2C_STATE_BUSY_TX | \ + (uint32_t)HAL_FMPI2C_STATE_BUSY_RX) & \ + (uint32_t)(~((uint32_t)HAL_FMPI2C_STATE_READY)))) +/*!< Mask State define, keep only RX and TX bits */ +#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) +/*!< Default Value */ +#define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_MASTER)) +/*!< Master Busy TX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_MASTER)) +/*!< Master Busy RX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_SLAVE)) +/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_SLAVE)) +/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_MEM)) +/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ +#define FMPI2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | \ + (uint32_t)HAL_FMPI2C_MODE_MEM)) +/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ /* Private define to centralize the enable/disable of Interrupts */ -#define FMPI2C_XFER_TX_IT (uint16_t)(0x0001U) /* Bit field can be combinated with @ref FMPI2C_XFER_LISTEN_IT */ -#define FMPI2C_XFER_RX_IT (uint16_t)(0x0002U) /* Bit field can be combinated with @ref FMPI2C_XFER_LISTEN_IT */ -#define FMPI2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /* Bit field can be combinated with @ref FMPI2C_XFER_TX_IT and @ref FMPI2C_XFER_RX_IT */ - -#define FMPI2C_XFER_ERROR_IT (uint16_t)(0x0010U) /* Bit definition to manage addition of global Error and NACK treatment */ -#define FMPI2C_XFER_CPLT_IT (uint16_t)(0x0020U) /* Bit definition to manage only STOP evenement */ -#define FMPI2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /* Bit definition to manage only Reload of NBYTE */ +#define FMPI2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with + @ref FMPI2C_XFER_LISTEN_IT */ +#define FMPI2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with + @ref FMPI2C_XFER_LISTEN_IT */ +#define FMPI2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref FMPI2C_XFER_TX_IT + and @ref FMPI2C_XFER_RX_IT */ + +#define FMPI2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error + and NACK treatment */ +#define FMPI2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ +#define FMPI2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ /* Private define Sequential Transfer Options default/reset value */ #define FMPI2C_NO_OPTION_FRAME (0xFFFF0000U) @@ -367,6 +402,9 @@ */ /* Private macro -------------------------------------------------------------*/ +/* Macro to get remaining data to transfer on DMA side */ +#define FMPI2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) + /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -391,24 +429,38 @@ static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode); /* Private functions to handle IT transfer */ -static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart); /* Private functions for FMPI2C transfer IRQ handler */ -static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); -static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Mem_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Mem_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); +static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources); /* Private functions to handle flags during polling transfer */ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart); +static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart); /* Private functions to centralize the enable/disable of Interrupts */ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest); @@ -560,7 +612,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c) hfmpi2c->Instance->OAR2 &= ~FMPI2C_DUALADDRESS_ENABLE; /* Configure FMPI2Cx: Dual mode and Own Address2 */ - hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | (hfmpi2c->Init.OwnAddress2Masks << 8)); + hfmpi2c->Instance->OAR2 = (hfmpi2c->Init.DualAddressMode | hfmpi2c->Init.OwnAddress2 | \ + (hfmpi2c->Init.OwnAddress2Masks << 8)); /*---------------------------- FMPI2Cx CR1 Configuration ----------------------*/ /* Configure FMPI2Cx: Generalcall and NoStretch mode */ @@ -1066,10 +1119,11 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; + uint32_t xfermode; if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { @@ -1093,17 +1147,40 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint hfmpi2c->XferCount = Size; hfmpi2c->XferISR = NULL; - /* Send Slave Address */ - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); + xfermode = FMPI2C_RELOAD_MODE; } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE); + xfermode = FMPI2C_AUTOEND_MODE; + } + + if (hfmpi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + + /* Send Slave Address */ + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), xfermode, + FMPI2C_GENERATE_START_WRITE); + } + else + { + /* Send Slave Address */ + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, + FMPI2C_GENERATE_START_WRITE); } while (hfmpi2c->XferCount > 0U) @@ -1133,12 +1210,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_NO_STARTSTOP); } } } @@ -1181,8 +1260,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout) { uint32_t tickstart; @@ -1213,12 +1292,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_GENERATE_START_READ); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_READ); } while (hfmpi2c->XferCount > 0U) @@ -1249,12 +1330,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_NO_STARTSTOP); } } } @@ -1295,7 +1378,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint1 * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1377,22 +1461,27 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 hfmpi2c->XferCount--; } + /* Wait until AF flag is set */ + if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) + { + /* Disable Address Acknowledge */ + hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; + return HAL_ERROR; + } + + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); + + /* Clear AF flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + /* Wait until STOP flag is set */ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK) { /* Disable Address Acknowledge */ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK; - if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF) - { - /* Normal use case for Transmitter mode */ - /* A NACK is generated to confirm the end of transfer */ - hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; - } - else - { - return HAL_ERROR; - } + return HAL_ERROR; } /* Clear STOP flag */ @@ -1432,7 +1521,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8 * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; @@ -1456,6 +1546,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ /* Prepare transfer parameters */ hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; + hfmpi2c->XferSize = hfmpi2c->XferCount; hfmpi2c->XferISR = NULL; /* Enable Address Acknowledge */ @@ -1498,6 +1589,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ hfmpi2c->pBuffPtr++; hfmpi2c->XferCount--; + hfmpi2c->XferSize--; } return HAL_ERROR; @@ -1510,6 +1602,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_ hfmpi2c->pBuffPtr++; hfmpi2c->XferCount--; + hfmpi2c->XferSize--; } /* Wait until STOP flag is set */ @@ -1596,7 +1689,26 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u /* Send Slave Address */ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE); + if (hfmpi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), xfermode, + FMPI2C_GENERATE_START_WRITE); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, + FMPI2C_GENERATE_START_WRITE); + } /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -1607,7 +1719,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); return HAL_OK; @@ -1628,7 +1741,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, u * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size) { uint32_t xfermode; @@ -1676,7 +1790,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); return HAL_OK; @@ -1725,7 +1840,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, ui /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_LISTEN_IT); return HAL_OK; @@ -1774,7 +1890,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uin /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT); return HAL_OK; @@ -1800,6 +1917,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, { uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; if (hfmpi2c->State == HAL_FMPI2C_STATE_READY) { @@ -1832,6 +1950,20 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, xfermode = FMPI2C_AUTOEND_MODE; } + if (hfmpi2c->XferSize > 0U) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + sizetoxfer = hfmpi2c->XferSize; + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + if (hfmpi2c->XferSize > 0U) { if (hfmpi2c->hdmatx != NULL) @@ -1847,7 +1979,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, + (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); } else { @@ -1868,7 +2001,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, { /* Send Slave Address */ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)(hfmpi2c->XferSize + 1U), + xfermode, FMPI2C_GENERATE_START_WRITE); /* Update XferCount value */ hfmpi2c->XferCount -= hfmpi2c->XferSize; @@ -1907,7 +2041,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -1917,7 +2052,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } @@ -1991,7 +2127,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, + hfmpi2c->XferSize); } else { @@ -2051,7 +2188,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2061,7 +2199,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } @@ -2119,7 +2258,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, u hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize); } else { @@ -2222,7 +2362,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, ui hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, + hfmpi2c->XferSize); } else { @@ -2375,12 +2516,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t D if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_NO_STARTSTOP); } } @@ -2475,12 +2618,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_GENERATE_START_READ); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_READ); } do @@ -2511,12 +2656,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t) hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t) hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, + FMPI2C_NO_STARTSTOP); } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_NO_STARTSTOP); } } } while (hfmpi2c->XferCount > 0U); @@ -2562,9 +2709,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t De HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); @@ -2584,9 +2728,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -2595,29 +2736,29 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_IT; + hfmpi2c->Devaddress = DevAddress; - if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP); + /* Send Slave Address and Memory Address */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2628,7 +2769,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); return HAL_OK; @@ -2654,9 +2796,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; - /* Check the parameters */ assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize)); @@ -2676,9 +2815,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -2687,29 +2823,29 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_IT; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_IT; + hfmpi2c->Devaddress = DevAddress; - if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ else { - hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; - } + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); - /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); } - - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); + /* Send Slave Address and Memory Address */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2720,8 +2856,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t /* Enable ERR, TC, STOP, NACK, RXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT); + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + FMPI2C_Enable_IRQ(hfmpi2c, (FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT)); return HAL_OK; } @@ -2745,8 +2882,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2768,9 +2903,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -2779,27 +2911,36 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_DMA; + hfmpi2c->Devaddress = DevAddress; if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); + } if (hfmpi2c->hdmatx != NULL) { @@ -2814,7 +2955,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize); } else { @@ -2833,12 +2975,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 if (dmaxferstatus == HAL_OK) { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP); - - /* Update XferCount value */ - hfmpi2c->XferCount -= hfmpi2c->XferSize; + /* Send Slave Address and Memory Address */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2846,11 +2984,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } else { @@ -2890,8 +3028,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Write_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16 HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) { - uint32_t tickstart; - uint32_t xfermode; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -2913,9 +3049,6 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Process Locked */ __HAL_LOCK(hfmpi2c); - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX; hfmpi2c->Mode = HAL_FMPI2C_MODE_MEM; hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; @@ -2924,25 +3057,35 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ hfmpi2c->pBuffPtr = pData; hfmpi2c->XferCount = Size; hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME; - hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA; + hfmpi2c->XferISR = FMPI2C_Mem_ISR_DMA; + hfmpi2c->Devaddress = DevAddress; if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) { hfmpi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = FMPI2C_RELOAD_MODE; } else { hfmpi2c->XferSize = hfmpi2c->XferCount; - xfermode = FMPI2C_AUTOEND_MODE; } - /* Send Slave Address and Memory Address */ - if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK) + /* If Memory address size is 8Bit */ + if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT) { - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Prefetch Memory Address */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress); + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; + } + /* If Memory address size is 16Bit */ + else + { + /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ + hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress); + + /* Prepare Memaddress buffer for LSB part */ + hfmpi2c->Memaddress = FMPI2C_MEM_ADD_LSB(MemAddress); } if (hfmpi2c->hdmarx != NULL) @@ -2958,7 +3101,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, + hfmpi2c->XferSize); } else { @@ -2977,11 +3121,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ if (dmaxferstatus == HAL_OK) { - /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ); - - /* Update XferCount value */ - hfmpi2c->XferCount -= hfmpi2c->XferSize; + /* Send Slave Address and Memory Address */ + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -2989,11 +3130,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ - /* Enable ERR and NACK interrupts */ - FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } else { @@ -3029,7 +3170,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Mem_Read_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_ * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) +HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, + uint32_t Timeout) { uint32_t tickstart; @@ -3175,6 +3317,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 { uint32_t xfermode; uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3206,9 +3349,26 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 xfermode = hfmpi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + if ((hfmpi2c->XferSize > 0U) && ((XferOptions == FMPI2C_FIRST_FRAME) || \ + (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + sizetoxfer = hfmpi2c->XferSize; + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && \ + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3225,7 +3385,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 } /* Send Slave Address and set NBYTES to write */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)) + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3233,6 +3400,10 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2 /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ + /* Enable ERR, TC, STOP, NACK, TXI interrupt */ + /* possible to enable all of these */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); return HAL_OK; @@ -3261,6 +3432,7 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi uint32_t xfermode; uint32_t xferrequest = FMPI2C_GENERATE_START_WRITE; HAL_StatusTypeDef dmaxferstatus; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3292,9 +3464,26 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi xfermode = hfmpi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + if ((hfmpi2c->XferSize > 0U) && ((XferOptions == FMPI2C_FIRST_FRAME) || \ + (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + sizetoxfer = hfmpi2c->XferSize; + hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + } + + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX) && \ + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3325,7 +3514,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, + (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); } else { @@ -3345,7 +3535,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi if (dmaxferstatus == HAL_OK) { /* Send Slave Address and set NBYTES to write */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)) + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + } /* Update XferCount value */ hfmpi2c->XferCount -= hfmpi2c->XferSize; @@ -3384,7 +3581,14 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi /* Send Slave Address */ /* Set NBYTES to write and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE); + if ((XferOptions == FMPI2C_FIRST_FRAME) || (XferOptions == FMPI2C_FIRST_AND_LAST_FRAME)) + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest); + } + else + { + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, xfermode, xferrequest); + } /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3394,7 +3598,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } @@ -3454,9 +3659,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c xfermode = hfmpi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && \ + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3540,9 +3747,11 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 xfermode = hfmpi2c->XferOptions; } - /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ + /* If transfer direction not change and there is no request to start another frame, + do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) + if ((hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX) && \ + (IS_FMPI2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) { xferrequest = FMPI2C_NO_STARTSTOP; } @@ -3573,7 +3782,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, + hfmpi2c->XferSize); } else { @@ -3632,7 +3842,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 /* Send Slave Address */ /* Set NBYTES to read and generate START condition */ - FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ); + FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, + FMPI2C_GENERATE_START_READ); /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); @@ -3642,7 +3853,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 process unlock */ /* Enable ERR, TC, STOP, NACK, TXI interrupt */ /* possible to enable all of these */ - /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ + /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | + FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT); } @@ -3667,6 +3879,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Master_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2 HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -3726,7 +3941,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c hfmpi2c->XferOptions = XferOptions; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -3763,6 +3979,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -3863,7 +4081,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 hfmpi2c->hdmatx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize); } else { @@ -3903,7 +4122,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 return HAL_ERROR; } - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -3913,15 +4133,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); + /* Enable DMA Request */ + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ /* Enable ERR, STOP, NACK, ADDR interrupts */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; - return HAL_OK; } else @@ -3943,6 +4163,9 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2 HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; + /* Check the parameters */ assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -4002,7 +4225,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, hfmpi2c->XferOptions = XferOptions; hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT; - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4039,6 +4263,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) { + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + FlagStatus tmp; HAL_StatusTypeDef dmaxferstatus; /* Check the parameters */ @@ -4139,7 +4365,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c hfmpi2c->hdmarx->XferAbortCallback = NULL; /* Enable the DMA stream */ - dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize); + dmaxferstatus = HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, + (uint32_t)pData, hfmpi2c->XferSize); } else { @@ -4179,7 +4406,8 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c return HAL_ERROR; } - if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) + tmp = __HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR); + if ((FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT) && (tmp != RESET)) { /* Clear ADDR flag after prepare the transfer parameters */ /* This action will generate an acknowledge to the Master */ @@ -4189,15 +4417,15 @@ HAL_StatusTypeDef HAL_FMPI2C_Slave_Seq_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); + /* Enable DMA Request */ + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + /* Note : The FMPI2C interrupts must be enabled after unlocking current process to avoid the risk of FMPI2C interrupt handle execution before current process unlock */ /* REnable ADDR interrupt */ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_LISTEN_IT); - /* Enable DMA Request */ - hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; - return HAL_OK; } else @@ -4357,7 +4585,8 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) uint32_t tmperror; /* FMPI2C Bus error interrupt occurred ------------------------------------*/ - if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_BERR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) + if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_BERR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR; @@ -4366,7 +4595,8 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) } /* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_OVR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) + if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_OVR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR; @@ -4375,7 +4605,8 @@ void HAL_FMPI2C_ER_IRQHandler(FMPI2C_HandleTypeDef *hfmpi2c) } /* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_ARLO) != RESET) && (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) + if ((FMPI2C_CHECK_FLAG(itflags, FMPI2C_FLAG_ARLO) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(itsources, FMPI2C_IT_ERRI) != RESET)) { hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO; @@ -4629,7 +4860,8 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c) * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t tmpITFlags = ITFlags; @@ -4637,7 +4869,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm /* Process Locked */ __HAL_LOCK(hfmpi2c); - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -4650,7 +4883,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) { /* Remove RXNE flag on temporary variable as read done */ tmpITFlags &= ~FMPI2C_FLAG_RXNE; @@ -4664,18 +4898,25 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm hfmpi2c->XferSize--; hfmpi2c->XferCount--; } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) == RESET) && \ + ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET))) { /* Write data to TXDR */ - hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + if (hfmpi2c->XferCount != 0U) + { + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; - /* Increment Buffer pointer */ - hfmpi2c->pBuffPtr++; + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; - hfmpi2c->XferSize--; - hfmpi2c->XferCount--; + hfmpi2c->XferSize--; + hfmpi2c->XferCount--; + } } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) { if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U)) { @@ -4691,11 +4932,13 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm hfmpi2c->XferSize = hfmpi2c->XferCount; if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) { - FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, + hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP); } else { - FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + FMPI2C_TransferConfig(hfmpi2c, devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); } } } @@ -4715,7 +4958,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm } } } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) { if (hfmpi2c->XferCount == 0U) { @@ -4746,7 +4990,145 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm /* Nothing to do */ } - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + { + /* Call FMPI2C Master complete process */ + FMPI2C_ITMasterCplt(hfmpi2c, tmpITFlags); + } + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. + * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains + * the configuration information for the specified FMPI2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef FMPI2C_Mem_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = FMPI2C_GENERATE_START_WRITE; + uint32_t tmpITFlags = ITFlags; + + /* Process Locked */ + __HAL_LOCK(hfmpi2c); + + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Set corresponding Error Code */ + /* No need to generate STOP, it is automatically done */ + /* Error callback will be send during stop flag treatment */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) + { + /* Remove RXNE flag on temporary variable as read done */ + tmpITFlags &= ~FMPI2C_FLAG_RXNE; + + /* Read data from RXDR */ + *hfmpi2c->pBuffPtr = (uint8_t)hfmpi2c->Instance->RXDR; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferSize--; + hfmpi2c->XferCount--; + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) + { + if (hfmpi2c->Memaddress == 0xFFFFFFFFU) + { + /* Write data to TXDR */ + hfmpi2c->Instance->TXDR = *hfmpi2c->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpi2c->pBuffPtr++; + + hfmpi2c->XferSize--; + hfmpi2c->XferCount--; + } + else + { + /* Write LSB part of Memory Address */ + hfmpi2c->Instance->TXDR = hfmpi2c->Memaddress; + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; + } + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TCR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + if ((hfmpi2c->XferCount != 0U) && (hfmpi2c->XferSize == 0U)) + { + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE); + } + } + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TC) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + direction = FMPI2C_GENERATE_START_READ; + } + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, direction); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, direction); + } + } + else + { + /* Nothing to do */ + } + + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Master complete process */ FMPI2C_ITMasterCplt(hfmpi2c, tmpITFlags); @@ -4766,7 +5148,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfm * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hfmpi2c->XferOptions; uint32_t tmpITFlags = ITFlags; @@ -4775,13 +5158,15 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp __HAL_LOCK(hfmpi2c); /* Check if STOPF is set */ - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Slave complete process */ FMPI2C_ITSlaveCplt(hfmpi2c, tmpITFlags); } - if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Check that FMPI2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -4789,8 +5174,9 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp /* So clear Flag NACKF only */ if (hfmpi2c->XferCount == 0U) { - /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call FMPI2C Listen complete process */ FMPI2C_ITListenCplt(hfmpi2c, tmpITFlags); @@ -4829,7 +5215,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp } } } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_RXNE) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_RXI) != RESET)) { if (hfmpi2c->XferCount > 0U) { @@ -4855,11 +5242,12 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp { FMPI2C_ITAddrCplt(hfmpi2c, tmpITFlags); } - else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(tmpITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) { /* Write data to TXDR only if XferCount not reach "0" */ /* A TXIS flag can be set, during STOP treatment */ - /* Check if all data have already been sent */ + /* Check if all Data have already been sent */ /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ if (hfmpi2c->XferCount > 0U) { @@ -4901,7 +5289,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmp * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) { uint16_t devaddress; uint32_t xfermode; @@ -4909,7 +5298,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf /* Process Locked */ __HAL_LOCK(hfmpi2c); - if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Clear NACK Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); @@ -4925,7 +5315,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); } - else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TCR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TCR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) { /* Disable TC interrupt */ __HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_TCI); @@ -4986,7 +5377,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf } } } - else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TC) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TC) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) { if (hfmpi2c->XferCount == 0U) { @@ -5012,7 +5404,147 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE); } } - else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + { + /* Call FMPI2C Master complete process */ + FMPI2C_ITMasterCplt(hfmpi2c, ITFlags); + } + else + { + /* Nothing to do */ + } + + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + + return HAL_OK; +} + +/** + * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. + * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains + * the configuration information for the specified FMPI2C. + * @param ITFlags Interrupt flags to handle. + * @param ITSources Interrupt sources enabled. + * @retval HAL status + */ +static HAL_StatusTypeDef FMPI2C_Mem_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) +{ + uint32_t direction = FMPI2C_GENERATE_START_WRITE; + + /* Process Locked */ + __HAL_LOCK(hfmpi2c); + + if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + { + /* Clear NACK Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Set corresponding Error Code */ + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + + /* No need to generate STOP, it is automatically done */ + /* But enable STOP interrupt, to treat it */ + /* Error callback will be send during stop flag treatment */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT); + + /* Flush TX register */ + FMPI2C_Flush_TXDR(hfmpi2c); + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TXIS) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TXI) != RESET)) + { + /* Write LSB part of Memory Address */ + hfmpi2c->Instance->TXDR = hfmpi2c->Memaddress; + + /* Reset Memaddress content */ + hfmpi2c->Memaddress = 0xFFFFFFFFU; + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TCR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + /* Enable only Error interrupt */ + FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT); + + if (hfmpi2c->XferCount != 0U) + { + /* Prepare the new XferSize to transfer */ + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP); + } + + /* Update XferCount value */ + hfmpi2c->XferCount -= hfmpi2c->XferSize; + + /* Enable DMA Request */ + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + } + else + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + } + } + else + { + /* Wrong size Status regarding TCR flag event */ + /* Call the corresponding callback to inform upper layer of End of Transfer */ + FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE); + } + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_TC) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_TCI) != RESET)) + { + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + direction = FMPI2C_GENERATE_START_READ; + } + + if (hfmpi2c->XferCount > MAX_NBYTE_SIZE) + { + hfmpi2c->XferSize = MAX_NBYTE_SIZE; + + /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_RELOAD_MODE, direction); + } + else + { + hfmpi2c->XferSize = hfmpi2c->XferCount; + + /* Set NBYTES to write and generate RESTART */ + FMPI2C_TransferConfig(hfmpi2c, (uint16_t)hfmpi2c->Devaddress, (uint8_t)hfmpi2c->XferSize, + FMPI2C_AUTOEND_MODE, direction); + } + + /* Update XferCount value */ + hfmpi2c->XferCount -= hfmpi2c->XferSize; + + /* Enable DMA Request */ + if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX) + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN; + } + else + { + hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN; + } + } + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Master complete process */ FMPI2C_ITMasterCplt(hfmpi2c, ITFlags); @@ -5036,7 +5568,8 @@ static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hf * @param ITSources Interrupt sources enabled. * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources) +static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, + uint32_t ITSources) { uint32_t tmpoptions = hfmpi2c->XferOptions; uint32_t treatdmanack = 0U; @@ -5046,13 +5579,15 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm __HAL_LOCK(hfmpi2c); /* Check if STOPF is set */ - if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) + if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_STOPF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_STOPI) != RESET)) { /* Call FMPI2C Slave complete process */ FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags); } - if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) + if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_AF) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_NACKI) != RESET)) { /* Check that FMPI2C transfer finished */ /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ @@ -5066,7 +5601,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm { if (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_RXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U) { treatdmanack = 1U; } @@ -5078,7 +5613,7 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm { if (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_CR1_TXDMAEN) != RESET) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx) == 0U) { treatdmanack = 1U; } @@ -5087,8 +5622,9 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm if (treatdmanack == 1U) { - /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for Warning[Pa134]: left and right operands are identical */ if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) && (tmpoptions == FMPI2C_FIRST_AND_LAST_FRAME)) + /* Same action must be done for (tmpoptions == FMPI2C_LAST_FRAME) which removed for + Warning[Pa134]: left and right operands are identical */ { /* Call FMPI2C Listen complete process */ FMPI2C_ITListenCplt(hfmpi2c, ITFlags); @@ -5149,7 +5685,8 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); } } - else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_ADDR) != RESET) && (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_ADDRI) != RESET)) + else if ((FMPI2C_CHECK_FLAG(ITFlags, FMPI2C_FLAG_ADDR) != RESET) && \ + (FMPI2C_CHECK_IT_SOURCE(ITSources, FMPI2C_IT_ADDRI) != RESET)) { FMPI2C_ITAddrCplt(hfmpi2c, ITFlags); } @@ -5176,8 +5713,9 @@ static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfm * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE); @@ -5230,8 +5768,9 @@ static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, + uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, + uint32_t Tickstart) { FMPI2C_TransferConfig(hfmpi2c, DevAddress, (uint8_t)MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE); @@ -5299,7 +5838,7 @@ static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) /* If 10bits addressing mode is selected */ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT) { - if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK)) + if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) { slaveaddrcode = ownadd1code; hfmpi2c->AddrEventCount++; @@ -5685,7 +6224,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) if (hfmpi2c->hdmatx != NULL) { - hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx); + hfmpi2c->XferCount = (uint16_t)FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx); } } else if (FMPI2C_CHECK_IT_SOURCE(tmpcr1value, FMPI2C_CR1_RXDMAEN) != RESET) @@ -5695,7 +6234,7 @@ static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags) if (hfmpi2c->hdmarx != NULL) { - hfmpi2c->XferCount = (uint16_t)__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx); + hfmpi2c->XferCount = (uint16_t)FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx); } } else @@ -6026,7 +6565,8 @@ static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c) */ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN; @@ -6054,7 +6594,8 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, + hfmpi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_DMA); @@ -6074,7 +6615,8 @@ static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hfmpi2c->XferOptions; if ((tmpoptions == FMPI2C_NEXT_FRAME) || (tmpoptions == FMPI2C_FIRST_FRAME)) @@ -6101,7 +6643,8 @@ static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable DMA Request */ hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN; @@ -6129,7 +6672,8 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) } /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize) != HAL_OK) + if (HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, + hfmpi2c->XferSize) != HAL_OK) { /* Call the corresponding callback to inform upper layer of End of Transfer */ FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_DMA); @@ -6149,10 +6693,11 @@ static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tmpoptions = hfmpi2c->XferOptions; - if ((__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) && \ + if ((FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U) && \ (tmpoptions != FMPI2C_NO_OPTION_FRAME)) { /* Disable DMA Request */ @@ -6177,11 +6722,12 @@ static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) { uint32_t treatdmaerror = 0U; - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); if (hfmpi2c->hdmatx != NULL) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmatx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmatx) == 0U) { treatdmaerror = 1U; } @@ -6189,7 +6735,7 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) if (hfmpi2c->hdmarx != NULL) { - if (__HAL_DMA_GET_COUNTER(hfmpi2c->hdmarx) == 0U) + if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c->hdmarx) == 0U) { treatdmaerror = 1U; } @@ -6214,7 +6760,8 @@ static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma) */ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) { - FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + /* Derogation MISRAC2012-Rule-11.5 */ + FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Reset AbortCpltCallback */ if (hfmpi2c->hdmatx != NULL) @@ -6230,11 +6777,12 @@ static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles FMPI2C Communication Timeout. + * @brief This function handles FMPI2C Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param Flag Specifies the FMPI2C flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status @@ -6249,13 +6797,16 @@ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfm { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); + return HAL_ERROR; + } } } } @@ -6270,12 +6821,13 @@ static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfm * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET) { - /* Check if a NACK is detected */ - if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6285,14 +6837,17 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -6307,12 +6862,13 @@ static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) { - /* Check if a NACK is detected */ - if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6320,14 +6876,17 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; + hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -6341,12 +6900,13 @@ static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, + uint32_t Tickstart) { while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET) { - /* Check if a NACK is detected */ - if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK) + /* Check if an error is detected */ + if (FMPI2C_IsErrorOccurred(hfmpi2c, Timeout, Tickstart) != HAL_OK) { return HAL_ERROR; } @@ -6364,13 +6924,22 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef } else { + if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) + { + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF; + } + else + { + hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; + } + /* Clear STOP Flag */ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); /* Clear Configuration Register 2 */ FMPI2C_RESET_CR2(hfmpi2c); - hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE; hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; @@ -6384,73 +6953,149 @@ static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)) + { + hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; + hfmpi2c->State = HAL_FMPI2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hfmpi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; } /** - * @brief This function handles Acknowledge failed detection during an FMPI2C Communication. + * @brief This function handles errors detection during an FMPI2C Communication. * @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains * the configuration information for the specified FMPI2C. * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) +static HAL_StatusTypeDef FMPI2C_IsErrorOccurred(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart) { - if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET) + HAL_StatusTypeDef status = HAL_OK; + uint32_t itflag = hfmpi2c->Instance->ISR; + uint32_t error_code = 0; + uint32_t tickstart = Tickstart; + uint32_t tmp1; + HAL_FMPI2C_ModeTypeDef tmp2; + + if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_AF)) { - /* Wait until STOP Flag is reset */ + /* Clear NACKF Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + + /* Wait until STOP Flag is set or timeout occurred */ /* AutoEnd should be initiate after AF */ - while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) + while ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT; - hfmpi2c->State = HAL_FMPI2C_STATE_READY; - hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; + tmp1 = (uint32_t)(hfmpi2c->Instance->CR2 & FMPI2C_CR2_STOP); + tmp2 = hfmpi2c->Mode; - /* Process Unlocked */ - __HAL_UNLOCK(hfmpi2c); + /* In case of FMPI2C still busy, try to regenerate a STOP manually */ + if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) != RESET) && \ + (tmp1 != FMPI2C_CR2_STOP) && \ + (tmp2 != HAL_FMPI2C_MODE_SLAVE)) + { + /* Generate Stop */ + hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP; - return HAL_ERROR; + /* Update Tick with new reference */ + tickstart = HAL_GetTick(); + } + + while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > FMPI2C_TIMEOUT_STOPF) + { + error_code |=HAL_FMPI2C_ERROR_TIMEOUT; + + status = HAL_ERROR; + + break; + } + } } } } - /* Clear NACKF Flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF); + /* In case STOP Flag is detected, clear it */ + if (status == HAL_OK) + { + /* Clear STOP Flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + } - /* Clear STOP Flag */ - __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF); + error_code |= HAL_FMPI2C_ERROR_AF; + + status = HAL_ERROR; + } + + /* Refresh Content of Status register */ + itflag = hfmpi2c->Instance->ISR; + + /* Then verify if an additional errors occurs */ + /* Check if a Bus error occurred */ + if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_BERR)) + { + error_code |= HAL_FMPI2C_ERROR_BERR; + + /* Clear BERR flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_BERR); + + status = HAL_ERROR; + } + /* Check if an Over-Run/Under-Run error occurred */ + if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_OVR)) + { + error_code |= HAL_FMPI2C_ERROR_OVR; + + /* Clear OVR flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_OVR); + + status = HAL_ERROR; + } + + /* Check if an Arbitration Loss error occurred */ + if (HAL_IS_BIT_SET(itflag, FMPI2C_FLAG_ARLO)) + { + error_code |= HAL_FMPI2C_ERROR_ARLO; + + /* Clear ARLO flag */ + __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ARLO); + + status = HAL_ERROR; + } + + if (status != HAL_OK) + { /* Flush TX register */ FMPI2C_Flush_TXDR(hfmpi2c); /* Clear Configuration Register 2 */ FMPI2C_RESET_CR2(hfmpi2c); - hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF; + hfmpi2c->ErrorCode |= error_code; hfmpi2c->State = HAL_FMPI2C_STATE_READY; hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE; /* Process Unlocked */ __HAL_UNLOCK(hfmpi2c); - - return HAL_ERROR; } - return HAL_OK; + + return status; } /** @@ -6480,12 +7125,16 @@ static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAdd assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); + /* Declaration of tmp to prevent undefined behavior of volatile usage */ + uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | \ + (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + /* update CR2 register */ - MODIFY_REG(hfmpi2c->Instance->CR2, + MODIFY_REG(hfmpi2c->Instance->CR2, \ ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | \ - (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP)), \ - (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | - (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | \ + FMPI2C_CR2_START | FMPI2C_CR2_STOP)), tmp); } /** @@ -6546,6 +7195,12 @@ static void FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptR tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI; } + if (InterruptRequest == FMPI2C_XFER_ERROR_IT) + { + /* Enable ERR and NACK interrupts */ + tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI; + } + if (InterruptRequest == FMPI2C_XFER_CPLT_IT) { /* Enable STOP interrupts */ @@ -6665,5 +7320,3 @@ static void FMPI2C_ConvertOtherXferOptions(FMPI2C_HandleTypeDef *hfmpi2c) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c.h index 270a92b7478..90ab2c6d71c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -49,29 +48,30 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the FMPI2C_TIMINGR_register value. - This parameter calculated by referring to FMPI2C initialization - section in Reference manual */ + This parameter calculated by referring to FMPI2C initialization section + in Reference manual */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref FMPI2C_ADDRESSING_MODE */ + This parameter can be a value of @ref FMPI2C_ADDRESSING_MODE */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref FMPI2C_DUAL_ADDRESSING_MODE */ + This parameter can be a value of @ref FMPI2C_DUAL_ADDRESSING_MODE */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref FMPI2C_OWN_ADDRESS2_MASKS */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing + mode is selected. + This parameter can be a value of @ref FMPI2C_OWN_ADDRESS2_MASKS */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref FMPI2C_GENERAL_CALL_ADDRESSING_MODE */ + This parameter can be a value of @ref FMPI2C_GENERAL_CALL_ADDRESSING_MODE */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */ + This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */ } FMPI2C_InitTypeDef; @@ -201,7 +201,8 @@ typedef struct __FMPI2C_HandleTypeDef __IO uint32_t PreviousState; /*!< FMPI2C communication Previous state */ - HAL_StatusTypeDef(*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); /*!< FMPI2C transfer IRQ handler function pointer */ + HAL_StatusTypeDef(*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); + /*!< FMPI2C transfer IRQ handler function pointer */ DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */ @@ -217,21 +218,37 @@ typedef struct __FMPI2C_HandleTypeDef __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */ -#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Listen Complete callback */ - void (* MemTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Memory Tx Transfer completed callback */ - void (* MemRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Memory Rx Transfer completed callback */ - void (* ErrorCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Error callback */ - void (* AbortCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Abort callback */ + __IO uint32_t Devaddress; /*!< FMPI2C Target device address */ - void (* AddrCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< FMPI2C Slave Address Match callback */ + __IO uint32_t Memaddress; /*!< FMPI2C Target memory address */ - void (* MspInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Msp Init callback */ - void (* MspDeInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); /*!< FMPI2C Msp DeInit callback */ +#if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) + void (* MasterTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Listen Complete callback */ + void (* MemTxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Memory Tx Transfer completed callback */ + void (* MemRxCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Memory Rx Transfer completed callback */ + void (* ErrorCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Error callback */ + void (* AbortCpltCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Abort callback */ + + void (* AddrCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< FMPI2C Slave Address Match callback */ + + void (* MspInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Msp Init callback */ + void (* MspDeInitCallback)(struct __FMPI2C_HandleTypeDef *hfmpi2c); + /*!< FMPI2C Msp DeInit callback */ #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ } FMPI2C_HandleTypeDef; @@ -260,8 +277,11 @@ typedef enum /** * @brief HAL FMPI2C Callback pointer definition */ -typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c); /*!< pointer to an FMPI2C callback function */ -typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an FMPI2C Address Match callback function */ +typedef void (*pFMPI2C_CallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c); +/*!< pointer to an FMPI2C callback function */ +typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an FMPI2C Address Match callback function */ #endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ /** @@ -441,14 +461,14 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint * @retval None */ #if (USE_HAL_FMPI2C_REGISTER_CALLBACKS == 1) -#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ +#define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_FMPI2C_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_FMPI2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPI2C_STATE_RESET) -#endif +#endif /* USE_HAL_FMPI2C_REGISTER_CALLBACKS */ /** @brief Enable the specified FMPI2C interrupt. * @param __HANDLE__ specifies the FMPI2C Handle. @@ -543,26 +563,27 @@ typedef void (*pFMPI2C_AddrCallbackTypeDef)(FMPI2C_HandleTypeDef *hfmpi2c, uint * * @retval None */ -#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \ - : ((__HANDLE__)->Instance->ICR = (__FLAG__))) +#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified FMPI2C peripheral. * @param __HANDLE__ specifies the FMPI2C Handle. * @retval None */ -#define __HAL_FMPI2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) +#define __HAL_FMPI2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) /** @brief Disable the specified FMPI2C peripheral. * @param __HANDLE__ specifies the FMPI2C Handle. * @retval None */ -#define __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) +#define __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) /** @brief Generate a Non-Acknowledge FMPI2C peripheral in Slave mode. * @param __HANDLE__ specifies the FMPI2C Handle. * @retval None */ -#define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) +#define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) /** * @} */ @@ -602,12 +623,14 @@ HAL_StatusTypeDef HAL_FMPI2C_UnRegisterAddrCallback(FMPI2C_HandleTypeDef *hfmpi2 */ /* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, +HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Mem_Write(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, @@ -758,10 +781,14 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); ((REQUEST) == FMPI2C_OTHER_AND_LAST_FRAME)) #define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN))) - -#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 16U)) -#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U)) + (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ + FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ + FMPI2C_CR2_RD_WRN))) + +#define FMPI2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) \ + >> 16U)) +#define FMPI2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) \ + >> 16U)) #define FMPI2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) #define FMPI2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & FMPI2C_OAR1_OA1)) #define FMPI2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & FMPI2C_OAR2_OA2)) @@ -773,10 +800,15 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); (uint16_t)(0xFF00U))) >> 8U))) #define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) -#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) +#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ + (~FMPI2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & \ + (~FMPI2C_CR2_RD_WRN))) -#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \ +#define FMPI2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPI2C_FLAG_MASK)) == \ ((__FLAG__) & FMPI2C_FLAG_MASK)) ? SET : RESET) #define FMPI2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) /** @@ -807,5 +839,3 @@ uint32_t HAL_FMPI2C_GetError(FMPI2C_HandleTypeDef *hfmpi2c); #endif /* STM32F4xx_HAL_FMPI2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c_ex.c index a6acc9e5cfb..267a9ef13d6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c_ex.c @@ -5,8 +5,20 @@ * @brief FMPI2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of FMPI2C Extended peripheral: - * + Extended features functions + * + Filter Mode Functions + * + FastModePlus Functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### FMPI2C peripheral Extended features ##### @@ -28,18 +40,6 @@ (++) HAL_FMPI2CEx_EnableFastModePlus() (++) HAL_FMPI2CEx_DisableFastModePlus() @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -68,16 +68,15 @@ * @{ */ -/** @defgroup FMPI2CEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions +/** @defgroup FMPI2CEx_Exported_Functions_Group1 Filter Mode Functions + * @brief Filter Mode Functions * @verbatim =============================================================================== - ##### Extended features functions ##### + ##### Filter Mode Functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters - (+) Configure Fast Mode Plus @endverbatim * @{ @@ -178,6 +177,23 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup FMPI2CEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * +@verbatim + =============================================================================== + ##### Fast Mode Plus Functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Configure Fast Mode Plus + +@endverbatim + * @{ + */ /** * @brief Enable the FMPI2C fast mode plus driving capability. @@ -224,11 +240,9 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /* Disable fast mode plus driving capability for selected pin */ CLEAR_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus); } - /** * @} */ - /** * @} */ @@ -242,5 +256,3 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c_ex.h index 326b05853a4..8b90f407521 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpi2c_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -79,7 +78,7 @@ extern "C" { * @{ */ -/** @addtogroup FMPI2CEx_Exported_Functions_Group1 FMPI2C Extended Filter Mode Functions +/** @addtogroup FMPI2CEx_Exported_Functions_Group1 Filter Mode Functions * @{ */ /* Peripheral Control functions ************************************************/ @@ -89,14 +88,7 @@ HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c * @} */ -/** @addtogroup FMPI2CEx_Exported_Functions_Group2 FMPI2C Extended WakeUp Mode Functions - * @{ - */ -/** - * @} - */ - -/** @addtogroup FMPI2CEx_Exported_Functions_Group3 FMPI2C Extended FastModePlus Functions +/** @addtogroup FMPI2CEx_Exported_Functions_Group3 Fast Mode Plus Functions * @{ */ void HAL_FMPI2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); @@ -105,7 +97,6 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); * @} */ - /** * @} */ @@ -138,7 +129,7 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** @defgroup FMPI2CEx_Private_Functions FMPI2C Extended Private Functions * @{ */ -/* Private functions are defined in stm32f4xx_hal_fmpfmpi2c_ex.c file */ +/* Private functions are defined in stm32f4xx_hal_fmpi2c_ex.c file */ /** * @} */ @@ -157,5 +148,3 @@ void HAL_FMPI2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif #endif /* STM32F4xx_HAL_FMPI2C_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus.c index c2bc779c1bd..1df2c7dfa49 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus.c @@ -10,6 +10,17 @@ * + IO operation functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -20,7 +31,7 @@ (#) Declare a FMPSMBUS_HandleTypeDef handle structure, for example: FMPSMBUS_HandleTypeDef hfmpsmbus; - (#)Initialize the FMPSMBUS low level resources by implementing the @ref HAL_FMPSMBUS_MspInit() API: + (#)Initialize the FMPSMBUS low level resources by implementing the HAL_FMPSMBUS_MspInit() API: (##) Enable the FMPSMBUSx interface clock (##) FMPSMBUS pins configuration (+++) Enable the clock for the FMPSMBUS GPIOs @@ -33,69 +44,75 @@ Dual Addressing mode, Own Address2, Own Address2 Mask, General call, Nostretch mode, Peripheral mode and Packet Error Check mode in the hfmpsmbus Init structure. - (#) Initialize the FMPSMBUS registers by calling the @ref HAL_FMPSMBUS_Init() API: + (#) Initialize the FMPSMBUS registers by calling the HAL_FMPSMBUS_Init() API: (++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized @ref HAL_FMPSMBUS_MspInit(&hfmpsmbus) API. + by calling the customized HAL_FMPSMBUS_MspInit(&hfmpsmbus) API. - (#) To check if target device is ready for communication, use the function @ref HAL_FMPSMBUS_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_FMPSMBUS_IsDeviceReady() (#) For FMPSMBUS IO operations, only one mode of operations is available within this driver *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master/host FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Master_Transmit_IT() - (++) At transmission end of transfer @ref HAL_FMPSMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_MasterTxCpltCallback() - (+) Receive in master/host FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Master_Receive_IT() - (++) At reception end of transfer @ref HAL_FMPSMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_MasterRxCpltCallback() - (+) Abort a master/host FMPSMBUS process communication with Interrupt using @ref HAL_FMPSMBUS_Master_Abort_IT() + (+) Transmit in master/host FMPSMBUS mode an amount of data in non-blocking mode + using HAL_FMPSMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_FMPSMBUS_MasterTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_MasterTxCpltCallback() + (+) Receive in master/host FMPSMBUS mode an amount of data in non-blocking mode + using HAL_FMPSMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_FMPSMBUS_MasterRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_MasterRxCpltCallback() + (+) Abort a master/host FMPSMBUS process communication with Interrupt using HAL_FMPSMBUS_Master_Abort_IT() (++) The associated previous transfer callback is called at the end of abort process - (++) mean @ref HAL_FMPSMBUS_MasterTxCpltCallback() in case of previous state was master transmit - (++) mean @ref HAL_FMPSMBUS_MasterRxCpltCallback() in case of previous state was master receive + (++) mean HAL_FMPSMBUS_MasterTxCpltCallback() in case of previous state was master transmit + (++) mean HAL_FMPSMBUS_MasterRxCpltCallback() in case of previous state was master receive (+) Enable/disable the Address listen mode in slave/device or host/slave FMPSMBUS mode - using @ref HAL_FMPSMBUS_EnableListen_IT() @ref HAL_FMPSMBUS_DisableListen_IT() - (++) When address slave/device FMPSMBUS match, @ref HAL_FMPSMBUS_AddrCallback() is executed and user can - add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end @ref HAL_FMPSMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_ListenCpltCallback() - (+) Transmit in slave/device FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer @ref HAL_FMPSMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device FMPSMBUS mode an amount of data in non-blocking mode using @ref HAL_FMPSMBUS_Slave_Receive_IT() - (++) At reception end of transfer @ref HAL_FMPSMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the FMPSMBUS alert mode using @ref HAL_FMPSMBUS_EnableAlert_IT() @ref HAL_FMPSMBUS_DisableAlert_IT() - (++) When FMPSMBUS Alert is generated @ref HAL_FMPSMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_ErrorCallback() - to check the Alert Error Code using function @ref HAL_FMPSMBUS_GetError() - (+) Get HAL state machine or error values using @ref HAL_FMPSMBUS_GetState() or @ref HAL_FMPSMBUS_GetError() - (+) In case of transfer Error, @ref HAL_FMPSMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_FMPSMBUS_ErrorCallback() - to check the Error Code using function @ref HAL_FMPSMBUS_GetError() + using HAL_FMPSMBUS_EnableListen_IT() HAL_FMPSMBUS_DisableListen_IT() + (++) When address slave/device FMPSMBUS match, HAL_FMPSMBUS_AddrCallback() is executed and users can + add their own code to check the Address Match Code and the transmission direction + request by master/host (Write/Read). + (++) At Listen mode end HAL_FMPSMBUS_ListenCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_ListenCpltCallback() + (+) Transmit in slave/device FMPSMBUS mode an amount of data in non-blocking mode + using HAL_FMPSMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_FMPSMBUS_SlaveTxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device FMPSMBUS mode an amount of data in non-blocking mode + using HAL_FMPSMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_FMPSMBUS_SlaveRxCpltCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the FMPSMBUS alert mode using + HAL_FMPSMBUS_EnableAlert_IT() or HAL_FMPSMBUS_DisableAlert_IT() + (++) When FMPSMBUS Alert is generated HAL_FMPSMBUS_ErrorCallback() is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_ErrorCallback() + to check the Alert Error Code using function HAL_FMPSMBUS_GetError() + (+) Get HAL state machine or error values using HAL_FMPSMBUS_GetState() or HAL_FMPSMBUS_GetError() + (+) In case of transfer Error, HAL_FMPSMBUS_ErrorCallback() function is executed and users can + add their own code by customization of function pointer HAL_FMPSMBUS_ErrorCallback() + to check the Error Code using function HAL_FMPSMBUS_GetError() *** FMPSMBUS HAL driver macros list *** ================================== [..] Below the list of most used macros in FMPSMBUS HAL driver. - (+) @ref __HAL_FMPSMBUS_ENABLE: Enable the FMPSMBUS peripheral - (+) @ref __HAL_FMPSMBUS_DISABLE: Disable the FMPSMBUS peripheral - (+) @ref __HAL_FMPSMBUS_GET_FLAG: Check whether the specified FMPSMBUS flag is set or not - (+) @ref __HAL_FMPSMBUS_CLEAR_FLAG: Clear the specified FMPSMBUS pending flag - (+) @ref __HAL_FMPSMBUS_ENABLE_IT: Enable the specified FMPSMBUS interrupt - (+) @ref __HAL_FMPSMBUS_DISABLE_IT: Disable the specified FMPSMBUS interrupt + (+) __HAL_FMPSMBUS_ENABLE: Enable the FMPSMBUS peripheral + (+) __HAL_FMPSMBUS_DISABLE: Disable the FMPSMBUS peripheral + (+) __HAL_FMPSMBUS_GET_FLAG: Check whether the specified FMPSMBUS flag is set or not + (+) __HAL_FMPSMBUS_CLEAR_FLAG: Clear the specified FMPSMBUS pending flag + (+) __HAL_FMPSMBUS_ENABLE_IT: Enable the specified FMPSMBUS interrupt + (+) __HAL_FMPSMBUS_DISABLE_IT: Disable the specified FMPSMBUS interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_FMPSMBUS_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_FMPSMBUS_RegisterCallback() or @ref HAL_FMPSMBUS_RegisterAddrCallback() + Use Functions HAL_FMPSMBUS_RegisterCallback() or HAL_FMPSMBUS_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_FMPSMBUS_RegisterCallback() allows to register following callbacks: + Function HAL_FMPSMBUS_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -107,11 +124,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_FMPSMBUS_RegisterAddrCallback. + For specific callback AddrCallback use dedicated register callbacks : HAL_FMPSMBUS_RegisterAddrCallback. [..] - Use function @ref HAL_FMPSMBUS_UnRegisterCallback to reset a callback to the default + Use function HAL_FMPSMBUS_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_FMPSMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_FMPSMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -123,24 +140,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_FMPSMBUS_UnRegisterAddrCallback. + For callback AddrCallback use dedicated register callbacks : HAL_FMPSMBUS_UnRegisterAddrCallback. [..] - By default, after the @ref HAL_FMPSMBUS_Init() and when the state is @ref HAL_FMPI2C_STATE_RESET + By default, after the HAL_FMPSMBUS_Init() and when the state is HAL_FMPI2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_FMPSMBUS_MasterTxCpltCallback(), @ref HAL_FMPSMBUS_MasterRxCpltCallback(). + examples HAL_FMPSMBUS_MasterTxCpltCallback(), HAL_FMPSMBUS_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_FMPSMBUS_Init()/ @ref HAL_FMPSMBUS_DeInit() only when + reset to the legacy weak functions in the HAL_FMPSMBUS_Init()/ HAL_FMPSMBUS_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_FMPSMBUS_Init()/ @ref HAL_FMPSMBUS_DeInit() + If MspInit or MspDeInit are not null, the HAL_FMPSMBUS_Init()/ HAL_FMPSMBUS_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_FMPI2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_FMPI2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_FMPI2C_STATE_READY or @ref HAL_FMPI2C_STATE_RESET state, + in HAL_FMPI2C_STATE_READY or HAL_FMPI2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_FMPSMBUS_RegisterCallback() before calling @ref HAL_FMPSMBUS_DeInit() - or @ref HAL_FMPSMBUS_Init() function. + using HAL_FMPSMBUS_RegisterCallback() before calling HAL_FMPSMBUS_DeInit() + or HAL_FMPSMBUS_Init() function. [..] When the compilation flag USE_HAL_FMPSMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -150,18 +167,6 @@ (@) You can refer to the FMPSMBUS HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -204,20 +209,28 @@ /** @addtogroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions * @{ */ -static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, - uint32_t Timeout); +/* Private functions to handle flags during polling transfer */ +static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout); -static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); -static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); +/* Private functions for FMPSMBUS transfer IRQ handler */ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t StatusFlags); +static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); -static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/* Private functions to centralize the enable/disable of Interrupts */ +static void FMPSMBUS_Enable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); +static void FMPSMBUS_Disable_IRQ(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t InterruptRequest); -static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/* Private function to flush TXDR register */ +static void FMPSMBUS_Flush_TXDR(FMPSMBUS_HandleTypeDef *hfmpsmbus); + +/* Private function to handle start, restart or stop a transfer */ +static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request); -static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); +/* Private function to Convert Specific options */ +static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus); /** * @} */ @@ -365,15 +378,20 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus) /*---------------------------- FMPSMBUSx OAR2 Configuration -----------------------*/ /* Configure FMPSMBUSx: Dual mode and Own Address2 */ - hfmpsmbus->Instance->OAR2 = (hfmpsmbus->Init.DualAddressMode | hfmpsmbus->Init.OwnAddress2 | (hfmpsmbus->Init.OwnAddress2Masks << 8U)); + hfmpsmbus->Instance->OAR2 = (hfmpsmbus->Init.DualAddressMode | hfmpsmbus->Init.OwnAddress2 | \ + (hfmpsmbus->Init.OwnAddress2Masks << 8U)); /*---------------------------- FMPSMBUSx CR1 Configuration ------------------------*/ /* Configure FMPSMBUSx: Generalcall and NoStretch mode */ - hfmpsmbus->Instance->CR1 = (hfmpsmbus->Init.GeneralCallMode | hfmpsmbus->Init.NoStretchMode | hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | hfmpsmbus->Init.AnalogFilter); + hfmpsmbus->Instance->CR1 = (hfmpsmbus->Init.GeneralCallMode | hfmpsmbus->Init.NoStretchMode | \ + hfmpsmbus->Init.PacketErrorCheckMode | hfmpsmbus->Init.PeripheralMode | \ + hfmpsmbus->Init.AnalogFilter); - /* Enable Slave Byte Control only in case of Packet Error Check is enabled and FMPSMBUS Peripheral is set in Slave mode */ - if ((hfmpsmbus->Init.PacketErrorCheckMode == FMPSMBUS_PEC_ENABLE) - && ((hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || (hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))) + /* Enable Slave Byte Control only in case of Packet Error Check is enabled + and FMPSMBUS Peripheral is set in Slave mode */ + if ((hfmpsmbus->Init.PacketErrorCheckMode == FMPSMBUS_PEC_ENABLE) && \ + ((hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ + (hfmpsmbus->Init.PeripheralMode == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP))) { hfmpsmbus->Instance->CR1 |= FMPI2C_CR1_SBC; } @@ -582,7 +600,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, pFMPSMBUS_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -696,7 +715,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbu * @arg @ref HAL_FMPSMBUS_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID) { HAL_StatusTypeDef status = HAL_OK; @@ -791,7 +811,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsm * @param pCallback pointer to the Address Match Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + pFMPSMBUS_AddrCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -915,10 +936,11 @@ HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hf * @param XferOptions Options of Transfer, value of @ref FMPSMBUS_XferOptions_definition * @retval HAL status */ -HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions) { uint32_t tmp; + uint32_t sizetoxfer = 0U; /* Check the parameters */ assert_param(IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions)); @@ -951,12 +973,30 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm hfmpsmbus->XferSize = Size; } + sizetoxfer = hfmpsmbus->XferSize; + if ((hfmpsmbus->XferSize > 0U) && ((XferOptions == FMPSMBUS_FIRST_FRAME) || + (XferOptions == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || + (XferOptions == FMPSMBUS_FIRST_FRAME_WITH_PEC) || + (XferOptions == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC))) + { + /* Preload TX register */ + /* Write data to TXDR */ + hfmpsmbus->Instance->TXDR = *hfmpsmbus->pBuffPtr; + + /* Increment Buffer pointer */ + hfmpsmbus->pBuffPtr++; + + hfmpsmbus->XferCount--; + hfmpsmbus->XferSize--; + } + /* Send Slave Address */ /* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */ - if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) + if ((sizetoxfer < hfmpsmbus->XferCount) && (sizetoxfer == MAX_NBYTE_SIZE)) { - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_WRITE); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer, + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_GENERATE_START_WRITE); } else { @@ -966,9 +1006,11 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm /* Store current volatile XferOptions, misra rule */ tmp = hfmpsmbus->XferOptions; - if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) && (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_TX) && \ + (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -977,7 +1019,9 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsm FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus); /* Handle Transfer */ - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_GENERATE_START_WRITE); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)sizetoxfer, + hfmpsmbus->XferOptions, + FMPSMBUS_GENERATE_START_WRITE); } /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ @@ -1058,7 +1102,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_GENERATE_START_READ); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_GENERATE_START_READ); } else { @@ -1068,9 +1113,11 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb /* Store current volatile XferOptions, Misra rule */ tmp = hfmpsmbus->XferOptions; - if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) && (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) + if ((hfmpsmbus->PreviousState == HAL_FMPSMBUS_STATE_MASTER_BUSY_RX) && \ + (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(tmp) == 0)) { - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); } /* Else transfer direction change, so generate Restart with new transfer direction */ else @@ -1079,7 +1126,9 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmb FMPSMBUS_ConvertOtherXferOptions(hfmpsmbus); /* Handle Transfer */ - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_GENERATE_START_READ); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, + hfmpsmbus->XferOptions, + FMPSMBUS_GENERATE_START_READ); } } @@ -1223,12 +1272,14 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmb if ((hfmpsmbus->XferSize < hfmpsmbus->XferCount) && (hfmpsmbus->XferSize == MAX_NBYTE_SIZE)) { FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, - FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_NO_STARTSTOP); } else { /* Set NBYTE to transmit */ - FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ @@ -1314,7 +1365,8 @@ HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbu /* This RELOAD bit will be reset for last BYTE to be receive in FMPSMBUS_Slave_ISR */ if (((FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) && (hfmpsmbus->XferSize == 2U)) || (hfmpsmbus->XferSize == 1U)) { - FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); } else { @@ -1577,7 +1629,8 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) uint32_t tmpcr1value = READ_REG(hfmpsmbus->Instance->CR1); /* FMPSMBUS in mode Transmitter ---------------------------------------------------*/ - if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && + if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TXIS) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || @@ -1601,7 +1654,8 @@ void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS in mode Receiver ----------------------------------------------------*/ - if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && + if ((FMPSMBUS_CHECK_IT_SOURCE(tmpcr1value, (FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI)) != RESET) && ((FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_RXNE) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TCR) != RESET) || (FMPSMBUS_CHECK_FLAG(tmpisrvalue, FMPSMBUS_FLAG_TC) != RESET) || @@ -1721,7 +1775,8 @@ __weak void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @param AddrMatchCode Address Match Code * @retval None */ -__weak void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) +__weak void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode) { /* Prevent unused argument(s) compilation warning */ UNUSED(hfmpsmbus); @@ -1843,6 +1898,9 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, /* No need to generate STOP, it is automatically done */ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF; + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hfmpsmbus); @@ -1968,13 +2026,15 @@ static HAL_StatusTypeDef FMPSMBUS_Master_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE) { FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, MAX_NBYTE_SIZE, - (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP); + (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), + FMPSMBUS_NO_STARTSTOP); hfmpsmbus->XferSize = MAX_NBYTE_SIZE; } else { hfmpsmbus->XferSize = hfmpsmbus->XferCount; - FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, DevAddress, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) @@ -2131,6 +2191,9 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u /* Clear NACK Flag */ __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_AF); + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hfmpsmbus); } @@ -2152,6 +2215,9 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u /* Set ErrorCode corresponding to a Non-Acknowledge */ hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ACKF; + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + /* Process Unlocked */ __HAL_UNLOCK(hfmpsmbus); @@ -2226,7 +2292,9 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u else { /* Set Reload for next Bytes */ - FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, 0, 1, + FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE), + FMPSMBUS_NO_STARTSTOP); /* Ack last Byte Read */ hfmpsmbus->Instance->CR2 &= ~FMPI2C_CR2_NACK; @@ -2238,14 +2306,16 @@ static HAL_StatusTypeDef FMPSMBUS_Slave_ISR(FMPSMBUS_HandleTypeDef *hfmpsmbus, u { if (hfmpsmbus->XferCount > MAX_NBYTE_SIZE) { - FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE, (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), + FMPSMBUS_TransferConfig(hfmpsmbus, 0, MAX_NBYTE_SIZE, + (FMPSMBUS_RELOAD_MODE | (hfmpsmbus->XferOptions & FMPSMBUS_SENDPEC_MODE)), FMPSMBUS_NO_STARTSTOP); hfmpsmbus->XferSize = MAX_NBYTE_SIZE; } else { hfmpsmbus->XferSize = hfmpsmbus->XferCount; - FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, FMPSMBUS_NO_STARTSTOP); + FMPSMBUS_TransferConfig(hfmpsmbus, 0, (uint8_t)hfmpsmbus->XferSize, hfmpsmbus->XferOptions, + FMPSMBUS_NO_STARTSTOP); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ if (FMPSMBUS_GET_PEC_MODE(hfmpsmbus) != 0UL) @@ -2490,7 +2560,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) uint32_t tmperror; /* FMPSMBUS Bus error interrupt occurred ------------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_BERR) == FMPSMBUS_FLAG_BERR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_BERR) == FMPSMBUS_FLAG_BERR) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_BERR; @@ -2499,7 +2570,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_OVR) == FMPSMBUS_FLAG_OVR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_OVR) == FMPSMBUS_FLAG_OVR) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_OVR; @@ -2508,7 +2580,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS Arbitration Loss error interrupt occurred ------------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_ARLO) == FMPSMBUS_FLAG_ARLO) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_ARLO) == FMPSMBUS_FLAG_ARLO) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ARLO; @@ -2517,7 +2590,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS Timeout error interrupt occurred ---------------------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_TIMEOUT) == FMPSMBUS_FLAG_TIMEOUT) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_TIMEOUT) == FMPSMBUS_FLAG_TIMEOUT) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_BUSTIMEOUT; @@ -2526,7 +2600,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS Alert error interrupt occurred -----------------------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_ALERT) == FMPSMBUS_FLAG_ALERT) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_ALERT) == FMPSMBUS_FLAG_ALERT) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_ALERT; @@ -2535,7 +2610,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) } /* FMPSMBUS Packet Error Check error interrupt occurred ----------------------------------*/ - if (((itflags & FMPSMBUS_FLAG_PECERR) == FMPSMBUS_FLAG_PECERR) && ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) + if (((itflags & FMPSMBUS_FLAG_PECERR) == FMPSMBUS_FLAG_PECERR) && \ + ((itsources & FMPSMBUS_IT_ERRI) == FMPSMBUS_IT_ERRI)) { hfmpsmbus->ErrorCode |= HAL_FMPSMBUS_ERROR_PECERR; @@ -2543,7 +2619,10 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_PECERR); } - /* Store current volatile hfmpsmbus->State, misra rule */ + /* Flush TX register */ + FMPSMBUS_Flush_TXDR(hfmpsmbus); + + /* Store current volatile hfmpsmbus->ErrorCode, misra rule */ tmperror = hfmpsmbus->ErrorCode; /* Call the Error Callback in case of Error detected */ @@ -2583,8 +2662,8 @@ static void FMPSMBUS_ITErrorHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus) * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, FlagStatus Status, - uint32_t Timeout) +static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t Flag, + FlagStatus Status, uint32_t Timeout) { uint32_t tickstart = HAL_GetTick(); @@ -2613,6 +2692,27 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef return HAL_OK; } +/** + * @brief FMPSMBUS Tx data register flush process. + * @param hfmpsmbus FMPSMBUS handle. + * @retval None + */ +static void FMPSMBUS_Flush_TXDR(FMPSMBUS_HandleTypeDef *hfmpsmbus) +{ + /* If a pending TXIS flag is set */ + /* Write a dummy data in TXDR to clear it */ + if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXIS) != RESET) + { + hfmpsmbus->Instance->TXDR = 0x00U; + } + + /* Flush TX register if not empty */ + if (__HAL_FMPSMBUS_GET_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXE) == RESET) + { + __HAL_FMPSMBUS_CLEAR_FLAG(hfmpsmbus, FMPSMBUS_FLAG_TXE); + } +} + /** * @brief Handle FMPSMBUSx communication when starting transfer or during transfer (TC or TCR flag are set). * @param hfmpsmbus FMPSMBUS handle. @@ -2633,8 +2733,8 @@ static HAL_StatusTypeDef FMPSMBUS_WaitOnFlagUntilTimeout(FMPSMBUS_HandleTypeDef * @arg @ref FMPSMBUS_GENERATE_START_WRITE Generate Restart for write request. * @retval None */ -static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request) +static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t Size, + uint32_t Mode, uint32_t Request) { /* Check the parameters */ assert_param(IS_FMPSMBUS_ALL_INSTANCE(hfmpsmbus->Instance)); @@ -2645,9 +2745,10 @@ static void FMPSMBUS_TransferConfig(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t MODIFY_REG(hfmpsmbus->Instance->CR2, ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | \ (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31UL - FMPI2C_CR2_RD_WRN_Pos))) | \ - FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_PECBYTE)), \ + FMPI2C_CR2_START | FMPI2C_CR2_STOP | FMPI2C_CR2_PECBYTE)), \ (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | \ - (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request)); + (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request)); } /** @@ -2705,5 +2806,3 @@ static void FMPSMBUS_ConvertOtherXferOptions(FMPSMBUS_HandleTypeDef *hfmpsmbus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus.h index c0dce289745..50867906b29 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -28,7 +27,6 @@ extern "C" { #if defined(FMPI2C_CR1_PE) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" -#include "stm32f4xx_hal_fmpsmbus_ex.h" /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -50,42 +48,43 @@ extern "C" { typedef struct { uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value. - This parameter calculated by referring to FMPSMBUS initialization - section in Reference manual */ + This parameter calculated by referring to FMPSMBUS initialization section + in Reference manual */ uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. - This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ + This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ + This parameter can be a 7-bit or 10-bit address. */ uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. - This parameter can be a value of @ref FMPSMBUS_addressing_mode */ + This parameter can be a value of @ref FMPSMBUS_addressing_mode */ uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ + This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ + This parameter can be a 7-bit address. */ - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected - This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ + uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address + if dual addressing mode is selected + This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ + This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ + This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. - This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ + This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. - This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ + This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value. - (Enable bits and different timeout values) - This parameter calculated by referring to FMPSMBUS initialization - section in Reference manual */ + (Enable bits and different timeout values) + This parameter calculated by referring to FMPSMBUS initialization section + in Reference manual */ } FMPSMBUS_InitTypeDef; /** * @} @@ -104,7 +103,7 @@ typedef struct #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ #define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ #define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ -#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ +#define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} */ @@ -123,7 +122,7 @@ typedef struct #define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ #define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) -#define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ +#define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ #define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ /** @@ -161,17 +160,26 @@ typedef struct __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Listen Complete callback */ - void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Error callback */ - - void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< FMPSMBUS Slave Address Match callback */ - - void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp Init callback */ - void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< FMPSMBUS Msp DeInit callback */ + void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Master Tx Transfer completed callback */ + void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Master Rx Transfer completed callback */ + void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Slave Tx Transfer completed callback */ + void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Slave Rx Transfer completed callback */ + void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Listen Complete callback */ + void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Error callback */ + + void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); + /*!< FMPSMBUS Slave Address Match callback */ + + void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Msp Init callback */ + void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); + /*!< FMPSMBUS Msp DeInit callback */ #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ } FMPSMBUS_HandleTypeDef; @@ -197,8 +205,11 @@ typedef enum /** * @brief HAL FMPSMBUS Callback pointer definition */ -typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); /*!< pointer to an FMPSMBUS callback function */ -typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an FMPSMBUS Address Match callback function */ +typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); +/*!< pointer to an FMPSMBUS callback function */ +typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, + uint16_t AddrMatchCode); +/*!< pointer to an FMPSMBUS Address Match callback function */ #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ /** @@ -360,9 +371,10 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus #define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE -#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI | \ - FMPSMBUS_IT_TXI) -#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | FMPSMBUS_IT_RXI) +#define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \ + FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) +#define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \ + FMPSMBUS_IT_RXI) #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) /** @@ -410,14 +422,14 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus * @retval None */ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) -#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ +#define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ } while(0) #else #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) -#endif +#endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ /** @brief Enable the specified FMPSMBUS interrupts. * @param __HANDLE__ specifies the FMPSMBUS Handle. @@ -493,12 +505,14 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus */ #define FMPSMBUS_FLAG_MASK (0x0001FFFFU) #define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ - (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) + (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ + ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) /** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__ specifies the FMPSMBUS Handle. * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: + * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) * @arg @ref FMPSMBUS_FLAG_AF NACK received flag * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag @@ -511,7 +525,9 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus * * @retval None */ -#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) +#define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPSMBUS_FLAG_TXE) ? \ + ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ + ((__HANDLE__)->Instance->ICR = (__FLAG__))) /** @brief Enable the specified FMPSMBUS peripheral. * @param __HANDLE__ specifies the FMPSMBUS Handle. @@ -576,43 +592,52 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) -#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ - ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ - ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ - ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ - ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ - ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | FMPSMBUS_RELOAD_MODE ))) +#define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ + ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ + ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ + ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ + ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ + ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ + FMPSMBUS_RELOAD_MODE ))) #define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ - ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ - ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ + ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ + ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) -#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ - ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ - ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ - ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ - ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ - ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) +#define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ + ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ + ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ + ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ + ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) -#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ - ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ +#define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ + ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) -#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | FMPI2C_CR1_PECEN))) -#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN))) - -#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) +#define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ + (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ + FMPI2C_CR1_PECEN))) +#define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ + (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ + FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ + FMPI2C_CR2_RD_WRN))) + +#define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ + (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ + (~FMPI2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & \ + (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ + (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) #define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) #define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) @@ -631,6 +656,9 @@ typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus * @} */ +/* Include FMPSMBUS HAL Extended module */ +#include "stm32f4xx_hal_fmpsmbus_ex.h" + /* Exported functions --------------------------------------------------------*/ /** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions * @{ @@ -650,11 +678,14 @@ HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmps /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, pFMPSMBUS_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, pFMPSMBUS_AddrCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, + pFMPSMBUS_AddrCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ /** @@ -680,10 +711,10 @@ HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, * @{ */ /******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); +HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, + uint8_t *pData, uint16_t Size, uint32_t XferOptions); HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); @@ -760,5 +791,3 @@ uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus); #endif /* STM32F4xx_HAL_FMPSMBUS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus_ex.c index 119c76f9b21..14ca0b4244b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus_ex.c @@ -7,6 +7,17 @@ * functionalities of FMPSMBUS Extended peripheral: * + Extended features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### FMPSMBUS peripheral Extended features ##### @@ -23,18 +34,6 @@ (++) HAL_FMPSMBUSEx_EnableFastModePlus() (++) HAL_FMPSMBUSEx_DisableFastModePlus() @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -63,15 +62,14 @@ * @{ */ -/** @defgroup FMPSMBUSEx_Exported_Functions_Group1 Extended features functions - * @brief Extended features functions - * +/** @defgroup FMPSMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions + * @brief Fast Mode Plus Functions + * @verbatim =============================================================================== - ##### Extended features functions ##### + ##### Fast Mode Plus Functions ##### =============================================================================== [..] This section provides functions allowing to: - (+) Configure Fast Mode Plus @endverbatim @@ -83,10 +81,10 @@ * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref FMPSMBUSEx_FastModePlus values * @note For FMPI2C1, fast mode plus driving capability can be enabled on all selected - * FMPI2C1 pins using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter or independently + * FMPI2C1 pins using FMPSMBUS_FASTMODEPLUS_FMPI2C1 parameter or independently * on each one of the following pins PB6, PB7, PB8 and PB9. * @note For remaining FMPI2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter. + * can be enabled only by using FMPSMBUS_FASTMODEPLUS_FMPI2C1 parameter. * @retval None */ void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) @@ -106,10 +104,10 @@ void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus) * @param ConfigFastModePlus Selects the pin. * This parameter can be one of the @ref FMPSMBUSEx_FastModePlus values * @note For FMPI2C1, fast mode plus driving capability can be disabled on all selected - * FMPI2C1 pins using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter or independently + * FMPI2C1 pins using FMPSMBUS_FASTMODEPLUS_FMPI2C1 parameter or independently * on each one of the following pins PB6, PB7, PB8 and PB9. * @note For remaining FMPI2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be disabled only by using FMPI2C_FASTMODEPLUS_FMPI2C1 parameter. + * can be disabled only by using FMPSMBUS_FASTMODEPLUS_FMPI2C1 parameter. * @retval None */ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) @@ -124,6 +122,9 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) CLEAR_BIT(SYSCFG->CFGR, (uint32_t)ConfigFastModePlus); } +/** + * @} + */ /** * @} @@ -142,5 +143,3 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus_ex.h index 541ce73228b..001dc547337 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_fmpsmbus_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -38,7 +37,6 @@ extern "C" { */ /* Exported types ------------------------------------------------------------*/ - /* Exported constants --------------------------------------------------------*/ /** @defgroup FMPSMBUSEx_Exported_Constants FMPSMBUS Extended Exported Constants * @{ @@ -71,7 +69,15 @@ extern "C" { * @{ */ -/** @addtogroup FMPSMBUSEx_Exported_Functions_Group3 FMPSMBUS Extended FastModePlus Functions +/** @addtogroup FMPSMBUSEx_Exported_Functions_Group2 WakeUp Mode Functions + * @{ + */ +/* Peripheral Control functions ************************************************/ +/** + * @} + */ + +/** @addtogroup FMPSMBUSEx_Exported_Functions_Group3 Fast Mode Plus Functions * @{ */ void HAL_FMPSMBUSEx_EnableFastModePlus(uint32_t ConfigFastModePlus); @@ -97,8 +103,10 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** @defgroup FMPSMBUSEx_Private_Macro FMPSMBUS Extended Private Macros * @{ */ -#define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == FMPSMBUS_FASTMODEPLUS_SCL) || \ - (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == FMPSMBUS_FASTMODEPLUS_SDA)) +#define IS_FMPSMBUS_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SCL)) == \ + FMPSMBUS_FASTMODEPLUS_SCL) || \ + (((__CONFIG__) & (FMPSMBUS_FASTMODEPLUS_SDA)) == \ + FMPSMBUS_FASTMODEPLUS_SDA)) /** * @} */ @@ -107,7 +115,7 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); /** @defgroup FMPSMBUSEx_Private_Functions FMPSMBUS Extended Private Functions * @{ */ -/* Private functions are defined in stm32f4xx_hal_fmpfmpsmbus_ex.c file */ +/* Private functions are defined in stm32f4xx_hal_fmpsmbus_ex.c file */ /** * @} */ @@ -126,5 +134,3 @@ void HAL_FMPSMBUSEx_DisableFastModePlus(uint32_t ConfigFastModePlus); #endif #endif /* STM32F4xx_HAL_FMPSMBUS_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.c index f96d2bb2ac5..b3ce9bbcbe5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### GPIO Peripheral features ##### @@ -91,17 +102,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -172,7 +172,6 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ for(position = 0U; position < GPIO_NUMBER; position++) @@ -200,12 +199,15 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /* Configure the IO Output Type */ temp = GPIOx->OTYPER; temp &= ~(GPIO_OTYPER_OT_0 << position) ; - temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); GPIOx->OTYPER = temp; } if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) { + /* Check the parameters */ + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U)); @@ -233,7 +235,7 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ - if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) + if((GPIO_Init->Mode & EXTI_MODE) != 0x00U) { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); @@ -243,39 +245,39 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U))); SYSCFG->EXTICR[position >> 2U] = temp; - /* Clear EXTI line configuration */ - temp = EXTI->IMR; + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) + if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U) { temp |= iocurrent; } - EXTI->IMR = temp; + EXTI->RTSR = temp; - temp = EXTI->EMR; + temp = EXTI->FTSR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) + if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U) { temp |= iocurrent; } - EXTI->EMR = temp; + EXTI->FTSR = temp; - /* Clear Rising Falling edge configuration */ - temp = EXTI->RTSR; + temp = EXTI->EMR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) + if((GPIO_Init->Mode & EXTI_EVT) != 0x00U) { temp |= iocurrent; } - EXTI->RTSR = temp; + EXTI->EMR = temp; - temp = EXTI->FTSR; + /* Clear EXTI line configuration */ + temp = EXTI->IMR; temp &= ~((uint32_t)iocurrent); - if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) + if((GPIO_Init->Mode & EXTI_IT) != 0x00U) { temp |= iocurrent; } - EXTI->FTSR = temp; + EXTI->IMR = temp; } } } @@ -319,8 +321,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) EXTI->EMR &= ~((uint32_t)iocurrent); /* Clear Rising Falling edge configuration */ - EXTI->RTSR &= ~((uint32_t)iocurrent); EXTI->FTSR &= ~((uint32_t)iocurrent); + EXTI->RTSR &= ~((uint32_t)iocurrent); /* Configure the External Interrupt or event for the current IO */ tmp = 0x0FU << (4U * (position & 0x03U)); @@ -435,7 +437,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); - /* get current Ouput Data Register value */ + /* get current Output Data Register value */ odr = GPIOx->ODR; /* Set selected pins that were at low level, and reset ones that were high */ @@ -529,4 +531,3 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.h index 38b567d1053..5f3d749ede9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -107,30 +106,29 @@ typedef enum */ /** @defgroup GPIO_mode_define GPIO mode define - * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, Alternate or Analog) + * @brief GPIO Configuration Mode + * Elements values convention: 0x00WX00YZ + * - W : EXTI trigger detection on 3 bits + * - X : EXTI mode (IT or Event) on 2 bits + * - Y : Output type (Push Pull or Open Drain) on 1 bit + * - Z : GPIO mode (Input, Output, Alternate or Analog) on 2 bits * @{ - */ -#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ -#define GPIO_MODE_OUTPUT_PP (MODE_PP | MODE_OUTPUT) /*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_OD (MODE_OD | MODE_OUTPUT) /*!< Output Open Drain Mode */ -#define GPIO_MODE_AF_PP (MODE_PP | MODE_AF) /*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_OD (MODE_OD | MODE_AF) /*!< Alternate Function Open Drain Mode */ - -#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ - -#define GPIO_MODE_IT_RISING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_FALLING (EXTI_MODE | GPIO_MODE_IT | FALLING_EDGE) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (EXTI_MODE | GPIO_MODE_IT | RISING_EDGE | FALLING_EDGE) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ - -#define GPIO_MODE_EVT_RISING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE) /*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (EXTI_MODE | GPIO_MODE_EVT | FALLING_EDGE) /*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (EXTI_MODE | GPIO_MODE_EVT | RISING_EDGE | FALLING_EDGE) /*!< External Event Mode with Rising/Falling edge trigger detection */ + */ +#define GPIO_MODE_INPUT MODE_INPUT /*!< Input Floating Mode */ +#define GPIO_MODE_OUTPUT_PP (MODE_OUTPUT | OUTPUT_PP) /*!< Output Push Pull Mode */ +#define GPIO_MODE_OUTPUT_OD (MODE_OUTPUT | OUTPUT_OD) /*!< Output Open Drain Mode */ +#define GPIO_MODE_AF_PP (MODE_AF | OUTPUT_PP) /*!< Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD (MODE_AF | OUTPUT_OD) /*!< Alternate Function Open Drain Mode */ + +#define GPIO_MODE_ANALOG MODE_ANALOG /*!< Analog Mode */ + +#define GPIO_MODE_IT_RISING (MODE_INPUT | EXTI_IT | TRIGGER_RISING) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define GPIO_MODE_IT_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_FALLING) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define GPIO_MODE_IT_RISING_FALLING (MODE_INPUT | EXTI_IT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ + +#define GPIO_MODE_EVT_RISING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING) /*!< External Event Mode with Rising edge trigger detection */ +#define GPIO_MODE_EVT_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_FALLING) /*!< External Event Mode with Falling edge trigger detection */ +#define GPIO_MODE_EVT_RISING_FALLING (MODE_INPUT | EXTI_EVT | TRIGGER_RISING | TRIGGER_FALLING) /*!< External Event Mode with Rising/Falling edge trigger detection */ /** * @} @@ -253,21 +251,24 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); /** @defgroup GPIO_Private_Constants GPIO Private Constants * @{ */ -#define GPIO_MODE 0x00000003U -#define EXTI_MODE 0x10000000U -#define GPIO_MODE_IT 0x00010000U -#define GPIO_MODE_EVT 0x00020000U -#define RISING_EDGE 0x00100000U -#define FALLING_EDGE 0x00200000U -#define GPIO_OUTPUT_TYPE 0x00000010U - -#define MODE_INPUT 0x00000000U /*!< Input Mode */ -#define MODE_OUTPUT 0x00000001U /*!< Output Mode */ -#define MODE_AF 0x00000002U /*!< Alternate Function Mode */ -#define MODE_ANALOG 0x00000003U /*!< Analog Mode */ - -#define MODE_PP 0x00000000U /*!< Push Pull Mode */ -#define MODE_OD 0x00000010U /*!< Open Drain Mode */ +#define GPIO_MODE_Pos 0U +#define GPIO_MODE (0x3UL << GPIO_MODE_Pos) +#define MODE_INPUT (0x0UL << GPIO_MODE_Pos) +#define MODE_OUTPUT (0x1UL << GPIO_MODE_Pos) +#define MODE_AF (0x2UL << GPIO_MODE_Pos) +#define MODE_ANALOG (0x3UL << GPIO_MODE_Pos) +#define OUTPUT_TYPE_Pos 4U +#define OUTPUT_TYPE (0x1UL << OUTPUT_TYPE_Pos) +#define OUTPUT_PP (0x0UL << OUTPUT_TYPE_Pos) +#define OUTPUT_OD (0x1UL << OUTPUT_TYPE_Pos) +#define EXTI_MODE_Pos 16U +#define EXTI_MODE (0x3UL << EXTI_MODE_Pos) +#define EXTI_IT (0x1UL << EXTI_MODE_Pos) +#define EXTI_EVT (0x2UL << EXTI_MODE_Pos) +#define TRIGGER_MODE_Pos 20U +#define TRIGGER_MODE (0x7UL << TRIGGER_MODE_Pos) +#define TRIGGER_RISING (0x1UL << TRIGGER_MODE_Pos) +#define TRIGGER_FALLING (0x2UL << TRIGGER_MODE_Pos) /** * @} @@ -322,4 +323,3 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); #endif /* __STM32F4xx_HAL_GPIO_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio_ex.h index 7db36ccaecf..5e0b7cc6d7c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_gpio_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1589,4 +1588,3 @@ #endif /* __STM32F4xx_HAL_GPIO_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.c index c901e19d61f..f3aafe0a57d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.c @@ -12,6 +12,17 @@ * + Peripheral State methods * + HASH or HMAC processing suspension/resumption * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -147,9 +158,9 @@ [..] (#) The compilation define USE_HAL_HASH_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use function @ref HAL_HASH_RegisterCallback() to register a user callback. + Use function HAL_HASH_RegisterCallback() to register a user callback. - (#) Function @ref HAL_HASH_RegisterCallback() allows to register following callbacks: + (#) Function HAL_HASH_RegisterCallback() allows to register following callbacks: (+) InCpltCallback : callback for input completion. (+) DgstCpltCallback : callback for digest computation completion. (+) ErrorCallback : callback for error. @@ -158,9 +169,9 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - (#) Use function @ref HAL_HASH_UnRegisterCallback() to reset a callback to the default + (#) Use function HAL_HASH_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_HASH_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) InCpltCallback : callback for input completion. @@ -169,13 +180,13 @@ (+) MspInitCallback : HASH MspInit. (+) MspDeInitCallback : HASH MspDeInit. - (#) By default, after the @ref HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET + (#) By default, after the HAL_HASH_Init and if the state is HAL_HASH_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions: - examples @ref HAL_HASH_InCpltCallback(), @ref HAL_HASH_DgstCpltCallback() + examples HAL_HASH_InCpltCallback(), HAL_HASH_DgstCpltCallback() Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_HASH_Init - and @ref HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) - If not, MspInit or MspDeInit are not null, the @ref HAL_HASH_Init and @ref HAL_HASH_DeInit + reset to the legacy weak (surcharged) functions in the HAL_HASH_Init + and HAL_HASH_DeInit only when these callbacks are null (not registered beforehand) + If not, MspInit or MspDeInit are not null, the HAL_HASH_Init and HAL_HASH_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand). Callbacks can be registered/unregistered in READY state only. @@ -183,8 +194,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_HASH_RegisterCallback before calling @ref HAL_HASH_DeInit - or @ref HAL_HASH_Init function. + using HAL_HASH_RegisterCallback before calling HAL_HASH_DeInit + or HAL_HASH_Init function. When The compilation define USE_HAL_HASH_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -192,17 +203,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1769,8 +1769,6 @@ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma) (((buffersize % 4U) != 0U) ? ((buffersize + (4U - (buffersize % 4U))) / 4U) : \ (buffersize / 4U))); - - /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); @@ -2909,8 +2907,8 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u Update HashInCount and pHashInBuffPtr accordingly. */ hhash->HashInCount = SizeVar; hhash->pHashInBuffPtr = (uint8_t *)inputaddr; - __HAL_HASH_SET_NBVALIDBITS( - SizeVar); /* Update the configuration of the number of valid bits in last word of the message */ + /* Update the configuration of the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ if (initialization_skipped == 1U) { @@ -2978,11 +2976,11 @@ HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, HAL_StatusTypeDef status ; HAL_HASH_StateTypeDef State_tmp = hhash->State; - #if defined (HASH_CR_MDMAT) +#if defined (HASH_CR_MDMAT) /* Make sure the input buffer size (in bytes) is a multiple of 4 when MDMAT bit is set (case of multi-buffer HASH processing) */ assert_param(IS_HASH_DMA_MULTIBUFFER_SIZE(Size)); - #endif /* MDMA defined*/ +#endif /* MDMA defined*/ /* If State is ready or suspended, start or resume polling-based HASH processing */ if ((State_tmp == HAL_HASH_STATE_READY) || (State_tmp == HAL_HASH_STATE_SUSPENDED)) { @@ -3478,6 +3476,7 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, status = HAL_DMA_Start_IT(hhash->hdmain, inputaddr, (uint32_t)&HASH->DIN, \ (((inputSize % 4U) != 0U) ? ((inputSize + (4U - (inputSize % 4U))) / 4U) \ : (inputSize / 4U))); + /* Enable DMA requests */ SET_BIT(HASH->CR, HASH_CR_DMAE); @@ -3513,6 +3512,3 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @} */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.h index f7c0b9d73eb..9a93fbbc060 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -244,13 +243,6 @@ typedef void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef *hhash); /*!< pointer #define HASH_IT_DINI HASH_IMR_DINIE /*!< A new block can be entered into the input buffer (DIN) */ #define HASH_IT_DCI HASH_IMR_DCIE /*!< Digest calculation complete */ -/** - * @} - */ -/** @defgroup HASH_alias HASH API alias - * @{ - */ -#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ /** * @} */ @@ -640,4 +632,3 @@ HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, #endif /* STM32F4xx_HAL_HASH_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash_ex.c index e733f5ad770..63cb38eaa2e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash_ex.c @@ -14,6 +14,17 @@ * and SHA-256. * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### HASH peripheral extended features ##### @@ -69,17 +80,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1038,6 +1038,3 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @} */ - - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash_ex.h index 0a9844c0ae0..91e65dca2ae 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hash_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -174,4 +173,3 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 #endif /* STM32F4xx_HAL_HASH_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.c index 18f4e3bd4c5..c7c5b70b908 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -40,17 +51,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -61,7 +61,6 @@ */ #ifdef HAL_HCD_MODULE_ENABLED - #if defined (USB_OTG_FS) || defined (USB_OTG_HS) /** @defgroup HCD HCD @@ -495,7 +494,8 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i, interrupt; + uint32_t i; + uint32_t interrupt; /* Ensure that we are in device mode */ if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST) @@ -537,14 +537,19 @@ void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd) if ((USBx_HPRT0 & USB_OTG_HPRT_PCSTS) == 0U) { + /* Flush USB Fifo */ + (void)USB_FlushTxFifo(USBx, 0x10U); + (void)USB_FlushRxFifo(USBx); + + /* Restore FS Clock */ + (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); + /* Handle Host Port Disconnect Interrupt */ #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->DisconnectCallback(hhcd); #else HAL_HCD_Disconnect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - - (void)USB_InitFSLSPClkSel(hhcd->Instance, HCFG_48_MHZ); } } @@ -961,7 +966,8 @@ HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef * /** * @brief Unregister the USB HCD Host Channel Notify URB Change Callback - * USB HCD Host Channel Notify URB Change Callback is redirected to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback + * USB HCD Host Channel Notify URB Change Callback is redirected + * to the weak HAL_HCD_HC_NotifyURBChange_Callback() predefined callback * @param hhcd HCD handle * @retval HAL status */ @@ -1019,8 +1025,11 @@ HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd) { __HAL_LOCK(hhcd); - __HAL_HCD_ENABLE(hhcd); + /* Enable port power */ (void)USB_DriveVbus(hhcd->Instance, 1U); + + /* Enable global interrupt */ + __HAL_HCD_ENABLE(hhcd); __HAL_UNLOCK(hhcd); return HAL_OK; @@ -1183,13 +1192,13 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_BBERR) == USB_OTG_HCINT_BBERR) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_BBERR); hhcd->hc[ch_num].state = HC_BBLERR; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) @@ -1198,26 +1207,21 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].state = HC_STALL; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); + hhcd->hc[ch_num].state = HC_STALL; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - hhcd->hc[ch_num].state = HC_DATATGLERR; - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); + hhcd->hc[ch_num].state = HC_DATATGLERR; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_TXERR) == USB_OTG_HCINT_TXERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); hhcd->hc[ch_num].state = HC_XACTERR; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_TXERR); } else { @@ -1226,7 +1230,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); } @@ -1245,26 +1248,15 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || (hhcd->hc[ch_num].ep_type == EP_TYPE_BULK)) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } - else if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) + else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) || + (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC)) { USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; hhcd->hc[ch_num].urb_state = URB_DONE; -#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) - hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); -#else - HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); -#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ - } - else if (hhcd->hc[ch_num].ep_type == EP_TYPE_ISOC) - { - hhcd->hc[ch_num].urb_state = URB_DONE; - hhcd->hc[ch_num].toggle_in ^= 1U; - #if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); #else @@ -1290,8 +1282,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(ch_num); - if (hhcd->hc[ch_num].state == HC_XFRC) { hhcd->hc[ch_num].urb_state = URB_DONE; @@ -1340,14 +1330,18 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) /* ... */ } __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { if (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR) { hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) || @@ -1358,7 +1352,6 @@ static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->Init.dma_enable == 0U) { hhcd->hc[ch_num].state = HC_NAK; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } @@ -1392,7 +1385,8 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_AHBERR) == USB_OTG_HCINT_AHBERR) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_AHBERR); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_XACTERR; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_ACK) == USB_OTG_HCINT_ACK) { @@ -1401,16 +1395,14 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->hc[ch_num].do_ping == 1U) { hhcd->hc[ch_num].do_ping = 0U; - hhcd->hc[ch_num].urb_state = URB_NOTREADY; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].urb_state = URB_NOTREADY; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_FRMOR) == USB_OTG_HCINT_FRMOR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_FRMOR); + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_XFRC) == USB_OTG_HCINT_XFRC) { @@ -1422,26 +1414,23 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) hhcd->hc[ch_num].do_ping = 1U; __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); } - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_XFRC); hhcd->hc[ch_num].state = HC_XFRC; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NYET) == USB_OTG_HCINT_NYET) { hhcd->hc[ch_num].state = HC_NYET; hhcd->hc[ch_num].do_ping = 1U; hhcd->hc[ch_num].ErrCnt = 0U; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NYET); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_STALL) == USB_OTG_HCINT_STALL) { __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_STALL); - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); - (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); hhcd->hc[ch_num].state = HC_STALL; + (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_NAK) == USB_OTG_HCINT_NAK) { @@ -1456,7 +1445,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } } - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); } @@ -1465,7 +1453,6 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) if (hhcd->Init.dma_enable == 0U) { hhcd->hc[ch_num].state = HC_XACTERR; - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); } else @@ -1475,7 +1462,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) { hhcd->hc[ch_num].ErrCnt = 0U; hhcd->hc[ch_num].urb_state = URB_ERROR; + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { @@ -1486,37 +1478,31 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_DTERR) == USB_OTG_HCINT_DTERR) { - __HAL_HCD_UNMASK_HALT_HC_INT(ch_num); + hhcd->hc[ch_num].state = HC_DATATGLERR; (void)USB_HC_Halt(hhcd->Instance, (uint8_t)ch_num); - __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_NAK); __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_DTERR); - hhcd->hc[ch_num].state = HC_DATATGLERR; } else if ((USBx_HC(ch_num)->HCINT & USB_OTG_HCINT_CHH) == USB_OTG_HCINT_CHH) { - __HAL_HCD_MASK_HALT_HC_INT(ch_num); - if (hhcd->hc[ch_num].state == HC_XFRC) { hhcd->hc[ch_num].urb_state = URB_DONE; if ((hhcd->hc[ch_num].ep_type == EP_TYPE_BULK) || (hhcd->hc[ch_num].ep_type == EP_TYPE_INTR)) { - if (hhcd->Init.dma_enable == 1U) + if (hhcd->Init.dma_enable == 0U) { - if (hhcd->hc[ch_num].xfer_len > 0U) - { - num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; - - if ((num_packets & 1U) != 0U) - { - hhcd->hc[ch_num].toggle_out ^= 1U; - } - } + hhcd->hc[ch_num].toggle_out ^= 1U; } - else + + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[ch_num].xfer_len > 0U)) { - hhcd->hc[ch_num].toggle_out ^= 1U; + num_packets = (hhcd->hc[ch_num].xfer_len + hhcd->hc[ch_num].max_packet - 1U) / hhcd->hc[ch_num].max_packet; + + if ((num_packets & 1U) != 0U) + { + hhcd->hc[ch_num].toggle_out ^= 1U; + } } } } @@ -1558,7 +1544,12 @@ static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum) } __HAL_HCD_CLEAR_HC_INT(ch_num, USB_OTG_HCINT_CHH); + +#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U) + hhcd->HC_NotifyURBChangeCallback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#else HAL_HCD_HC_NotifyURBChange_Callback(hhcd, (uint8_t)ch_num, hhcd->hc[ch_num].urb_state); +#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } else { @@ -1641,7 +1632,8 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) { USB_OTG_GlobalTypeDef *USBx = hhcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - __IO uint32_t hprt0, hprt0_dup; + __IO uint32_t hprt0; + __IO uint32_t hprt0_dup; /* Handle Host Port Interrupts */ hprt0 = USBx_HPRT0; @@ -1661,7 +1653,7 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) HAL_HCD_Connect_Callback(hhcd); #endif /* USE_HAL_HCD_REGISTER_CALLBACKS */ } - hprt0_dup |= USB_OTG_HPRT_PCDET; + hprt0_dup |= USB_OTG_HPRT_PCDET; } /* Check whether Port Enable Changed */ @@ -1734,5 +1726,3 @@ static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.h index c9ac38a9560..9cd148626cd 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_hcd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -111,11 +110,16 @@ typedef struct #define HCD_SPEED_HIGH USBH_HS_SPEED #define HCD_SPEED_FULL USBH_FSLS_SPEED #define HCD_SPEED_LOW USBH_FSLS_SPEED +/** + * @} + */ +/** @defgroup HCD_Device_Speed HCD Device Speed + * @{ + */ #define HCD_DEVICE_SPEED_HIGH 0U #define HCD_DEVICE_SPEED_FULL 1U #define HCD_DEVICE_SPEED_LOW 2U - /** * @} */ @@ -153,7 +157,8 @@ typedef struct #define __HAL_HCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_HCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__)) #define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) @@ -296,10 +301,10 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); */ /* Private functions prototypes ----------------------------------------------*/ - /** +/** * @} */ - /** +/** * @} */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ @@ -309,5 +314,3 @@ uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd); #endif #endif /* STM32F4xx_HAL_HCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.c index cdf4ac7196b..8034cf90e15 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.c @@ -9,6 +9,17 @@ * + IO operation functions * + Peripheral State, Mode and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -19,7 +30,7 @@ (#) Declare a I2C_HandleTypeDef handle structure, for example: I2C_HandleTypeDef hi2c; - (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: + (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: (##) Enable the I2Cx interface clock (##) I2C pins configuration (+++) Enable the clock for the I2C GPIOs @@ -39,48 +50,48 @@ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API. + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API. - (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= [..] - (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() + (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() + (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() + (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() + (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() *** Polling mode IO MEM operation *** ===================================== [..] - (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() + (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() + (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() *** Interrupt mode IO operation *** =================================== [..] - (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() *** Interrupt mode or DMA mode IO sequential operation *** ========================================================== @@ -89,14 +100,14 @@ when a direction change during transfer [..] (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below: + (+) Option field values are defined through I2C_XferOptions_definition and are listed below: (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address and data to transfer without a final stop condition, an then permit a call the same master sequential interface - several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() - or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) + several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() + or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address and with new data to transfer if the direction change or manage only the new data to transfer if no direction change and without a final stop condition in both cases @@ -120,85 +131,85 @@ Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. (+) Different sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() - or using @ref HAL_I2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() - or using @ref HAL_I2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() - (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can + (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT() + or using HAL_I2C_Master_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() + (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT() + or using HAL_I2C_Master_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() + (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() + (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() + (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). - (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() - or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() - or using @ref HAL_I2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() + (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT() + or using HAL_I2C_Slave_Seq_Transmit_DMA() + (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() + (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT() + or using HAL_I2C_Slave_Seq_Receive_DMA() + (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** Interrupt mode IO MEM operation *** ======================================= [..] (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - @ref HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_IT() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - @ref HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_IT() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** DMA mode IO operation *** ============================== [..] (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() + HAL_I2C_Master_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() + HAL_I2C_Master_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() + HAL_I2C_Slave_Transmit_DMA() + (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - @ref HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() - (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() - (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() + HAL_I2C_Slave_Receive_DMA() + (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() + (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() + (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() *** DMA mode IO MEM operation *** ================================= [..] (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - @ref HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() + HAL_I2C_Mem_Write_DMA() + (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - @ref HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() + HAL_I2C_Mem_Read_DMA() + (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() + (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_I2C_ErrorCallback() *** I2C HAL driver macros list *** @@ -206,22 +217,22 @@ [..] Below the list of most used macros in I2C HAL driver. - (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) @ref __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not - (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt + (+) __HAL_I2C_ENABLE: Enable the I2C peripheral + (+) __HAL_I2C_DISABLE: Disable the I2C peripheral + (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt *** Callback registration *** ============================================= [..] The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() + Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() to register an interrupt callback. [..] - Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: + Function HAL_I2C_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -236,11 +247,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). + For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). [..] - Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default + Use function HAL_I2C_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -255,24 +266,24 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). + For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). [..] - By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET + By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). + examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when + reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() + If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, + in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() - or @ref HAL_I2C_Init() function. + using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() + or HAL_I2C_Init() function. [..] When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks @@ -284,18 +295,6 @@ (@) You can refer to the I2C HAL driver header file for more useful macros @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -384,6 +383,9 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); /* Private function to Convert Specific options */ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); + +/* Private function to flush DR register */ +static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c); /** * @} */ @@ -941,6 +943,20 @@ HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ +/** + * @brief I2C data register flush process. + * @param hi2c I2C handle. + * @retval None + */ +static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c) +{ + /* Write a dummy data in DR to clear TXE flag */ + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET) + { + hi2c->Instance->DR = 0x00U; + } +} + /** * @} */ @@ -1358,6 +1374,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) { + + if (hi2c->XferSize == 3U) + { + /* Disable Acknowledge */ + CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + } + /* Read data from DR */ *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; @@ -1663,10 +1686,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -1695,9 +1715,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->Devaddress = DevAddress; - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1707,6 +1724,9 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + return HAL_OK; } else @@ -1743,10 +1763,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -1775,11 +1792,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De hi2c->XferOptions = I2C_NO_OPTION_FRAME; hi2c->Devaddress = DevAddress; - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -1791,6 +1803,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); + return HAL_OK; } else @@ -1952,10 +1970,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -2020,12 +2035,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t if (dmaxferstatus == HAL_OK) { - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2038,6 +2047,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t /* Enable DMA Request */ SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); } else { @@ -2110,10 +2125,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -2214,12 +2226,6 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D } else { - /* Enable Acknowledge */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); - - /* Generate Start */ - SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); - /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -2229,6 +2235,12 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D /* Enable EVT, BUF and ERR interrupt */ __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); + + /* Enable Acknowledge */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + + /* Generate Start */ + SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); } return HAL_OK; @@ -2871,10 +2883,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -2959,10 +2968,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3057,10 +3063,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3087,6 +3090,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; if (hi2c->XferSize > 0U) { @@ -3237,10 +3244,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3267,6 +3271,10 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr hi2c->XferCount = Size; hi2c->XferSize = hi2c->XferCount; hi2c->XferOptions = I2C_NO_OPTION_FRAME; + hi2c->Devaddress = DevAddress; + hi2c->Memaddress = MemAddress; + hi2c->MemaddSize = MemAddSize; + hi2c->EventCount = 0U; if (hi2c->XferSize > 0U) { @@ -3412,7 +3420,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd { /* Get tick */ uint32_t tickstart = HAL_GetTick(); - uint32_t I2C_Trials = 1U; + uint32_t I2C_Trials = 0U; FlagStatus tmp1; FlagStatus tmp2; @@ -3569,10 +3577,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16 hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3668,10 +3673,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1 hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3851,10 +3853,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_ hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -3976,10 +3975,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16 hi2c->Mode = HAL_I2C_MODE_NONE; hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; + return HAL_BUSY; } } while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); @@ -4823,13 +4819,16 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* BTF set -------------------------------------------------------------*/ else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) { - if (CurrentMode == HAL_I2C_MODE_MASTER) + if (CurrentState == HAL_I2C_STATE_BUSY_TX) { I2C_MasterTransmit_BTF(hi2c); } else /* HAL_I2C_MODE_MEM */ { - I2C_MemoryTransmit_TXE_BTF(hi2c); + if (CurrentMode == HAL_I2C_MODE_MEM) + { + I2C_MemoryTransmit_TXE_BTF(hi2c); + } } } else @@ -5383,13 +5382,25 @@ static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) hi2c->PreviousState = I2C_STATE_NONE; hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; + if (hi2c->Mode == HAL_I2C_MODE_MEM) + { + hi2c->Mode = HAL_I2C_MODE_NONE; +#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) + hi2c->MemTxCpltCallback(hi2c); +#else + HAL_I2C_MemTxCpltCallback(hi2c); +#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } + else + { + hi2c->Mode = HAL_I2C_MODE_NONE; #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterTxCpltCallback(hi2c); + hi2c->MasterTxCpltCallback(hi2c); #else - HAL_I2C_MasterTxCpltCallback(hi2c); + HAL_I2C_MasterTxCpltCallback(hi2c); #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ + } } } } @@ -5442,6 +5453,8 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) { /* Generate Restart */ hi2c->Instance->CR1 |= I2C_CR1_START; + + hi2c->EventCount++; } else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) { @@ -5479,7 +5492,8 @@ static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) } else { - /* Do nothing */ + /* Clear TXE and BTF flag */ + I2C_Flush_DR(hi2c); } } @@ -5586,7 +5600,9 @@ static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) } else { - /* Do nothing */ + /* Disable BUF interrupt, this help to treat correctly the last 2 bytes + on BTF subroutine if there is a reception delay between N-1 and N byte */ + __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); } } } @@ -6111,7 +6127,7 @@ static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) else { /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); + __HAL_I2C_CLEAR_ADDRFLAG(hi2c); /* Process Unlocked */ __HAL_UNLOCK(hi2c); @@ -6340,6 +6356,9 @@ static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) /* Disable Acknowledge */ CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); + /*Clear TXE flag*/ + I2C_Flush_DR(hi2c); + #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) hi2c->SlaveTxCpltCallback(hi2c); #else @@ -7176,15 +7195,18 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7228,15 +7250,18 @@ static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeD { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7266,15 +7291,18 @@ static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7304,15 +7332,18 @@ static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } } @@ -7340,15 +7371,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -7414,15 +7448,18 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; + if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + { + hi2c->PreviousState = I2C_STATE_NONE; + hi2c->State = HAL_I2C_STATE_READY; + hi2c->Mode = HAL_I2C_MODE_NONE; + hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_ERROR; + return HAL_ERROR; + } } } return HAL_OK; @@ -7495,4 +7532,3 @@ static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.h index 9a622b82b3a..9a7a67efb96 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -740,4 +739,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* __STM32F4xx_HAL_I2C_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c_ex.c index ed50332005c..64aabaa46e3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c_ex.c @@ -7,6 +7,17 @@ * functionalities of I2C extension peripheral: * + Extension features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### I2C peripheral extension features ##### @@ -25,18 +36,6 @@ (#) Configure I2C Digital noise filter using the function HAL_I2C_DigitalFilter_Config() @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -181,4 +180,3 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c_ex.h index 6864d83519f..31ad99c3a2d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2c_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -114,4 +113,3 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_ #endif /* __STM32F4xx_HAL_I2C_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.c index 5febc391a87..700a0cae4d2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.c @@ -8,6 +8,17 @@ * + Initialization and de-initialization functions * + IO operation functions * + Peripheral State and Errors functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -169,18 +180,7 @@ and weak (surcharged) callbacks are used. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ @@ -303,12 +303,12 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) hi2s->RxCpltCallback = HAL_I2S_RxCpltCallback; /* Legacy weak RxCpltCallback */ #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ hi2s->RxHalfCpltCallback = HAL_I2S_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ if (hi2s->MspInitCallback == NULL) @@ -368,7 +368,7 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) } #else i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); -#endif +#endif /* I2S_APB1_APB2_FEATURE */ /* Compute the Real divider depending on the MCLK output state, with a floating point */ if (hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) @@ -603,7 +603,7 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call case HAL_I2S_TX_RX_COMPLETE_CB_ID : hi2s->TxRxCpltCallback = pCallback; break; -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ case HAL_I2S_TX_HALF_COMPLETE_CB_ID : hi2s->TxHalfCpltCallback = pCallback; @@ -617,7 +617,7 @@ HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Call case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : hi2s->TxRxHalfCpltCallback = pCallback; break; -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ case HAL_I2S_ERROR_CB_ID : hi2s->ErrorCallback = pCallback; @@ -706,7 +706,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca case HAL_I2S_TX_RX_COMPLETE_CB_ID : hi2s->TxRxCpltCallback = HAL_I2SEx_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ break; -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ case HAL_I2S_TX_HALF_COMPLETE_CB_ID : hi2s->TxHalfCpltCallback = HAL_I2S_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ @@ -720,7 +720,7 @@ HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_Ca case HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID : hi2s->TxRxHalfCpltCallback = HAL_I2SEx_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ break; -#endif +#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ case HAL_I2S_ERROR_CB_ID : hi2s->ErrorCallback = HAL_I2S_ErrorCallback; /* Legacy weak ErrorCallback */ @@ -2092,4 +2092,3 @@ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, #endif /* HAL_I2S_MODULE_ENABLED */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.h index 1e9676f868d..66cee01b260 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -617,4 +616,3 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); #endif /* STM32F4xx_HAL_I2S_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s_ex.c index cd0db5e90ae..643bf74d12e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s_ex.c @@ -6,7 +6,17 @@ * This file provides firmware functions to manage the following * functionalities of I2S extension peripheral: * + Extension features Functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### I2S Extension features ##### @@ -73,18 +83,6 @@ | | I2Sx_ext |------------------->I2Sx_extSD(in/out) +----->| | +-----------------------+ - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -1135,4 +1133,3 @@ static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTyp * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s_ex.h index 10335f49f4d..3aaa45b76e1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_i2s_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -182,4 +181,3 @@ void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s); #endif /* STM32F4xx_HAL_I2S_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.c index 511a5bf826b..c754d461f1b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.c @@ -9,6 +9,18 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -111,8 +123,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_IRDA_RegisterCallback() to register a user callback. - Function @ref HAL_IRDA_RegisterCallback() allows to register following callbacks: + Use Function HAL_IRDA_RegisterCallback() to register a user callback. + Function HAL_IRDA_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -127,9 +139,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_IRDA_UnRegisterCallback() to reset a callback to the default + Use function HAL_IRDA_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_IRDA_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -144,13 +156,13 @@ (+) MspDeInitCallback : IRDA MspDeInit. [..] - By default, after the @ref HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET + By default, after the HAL_IRDA_Init() and when the state is HAL_IRDA_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_IRDA_TxCpltCallback(), @ref HAL_IRDA_RxHalfCpltCallback(). + examples HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_IRDA_Init() - and @ref HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_IRDA_Init() and @ref HAL_IRDA_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_IRDA_Init() + and HAL_IRDA_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_IRDA_Init() and HAL_IRDA_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -159,8 +171,8 @@ in HAL_IRDA_STATE_READY or HAL_IRDA_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_IRDA_RegisterCallback() before calling @ref HAL_IRDA_DeInit() - or @ref HAL_IRDA_Init() function. + using HAL_IRDA_RegisterCallback() before calling HAL_IRDA_DeInit() + or HAL_IRDA_Init() function. [..] When The compilation define USE_HAL_IRDA_REGISTER_CALLBACKS is set to 0 or @@ -169,7 +181,7 @@ @endverbatim [..] - (@) Additionnal remark: If the parity is enabled, then the MSB bit of the data written + (@) Additional remark: If the parity is enabled, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit. Depending on the frame length defined by the M bit (8-bits or 9-bits), the possible IRDA frame formats are as listed in the following table: @@ -185,17 +197,6 @@ | 1 | 1 | | SB | 8 bit data | PB | 1 STB | | +-------------------------------------------------------------+ ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -767,9 +768,9 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD * @param Timeout Specify timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint16_t *tmp; + const uint16_t *tmp; uint32_t tickstart = 0U; /* Check that a Tx process is not already ongoing */ @@ -786,7 +787,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->gState = HAL_IRDA_STATE_BUSY_TX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); hirda->TxXferSize = Size; @@ -800,7 +801,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u { return HAL_TIMEOUT; } - tmp = (uint16_t *) pData; + tmp = (const uint16_t *) pData; hirda->Instance->DR = (*tmp & (uint16_t)0x01FF); if (hirda->Init.Parity == IRDA_PARITY_NONE) { @@ -871,7 +872,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui hirda->ErrorCode = HAL_IRDA_ERROR_NONE; hirda->RxState = HAL_IRDA_STATE_BUSY_RX; - /* Init tickstart for timeout managment*/ + /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); hirda->RxXferSize = Size; @@ -942,7 +943,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (hirda->gState == HAL_IRDA_STATE_READY) @@ -1010,8 +1011,16 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Parity Error and Data Register Not Empty Interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the IRDA Parity Error and Data Register Not Empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + } + else + { + /* Enable the IRDA Data Register Not Empty Interrupts */ + SET_BIT(hirda->Instance->CR1, USART_CR1_RXNEIE); + } /* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1035,9 +1044,9 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size) { - uint32_t *tmp; + const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (hirda->gState == HAL_IRDA_STATE_READY) @@ -1070,8 +1079,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat hirda->hdmatx->XferAbortCallback = NULL; /* Enable the IRDA transmit DMA stream */ - tmp = (uint32_t *)&pData; - HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t *)tmp, (uint32_t)&hirda->Instance->DR, Size); + tmp = (const uint32_t *)&pData; + HAL_DMA_Start_IT(hirda->hdmatx, *(const uint32_t *)tmp, (uint32_t)&hirda->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC); @@ -1146,8 +1155,11 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Parity Error Interrupt */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + /* Enable the IRDA Parity Error Interrupt */ + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } /* Enable the IRDA Error Interrupt: (Frame error, Noise error, Overrun error) */ SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); @@ -1223,8 +1235,11 @@ HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda) /* Clear the Overrun flag before resuming the Rx transfer */ __HAL_IRDA_CLEAR_OREFLAG(hirda); - /* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (hirda->Init.Parity != IRDA_PARITY_NONE) + { + SET_BIT(hirda->Instance->CR1, USART_CR1_PEIE); + } SET_BIT(hirda->Instance->CR3, USART_CR3_EIE); /* Enable the IRDA DMA Rx request */ @@ -2015,7 +2030,7 @@ __weak void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA. * @retval HAL state */ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda) { uint32_t temp1 = 0x00U, temp2 = 0x00U; temp1 = hirda->gState; @@ -2030,7 +2045,7 @@ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda) * the configuration information for the specified IRDA. * @retval IRDA Error Code */ -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda) +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda) { return hirda->ErrorCode; } @@ -2215,11 +2230,12 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles IRDA Communication Timeout. + * @brief This function handles IRDA Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA. * @param Flag specifies the IRDA flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status @@ -2451,14 +2467,14 @@ static void IRDA_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (hirda->gState == HAL_IRDA_STATE_BUSY_TX) { if (hirda->Init.WordLength == IRDA_WORDLENGTH_9B) { - tmp = (uint16_t *) hirda->pTxBuffPtr; + tmp = (const uint16_t *) hirda->pTxBuffPtr; hirda->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); if (hirda->Init.Parity == IRDA_PARITY_NONE) { @@ -2669,4 +2685,3 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.h index 4d83abc22d0..5735215dc19 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_irda.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -145,7 +144,7 @@ typedef struct IRDA_InitTypeDef Init; /*!< IRDA communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to IRDA Tx transfer Buffer */ uint16_t TxXferSize; /*!< IRDA Tx Transfer size */ @@ -560,11 +559,11 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD * @{ */ /* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda); @@ -594,8 +593,8 @@ void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda); * @{ */ /* Peripheral State functions **************************************************/ -HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); -uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); +HAL_IRDA_StateTypeDef HAL_IRDA_GetState(const IRDA_HandleTypeDef *hirda); +uint32_t HAL_IRDA_GetError(const IRDA_HandleTypeDef *hirda); /** * @} */ @@ -681,4 +680,3 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); #endif /* __STM32F4xx_HAL_IRDA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.c index 6cbbc24ecfa..c01eb29c0e1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.c @@ -8,6 +8,17 @@ * + Initialization and Start functions * + IO operation functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### IWDG Generic features ##### @@ -80,18 +91,6 @@ the reload register @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -115,11 +114,13 @@ /* Status register needs up to 5 LSI clock periods divided by the clock prescaler to be updated. The number of LSI clock periods is upper-rounded to 6 for the timeout value calculation. - The timeout value is also calculated using the highest prescaler (256) and + The timeout value is calculated using the highest prescaler (256) and the LSI_VALUE constant. The value of this constant can be changed by the user to take into account possible LSI clock period variations. - The timeout value is multiplied by 1000 to be converted in milliseconds. */ -#define HAL_IWDG_DEFAULT_TIMEOUT ((6UL * 256UL * 1000UL) / LSI_VALUE) + The timeout value is multiplied by 1000 to be converted in milliseconds. + LSI startup time is also considered here by adding LSI_STARTUP_TIME + converted in milliseconds. */ +#define HAL_IWDG_DEFAULT_TIMEOUT (((6UL * 256UL * 1000UL) / LSI_VALUE) + ((LSI_STARTUP_TIME / 1000UL) + 1UL)) #define IWDG_KERNEL_UPDATE_FLAGS (IWDG_SR_RVU | IWDG_SR_PVU) /** * @} @@ -259,5 +260,3 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.h index 32f5ff027ae..5273730c147 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_iwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -219,5 +218,3 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); #endif #endif /* STM32F4xx_HAL_IWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_lptim.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_lptim.c index 338bc8130af..e302d59f2e7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_lptim.c @@ -11,6 +11,17 @@ * + Reading operation functions. * + Peripheral State functions. * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -93,13 +104,13 @@ The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. - @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, + Use Function HAL_LPTIM_RegisterCallback() to register a callback. + HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the + Use function HAL_LPTIM_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] These functions allow to register/unregister following callbacks: @@ -117,7 +128,7 @@ [..] By default, after the Init and when the state is HAL_LPTIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). + examples HAL_LPTIM_TriggerCallback(), HAL_LPTIM_CompareMatchCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak @@ -131,7 +142,7 @@ in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. + using HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or @@ -140,17 +151,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -232,8 +232,8 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) assert_param(IS_LPTIM_CLOCK_SOURCE(hlptim->Init.Clock.Source)); assert_param(IS_LPTIM_CLOCK_PRESCALER(hlptim->Init.Clock.Prescaler)); - if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { assert_param(IS_LPTIM_CLOCK_POLARITY(hlptim->Init.UltraLowPowerClock.Polarity)); assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(hlptim->Init.UltraLowPowerClock.SampleTime)); @@ -276,8 +276,8 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /* Get the LPTIMx CFGR value */ tmpcfgr = hlptim->Instance->CFGR; - if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { tmpcfgr &= (uint32_t)(~(LPTIM_CFGR_CKPOL | LPTIM_CFGR_CKFLT)); } @@ -307,8 +307,8 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) } /* Configure LPTIM external clock polarity and digital filter */ - if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) - || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) + if ((hlptim->Init.Clock.Source == LPTIM_CLOCKSOURCE_ULPTIM) + || (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL)) { tmpcfgr |= (hlptim->Init.UltraLowPowerClock.Polarity | hlptim->Init.UltraLowPowerClock.SampleTime); @@ -444,7 +444,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM PWM generation. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -492,7 +492,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -509,7 +509,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ @@ -520,7 +520,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -531,7 +531,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM PWM generation in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF + * This parameter must be a value between 0x0001 and 0xFFFF * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF * @retval HAL status @@ -609,7 +609,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -626,7 +626,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; /* Disable the Peripheral */ @@ -656,7 +656,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -667,7 +667,7 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM One pulse generation. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -715,7 +715,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -743,7 +743,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -754,7 +754,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM One pulse generation in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -832,7 +832,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -852,6 +852,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Set the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -879,7 +880,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -890,7 +891,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the LPTIM in Set once mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Pulse Specifies the compare value. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -938,7 +939,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -966,7 +967,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1055,7 +1056,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in single (one shot) mode */ __HAL_LPTIM_START_SINGLE(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1102,7 +1103,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1113,7 +1114,7 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Encoder interface. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1163,7 +1164,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1194,7 +1195,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset ENC bit to disable the encoder interface */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1273,7 +1274,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1310,7 +1311,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable "switch to up direction" interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1323,7 +1324,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) * trigger event will reset the counter and the timer restarts. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1371,7 +1372,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1402,7 +1403,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) /* Reset TIMOUT bit to enable the timeout function */ hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1415,7 +1416,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim) * trigger event will reset the counter and the timer restarts. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @param Timeout Specifies the TimeOut value to reset the counter. * This parameter must be a value between 0x0000 and 0xFFFF. * @retval HAL status @@ -1484,7 +1485,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1501,8 +1502,6 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; #if defined(EXTI_IMR_MR23) /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); @@ -1511,6 +1510,9 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1525,7 +1527,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Compare match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1536,7 +1538,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @brief Start the Counter mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1576,7 +1578,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1604,7 +1606,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) return HAL_TIMEOUT; } - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1615,7 +1617,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim) * @brief Start the Counter mode in interrupt mode. * @param hlptim LPTIM handle * @param Period Specifies the Autoreload value. - * This parameter must be a value between 0x0000 and 0xFFFF. + * This parameter must be a value between 0x0001 and 0xFFFF. * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period) @@ -1679,7 +1681,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 /* Start timer in continuous mode */ __HAL_LPTIM_START_CONTINUOUS(hlptim); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1696,8 +1698,6 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); - /* Set the LPTIM state */ - hlptim->State = HAL_LPTIM_STATE_BUSY; #if defined(EXTI_IMR_MR23) /* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); @@ -1706,6 +1706,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */ __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT(); + /* Set the LPTIM state */ + hlptim->State = HAL_LPTIM_STATE_BUSY; + /* Disable the Peripheral */ __HAL_LPTIM_DISABLE(hlptim); @@ -1719,7 +1722,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) /* Disable Autoreload match interrupt */ __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); - /* Change the TIM state*/ + /* Change the LPTIM state */ hlptim->State = HAL_LPTIM_STATE_READY; /* Return function status */ @@ -1750,7 +1753,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Counter value. */ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1763,7 +1766,7 @@ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Autoreload value. */ -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -1776,7 +1779,7 @@ uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim) * @param hlptim LPTIM handle * @retval Compare value. */ -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim) { /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(hlptim->Instance)); @@ -2183,39 +2186,48 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti switch (CallbackID) { case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; break; case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; break; case HAL_LPTIM_COMPARE_MATCH_CB_ID : - hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare match Callback */ + /* Legacy weak Compare match Callback */ + hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; break; case HAL_LPTIM_AUTORELOAD_MATCH_CB_ID : - hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto-reload match Callback */ + /* Legacy weak Auto-reload match Callback */ + hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; break; case HAL_LPTIM_TRIGGER_CB_ID : - hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak External trigger event detection Callback */ + /* Legacy weak External trigger event detection Callback */ + hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; break; case HAL_LPTIM_COMPARE_WRITE_CB_ID : - hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare register write complete Callback */ + /* Legacy weak Compare register write complete Callback */ + hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; break; case HAL_LPTIM_AUTORELOAD_WRITE_CB_ID : - hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto-reload register write complete Callback */ + /* Legacy weak Auto-reload register write complete Callback */ + hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; break; case HAL_LPTIM_DIRECTION_UP_CB_ID : - hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Up-counting direction change Callback */ + /* Legacy weak Up-counting direction change Callback */ + hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; break; case HAL_LPTIM_DIRECTION_DOWN_CB_ID : - hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Down-counting direction change Callback */ + /* Legacy weak Down-counting direction change Callback */ + hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; break; default : @@ -2229,11 +2241,13 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlpti switch (CallbackID) { case HAL_LPTIM_MSPINIT_CB_ID : - hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */ + /* Legacy weak MspInit Callback */ + hlptim->MspInitCallback = HAL_LPTIM_MspInit; break; case HAL_LPTIM_MSPDEINIT_CB_ID : - hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak Msp DeInit Callback */ + /* Legacy weak Msp DeInit Callback */ + hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; break; default : @@ -2308,13 +2322,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim) { /* Reset the LPTIM callback to the legacy weak callbacks */ - lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Compare match Callback */ - lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Auto-reload match Callback */ - lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* External trigger event detection Callback */ - lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Compare register write complete Callback */ - lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Auto-reload register write complete Callback */ - lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Up-counting direction change Callback */ - lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Down-counting direction change Callback */ + lptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; + lptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; + lptim->TriggerCallback = HAL_LPTIM_TriggerCallback; + lptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; + lptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; + lptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; + lptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; } #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ @@ -2357,9 +2371,12 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; + uint32_t primask_bit; uint32_t tmpOR; - __disable_irq(); + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1) ; /*********** Save LPTIM Config ***********/ /* Save LPTIM source clock */ @@ -2449,7 +2466,8 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) hlptim->Instance->CFGR = tmpCFGR; hlptim->Instance->OR = tmpOR; - __enable_irq(); + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); } /** * @} @@ -2464,5 +2482,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_lptim.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_lptim.h index a5ab815fdd4..dd4b2ca52ae 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_lptim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -97,22 +96,22 @@ typedef struct */ typedef struct { - LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ + LPTIM_ClockConfigTypeDef Clock; /*!< Specifies the clock parameters */ - LPTIM_ULPClockConfigTypeDef UltraLowPowerClock; /*!< Specifies the Ultra Low Power clock parameters */ + LPTIM_ULPClockConfigTypeDef UltraLowPowerClock;/*!< Specifies the Ultra Low Power clock parameters */ - LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ + LPTIM_TriggerConfigTypeDef Trigger; /*!< Specifies the Trigger parameters */ - uint32_t OutputPolarity; /*!< Specifies the Output polarity. - This parameter can be a value of @ref LPTIM_Output_Polarity */ + uint32_t OutputPolarity; /*!< Specifies the Output polarity. + This parameter can be a value of @ref LPTIM_Output_Polarity */ - uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare - values is done immediately or after the end of current period. - This parameter can be a value of @ref LPTIM_Updating_Mode */ + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare + values is done immediately or after the end of current period. + This parameter can be a value of @ref LPTIM_Updating_Mode */ - uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event - or each external event. - This parameter can be a value of @ref LPTIM_Counter_Source */ + uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event + or each external event. + This parameter can be a value of @ref LPTIM_Counter_Source */ } LPTIM_InitTypeDef; /** @@ -690,9 +689,9 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); * @{ */ /* Reading operation functions ************************************************/ -uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); -uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCounter(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadAutoReload(const LPTIM_HandleTypeDef *hlptim); +uint32_t HAL_LPTIM_ReadCompare(const LPTIM_HandleTypeDef *hlptim); /** * @} */ @@ -819,11 +818,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFUL) +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ + ((__AUTORELOAD__) <= 0x0000FFFFUL)) #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) -#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFFUL) +#define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ + ((__PERIOD__) <= 0x0000FFFFUL)) #define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFFUL) @@ -854,5 +855,3 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim); #endif #endif /* STM32F4xx_HAL_LPTIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.c index 7e4413067fb..fcc5fa1611c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Errors functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -146,17 +157,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -178,6 +178,7 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +#define LTDC_TIMEOUT_VALUE ((uint32_t)100U) /* 100ms */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -211,7 +212,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay */ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) { - uint32_t tmp, tmp1; + uint32_t tmp; + uint32_t tmp1; /* Check the LTDC peripheral state */ if (hltdc == NULL) @@ -320,6 +322,44 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc) { + uint32_t tickstart; + + /* Check the LTDC peripheral state */ + if (hltdc == NULL) + { + return HAL_ERROR; + } + + /* Check function parameters */ + assert_param(IS_LTDC_ALL_INSTANCE(hltdc->Instance)); + + /* Disable LTDC Layer 1 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_1); + +#if defined(LTDC_Layer2_BASE) + /* Disable LTDC Layer 2 */ + __HAL_LTDC_LAYER_DISABLE(hltdc, LTDC_LAYER_2); +#endif /* LTDC_Layer2_BASE */ + + /* Reload during vertical blanking period */ + __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(hltdc); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Wait for VSYNC Interrupt */ + while (READ_BIT(hltdc->Instance->CDSR, LTDC_CDSR_VSYNCS) == 0U) + { + /* Check for the Timeout */ + if ((HAL_GetTick() - tickstart) > LTDC_TIMEOUT_VALUE) + { + break; + } + } + + /* Disable LTDC */ + __HAL_LTDC_DISABLE(hltdc); + #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) if (hltdc->MspDeInitCallback == NULL) { @@ -391,7 +431,8 @@ __weak void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc) * @param pCallback pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -473,7 +514,7 @@ HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_ /** * @brief Unregister an LTDC Callback - * LTDC callabck is redirected to the weak predefined callback + * LTDC callback is redirected to the weak predefined callback * @param hltdc ltdc handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -887,11 +928,13 @@ HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT { if (hltdc->LayerCfg[LayerIdx].PixelFormat == LTDC_PIXEL_FORMAT_AL44) { - tmp = (((counter + (16U*counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + tmp = (((counter + (16U * counter)) << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); } else { - tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); + tmp = ((counter << 24U) | ((uint32_t)(*pcolorlut) & 0xFFU) | \ + ((uint32_t)(*pcolorlut) & 0xFF00U) | ((uint32_t)(*pcolorlut) & 0xFF0000U)); } pcolorlut++; @@ -1345,12 +1388,14 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres } /** - * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels - * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). - * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch - * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by previous + * call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'. @@ -1504,7 +1549,8 @@ HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadTyp * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx) { /* Check the parameters */ assert_param(IS_LTDC_LAYER(LayerIdx)); @@ -1553,7 +1599,8 @@ HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_ * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; @@ -1607,7 +1654,8 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uin * LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1) * @retval HAL status */ -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx) +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx) { LTDC_LayerCfgTypeDef *pLayerCfg; @@ -1774,12 +1822,14 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32 } /** - * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is - * larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we - * want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels - * will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer(). - * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch - * configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). + * @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width + * that is larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to + * layer for which we want to read and display on screen only a portion 320x240 taken in the center + * of the buffer. + * The pitch in pixels will be in that case 800 pixels and not 320 pixels as initially configured by + * previous call to HAL_LTDC_ConfigLayer(). + * @note This function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default + * pitch configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above). * Variant of the function HAL_LTDC_SetPitch without immediate reload. * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. @@ -2082,7 +2132,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /* Configure the horizontal start and stop position */ tmp = ((pLayerCfg->WindowX1 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U)) << 16U); LTDC_LAYER(hltdc, LayerIdx)->WHPCR &= ~(LTDC_LxWHPCR_WHSTPOS | LTDC_LxWHPCR_WHSPPOS); - LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); + LTDC_LAYER(hltdc, LayerIdx)->WHPCR = ((pLayerCfg->WindowX0 + \ + ((hltdc->Instance->BPCR & LTDC_BPCR_AHBP) >> 16U) + 1U) | tmp); /* Configure the vertical start and stop position */ tmp = ((pLayerCfg->WindowY1 + (hltdc->Instance->BPCR & LTDC_BPCR_AVBP)) << 16U); @@ -2097,7 +2148,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay tmp = ((uint32_t)(pLayerCfg->Backcolor.Green) << 8U); tmp1 = ((uint32_t)(pLayerCfg->Backcolor.Red) << 16U); tmp2 = (pLayerCfg->Alpha0 << 24U); - LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | LTDC_LxDCCR_DCALPHA); + LTDC_LAYER(hltdc, LayerIdx)->DCCR &= ~(LTDC_LxDCCR_DCBLUE | LTDC_LxDCCR_DCGREEN | LTDC_LxDCCR_DCRED | + LTDC_LxDCCR_DCALPHA); LTDC_LAYER(hltdc, LayerIdx)->DCCR = (pLayerCfg->Backcolor.Blue | tmp | tmp1 | tmp2); /* Specifies the constant alpha value */ @@ -2134,7 +2186,8 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay /* Configure the color frame buffer pitch in byte */ LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~(LTDC_LxCFBLR_CFBLL | LTDC_LxCFBLR_CFBP); - LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); + LTDC_LAYER(hltdc, LayerIdx)->CFBLR = (((pLayerCfg->ImageWidth * tmp) << 16U) | \ + (((pLayerCfg->WindowX1 - pLayerCfg->WindowX0) * tmp) + 3U)); /* Configure the frame buffer line number */ LTDC_LAYER(hltdc, LayerIdx)->CFBLNR &= ~(LTDC_LxCFBLNR_CFBLNBR); LTDC_LAYER(hltdc, LayerIdx)->CFBLNR = (pLayerCfg->ImageHeight); @@ -2160,4 +2213,3 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.h index 0cab8446ef6..ab951d3ea70 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -80,28 +79,36 @@ typedef struct This parameter can be one of value of @ref LTDC_PC_POLARITY */ uint32_t HorizontalSync; /*!< configures the number of Horizontal synchronization width. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t VerticalSync; /*!< configures the number of Vertical synchronization height. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ uint32_t AccumulatedHBP; /*!< configures the accumulated horizontal back porch width. - This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */ uint32_t AccumulatedVBP; /*!< configures the accumulated vertical back porch height. - This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */ uint32_t AccumulatedActiveW; /*!< configures the accumulated active width. - This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */ uint32_t AccumulatedActiveH; /*!< configures the accumulated active height. - This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */ uint32_t TotalWidth; /*!< configures the total width. - This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */ uint32_t TotalHeigh; /*!< configures the total height. - This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */ LTDC_ColorTypeDef Backcolor; /*!< Configures the background color. */ } LTDC_InitTypeDef; @@ -112,25 +119,31 @@ typedef struct typedef struct { uint32_t WindowX0; /*!< Configures the Window Horizontal Start Position. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WindowX1; /*!< Configures the Window Horizontal Stop Position. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0xFFF. */ uint32_t WindowY0; /*!< Configures the Window vertical Start Position. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ uint32_t WindowY1; /*!< Configures the Window vertical Stop Position. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x7FF. */ uint32_t PixelFormat; /*!< Specifies the pixel format. This parameter can be one of value of @ref LTDC_Pixelformat */ uint32_t Alpha; /*!< Specifies the constant alpha used for blending. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ uint32_t Alpha0; /*!< Configures the default alpha value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ + This parameter must be a number between + Min_Data = 0x00 and Max_Data = 0xFF. */ uint32_t BlendingFactor1; /*!< Select the blending factor 1. This parameter can be one of value of @ref LTDC_BlendingFactor1 */ @@ -141,10 +154,12 @@ typedef struct uint32_t FBStartAdress; /*!< Configures the color frame buffer address */ uint32_t ImageWidth; /*!< Configures the color frame buffer line length. - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */ + This parameter must be a number between + Min_Data = 0x0000 and Max_Data = 0x1FFF. */ uint32_t ImageHeight; /*!< Specifies the number of line in frame buffer. - This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */ + This parameter must be a number between + Min_Data = 0x000 and Max_Data = 0x7FF. */ LTDC_ColorTypeDef Backcolor; /*!< Configures the layer background color. */ } LTDC_LayerCfgTypeDef; @@ -400,7 +415,7 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer * @retval None */ #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ +#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{ \ (__HANDLE__)->State = HAL_LTDC_STATE_RESET; \ (__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \ @@ -430,7 +445,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). * @retval None. */ -#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN) +#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + |= (uint32_t)LTDC_LxCR_LEN) /** * @brief Disable the LTDC Layer. @@ -439,7 +455,8 @@ typedef void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc); /*!< pointer * This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1). * @retval None. */ -#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN) +#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR\ + &= ~(uint32_t)LTDC_LxCR_LEN) /** * @brief Reload immediately all LTDC Layers. @@ -545,7 +562,8 @@ void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, + pLTDC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */ @@ -583,9 +601,12 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc); HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc); HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType); -HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx); -HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, + uint32_t LayerIdx); +HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, + uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx); HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx); @@ -621,12 +642,18 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** @defgroup LTDC_Private_Macros LTDC Private Macros * @{ */ -#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__))))) +#define LTDC_LAYER(__HANDLE__, __LAYER__) ((LTDC_Layer_TypeDef *)((uint32_t)(\ + ((uint32_t)((__HANDLE__)->Instance))\ + + 0x84U + (0x80U*(__LAYER__))))) #define IS_LTDC_LAYER(__LAYER__) ((__LAYER__) < MAX_LAYER) -#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) -#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) -#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) -#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) +#define IS_LTDC_HSPOL(__HSPOL__) (((__HSPOL__) == LTDC_HSPOLARITY_AL)\ + || ((__HSPOL__) == LTDC_HSPOLARITY_AH)) +#define IS_LTDC_VSPOL(__VSPOL__) (((__VSPOL__) == LTDC_VSPOLARITY_AL)\ + || ((__VSPOL__) == LTDC_VSPOLARITY_AH)) +#define IS_LTDC_DEPOL(__DEPOL__) (((__DEPOL__) == LTDC_DEPOLARITY_AL)\ + || ((__DEPOL__) == LTDC_DEPOLARITY_AH)) +#define IS_LTDC_PCPOL(__PCPOL__) (((__PCPOL__) == LTDC_PCPOLARITY_IPC)\ + || ((__PCPOL__) == LTDC_PCPOLARITY_IIPC)) #define IS_LTDC_HSYNC(__HSYNC__) ((__HSYNC__) <= LTDC_HORIZONTALSYNC) #define IS_LTDC_VSYNC(__VSYNC__) ((__VSYNC__) <= LTDC_VERTICALSYNC) #define IS_LTDC_AHBP(__AHBP__) ((__AHBP__) <= LTDC_HORIZONTALSYNC) @@ -642,10 +669,14 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA)) #define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \ ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA)) -#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ - ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) +#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__) (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44) || \ + ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88)) #define IS_LTDC_ALPHA(__ALPHA__) ((__ALPHA__) <= LTDC_ALPHA) #define IS_LTDC_HCONFIGST(__HCONFIGST__) ((__HCONFIGST__) <= LTDC_STARTPOSITION) #define IS_LTDC_HCONFIGSP(__HCONFIGSP__) ((__HCONFIGSP__) <= LTDC_STOPPOSITION) @@ -655,7 +686,8 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); #define IS_LTDC_CFBLL(__CFBLL__) ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER) #define IS_LTDC_CFBLNBR(__CFBLNBR__) ((__CFBLNBR__) <= LTDC_LINE_NUMBER) #define IS_LTDC_LIPOS(__LIPOS__) ((__LIPOS__) <= 0x7FFU) -#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) +#define IS_LTDC_RELOAD(__RELOADTYPE__) (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || \ + ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING)) /** * @} */ @@ -685,4 +717,3 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); #endif /* STM32F4xx_HAL_LTDC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc_ex.c index 8c39194a665..2ee7795bf37 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc_ex.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -76,7 +75,8 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH */ /* Note 1 : Code in line w/ Current LTDC specification */ - hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.DEPolarity = (VidCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AH : LTDC_VSPOLARITY_AL; hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AH : LTDC_HSPOLARITY_AL; @@ -88,8 +88,10 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc /* Retrieve vertical timing parameters from DSI */ hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1U; hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1U; - hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1U; - hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; + hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive - 1U; + hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + \ + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1U; return HAL_OK; } @@ -114,7 +116,8 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/ /* Note 1 : Code in line w/ Current LTDC specification */ - hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; + hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == \ + DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH; hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH; hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH; @@ -146,4 +149,3 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc_ex.h index 37a5fdf47a3..b9c39e49ae2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_ltdc_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -82,5 +81,3 @@ HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeD #endif #endif /* STM32F4xx_HAL_LTDC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.c index 0be986081f9..466eab5f976 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + MMC card Control functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -63,7 +74,7 @@ SDMMC Peripheral (STM32 side) and the MMC Card, and put it into StandBy State (Ready for data transfer). This function provide the following operations: - (#) Initialize the SDMMC peripheral interface with defaullt configuration. + (#) Initialize the SDMMC peripheral interface with default configuration. The initialization process is done at 400KHz. You can change or adapt this frequency by adjusting the "ClockDiv" field. The MMC Card frequency (SDMMC_CK) is computed as follows: @@ -195,7 +206,7 @@ The compilation define USE_HAL_MMC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_MMC_RegisterCallback() to register a user callback, + Use Functions HAL_MMC_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -206,7 +217,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_MMC_UnRegisterCallback() to reset a callback to the default + Use function HAL_MMC_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -216,12 +227,12 @@ (+) MspDeInitCallback : MMC MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET + By default, after the HAL_MMC_Init and if the state is HAL_MMC_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_MMC_Init - and @ref HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_MMC_Init and @ref HAL_MMC_DeInit + reset to the legacy weak (surcharged) functions in the HAL_MMC_Init + and HAL_MMC_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_MMC_Init and HAL_MMC_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -229,8 +240,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_MMC_RegisterCallback before calling @ref HAL_MMC_DeInit - or @ref HAL_MMC_Init function. + using HAL_MMC_RegisterCallback before calling HAL_MMC_DeInit + or HAL_MMC_Init function. When The compilation define USE_HAL_MMC_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -238,17 +249,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -272,7 +272,30 @@ /** @addtogroup MMC_Private_Defines * @{ */ +#if defined (VDD_VALUE) && (VDD_VALUE <= 1950U) +#define MMC_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 201 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 200 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 238 + +#define MMC_EXT_CSD_PWR_CL_26_POS 8 +#define MMC_EXT_CSD_PWR_CL_52_POS 0 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 16 +#else +#define MMC_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE + +#define MMC_EXT_CSD_PWR_CL_26_INDEX 203 +#define MMC_EXT_CSD_PWR_CL_52_INDEX 202 +#define MMC_EXT_CSD_PWR_CL_DDR_52_INDEX 239 + +#define MMC_EXT_CSD_PWR_CL_26_POS 24 +#define MMC_EXT_CSD_PWR_CL_52_POS 16 +#define MMC_EXT_CSD_PWR_CL_DDR_52_POS 24 +#endif +/* Frequencies used in the driver for clock divider calculation */ +#define MMC_INIT_FREQ 400000U /* Initialization phase : 400 kHz max */ /** * @} */ @@ -296,6 +319,7 @@ static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void MMC_DMAError(DMA_HandleTypeDef *hdma); static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma); static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma); +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide); /** * @} */ @@ -375,7 +399,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) } /* Initialize the error code */ - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; /* Initialize the MMC operation */ hmmc->Context = MMC_CONTEXT_NONE; @@ -383,6 +407,15 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) /* Initialize the MMC state */ hmmc->State = HAL_MMC_STATE_READY; + /* Configure bus width */ + if (hmmc->Init.BusWide != SDIO_BUS_WIDE_1B) + { + if (HAL_MMC_ConfigWideBusOperation(hmmc, hmmc->Init.BusWide) != HAL_OK) + { + return HAL_ERROR; + } + } + return HAL_OK; } @@ -427,6 +460,9 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Enable MMC Clock */ __HAL_MMC_ENABLE(hmmc); + /* Required power up waiting time before starting the MMC initialization sequence */ + HAL_Delay(2); + /* Identify card operating voltage */ errorstate = MMC_PowerON(hmmc); if(errorstate != HAL_MMC_ERROR_NONE) @@ -1151,7 +1187,7 @@ HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData if(hmmc->State == HAL_MMC_STATE_READY) { - hmmc->ErrorCode = HAL_DMA_ERROR_NONE; + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; if((BlockAdd + NumberOfBlocks) > (hmmc->MmcCard.LogBlockNbr)) { @@ -2128,6 +2164,122 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT return HAL_OK; } +/** + * @brief Returns information the information of the card which are stored on + * the Extended CSD register. + * @param hmmc Pointer to MMC handle + * @param pExtCSD Pointer to a memory area (512 bytes) that contains all + * Extended CSD register parameters + * @param Timeout Specify timeout value + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout) +{ + SDIO_DataInitTypeDef config; + uint32_t errorstate; + uint32_t tickstart = HAL_GetTick(); + uint32_t count; + uint32_t *tmp_buf; + + if(NULL == pExtCSD) + { + hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; + return HAL_ERROR; + } + + if(hmmc->State == HAL_MMC_STATE_READY) + { + hmmc->ErrorCode = HAL_MMC_ERROR_NONE; + + hmmc->State = HAL_MMC_STATE_BUSY; + + /* Initialize data control register */ + hmmc->Instance->DCTRL = 0; + + /* Initiaize the destination pointer */ + tmp_buf = pExtCSD; + + /* Configure the MMC DPSM (Data Path State Machine) */ + config.DataTimeOut = SDMMC_DATATIMEOUT; + config.DataLength = 512; + config.DataBlockSize = SDIO_DATABLOCK_SIZE_512B; + config.TransferDir = SDIO_TRANSFER_DIR_TO_SDIO; + config.TransferMode = SDIO_TRANSFER_MODE_BLOCK; + config.DPSM = SDIO_DPSM_ENABLE; + (void)SDIO_ConfigData(hmmc->Instance, &config); + + /* Send ExtCSD Read command to Card */ + errorstate = SDMMC_CmdSendEXTCSD(hmmc->Instance, 0); + if(errorstate != HAL_MMC_ERROR_NONE) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + + /* Poll on SDMMC flags */ + while(!__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND)) + { + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXFIFOHF)) + { + /* Read data from SDMMC Rx FIFO */ + for(count = 0U; count < 8U; count++) + { + *tmp_buf = SDIO_ReadFIFO(hmmc->Instance); + tmp_buf++; + } + } + + if(((HAL_GetTick()-tickstart) >= Timeout) || (Timeout == 0U)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_TIMEOUT; + hmmc->State= HAL_MMC_STATE_READY; + return HAL_TIMEOUT; + } + } + + /* Get error state */ + if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DTIMEOUT)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_TIMEOUT; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_DCRCFAIL)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_DATA_CRC_FAIL; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else if(__HAL_MMC_GET_FLAG(hmmc, SDIO_FLAG_RXOVERR)) + { + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); + hmmc->ErrorCode |= HAL_MMC_ERROR_RX_OVERRUN; + hmmc->State = HAL_MMC_STATE_READY; + return HAL_ERROR; + } + else + { + /* Nothing to do */ + } + + /* Clear all the static flags */ + __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_DATA_FLAGS); + hmmc->State = HAL_MMC_STATE_READY; + } + + return HAL_OK; +} + /** * @brief Enables wide bus operation for the requested card if supported by * card. @@ -2141,10 +2293,10 @@ HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoT */ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode) { - __IO uint32_t count = 0U; + uint32_t count; SDIO_InitTypeDef Init; uint32_t errorstate; - uint32_t response = 0U, busy = 0U; + uint32_t response = 0U; /* Check the parameters */ assert_param(IS_SDIO_BUS_WIDE(WideMode)); @@ -2152,115 +2304,83 @@ HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32 /* Change State */ hmmc->State = HAL_MMC_STATE_BUSY; - /* Update Clock for Bus mode update */ - Init.ClockEdge = SDIO_CLOCK_EDGE_RISING; - Init.ClockBypass = SDIO_CLOCK_BYPASS_DISABLE; - Init.ClockPowerSave = SDIO_CLOCK_POWER_SAVE_DISABLE; - Init.BusWide = WideMode; - Init.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE; - Init.ClockDiv = SDIO_INIT_CLK_DIV; - /* Initialize SDIO*/ - (void)SDIO_Init(hmmc->Instance, Init); + errorstate = MMC_PwrClassUpdate(hmmc, WideMode); - if(WideMode == SDIO_BUS_WIDE_8B) - { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->ErrorCode |= errorstate; - } - } - else if(WideMode == SDIO_BUS_WIDE_4B) + if(errorstate == HAL_MMC_ERROR_NONE) { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); - if(errorstate != HAL_MMC_ERROR_NONE) + if(WideMode == SDIO_BUS_WIDE_8B) { - hmmc->ErrorCode |= errorstate; + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70200U); } - } - else if(WideMode == SDIO_BUS_WIDE_1B) - { - errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); - if(errorstate != HAL_MMC_ERROR_NONE) + else if(WideMode == SDIO_BUS_WIDE_4B) { - hmmc->ErrorCode |= errorstate; + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70100U); } - } - else - { - /* WideMode is not a valid argument*/ - hmmc->ErrorCode |= HAL_MMC_ERROR_PARAM; - } - - /* Check for switch error and violation of the trial number of sending CMD 13 */ - while(busy == 0U) - { - if(count == SDMMC_MAX_TRIAL) + else if(WideMode == SDIO_BUS_WIDE_1B) { - hmmc->State = HAL_MMC_STATE_READY; - hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; - return HAL_ERROR; + errorstate = SDMMC_CmdSwitch(hmmc->Instance, 0x03B70000U); } - count++; - - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) + else { - hmmc->ErrorCode |= errorstate; + /* WideMode is not a valid argument*/ + errorstate = HAL_MMC_ERROR_PARAM; } - /* Get command response */ - response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); - - /* Get operating voltage*/ - busy = (((response >> 7U) == 1U) ? 0U : 1U); - } - - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - count = SDMMC_DATATIMEOUT; - while((response & 0x00000100U) == 0U) - { - if(count == 0U) + /* Check for switch error and violation of the trial number of sending CMD 13 */ + if(errorstate == HAL_MMC_ERROR_NONE) { - hmmc->State = HAL_MMC_STATE_READY; - hmmc->ErrorCode |= HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE; - return HAL_ERROR; - } - count--; + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + count--; + }while(((response & 0x100U) == 0U) && (count != 0U)); - /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ - errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); - if(errorstate != HAL_MMC_ERROR_NONE) - { - hmmc->ErrorCode |= errorstate; + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + /* Configure the SDIO peripheral */ + Init = hmmc->Init; + Init.BusWide = WideMode; + (void)SDIO_Init(hmmc->Instance, Init); + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } } - - /* Get command response */ - response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); } - if(hmmc->ErrorCode != HAL_MMC_ERROR_NONE) + /* Change State */ + hmmc->State = HAL_MMC_STATE_READY; + + if(errorstate != HAL_MMC_ERROR_NONE) { /* Clear all the static flags */ - __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS); - hmmc->State = HAL_MMC_STATE_READY; + __HAL_MMC_CLEAR_FLAG(hmmc, SDMMC_STATIC_FLAGS); + hmmc->ErrorCode |= errorstate; return HAL_ERROR; } - else - { - /* Configure the SDIO peripheral */ - Init.ClockEdge = hmmc->Init.ClockEdge; - Init.ClockBypass = hmmc->Init.ClockBypass; - Init.ClockPowerSave = hmmc->Init.ClockPowerSave; - Init.BusWide = WideMode; - Init.HardwareFlowControl = hmmc->Init.HardwareFlowControl; - Init.ClockDiv = hmmc->Init.ClockDiv; - (void)SDIO_Init(hmmc->Instance, Init); - } - - /* Change State */ - hmmc->State = HAL_MMC_STATE_READY; return HAL_OK; } @@ -2622,7 +2742,8 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) { HAL_MMC_CardCSDTypeDef CSD; uint32_t errorstate; - uint16_t mmc_rca = 1U; + uint16_t mmc_rca = 2U; + MMC_InitTypeDef Init; /* Check the power State */ if(SDIO_GetPowerState(hmmc->Instance) == 0U) @@ -2646,9 +2767,9 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->CID[3U] = SDIO_GetResponse(hmmc->Instance, SDIO_RESP4); } - /* Send CMD3 SET_REL_ADDR with argument 0 */ + /* Send CMD3 SET_REL_ADDR with RCA = 2 (should be greater than 1) */ /* MMC Card publishes its RCA. */ - errorstate = SDMMC_CmdSetRelAdd(hmmc->Instance, &mmc_rca); + errorstate = SDMMC_CmdSetRelAddMmc(hmmc->Instance, mmc_rca); if(errorstate != HAL_MMC_ERROR_NONE) { return errorstate; @@ -2675,21 +2796,43 @@ static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc) /* Get the Card Class */ hmmc->MmcCard.Class = (SDIO_GetResponse(hmmc->Instance, SDIO_RESP2) >> 20U); + /* Select the Card */ + errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + return errorstate; + } + /* Get CSD parameters */ if (HAL_MMC_GetCardCSD(hmmc, &CSD) != HAL_OK) { return hmmc->ErrorCode; } - /* Select the Card */ - errorstate = SDMMC_CmdSelDesel(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); if(errorstate != HAL_MMC_ERROR_NONE) { - return errorstate; + hmmc->ErrorCode |= errorstate; + } + + /* Get Extended CSD parameters */ + if (HAL_MMC_GetCardExtCSD(hmmc, hmmc->Ext_CSD, SDMMC_DATATIMEOUT) != HAL_OK) + { + return hmmc->ErrorCode; + } + + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + hmmc->ErrorCode |= errorstate; } - /* Configure SDIO peripheral interface */ - (void)SDIO_Init(hmmc->Instance, hmmc->Init); + /* Configure the SDIO peripheral */ + Init = hmmc->Init; + Init.BusWide = SDIO_BUS_WIDE_1B; + (void)SDIO_Init(hmmc->Instance, Init); /* All cards are initialized */ return HAL_MMC_ERROR_NONE; @@ -2722,8 +2865,8 @@ static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc) return HAL_MMC_ERROR_INVALID_VOLTRANGE; } - /* SEND CMD1 APP_CMD with MMC_HIGH_VOLTAGE_RANGE(0xC0FF8000) as argument */ - errorstate = SDMMC_CmdOpCondition(hmmc->Instance, eMMC_HIGH_VOLTAGE_RANGE); + /* SEND CMD1 APP_CMD with voltage range as argument */ + errorstate = SDMMC_CmdOpCondition(hmmc->Instance, MMC_VOLTAGE_RANGE); if(errorstate != HAL_MMC_ERROR_NONE) { return HAL_MMC_ERROR_UNSUPPORTED_FEATURE; @@ -2954,6 +3097,93 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) } } +/** + * @brief Update the power class of the device. + * @param hmmc MMC handle + * @param Wide Wide of MMC bus + * @param Speed Speed of the MMC bus + * @retval MMC Card error state + */ +static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide) +{ + uint32_t count; + uint32_t response = 0U; + uint32_t errorstate = HAL_MMC_ERROR_NONE; + uint32_t power_class, supported_pwr_class; + + if((Wide == SDIO_BUS_WIDE_8B) || (Wide == SDIO_BUS_WIDE_4B)) + { + power_class = 0U; /* Default value after power-on or software reset */ + + /* Read the PowerClass field of the Extended CSD register */ + if(MMC_ReadExtCSD(hmmc, &power_class, 187, SDMMC_DATATIMEOUT) != HAL_OK) /* Field POWER_CLASS [187] */ + { + errorstate = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else + { + power_class = ((power_class >> 24U) & 0x000000FFU); + } + + /* Get the supported PowerClass field of the Extended CSD register */ + /* Field PWR_CL_26_xxx [201 or 203] */ + supported_pwr_class = ((hmmc->Ext_CSD[(MMC_EXT_CSD_PWR_CL_26_INDEX/4)] >> MMC_EXT_CSD_PWR_CL_26_POS) & 0x000000FFU); + + if(errorstate == HAL_MMC_ERROR_NONE) + { + if(Wide == SDIO_BUS_WIDE_8B) + { + /* Bit [7:4] : power class for 8-bits bus configuration - Bit [3:0] : power class for 4-bits bus configuration */ + supported_pwr_class = (supported_pwr_class >> 4U); + } + + if ((power_class & 0x0FU) != (supported_pwr_class & 0x0FU)) + { + /* Need to change current power class */ + errorstate = SDMMC_CmdSwitch(hmmc->Instance, (0x03BB0000U | ((supported_pwr_class & 0x0FU) << 8U))); + + if(errorstate == HAL_MMC_ERROR_NONE) + { + /* While card is not ready for data and trial number for sending CMD13 is not exceeded */ + count = SDMMC_MAX_TRIAL; + do + { + errorstate = SDMMC_CmdSendStatus(hmmc->Instance, (uint32_t)(((uint32_t)hmmc->MmcCard.RelCardAdd) << 16U)); + if(errorstate != HAL_MMC_ERROR_NONE) + { + break; + } + + /* Get command response */ + response = SDIO_GetResponse(hmmc->Instance, SDIO_RESP1); + count--; + }while(((response & 0x100U) == 0U) && (count != 0U)); + + /* Check the status after the switch command execution */ + if ((count != 0U) && (errorstate == HAL_MMC_ERROR_NONE)) + { + /* Check the bit SWITCH_ERROR of the device status */ + if ((response & 0x80U) != 0U) + { + errorstate = SDMMC_ERROR_UNSUPPORTED_FEATURE; + } + } + else if (count == 0U) + { + errorstate = SDMMC_ERROR_TIMEOUT; + } + else + { + /* Nothing to do */ + } + } + } + } + } + + return errorstate; +} + /** * @} */ @@ -2969,5 +3199,3 @@ static void MMC_Write_IT(MMC_HandleTypeDef *hmmc) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.h index e65172acd65..30921aaac50 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_mmc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -145,6 +144,8 @@ typedef struct uint32_t CID[4U]; /*!< MMC card identification number table */ + uint32_t Ext_CSD[128]; + #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U) void (* TxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); void (* RxCpltCallback) (struct __MMC_HandleTypeDef *hmmc); @@ -334,10 +335,12 @@ typedef void (*pMMC_CallbackTypeDef) (MMC_HandleTypeDef *hmmc); /** * @brief */ -#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */ -#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */ -#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */ -#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */ +#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< High voltage in byte mode */ +#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< Dual voltage in byte mode */ +#define MMC_LOW_VOLTAGE_RANGE 0x80000080U /*!< Low voltage in byte mode */ +#define EMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< High voltage in sector mode */ +#define EMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< Dual voltage in sector mode */ +#define EMMC_LOW_VOLTAGE_RANGE 0xC0000080U /*!< Low voltage in sector mode */ #define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U /** * @} @@ -636,6 +639,7 @@ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} */ @@ -649,7 +653,7 @@ uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc); * @} */ -/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management +/** @defgroup MMC_Exported_Functions_Group6 Peripheral Abort management * @{ */ HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc); @@ -741,5 +745,3 @@ HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc); #endif /* SDIO */ #endif /* STM32F4xx_HAL_MMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.c index 2bff47fc564..a0b89e621c7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.c @@ -3,53 +3,64 @@ * @file stm32f4xx_hal_nand.c * @author MCD Application Team * @brief NAND HAL module driver. - * This file provides a generic firmware to drive NAND memories mounted + * This file provides a generic firmware to drive NAND memories mounted * as external device. - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] - This driver is a generic layered driver which contains a set of APIs used to - control NAND flash memories. It uses the FMC/FSMC layer functions to interface + This driver is a generic layered driver which contains a set of APIs used to + control NAND flash memories. It uses the FMC/FSMC layer functions to interface with NAND devices. This driver is used as follows: - - (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() + + (+) NAND flash memory configuration sequence using the function HAL_NAND_Init() with control and timing parameters for both common and attribute spaces. - + (+) Read NAND flash memory maker and device IDs using the function - HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef - structure declared by the function caller. - + HAL_NAND_Read_ID(). The read information is stored in the NAND_ID_TypeDef + structure declared by the function caller. + (+) Access NAND flash memory by read/write operations using the functions - HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(), + HAL_NAND_Read_Page_8b()/HAL_NAND_Read_SpareArea_8b(), HAL_NAND_Write_Page_8b()/HAL_NAND_Write_SpareArea_8b(), - HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(), + HAL_NAND_Read_Page_16b()/HAL_NAND_Read_SpareArea_16b(), HAL_NAND_Write_Page_16b()/HAL_NAND_Write_SpareArea_16b() - to read/write page(s)/spare area(s). These functions use specific device - information (Block, page size..) predefined by the user in the HAL_NAND_Info_TypeDef + to read/write page(s)/spare area(s). These functions use specific device + information (Block, page size..) predefined by the user in the NAND_DeviceConfigTypeDef structure. The read/write address information is contained by the Nand_Address_Typedef structure passed as parameter. - + (+) Perform NAND flash Reset chip operation using the function HAL_NAND_Reset(). - + (+) Perform NAND flash erase block operation using the function HAL_NAND_Erase_Block(). - The erase block address information is contained in the Nand_Address_Typedef + The erase block address information is contained in the Nand_Address_Typedef structure passed as parameter. - + (+) Read the NAND flash status operation using the function HAL_NAND_Read_Status(). - + (+) You can also control the NAND device by calling the control APIs HAL_NAND_ECC_Enable()/ HAL_NAND_ECC_Disable() to respectively enable/disable the ECC code correction - feature or the function HAL_NAND_GetECC() to get the ECC correction code. - + feature or the function HAL_NAND_GetECC() to get the ECC correction code. + (+) You can monitor the NAND device HAL state by calling the function - HAL_NAND_GetState() + HAL_NAND_GetState() [..] (@) This driver is a set of generic APIs which handle standard NAND flash operations. - If a NAND flash device contains different operations and/or implementations, + If a NAND flash device contains different operations and/or implementations, it should be implemented separately. *** Callback registration *** @@ -58,25 +69,25 @@ The compilation define USE_HAL_NAND_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_NAND_RegisterCallback() to register a user callback, + Use Functions HAL_NAND_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_NAND_UnRegisterCallback() to reset a callback to the default + Use function HAL_NAND_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : NAND MspInit. (+) MspDeInitCallback : NAND MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET + By default, after the HAL_NAND_Init and if the state is HAL_NAND_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_NAND_Init - and @ref HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_NAND_Init and @ref HAL_NAND_DeInit + reset to the legacy weak (surcharged) functions in the HAL_NAND_Init + and HAL_NAND_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_NAND_Init and HAL_NAND_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -84,8 +95,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_NAND_RegisterCallback before calling @ref HAL_NAND_DeInit - or @ref HAL_NAND_Init function. + using HAL_NAND_RegisterCallback before calling HAL_NAND_DeInit + or HAL_NAND_Init function. When The compilation define USE_HAL_NAND_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -93,78 +104,50 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ - #ifdef HAL_NAND_MODULE_ENABLED -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - -/** @defgroup NAND NAND +/** @defgroup NAND NAND * @brief NAND HAL module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup NAND_Private_Constants NAND Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup NAND_Private_Macros NAND Private Macros - * @{ - */ - -/** - * @} - */ +/* Private Constants ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ + /** @defgroup NAND_Exported_Functions NAND Exported Functions * @{ */ - -/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + +/** @defgroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim ============================================================================== ##### NAND Initialization and de-initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to initialize/de-initialize the NAND memory - + @endverbatim * @{ */ - + /** * @brief Perform NAND memory Initialization sequence * @param hnand pointer to a NAND_HandleTypeDef structure that contains @@ -173,21 +156,22 @@ * @param AttSpace_Timing pointer to Attribute space timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing) { /* Check the NAND handle state */ - if(hnand == NULL) + if (hnand == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - if(hnand->State == HAL_NAND_STATE_RESET) + if (hnand->State == HAL_NAND_STATE_RESET) { /* Allocate lock resource and initialize it */ hnand->Lock = HAL_UNLOCKED; #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if(hnand->MspInitCallback == NULL) + if (hnand->MspInitCallback == NULL) { hnand->MspInitCallback = HAL_NAND_MspInit; } @@ -198,21 +182,25 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT #else /* Initialize the low level hardware (MSP) */ HAL_NAND_MspInit(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ } /* Initialize NAND control Interface */ - FMC_NAND_Init(hnand->Instance, &(hnand->Init)); - - /* Initialize NAND common space timing Interface */ - FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); - - /* Initialize NAND attribute space timing Interface */ - FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); - + (void)FMC_NAND_Init(hnand->Instance, &(hnand->Init)); + + /* Initialize NAND common space timing Interface */ + (void)FMC_NAND_CommonSpace_Timing_Init(hnand->Instance, ComSpace_Timing, hnand->Init.NandBank); + + /* Initialize NAND attribute space timing Interface */ + (void)FMC_NAND_AttributeSpace_Timing_Init(hnand->Instance, AttSpace_Timing, hnand->Init.NandBank); + /* Enable the NAND device */ +#if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) __FMC_NAND_ENABLE(hnand->Instance, hnand->Init.NandBank); - +#else + __FMC_NAND_ENABLE(hnand->Instance); +#endif + /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; @@ -225,10 +213,10 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT * the configuration information for NAND module. * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) +HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) { #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) - if(hnand->MspDeInitCallback == NULL) + if (hnand->MspDeInitCallback == NULL) { hnand->MspDeInitCallback = HAL_NAND_MspDeInit; } @@ -238,10 +226,10 @@ HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand) #else /* Initialize the low level hardware (MSP) */ HAL_NAND_MspDeInit(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Configure the NAND registers with their reset values */ - FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); + (void)FMC_NAND_DeInit(hnand->Instance, hnand->Init.NandBank); /* Reset the NAND controller state */ hnand->State = HAL_NAND_STATE_RESET; @@ -262,9 +250,10 @@ __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnand); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NAND_MspInit could be implemented in the user file - */ + */ } /** @@ -277,9 +266,10 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnand); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NAND_MspDeInit could be implemented in the user file - */ + */ } @@ -288,64 +278,81 @@ __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status -*/ + */ void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand) { /* Check NAND interrupt Rising edge flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE)) + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE)) { /* NAND interrupt callback*/ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Rising edge pending bit */ +#if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_RISING_EDGE); +#else + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_RISING_EDGE); +#endif /* FMC_Bank2_3 || FSMC_Bank2_3 */ } - + /* Check NAND interrupt Level flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL)) { /* NAND interrupt callback*/ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Level pending bit */ +#if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_LEVEL); +#else + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_LEVEL); +#endif /* FMC_Bank2_3 || FSMC_Bank2_3 */ } /* Check NAND interrupt Falling edge flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE)) + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE)) { /* NAND interrupt callback*/ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt Falling edge pending bit */ +#if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FALLING_EDGE); +#else + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FALLING_EDGE); +#endif /* FMC_Bank2_3 || FSMC_Bank2_3 */ } - + /* Check NAND interrupt FIFO empty flag */ - if(__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) + if (__FMC_NAND_GET_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT)) { /* NAND interrupt callback*/ #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) hnand->ItCallback(hnand); #else HAL_NAND_ITCallback(hnand); -#endif +#endif /* (USE_HAL_NAND_REGISTER_CALLBACKS) */ /* Clear NAND interrupt FIFO empty pending bit */ +#if defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) __FMC_NAND_CLEAR_FLAG(hnand->Instance, hnand->Init.NandBank, FMC_FLAG_FEMPT); +#else + __FMC_NAND_CLEAR_FLAG(hnand->Instance, FMC_FLAG_FEMPT); +#endif /* FMC_Bank2_3 || FSMC_Bank2_3 */ } + } /** @@ -358,26 +365,27 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnand); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NAND_ITCallback could be implemented in the user file */ } - + /** * @} */ - -/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions + +/** @defgroup NAND_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions * - @verbatim + @verbatim ============================================================================== ##### NAND Input and Output functions ##### ============================================================================== - [..] - This section provides functions allowing to use and control the NAND + [..] + This section provides functions allowing to use and control the NAND memory - + @endverbatim * @{ */ @@ -391,69 +399,81 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand) */ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID) { - __IO uint32_t data = 0U; - __IO uint32_t data1 = 0U; - uint32_t deviceaddress = 0U; + __IO uint32_t data = 0; + __IO uint32_t data1 = 0; + uint32_t deviceaddress; - /* Process Locked */ - __HAL_LOCK(hnand); - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE1; + return HAL_BUSY; } - else + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE2; - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send Read ID command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - - /* Read the electronic signature from NAND flash */ + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + + /* Send Read ID command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_READID; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; + __DSB(); + + /* Read the electronic signature from NAND flash */ #ifdef FSMC_PCR2_PWID - if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) #else /* FMC_PCR2_PWID is defined */ - if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) + if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) #endif - { - data = *(__IO uint32_t *)deviceaddress; + { + data = *(__IO uint32_t *)deviceaddress; + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); + pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); + } + else + { + data = *(__IO uint32_t *)deviceaddress; + data1 = *((__IO uint32_t *)deviceaddress + 4); + + /* Return the data read */ + pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); + pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); + pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); + pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); + } - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data); - pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data); + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); } else { - data = *(__IO uint32_t *)deviceaddress; - data1 = *((__IO uint32_t *)deviceaddress + 4U); - - /* Return the data read */ - pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data); - pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data); - pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1); - pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1); + return HAL_ERROR; } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - + return HAL_OK; } @@ -465,39 +485,48 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN */ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t deviceaddress; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE1; + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + + /* Send NAND reset command */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); } else { - deviceaddress = NAND_DEVICE2; - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send NAND reset command */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = 0xFF; - - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); + return HAL_ERROR; + } return HAL_OK; @@ -519,138 +548,175 @@ HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceC hnand->Config.PlaneSize = pDeviceConfig->PlaneSize; hnand->Config.PlaneNbr = pDeviceConfig->PlaneNbr; hnand->Config.ExtraCommandEnable = pDeviceConfig->ExtraCommandEnable; - + return HAL_OK; } - + /** * @brief Read Page(s) from NAND memory block (8-bits addressing) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress pointer to NAND address structure * @param pBuffer pointer to destination read buffer - * @param NumPageToRead number of pages to read from block + * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead) -{ - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); - +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead) +{ + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint8_t *buff = pBuffer; + /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE1; + return HAL_BUSY; } - else + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE2; - } + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Page(s) read loop */ - while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* update the buffer size */ - size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); - - /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE1; } - else /* (hnand->Config.PageSize) > 512 */ + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) read loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - - /* Check if an extra command is needed for reading pages */ - if(hnand->Config.ExtraCommandEnable == ENABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + + if (hnand->Config.ExtraCommandEnable == ENABLE) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); } - - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - __DSB(); - } - - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; + + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.PageSize; index++) + { + *buff = *(uint8_t *)deviceaddress; + buff++; + } + + /* Increment read pages number */ + numpagesread++; + + /* Decrement pages to read */ + nbpages--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); } - - /* Increment read pages number */ - numPagesRead++; - - /* Decrement pages to read */ - NumPageToRead--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); return HAL_OK; } @@ -661,143 +727,180 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressT * the configuration information for NAND module. * @param pAddress pointer to NAND address structure * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned - * @param NumPageToRead number of pages to read from block + * @param NumPageToRead number of pages to read from block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead) -{ - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numPagesRead = 0U, nandaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); - +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead) +{ + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpagesread = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToRead; + uint16_t *buff = pBuffer; + /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; + return HAL_BUSY; } - else + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE2; - } + /* Process Locked */ + __HAL_LOCK(hnand); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) read loop */ - while((NumPageToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* update the buffer size */ - size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesRead); - - /* Send read page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; } - else /* (hnand->Config.PageSize) > 512 */ +#else + deviceaddress = NAND_DEVICE; +#endif + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) read loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + /* Send read page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - - if(hnand->Config.ExtraCommandEnable == ENABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); } - - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - } - /* Calculate PageSize */ -#ifdef FSMC_PCR2_PWID + /* Calculate PageSize */ +#if defined(FSMC_PCR2_PWID) if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) -#else /* FMC_PCR2_PWID is defined */ +#else if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) -#endif - { - size = size / 2U; - } - else - { - /* Do nothing */ - /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ - } - - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress; +#endif /* FSMC_PCR2_PWID */ + { + hnand->Config.PageSize = hnand->Config.PageSize / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } + + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.PageSize; index++) + { + *buff = *(uint16_t *)deviceaddress; + buff++; + } + + /* Increment read pages number */ + numpagesread++; + + /* Decrement pages to read */ + nbpages--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); } - - /* Increment read pages number */ - numPagesRead++; - - /* Decrement pages to read */ - NumPageToRead--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - + else + { + return HAL_ERROR; + } + return HAL_OK; } @@ -806,127 +909,162 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_Address * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to source buffer to write - * @param NumPageToWrite number of pages to write to block + * @param pBuffer pointer to source buffer to write + * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + uint8_t *buff = pBuffer; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; - } - else + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE2; + return HAL_BUSY; } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) write loop */ - while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + else if (hnand->State == HAL_NAND_STATE_READY) { - /* update the buffer size */ - size = hnand->Config.PageSize + ((hnand->Config.PageSize) * numPagesWritten); - - /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE1; } - else /* (hnand->Config.PageSize) > 512 */ + else { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) write loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) + { + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } + } + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.PageSize; index++) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + *(__IO uint8_t *)deviceaddress = *buff; + buff++; __DSB(); } - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } + + /* Increment written pages number */ + numpageswritten++; + + /* Decrement pages to write */ + nbpages--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); } - - /* Increment written pages number */ - numPagesWritten++; - - /* Decrement pages to write */ - NumPageToWrite--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - + else + { + return HAL_ERROR; + } + return HAL_OK; } @@ -936,276 +1074,353 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_Address * the configuration information for NAND module. * @param pAddress pointer to NAND address structure * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned - * @param NumPageToWrite number of pages to write to block + * @param NumPageToWrite number of pages to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite) +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numPagesWritten = 0U, nandaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numpageswritten = 0U; + uint32_t nandaddress; + uint32_t nbpages = NumPageToWrite; + uint16_t *buff = pBuffer; /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; - } - else + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE2; + return HAL_BUSY; } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Page(s) write loop */ - while((NumPageToWrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + else if (hnand->State == HAL_NAND_STATE_READY) { - /* update the buffer size */ - size = (hnand->Config.PageSize) + ((hnand->Config.PageSize) * numPagesWritten); - - /* Send write page command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - __DSB(); - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - __DSB(); + /* Process Locked */ + __HAL_LOCK(hnand); - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; } - else /* (hnand->Config.PageSize) > 512 */ +#else + deviceaddress = NAND_DEVICE; +#endif + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Page(s) write loop */ + while ((nbpages != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) { - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + /* Send write page command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - } - /* Calculate PageSize */ -#ifdef FSMC_PCR2_PWID + /* Calculate PageSize */ +#if defined(FSMC_PCR2_PWID) if (hnand->Init.MemoryDataWidth == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) -#else /* FMC_PCR2_PWID is defined */ +#else if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8) -#endif - { - size = size / 2U; - } - else - { - /* Do nothing */ - /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++; - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) +#endif /* FSMC_PCR2_PWID */ + { + hnand->Config.PageSize = hnand->Config.PageSize / 2U; + } + else + { + /* Do nothing */ + /* Keep the same PageSize for FMC_NAND_MEM_BUS_WIDTH_16*/ + } + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.PageSize; index++) + { + *(__IO uint16_t *)deviceaddress = *buff; + buff++; + __DSB(); + } + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; - } - } - - /* Increment written pages number */ - numPagesWritten++; - - /* Decrement pages to write */ - NumPageToWrite--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Increment written pages number */ + numpageswritten++; + + /* Decrement pages to write */ + nbpages--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - + else + { + return HAL_ERROR; + } + return HAL_OK; } /** - * @brief Read Spare area(s) from NAND memory + * @brief Read Spare area(s) from NAND memory (8-bits addressing) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to source buffer to write - * @param NumSpareAreaToRead Number of spare area to read + * @param pBuffer pointer to source buffer to write + * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead) + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumSpareAreaToRead) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); - + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint8_t *buff = pBuffer; + /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE1; + return HAL_BUSY; } - else + else if (hnand->State == HAL_NAND_STATE_READY) { - deviceaddress = NAND_DEVICE2; - } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Column in page address */ - columnaddress = COLUMN_ADDRESS(hnand); - - /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) - { - /* update the buffer size */ - size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); - - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE1; } - else /* (hnand->Config.PageSize) > 512 */ + else { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = COLUMN_ADDRESS(hnand); + + /* Spare area(s) read loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - } - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; - - if(hnand->Config.ExtraCommandEnable == ENABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); + + if (hnand->Config.ExtraCommandEnable == ENABLE) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); } - - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - } - - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint8_t *)pBuffer++ = *(uint8_t *)deviceaddress; + + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) + { + *buff = *(uint8_t *)deviceaddress; + buff++; + } + + /* Increment read spare areas number */ + numsparearearead++; + + /* Decrement spare areas to read */ + nbspare--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); } - - /* Increment read spare areas number */ - numSpareAreaRead++; - - /* Decrement spare areas to read */ - NumSpareAreaToRead--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - return HAL_OK; + return HAL_OK; } /** @@ -1214,265 +1429,347 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Add * the configuration information for NAND module. * @param pAddress pointer to NAND address structure * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. - * @param NumSpareAreaToRead Number of spare area to read + * @param NumSpareAreaToRead Number of spare area to read * @retval HAL status -*/ -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead) + */ +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numSpareAreaRead = 0U, nandaddress = 0U, columnaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); - + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numsparearearead = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaToRead; + uint16_t *buff = pBuffer; + /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE1; - } - else - { - deviceaddress = NAND_DEVICE2; + return HAL_BUSY; } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Column in page address */ - columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); - - /* Spare area(s) read loop */ - while((NumSpareAreaToRead != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + else if (hnand->State == HAL_NAND_STATE_READY) { - /* update the buffer size */ - size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaRead); + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE1; } - else /* (hnand->Config.PageSize) > 512 */ + else { - /* Send read spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); + + /* Spare area(s) read loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + /* Send read spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - } - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1; + __DSB(); - if(hnand->Config.ExtraCommandEnable == ENABLE) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + if (hnand->Config.ExtraCommandEnable == ENABLE) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } + + /* Go back to read mode */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); + __DSB(); } - - /* Go back to read mode */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = ((uint8_t)0x00); - } - - /* Get Data into Buffer */ - for(; index < size; index++) - { - *(uint16_t *)pBuffer++ = *(uint16_t *)deviceaddress; + + /* Get Data into Buffer */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) + { + *buff = *(uint16_t *)deviceaddress; + buff++; + } + + /* Increment read spare areas number */ + numsparearearead++; + + /* Decrement spare areas to read */ + nbspare--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); } - - /* Increment read spare areas number */ - numSpareAreaRead++; - - /* Decrement spare areas to read */ - NumSpareAreaToRead--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - return HAL_OK; + return HAL_OK; } /** - * @brief Write Spare area(s) to NAND memory + * @brief Write Spare area(s) to NAND memory (8-bits addressing) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to source buffer to write + * @param pBuffer pointer to source buffer to write * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U; + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + uint8_t *buff = pBuffer; - /* Process Locked */ - __HAL_LOCK(hnand); - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; - } - else + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE2; + return HAL_BUSY; } - - /* Update the FMC_NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Page address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Column in page address */ - columnaddress = COLUMN_ADDRESS(hnand); - - /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + else if (hnand->State == HAL_NAND_STATE_READY) { - /* update the buffer size */ - size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); + /* Process Locked */ + __HAL_LOCK(hnand); - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + + /* Page address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = COLUMN_ADDRESS(hnand); + + /* Spare area(s) write loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - } - else /* (hnand->Config.PageSize) > 512 */ - { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + *(__IO uint8_t *)deviceaddress = *buff; + buff++; + __DSB(); } - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) { - return HAL_TIMEOUT; + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } } + + /* Increment written spare areas number */ + numspareareawritten++; + + /* Decrement spare areas to write */ + nbspare--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); } - /* Increment written spare areas number */ - numSpareAreaWritten++; - - /* Decrement spare areas to write */ - NumSpareAreaTowrite--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } - /* Process unlocked */ - __HAL_UNLOCK(hnand); - return HAL_OK; } @@ -1481,135 +1778,177 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_Ad * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress pointer to NAND address structure - * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. + * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned. * @param NumSpareAreaTowrite number of spare areas to write to block * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite) { - __IO uint32_t index = 0U; - uint32_t tickstart = 0U; - uint32_t deviceaddress = 0U, size = 0U, numSpareAreaWritten = 0U, nandaddress = 0U, columnaddress = 0U; + uint32_t index; + uint32_t tickstart; + uint32_t deviceaddress; + uint32_t numspareareawritten = 0U; + uint32_t nandaddress; + uint32_t columnaddress; + uint32_t nbspare = NumSpareAreaTowrite; + uint16_t *buff = pBuffer; - /* Process Locked */ - __HAL_LOCK(hnand); - /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; - } - else + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE2; + return HAL_BUSY; } - - /* Update the FMC_NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* NAND raw address calculation */ - nandaddress = ARRAY_ADDRESS(pAddress, hnand); - - /* Column in page address */ - columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); - - /* Spare area(s) write loop */ - while((NumSpareAreaTowrite != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + else if (hnand->State == HAL_NAND_STATE_READY) { - /* update the buffer size */ - size = (hnand->Config.SpareAreaSize) + ((hnand->Config.SpareAreaSize) * numSpareAreaWritten); + /* Process Locked */ + __HAL_LOCK(hnand); - /* Cards with page size <= 512 bytes */ - if((hnand->Config.PageSize) <= 512U) + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ - { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); - } + deviceaddress = NAND_DEVICE1; } - else /* (hnand->Config.PageSize) > 512 */ + else { - /* Send write Spare area command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; - - if (((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) <= 65535U) + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + + /* NAND raw address calculation */ + nandaddress = ARRAY_ADDRESS(pAddress, hnand); + + /* Column in page address */ + columnaddress = (uint32_t)(COLUMN_ADDRESS(hnand)); + + /* Spare area(s) write loop */ + while ((nbspare != 0U) && (nandaddress < ((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)))) + { + /* Cards with page size <= 512 bytes */ + if ((hnand->Config.PageSize) <= 512U) { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00U; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + else /* (hnand->Config.PageSize) > 512 */ { - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + /* Send write Spare area command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_A; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; + __DSB(); + + if (((hnand->Config.BlockSize) * (hnand->Config.BlockNbr)) <= 65535U) + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + } + else /* ((hnand->Config.BlockSize)*(hnand->Config.BlockNbr)) > 65535 */ + { + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_1ST_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = COLUMN_2ND_CYCLE(columnaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandaddress); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandaddress); + __DSB(); + } } - } - - /* Write data to memory */ - for(; index < size; index++) - { - *(__IO uint16_t *)deviceaddress = *(uint16_t *)pBuffer++; - } - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) - { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + + /* Write data to memory */ + for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - return HAL_TIMEOUT; + *(__IO uint16_t *)deviceaddress = *buff; + buff++; + __DSB(); } - } - /* Increment written spare areas number */ - numSpareAreaWritten++; - - /* Decrement spare areas to write */ - NumSpareAreaTowrite--; - - /* Increment the NAND address */ - nandaddress = (uint32_t)(nandaddress + 1U); - } + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; + __DSB(); - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; + /* Get tick */ + tickstart = HAL_GetTick(); - /* Process unlocked */ - __HAL_UNLOCK(hnand); + /* Read status until NAND is ready */ + while (HAL_NAND_Read_Status(hnand) != NAND_READY) + { + if ((HAL_GetTick() - tickstart) > NAND_WRITE_TIMEOUT) + { + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + + return HAL_TIMEOUT; + } + } + + /* Increment written spare areas number */ + numspareareawritten++; + + /* Decrement spare areas to write */ + nbspare--; + + /* Increment the NAND address */ + nandaddress = (uint32_t)(nandaddress + 1U); + } + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else + { + return HAL_ERROR; + } - return HAL_OK; + return HAL_OK; } /** - * @brief NAND memory Block erase + * @brief NAND memory Block erase * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress pointer to NAND address structure @@ -1617,102 +1956,60 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_A */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { - uint32_t deviceaddress = 0U; - uint32_t tickstart = 0U; - - /* Process Locked */ - __HAL_LOCK(hnand); - + uint32_t deviceaddress; + /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; - } - else + if (hnand->State == HAL_NAND_STATE_BUSY) { - deviceaddress = NAND_DEVICE2; + return HAL_BUSY; } - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Send Erase block command sequence */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; - - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); - - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; - - /* Update the NAND controller state */ - hnand->State = HAL_NAND_STATE_READY; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Read status until NAND is ready */ - while(HAL_NAND_Read_Status(hnand) != NAND_READY) + else if (hnand->State == HAL_NAND_STATE_READY) { - if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) + /* Process Locked */ + __HAL_LOCK(hnand); + + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) { - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_TIMEOUT; - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hnand); - - return HAL_OK; -} + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif -/** - * @brief NAND memory read status - * @param hnand pointer to a NAND_HandleTypeDef structure that contains - * the configuration information for NAND module. - * @retval NAND status - */ -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) -{ - uint32_t data = 0U; - uint32_t deviceaddress = 0U; - - /* Identify the device address */ - if(hnand->Init.NandBank == FMC_NAND_BANK2) - { - deviceaddress = NAND_DEVICE1; - } - else - { - deviceaddress = NAND_DEVICE2; - } + /* Send Erase block command sequence */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); + *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); + __DSB(); - /* Send Read status operation command */ - *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; - - /* Read status register data */ - data = *(__IO uint8_t *)deviceaddress; + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; + __DSB(); - /* Return the status */ - if((data & NAND_ERROR) == NAND_ERROR) - { - return NAND_ERROR; - } - else if((data & NAND_READY) == NAND_READY) + /* Update the NAND controller state */ + hnand->State = HAL_NAND_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnand); + } + else { - return NAND_READY; + return HAL_ERROR; } - return NAND_BUSY; + return HAL_OK; } /** @@ -1727,28 +2024,28 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { uint32_t status = NAND_VALID_ADDRESS; - + /* Increment page address */ pAddress->Page++; /* Check NAND address is valid */ - if(pAddress->Page == hnand->Config.BlockSize) + if (pAddress->Page == hnand->Config.BlockSize) { - pAddress->Page = 0U; + pAddress->Page = 0; pAddress->Block++; - - if(pAddress->Block == hnand->Config.PlaneSize) + + if (pAddress->Block == hnand->Config.PlaneSize) { - pAddress->Block = 0U; + pAddress->Block = 0; pAddress->Plane++; - if(pAddress->Plane == (hnand->Config.PlaneNbr)) + if (pAddress->Plane == (hnand->Config.PlaneNbr)) { status = NAND_INVALID_ADDRESS; } } - } - + } + return (status); } @@ -1765,11 +2062,12 @@ uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pA * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -1777,39 +2075,39 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND /* Process locked */ __HAL_LOCK(hnand); - if(hnand->State == HAL_NAND_STATE_READY) + if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hnand->State == HAL_NAND_STATE_RESET) + else if (hnand->State == HAL_NAND_STATE_RESET) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = pCallback; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = pCallback; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1834,46 +2132,46 @@ HAL_StatusTypeDef HAL_NAND_RegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND * @arg @ref HAL_NAND_IT_CB_ID NAND IT callback ID * @retval status */ -HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hnand); - if(hnand->State == HAL_NAND_STATE_READY) + if (hnand->State == HAL_NAND_STATE_READY) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - case HAL_NAND_IT_CB_ID : - hnand->ItCallback = HAL_NAND_ITCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + case HAL_NAND_IT_CB_ID : + hnand->ItCallback = HAL_NAND_ITCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hnand->State == HAL_NAND_STATE_RESET) + else if (hnand->State == HAL_NAND_STATE_RESET) { switch (CallbackId) { - case HAL_NAND_MSP_INIT_CB_ID : - hnand->MspInitCallback = HAL_NAND_MspInit; - break; - case HAL_NAND_MSP_DEINIT_CB_ID : - hnand->MspDeInitCallback = HAL_NAND_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NAND_MSP_INIT_CB_ID : + hnand->MspInitCallback = HAL_NAND_MspInit; + break; + case HAL_NAND_MSP_DEINIT_CB_ID : + hnand->MspDeInitCallback = HAL_NAND_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1886,51 +2184,57 @@ HAL_StatusTypeDef HAL_NAND_UnRegisterCallback (NAND_HandleTypeDef *hnand, HAL_NA __HAL_UNLOCK(hnand); return status; } -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} */ -/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim +/** @defgroup NAND_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim ============================================================================== ##### NAND Control functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to control dynamically the NAND interface. @endverbatim * @{ - */ + */ + - /** * @brief Enables dynamically NAND ECC feature. * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) { /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Enable ECC feature */ + (void)FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); + + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_READY; + } + else + { + return HAL_ERROR; } - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Enable ECC feature */ - FMC_NAND_ECC_Enable(hnand->Instance, hnand->Init.NandBank); - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; - return HAL_OK; } @@ -1939,77 +2243,89 @@ HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand) * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand) { /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_BUSY; - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Disable ECC feature */ - FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; - - return HAL_OK; + /* Disable ECC feature */ + (void)FMC_NAND_ECC_Disable(hnand->Instance, hnand->Init.NandBank); + + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; } /** * @brief Disables dynamically NAND ECC feature. * @param hnand pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. - * @param ECCval pointer to ECC value - * @param Timeout maximum timeout to wait + * @param ECCval pointer to ECC value + * @param Timeout maximum timeout to wait * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout) { - HAL_StatusTypeDef status = HAL_OK; - + HAL_StatusTypeDef status; + /* Check the NAND controller state */ - if(hnand->State == HAL_NAND_STATE_BUSY) + if (hnand->State == HAL_NAND_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; + } + else if (hnand->State == HAL_NAND_STATE_READY) + { + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_BUSY; + + /* Get NAND ECC value */ + status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); + + /* Update the NAND state */ + hnand->State = HAL_NAND_STATE_READY; + } + else + { + return HAL_ERROR; } - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_BUSY; - - /* Get NAND ECC value */ - status = FMC_NAND_GetECC(hnand->Instance, ECCval, hnand->Init.NandBank, Timeout); - - /* Update the NAND state */ - hnand->State = HAL_NAND_STATE_READY; - return status; + return status; } /** * @} */ - - -/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim + + +/** @defgroup NAND_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim ============================================================================== ##### NAND State functions ##### - ============================================================================== + ============================================================================== [..] - This subsection permits to get in run-time the status of the NAND controller + This subsection permits to get in run-time the status of the NAND controller and the data flow. @endverbatim * @{ */ - + /** * @brief return the NAND state * @param hnand pointer to a NAND_HandleTypeDef structure that contains @@ -2021,9 +2337,56 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) return hnand->State; } +/** + * @brief NAND memory read status + * @param hnand pointer to a NAND_HandleTypeDef structure that contains + * the configuration information for NAND module. + * @retval NAND status + */ +uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand) +{ + uint32_t data; + uint32_t deviceaddress; + UNUSED(hnand); + + /* Identify the device address */ +#if defined(FMC_Bank2_3) + if (hnand->Init.NandBank == FMC_NAND_BANK2) + { + deviceaddress = NAND_DEVICE1; + } + else + { + deviceaddress = NAND_DEVICE2; + } +#else + deviceaddress = NAND_DEVICE; +#endif + + /* Send Read status operation command */ + *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_STATUS; + + /* Read status register data */ + data = *(__IO uint8_t *)deviceaddress; + + /* Return the status */ + if ((data & NAND_ERROR) == NAND_ERROR) + { + return NAND_ERROR; + } + else if ((data & NAND_READY) == NAND_READY) + { + return NAND_READY; + } + else + { + return NAND_BUSY; + } +} + /** * @} - */ + */ /** * @} @@ -2033,13 +2396,10 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ - STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx || STM32F469xx || STM32F479xx */ #endif /* HAL_NAND_MODULE_ENABLED */ /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.h index e6aaabbb5d3..26f650256f3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nand.h @@ -6,35 +6,32 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_NAND_H -#define __STM32F4xx_HAL_NAND_H +#ifndef STM32F4xx_HAL_NAND_H +#define STM32F4xx_HAL_NAND_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ - STM32F479xx */ +/* Includes ------------------------------------------------------------------*/ +#if defined(FSMC_Bank2_3) +#include "stm32f4xx_ll_fsmc.h" +#else +#include "stm32f4xx_ll_fmc.h" +#endif /* FSMC_Bank2_3 */ /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -42,11 +39,7 @@ /** @addtogroup NAND * @{ - */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) + */ /* Exported typedef ----------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ @@ -54,7 +47,7 @@ * @{ */ -/** +/** * @brief HAL NAND State structures definition */ typedef enum @@ -63,65 +56,65 @@ typedef enum HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ -}HAL_NAND_StateTypeDef; - -/** +} HAL_NAND_StateTypeDef; + +/** * @brief NAND Memory electronic signature Structure definition */ typedef struct { /*State = HAL_NAND_STATE_RESET) -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} @@ -196,14 +189,14 @@ typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); /** @addtogroup NAND_Exported_Functions NAND Exported Functions * @{ */ - -/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions + +/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions * @{ */ /* Initialization/de-initialization functions ********************************/ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); +HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, + FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); @@ -218,40 +211,48 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); /** * @} */ - -/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions + +/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions * @{ */ /* IO operation functions ****************************************************/ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); - -HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); -HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); -HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); -HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); +HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); + +HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToRead); +HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, + uint32_t NumPageToWrite); +HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaToRead); +HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, + uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); -uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) /* NAND callback registering/unregistering */ -HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, + pNAND_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ /** * @} */ -/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions +/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions * @{ */ @@ -263,12 +264,13 @@ HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, /** * @} */ - -/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions + +/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions * @{ */ /* NAND State functions *******************************************************/ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); +uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** * @} */ @@ -276,19 +278,23 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); /** * @} */ - + /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /** @defgroup NAND_Private_Constants NAND Private Constants * @{ */ -#define NAND_DEVICE1 0x70000000U -#define NAND_DEVICE2 0x80000000U -#define NAND_WRITE_TIMEOUT 0x01000000U +#if defined(FMC_Bank2_3) +#define NAND_DEVICE1 0x70000000UL +#define NAND_DEVICE2 0x80000000UL +#else +#define NAND_DEVICE 0x80000000UL +#endif +#define NAND_WRITE_TIMEOUT 0x01000000UL -#define CMD_AREA ((uint32_t)(1U<<16U)) /* A16 = CLE high */ -#define ADDR_AREA ((uint32_t)(1U<<17U)) /* A17 = ALE high */ +#define CMD_AREA (1UL<<16U) /* A16 = CLE high */ +#define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ #define NAND_CMD_AREA_A ((uint8_t)0x00) #define NAND_CMD_AREA_B ((uint8_t)0x01) @@ -305,12 +311,12 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); #define NAND_CMD_RESET ((uint8_t)0xFF) /* NAND memory status */ -#define NAND_VALID_ADDRESS 0x00000100U -#define NAND_INVALID_ADDRESS 0x00000200U -#define NAND_TIMEOUT_ERROR 0x00000400U -#define NAND_BUSY 0x00000000U -#define NAND_ERROR 0x00000001U -#define NAND_READY 0x00000040U +#define NAND_VALID_ADDRESS 0x00000100UL +#define NAND_INVALID_ADDRESS 0x00000200UL +#define NAND_TIMEOUT_ERROR 0x00000400UL +#define NAND_BUSY 0x00000000UL +#define NAND_ERROR 0x00000001UL +#define NAND_READY 0x00000040UL /** * @} */ @@ -323,11 +329,14 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); /** * @brief NAND memory address computation. * @param __ADDRESS__ NAND memory address. - * @param __HANDLE__ NAND handle. + * @param __HANDLE__ NAND handle. * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ - (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) + (((__ADDRESS__)->Block + \ + (((__ADDRESS__)->Plane) * \ + ((__HANDLE__)->Config.PlaneSize))) * \ + ((__HANDLE__)->Config.BlockSize))) /** * @brief NAND memory Column address computation. @@ -351,31 +360,29 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); * @param __ADDRESS__ NAND memory address. * @retval NAND Column address cycling value. */ -#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ +#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ - STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx || STM32F469xx || STM32F479xx */ - + /** * @} */ + /** * @} - */ + */ /** * @} - */ + */ + +#endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */ #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_NAND_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_NAND_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.c index 34a009cafb8..0a820448660 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.c @@ -3,50 +3,61 @@ * @file stm32f4xx_hal_nor.c * @author MCD Application Team * @brief NOR HAL module driver. - * This file provides a generic firmware to drive NOR memories mounted + * This file provides a generic firmware to drive NOR memories mounted * as external device. - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] - This driver is a generic layered driver which contains a set of APIs used to - control NOR flash memories. It uses the FMC/FSMC layer functions to interface + This driver is a generic layered driver which contains a set of APIs used to + control NOR flash memories. It uses the FMC/FSMC layer functions to interface with NOR devices. This driver is used as follows: - - (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() + + (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() with control and timing parameters for both normal and extended mode. - + (+) Read NOR flash memory manufacturer code and device IDs using the function - HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef - structure declared by the function caller. - + HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef + structure declared by the function caller. + (+) Access NOR flash memory by read/write data unit operations using the functions HAL_NOR_Read(), HAL_NOR_Program(). - - (+) Perform NOR flash erase block/chip operations using the functions + + (+) Perform NOR flash erase block/chip operations using the functions HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip(). - + (+) Read the NOR flash CFI (common flash interface) IDs using the function HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef structure declared by the function caller. - + (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/ - HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation - + HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation + (+) You can monitor the NOR device HAL state by calling the function - HAL_NOR_GetState() + HAL_NOR_GetState() [..] (@) This driver is a set of generic APIs which handle standard NOR flash operations. - If a NOR flash device contains different operations and/or implementations, + If a NOR flash device contains different operations and/or implementations, it should be implemented separately. *** NOR HAL driver macros list *** - ============================================= + ============================================= [..] Below the list of most used macros in NOR HAL driver. - + (+) NOR_WRITE : NOR memory write data to specified address *** Callback registration *** @@ -55,25 +66,25 @@ The compilation define USE_HAL_NOR_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback, + Use Functions HAL_NOR_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default + Use function HAL_NOR_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : NOR MspInit. (+) MspDeInitCallback : NOR MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET + By default, after the HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init - and @ref HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit + reset to the legacy weak (surcharged) functions in the HAL_NOR_Init + and HAL_NOR_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_NOR_Init and HAL_NOR_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -81,8 +92,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit - or @ref HAL_NOR_Init function. + using HAL_NOR_RegisterCallback before calling HAL_NOR_DeInit + or HAL_NOR_Init function. When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -90,38 +101,27 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(FMC_Bank1) || defined(FSMC_Bank1) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#ifdef HAL_NOR_MODULE_ENABLED + /** @defgroup NOR NOR * @brief NOR driver modules * @{ */ -#ifdef HAL_NOR_MODULE_ENABLED -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ - + /** @defgroup NOR_Private_Defines NOR Private Defines * @{ */ @@ -151,14 +151,40 @@ #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM (uint8_t)0x29 #define NOR_CMD_DATA_BLOCK_ERASE (uint8_t)0x30 +#define NOR_CMD_READ_ARRAY (uint16_t)0x00FF +#define NOR_CMD_WORD_PROGRAM (uint16_t)0x0040 +#define NOR_CMD_BUFFERED_PROGRAM (uint16_t)0x00E8 +#define NOR_CMD_CONFIRM (uint16_t)0x00D0 +#define NOR_CMD_BLOCK_ERASE (uint16_t)0x0020 +#define NOR_CMD_BLOCK_UNLOCK (uint16_t)0x0060 +#define NOR_CMD_READ_STATUS_REG (uint16_t)0x0070 +#define NOR_CMD_CLEAR_STATUS_REG (uint16_t)0x0050 + /* Mask on NOR STATUS REGISTER */ +#define NOR_MASK_STATUS_DQ4 (uint16_t)0x0010 #define NOR_MASK_STATUS_DQ5 (uint16_t)0x0020 #define NOR_MASK_STATUS_DQ6 (uint16_t)0x0040 +#define NOR_MASK_STATUS_DQ7 (uint16_t)0x0080 + +/* Address of the primary command set */ +#define NOR_ADDRESS_COMMAND_SET (uint16_t)0x0013 + +/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */ +#define NOR_INTEL_SHARP_EXT_COMMAND_SET (uint16_t)0x0001 /* Supported in this driver */ +#define NOR_AMD_FUJITSU_COMMAND_SET (uint16_t)0x0002 /* Supported in this driver */ +#define NOR_INTEL_STANDARD_COMMAND_SET (uint16_t)0x0003 /* Not Supported in this driver */ +#define NOR_AMD_FUJITSU_EXT_COMMAND_SET (uint16_t)0x0004 /* Not Supported in this driver */ +#define NOR_WINDBOND_STANDARD_COMMAND_SET (uint16_t)0x0006 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_STANDARD_COMMAND_SET (uint16_t)0x0100 /* Not Supported in this driver */ +#define NOR_MITSUBISHI_EXT_COMMAND_SET (uint16_t)0x0101 /* Not Supported in this driver */ +#define NOR_PAGE_WRITE_COMMAND_SET (uint16_t)0x0102 /* Not Supported in this driver */ +#define NOR_INTEL_PERFORMANCE_COMMAND_SET (uint16_t)0x0200 /* Not Supported in this driver */ +#define NOR_INTEL_DATA_COMMAND_SET (uint16_t)0x0210 /* Not Supported in this driver */ /** * @} */ - + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /** @defgroup NOR_Private_Variables NOR Private Variables @@ -177,44 +203,48 @@ static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B; * @{ */ -/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim ============================================================================== ##### NOR Initialization and de_initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to initialize/de-initialize the NOR memory - + @endverbatim * @{ */ - + /** * @brief Perform the NOR memory Initialization sequence * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Timing pointer to NOR control timing structure - * @param ExtTiming pointer to NOR extended mode timing structure + * @param Timing pointer to NOR control timing structure + * @param ExtTiming pointer to NOR extended mode timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming) { + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; + /* Check the NOR handle parameter */ - if(hnor == NULL) + if (hnor == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - - if(hnor->State == HAL_NOR_STATE_RESET) + + if (hnor->State == HAL_NOR_STATE_RESET) { /* Allocate lock resource and initialize it */ hnor->Lock = HAL_UNLOCKED; #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if(hnor->MspInitCallback == NULL) + if (hnor->MspInitCallback == NULL) { hnor->MspInitCallback = HAL_NOR_MspInit; } @@ -226,15 +256,15 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe HAL_NOR_MspInit(hnor); #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ } - + /* Initialize NOR control Interface */ - FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); + (void)FMC_NORSRAM_Init(hnor->Instance, &(hnor->Init)); /* Initialize NOR timing Interface */ - FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); + (void)FMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); /* Initialize NOR extended mode timing Interface */ - FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); + (void)FMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode); /* Enable the NORSRAM device */ __FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank); @@ -249,10 +279,44 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe uwNORMemoryDataWidth = NOR_MEMORY_16B; } - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - return HAL_OK; + /* Initialize the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + if (hnor->Init.WriteOperation == FMC_WRITE_OPERATION_DISABLE) + { + (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_PROTECTED; + } + else + { + /* Get the value of the command set */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET); + + status = HAL_NOR_ReturnToReadMode(hnor); + } + + return status; } /** @@ -261,10 +325,10 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe * the configuration information for NOR module. * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) +HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) { #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - if(hnor->MspDeInitCallback == NULL) + if (hnor->MspDeInitCallback == NULL) { hnor->MspDeInitCallback = HAL_NOR_MspDeInit; } @@ -277,9 +341,9 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor) #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ /* Configure the NOR registers with their reset values */ - FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); - - /* Update the NOR controller state */ + (void)FMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank); + + /* Reset the NOR controller state */ hnor->State = HAL_NOR_STATE_RESET; /* Release Lock */ @@ -298,9 +362,10 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnor); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NOR_MspInit could be implemented in the user file - */ + */ } /** @@ -313,9 +378,10 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor) { /* Prevent unused argument(s) compilation warning */ UNUSED(hnor); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NOR_MspDeInit could be implemented in the user file - */ + */ } /** @@ -330,30 +396,30 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) /* Prevent unused argument(s) compilation warning */ UNUSED(hnor); UNUSED(Timeout); - + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_NOR_MspWait could be implemented in the user file - */ + */ } - + /** * @} */ -/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions +/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions * - @verbatim + @verbatim ============================================================================== ##### NOR Input and Output functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to use and control the NOR memory - + @endverbatim * @{ */ - + /** * @brief Read NOR flash IDs * @param hnor pointer to a NOR_HandleTypeDef structure that contains @@ -363,56 +429,87 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout) */ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); - + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; + /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + else if (state == HAL_NOR_STATE_PROTECTED) { - deviceaddress = NOR_MEMORY_ADRESS1; + return HAL_ERROR; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + else if (state == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS2; + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send read ID command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Read the NOR IDs */ + pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); + pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE1_ADDR); + pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE2_ADDR); + pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, + DEVICE_CODE3_ADDR); + } + + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_ERROR; } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read ID command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT); - - /* Read the NOR IDs */ - pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS); - pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR); - pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR); - pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + + return status; } /** @@ -423,487 +520,681 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I */ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); - + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; + /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + else if (state == HAL_NOR_STATE_PROTECTED) { - deviceaddress = NOR_MEMORY_ADRESS1; + return HAL_ERROR; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + else if (state == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS2; + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_ERROR; } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET); - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + return status; } /** - * @brief Read data from NOR memory + * @brief Read data from NOR memory * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @param pAddress pointer to Device address - * @param pData pointer to read data + * @param pData pointer to read data * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); - + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; + /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + else if (state == HAL_NOR_STATE_PROTECTED) { - deviceaddress = NOR_MEMORY_ADRESS1; + return HAL_ERROR; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + else if (state == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS2; + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send read data command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Read the data */ + *pData = (uint16_t)(*(__IO uint32_t *)pAddress); + } + + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_ERROR; } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); - - /* Read the data */ - *pData = *(__IO uint32_t *)(uint32_t)pAddress; - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + + return status; } /** - * @brief Program data to NOR memory + * @brief Program data to NOR memory * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. * @param pAddress Device address - * @param pData pointer to the data to write + * @param pData pointer to the data to write * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); - + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; + /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + if (hnor->State == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS1; + return HAL_BUSY; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + else if (hnor->State == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS2; + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send program data command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Write the data */ + NOR_WRITE(pAddress, *pData); + } + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_ERROR; } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send program data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM); - - /* Write the data */ - NOR_WRITE(pAddress, *pData); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + + return status; } /** * @brief Reads a half-word buffer from the NOR memory. * @param hnor pointer to the NOR handle * @param uwAddress NOR memory internal address to read from. - * @param pData pointer to the buffer that receives the data read from the + * @param pData pointer to the buffer that receives the data read from the * NOR memory. * @param uwBufferSize number of Half word to read. * @retval HAL status */ -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); - + uint32_t deviceaddress; + uint32_t size = uwBufferSize; + uint32_t address = uwAddress; + uint16_t *data = pData; + HAL_NOR_StateTypeDef state; + HAL_StatusTypeDef status = HAL_OK; + /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + else if (state == HAL_NOR_STATE_PROTECTED) { - deviceaddress = NOR_MEMORY_ADRESS1; + return HAL_ERROR; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + else if (state == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS2; + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send read data command */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Read buffer */ + while (size > 0U) + { + *data = *(__IO uint16_t *)address; + data++; + address += 2U; + size--; + } + } + + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_ERROR; } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read data command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET); - - /* Read buffer */ - while( uwBufferSize > 0U) - { - *pData++ = *(__IO uint16_t *)uwAddress; - uwAddress += 2U; - uwBufferSize--; - } - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + + return status; } /** - * @brief Writes a half-word buffer to the NOR memory. This function must be used - only with S29GL128P NOR memory. + * @brief Writes a half-word buffer to the NOR memory. This function must be used + only with S29GL128P NOR memory. * @param hnor pointer to the NOR handle - * @param uwAddress NOR memory internal start write address - * @param pData pointer to source data buffer. + * @param uwAddress NOR memory internal start write address + * @param pData pointer to source data buffer. * @param uwBufferSize Size of the buffer to write * @retval HAL status - */ -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize) + */ +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize) { - uint16_t * p_currentaddress = (uint16_t *)NULL; - uint16_t * p_endaddress = (uint16_t *)NULL; - uint32_t lastloadedaddress = 0U, deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); - + uint16_t *p_currentaddress; + const uint16_t *p_endaddress; + uint16_t *data = pData; + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; + /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + if (hnor->State == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS1; + return HAL_BUSY; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + else if (hnor->State == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Initialize variables */ + p_currentaddress = (uint16_t *)(deviceaddress + uwAddress); + p_endaddress = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U))); + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + /* Issue unlock command sequence */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + /* Write Buffer Load Command */ + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM); + NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U)); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + if (status != HAL_ERROR) + { + /* Load Data into NOR Buffer */ + while (p_currentaddress <= p_endaddress) + { + NOR_WRITE(p_currentaddress, *data); + + data++; + p_currentaddress ++; + } + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); + } + else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */ + { + NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM); + } + } + + /* Check the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Initialize variables */ - p_currentaddress = (uint16_t*)((uint32_t)(uwAddress)); - p_endaddress = p_currentaddress + (uwBufferSize-1U); - lastloadedaddress = (uint32_t)(uwAddress); - - /* Issue unlock command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - - /* Write Buffer Load Command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1U)); - - /* Load Data into NOR Buffer */ - while(p_currentaddress <= p_endaddress) + else { - /* Store last loaded address & data value (for polling) */ - lastloadedaddress = (uint32_t)p_currentaddress; - - NOR_WRITE(p_currentaddress, *pData++); - - p_currentaddress ++; + return HAL_ERROR; } - NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM); - - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; - + return status; + } /** - * @brief Erase the specified block of the NOR memory + * @brief Erase the specified block of the NOR memory * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param BlockAddress Block to erase address + * @param BlockAddress Block to erase address * @param Address Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address) { - uint32_t deviceaddress = 0U; + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; - /* Process Locked */ - __HAL_LOCK(hnor); - /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) + if (hnor->State == HAL_NOR_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + else if (hnor->State == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS1; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) - { - deviceaddress = NOR_MEMORY_ADRESS3; + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send block erase command sequence */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE); + NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + /* Check the NOR memory status and update the controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); } - else /* FMC_NORSRAM_BANK4 */ + else { - deviceaddress = NOR_MEMORY_ADRESS4; + return HAL_ERROR; } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send block erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE); - - /* Check the NOR memory status and update the controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; - + + return status; + } /** * @brief Erase the entire NOR chip. * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param Address Device address + * @param Address Device address * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address) { - uint32_t deviceaddress = 0U; - - /* Prevent unused argument(s) compilation warning */ + uint32_t deviceaddress; + HAL_StatusTypeDef status = HAL_OK; UNUSED(Address); - - /* Process Locked */ - __HAL_LOCK(hnor); - + /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) - { - return HAL_BUSY; - } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + if (hnor->State == HAL_NOR_STATE_BUSY) { - deviceaddress = NOR_MEMORY_ADRESS1; + return HAL_BUSY; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) - { - deviceaddress = NOR_MEMORY_ADRESS2; - } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else if (hnor->State == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS3; + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send NOR chip erase command sequence */ + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) + { + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), + NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_ERROR; + } + + /* Check the NOR memory status and update the controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); } - else /* FMC_NORSRAM_BANK4 */ + else { - deviceaddress = NOR_MEMORY_ADRESS4; + return HAL_ERROR; } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send NOR chip erase command sequence */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH); - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE); - - /* Check the NOR memory status and update the controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + + return status; } /** * @brief Read NOR flash CFI IDs * @param hnor pointer to a NOR_HandleTypeDef structure that contains * the configuration information for NOR module. - * @param pNOR_CFI pointer to NOR CFI IDs structure + * @param pNOR_CFI pointer to NOR CFI IDs structure * @retval HAL status */ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI) { - uint32_t deviceaddress = 0U; - - /* Process Locked */ - __HAL_LOCK(hnor); - + uint32_t deviceaddress; + HAL_NOR_StateTypeDef state; + /* Check the NOR controller state */ - if(hnor->State == HAL_NOR_STATE_BUSY) + state = hnor->State; + if (state == HAL_NOR_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - - /* Select the NOR device address */ - if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + else if (state == HAL_NOR_STATE_PROTECTED) { - deviceaddress = NOR_MEMORY_ADRESS1; + return HAL_ERROR; } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + else if (state == HAL_NOR_STATE_READY) { - deviceaddress = NOR_MEMORY_ADRESS2; + /* Process Locked */ + __HAL_LOCK(hnor); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Select the NOR device address */ + if (hnor->Init.NSBank == FMC_NORSRAM_BANK1) + { + deviceaddress = NOR_MEMORY_ADRESS1; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK2) + { + deviceaddress = NOR_MEMORY_ADRESS2; + } + else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + { + deviceaddress = NOR_MEMORY_ADRESS3; + } + else /* FMC_NORSRAM_BANK4 */ + { + deviceaddress = NOR_MEMORY_ADRESS4; + } + + /* Send read CFI query command */ + NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); + + /* read the NOR CFI information */ + pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); + pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); + pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); + pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); + + /* Check the NOR controller state */ + hnor->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); } - else if (hnor->Init.NSBank == FMC_NORSRAM_BANK3) + else { - deviceaddress = NOR_MEMORY_ADRESS3; + return HAL_ERROR; } - else /* FMC_NORSRAM_BANK4 */ - { - deviceaddress = NOR_MEMORY_ADRESS4; - } - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Send read CFI query command */ - NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI); - - /* read the NOR CFI information */ - pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS); - pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS); - pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS); - pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS); - /* Check the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - return HAL_OK; } @@ -919,12 +1210,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -933,20 +1225,20 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal __HAL_LOCK(hnor); state = hnor->State; - if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = pCallback; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = pCallback; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -970,7 +1262,7 @@ HAL_StatusTypeDef HAL_NOR_RegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_Cal * @arg @ref HAL_NOR_MSP_DEINIT_CB_ID NOR MspDeInit callback ID * @retval status */ -HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_NOR_StateTypeDef state; @@ -979,20 +1271,20 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C __HAL_LOCK(hnor); state = hnor->State; - if((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) + if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_NOR_MSP_INIT_CB_ID : - hnor->MspInitCallback = HAL_NOR_MspInit; - break; - case HAL_NOR_MSP_DEINIT_CB_ID : - hnor->MspDeInitCallback = HAL_NOR_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_NOR_MSP_INIT_CB_ID : + hnor->MspInitCallback = HAL_NOR_MspInit; + break; + case HAL_NOR_MSP_DEINIT_CB_ID : + hnor->MspDeInitCallback = HAL_NOR_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -1006,14 +1298,15 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C return status; } #endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */ + /** * @} */ - + /** @defgroup NOR_Exported_Functions_Group3 NOR Control functions - * @brief management functions - * -@verbatim + * @brief management functions + * +@verbatim ============================================================================== ##### NOR Control functions ##### ============================================================================== @@ -1024,7 +1317,7 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C @endverbatim * @{ */ - + /** * @brief Enables dynamically NOR write operation. * @param hnor pointer to a NOR_HandleTypeDef structure that contains @@ -1033,19 +1326,30 @@ HAL_StatusTypeDef HAL_NOR_UnRegisterCallback (NOR_HandleTypeDef *hnor, HAL_NOR_C */ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) { - /* Process Locked */ - __HAL_LOCK(hnor); + /* Check the NOR controller state */ + if (hnor->State == HAL_NOR_STATE_PROTECTED) + { + /* Process Locked */ + __HAL_LOCK(hnor); - /* Enable write operation */ - FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Enable write operation */ + (void)FMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; } /** @@ -1056,43 +1360,51 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor) */ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) { - /* Process Locked */ - __HAL_LOCK(hnor); + /* Check the NOR controller state */ + if (hnor->State == HAL_NOR_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hnor); - /* Update the SRAM controller state */ - hnor->State = HAL_NOR_STATE_BUSY; - - /* Disable write operation */ - FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); - - /* Update the NOR controller state */ - hnor->State = HAL_NOR_STATE_PROTECTED; - - /* Process unlocked */ - __HAL_UNLOCK(hnor); - - return HAL_OK; + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_BUSY; + + /* Disable write operation */ + (void)FMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); + + /* Update the NOR controller state */ + hnor->State = HAL_NOR_STATE_PROTECTED; + + /* Process unlocked */ + __HAL_UNLOCK(hnor); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; } /** * @} - */ - -/** @defgroup NOR_Exported_Functions_Group4 NOR State functions - * @brief Peripheral State functions - * -@verbatim + */ + +/** @defgroup NOR_Exported_Functions_Group4 NOR State functions + * @brief Peripheral State functions + * +@verbatim ============================================================================== ##### NOR State functions ##### - ============================================================================== + ============================================================================== [..] - This subsection permits to get in run-time the status of the NOR controller + This subsection permits to get in run-time the status of the NOR controller and the data flow. @endverbatim * @{ */ - + /** * @brief return the NOR controller state * @param hnor pointer to a NOR_HandleTypeDef structure that contains @@ -1107,63 +1419,103 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor) /** * @brief Returns the NOR operation status. * @param hnor pointer to a NOR_HandleTypeDef structure that contains - * the configuration information for NOR module. + * the configuration information for NOR module. * @param Address Device address * @param Timeout NOR programming Timeout - * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR + * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR * or HAL_NOR_STATUS_TIMEOUT */ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout) -{ +{ HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING; - uint16_t tmpSR1 = 0, tmpSR2 = 0; - uint32_t tickstart = 0U; + uint16_t tmpsr1; + uint16_t tmpsr2; + uint32_t tickstart; /* Poll on NOR memory Ready/Busy signal ------------------------------------*/ HAL_NOR_MspWait(hnor, Timeout); - + /* Get the NOR memory operation status -------------------------------------*/ - + /* Get tick */ tickstart = HAL_GetTick(); - while((status != HAL_NOR_STATUS_SUCCESS ) && (status != HAL_NOR_STATUS_TIMEOUT)) + + if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET) { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT)) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + status = HAL_NOR_STATUS_TIMEOUT; + } + } + + /* Read NOR status register (DQ6 and DQ5) */ + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) { - status = HAL_NOR_STATUS_TIMEOUT; - } - } + return HAL_NOR_STATUS_SUCCESS ; + } - /* Read NOR status register (DQ6 and DQ5) */ - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + status = HAL_NOR_STATUS_ONGOING; + } - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) - { - return HAL_NOR_STATUS_SUCCESS ; + tmpsr1 = *(__IO uint16_t *)Address; + tmpsr2 = *(__IO uint16_t *)Address; + + /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ + if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6)) + { + return HAL_NOR_STATUS_SUCCESS; + } + if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + { + return HAL_NOR_STATUS_ERROR; + } } - - if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + } + else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET) + { + do { - status = HAL_NOR_STATUS_ONGOING; - } - - tmpSR1 = *(__IO uint16_t *)Address; - tmpSR2 = *(__IO uint16_t *)Address; + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr2 = *(__IO uint16_t *)(Address); - /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS */ - if((tmpSR1 & NOR_MASK_STATUS_DQ6) == (tmpSR2 & NOR_MASK_STATUS_DQ6)) + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + return HAL_NOR_STATUS_TIMEOUT; + } + } + } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U); + + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + tmpsr1 = *(__IO uint16_t *)(Address); + if ((tmpsr1 & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U) { - return HAL_NOR_STATUS_SUCCESS; + /* Clear the Status Register */ + NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG); + status = HAL_NOR_STATUS_ERROR; } - if((tmpSR1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5) + else { - return HAL_NOR_STATUS_ERROR; - } + status = HAL_NOR_STATUS_SUCCESS; + } + } + else + { + /* Primary command set not supported by the driver */ + status = HAL_NOR_STATUS_ERROR; } /* Return the operation status */ @@ -1177,17 +1529,15 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ - STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ - STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx ||\ - STM32F423xx */ -#endif /* HAL_NOR_MODULE_ENABLED */ + /** * @} */ +#endif /* HAL_NOR_MODULE_ENABLED */ + /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* FMC_Bank1 || FSMC_Bank1 */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.h index dcd25c50572..cc7f1b5e50d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_nor.h @@ -6,35 +6,32 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_NOR_H -#define __STM32F4xx_HAL_NOR_H +#ifndef STM32F4xx_HAL_NOR_H +#define STM32F4xx_HAL_NOR_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#if defined(FMC_Bank1) || defined(FSMC_Bank1) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +/* Includes ------------------------------------------------------------------*/ +#if defined(FSMC_Bank1) +#include "stm32f4xx_ll_fsmc.h" +#else +#include "stm32f4xx_ll_fmc.h" +#endif /* FMC_Bank1 */ /** @addtogroup STM32F4xx_HAL_Driver * @{ @@ -42,29 +39,24 @@ /** @addtogroup NOR * @{ - */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) + */ /* Exported typedef ----------------------------------------------------------*/ /** @defgroup NOR_Exported_Types NOR Exported Types * @{ */ -/** - * @brief HAL SRAM State structures definition - */ +/** + * @brief HAL SRAM State structures definition + */ typedef enum -{ +{ HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ -}HAL_NOR_StateTypeDef; +} HAL_NOR_StateTypeDef; /** * @brief FMC NOR Status typedef @@ -75,7 +67,7 @@ typedef enum HAL_NOR_STATUS_ONGOING, HAL_NOR_STATUS_ERROR, HAL_NOR_STATUS_TIMEOUT -}HAL_NOR_StatusTypeDef; +} HAL_NOR_StatusTypeDef; /** * @brief FMC NOR ID typedef @@ -88,11 +80,11 @@ typedef struct uint16_t Device_Code2; - uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. - These codes can be accessed by performing read operations with specific - control signals and addresses set.They can also be accessed by issuing + uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. + These codes can be accessed by performing read operations with specific + control signals and addresses set.They can also be accessed by issuing an Auto Select command */ -}NOR_IDTypeDef; +} NOR_IDTypeDef; /** * @brief FMC NOR CFI typedef @@ -100,7 +92,7 @@ typedef struct typedef struct { /*!< Defines the information stored in the memory's Common flash interface - which contains a description of various electrical and timing parameters, + which contains a description of various electrical and timing parameters, density information and functions supported by the memory */ uint16_t CFI_1; @@ -110,9 +102,9 @@ typedef struct uint16_t CFI_3; uint16_t CFI_4; -}NOR_CFITypeDef; +} NOR_CFITypeDef; -/** +/** * @brief NOR handle Structure definition */ #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) @@ -132,10 +124,12 @@ typedef struct __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ + uint32_t CommandSet; /*!< NOR algorithm command set and control */ + #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp Init callback */ - void (* MspDeInitCallback) ( struct __NOR_HandleTypeDef * hnor); /*!< NOR Msp DeInit callback */ -#endif + void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ + void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ } NOR_HandleTypeDef; #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) @@ -146,19 +140,19 @@ typedef enum { HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ -}HAL_NOR_CallbackIDTypeDef; +} HAL_NOR_CallbackIDTypeDef; /** * @brief HAL NOR Callback pointer definition */ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ - + /* Exported constants --------------------------------------------------------*/ -/* Exported macros ------------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ /** @defgroup NOR_Exported_Macros NOR Exported Macros * @{ */ @@ -174,21 +168,23 @@ typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); } while(0) #else #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup NOR_Exported_Functions - * @{ - */ +/** @addtogroup NOR_Exported_Functions NOR Exported Functions + * @{ + */ + +/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ -/** @addtogroup NOR_Exported_Functions_Group1 - * @{ - */ /* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); @@ -196,18 +192,21 @@ void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); /** * @} */ - -/** @addtogroup NOR_Exported_Functions_Group2 - * @{ - */ + +/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions + * @{ + */ + /* I/O operation functions ***************************************************/ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); -HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); -HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); +HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, + uint32_t uwBufferSize); HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); @@ -215,37 +214,40 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) /* NOR callback registering/unregistering */ -HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, + pNOR_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); -#endif +#endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ /** * @} */ - -/** @addtogroup NOR_Exported_Functions_Group3 - * @{ - */ + +/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions + * @{ + */ + /* NOR Control functions *****************************************************/ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); /** * @} */ - -/** @addtogroup NOR_Exported_Functions_Group4 - * @{ - */ + +/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions + * @{ + */ + /* NOR State functions ********************************************************/ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); /** * @} */ - + /** * @} */ - + /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ @@ -266,16 +268,16 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /* NOR operation wait timeout */ #define NOR_TMEOUT ((uint16_t)0xFFFF) - + /* NOR memory data width */ #define NOR_MEMORY_8B ((uint8_t)0x00) #define NOR_MEMORY_16B ((uint8_t)0x01) /* NOR memory device read/write start address */ -#define NOR_MEMORY_ADRESS1 0x60000000U -#define NOR_MEMORY_ADRESS2 0x64000000U -#define NOR_MEMORY_ADRESS3 0x68000000U -#define NOR_MEMORY_ADRESS4 0x6C000000U +#define NOR_MEMORY_ADRESS1 (0x60000000U) +#define NOR_MEMORY_ADRESS2 (0x64000000U) +#define NOR_MEMORY_ADRESS3 (0x68000000U) +#define NOR_MEMORY_ADRESS4 (0x6C000000U) /** * @} */ @@ -286,41 +288,43 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres */ /** * @brief NOR memory address shifting. - * @param __NOR_ADDRESS__ NOR base address - * @param NOR_MEMORY_WIDTH NOR memory width - * @param ADDRESS NOR memory address + * @param __NOR_ADDRESS NOR base address + * @param __NOR_MEMORY_WIDTH_ NOR memory width + * @param __ADDRESS__ NOR memory address * @retval NOR shifted address value */ -#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\ - ((uint32_t)((__NOR_ADDRESS__) + (ADDRESS)))) - +#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ + ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ + ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ + ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) + /** * @brief NOR memory write data to specified address. - * @param ADDRESS NOR memory address - * @param DATA Data to write + * @param __ADDRESS__ NOR memory address + * @param __DATA__ Data to write * @retval None */ -#define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA)) +#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ + (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ + __DSB(); \ + } while(0) /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ - STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\ - STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ + /** * @} - */ + */ /** * @} */ +#endif /* FMC_Bank1 || FSMC_Bank1 */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_NOR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_NOR_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pccard.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pccard.c index 2f7d3e0ff52..14deb478fdc 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pccard.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pccard.c @@ -3,72 +3,83 @@ * @file stm32f4xx_hal_pccard.c * @author MCD Application Team * @brief PCCARD HAL module driver. - * This file provides a generic firmware to drive PCCARD memories mounted + * This file provides a generic firmware to drive PCCARD memories mounted * as external device. - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### - =============================================================================== + =============================================================================== [..] - This driver is a generic layered driver which contains a set of APIs used to - control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions + This driver is a generic layered driver which contains a set of APIs used to + control PCCARD/compact flash memories. It uses the FMC/FSMC layer functions to interface with PCCARD devices. This driver is used for: - - (+) PCCARD/Compact Flash memory configuration sequence using the function + + (+) PCCARD/Compact Flash memory configuration sequence using the function HAL_PCCARD_Init()/HAL_CF_Init() with control and timing parameters for both common and attribute spaces. - + (+) Read PCCARD/Compact Flash memory maker and device IDs using the function HAL_PCCARD_Read_ID()/HAL_CF_Read_ID(). The read information is stored in - the CompactFlash_ID structure declared by the function caller. - + the CompactFlash_ID structure declared by the function caller. + (+) Access PCCARD/Compact Flash memory by read/write operations using the functions - HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() - - HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector. - + HAL_PCCARD_Read_Sector()/ HAL_PCCARD_Write_Sector() - + HAL_CF_Read_Sector()/HAL_CF_Write_Sector(), to read/write sector. + (+) Perform PCCARD/Compact Flash Reset chip operation using the function HAL_PCCARD_Reset()/HAL_CF_Reset. - - (+) Perform PCCARD/Compact Flash erase sector operation using the function + + (+) Perform PCCARD/Compact Flash erase sector operation using the function HAL_PCCARD_Erase_Sector()/HAL_CF_Erase_Sector. - + (+) Read the PCCARD/Compact Flash status operation using the function HAL_PCCARD_ReadStatus()/HAL_CF_ReadStatus(). - + (+) You can monitor the PCCARD/Compact Flash device HAL state by calling the function HAL_PCCARD_GetState()/HAL_CF_GetState() - + [..] - (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash - operations. If a PCCARD/Compact Flash device contains different operations + (@) This driver is a set of generic APIs which handle standard PCCARD/compact flash + operations. If a PCCARD/Compact Flash device contains different operations and/or implementations, it should be implemented separately. - + *** Callback registration *** ============================================= [..] The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_PCCARD_RegisterCallback() to register a user callback, + Use Functions HAL_PCCARD_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : PCCARD MspInit. (+) MspDeInitCallback : PCCARD MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_PCCARD_UnRegisterCallback() to reset a callback to the default + Use function HAL_PCCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : PCCARD MspInit. (+) MspDeInitCallback : PCCARD MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_PCCARD_Init and if the state is HAL_PCCARD_STATE_RESET + By default, after the HAL_PCCARD_Init and if the state is HAL_PCCARD_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_PCCARD_Init - and @ref HAL_PCCARD_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_PCCARD_Init and @ref HAL_PCCARD_DeInit + reset to the legacy weak (surcharged) functions in the HAL_PCCARD_Init + and HAL_PCCARD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_PCCARD_Init and HAL_PCCARD_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -76,8 +87,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_PCCARD_RegisterCallback before calling @ref HAL_PCCARD_DeInit - or @ref HAL_PCCARD_Init function. + using HAL_PCCARD_RegisterCallback before calling HAL_PCCARD_DeInit + or HAL_PCCARD_Init function. When The compilation define USE_HAL_PCCARD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -85,36 +96,26 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(FMC_Bank4) || defined(FSMC_Bank4) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ #ifdef HAL_PCCARD_MODULE_ENABLED -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -/** @defgroup PCCARD PCCARD + +/** @defgroup PCCARD PCCARD * @brief PCCARD HAL module driver * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ - + /** @defgroup PCCARD_Private_Defines PCCARD Private Defines * @{ */ @@ -127,8 +128,8 @@ #define PCCARD_STATUS_WRITE_OK (uint8_t)0x50 /** * @} - */ - + */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function ----------------------------------------------------------*/ @@ -137,44 +138,45 @@ * @{ */ -/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @defgroup PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim ============================================================================== ##### PCCARD Initialization and de-initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to initialize/de-initialize the PCCARD memory - + @endverbatim * @{ */ - + /** * @brief Perform the PCCARD memory Initialization sequence * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @param ComSpaceTiming Common space timing structure * @param AttSpaceTiming Attribute space timing structure - * @param IOSpaceTiming IO space timing structure + * @param IOSpaceTiming IO space timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) +HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, + FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming) { /* Check the PCCARD controller state */ - if(hpccard == NULL) + if (hpccard == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - - if(hpccard->State == HAL_PCCARD_STATE_RESET) - { + + if (hpccard->State == HAL_PCCARD_STATE_RESET) + { /* Allocate lock resource and initialize it */ hpccard->Lock = HAL_UNLOCKED; #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) - if(hpccard->MspInitCallback == NULL) + if (hpccard->MspInitCallback == NULL) { hpccard->MspInitCallback = HAL_PCCARD_MspInit; } @@ -187,28 +189,28 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti HAL_PCCARD_MspInit(hpccard); #endif } - + /* Initialize the PCCARD state */ - hpccard->State = HAL_PCCARD_STATE_BUSY; + hpccard->State = HAL_PCCARD_STATE_BUSY; /* Initialize PCCARD control Interface */ FMC_PCCARD_Init(hpccard->Instance, &(hpccard->Init)); - + /* Init PCCARD common space timing Interface */ FMC_PCCARD_CommonSpace_Timing_Init(hpccard->Instance, ComSpaceTiming); - - /* Init PCCARD attribute space timing Interface */ + + /* Init PCCARD attribute space timing Interface */ FMC_PCCARD_AttributeSpace_Timing_Init(hpccard->Instance, AttSpaceTiming); - - /* Init PCCARD IO space timing Interface */ + + /* Init PCCARD IO space timing Interface */ FMC_PCCARD_IOSpace_Timing_Init(hpccard->Instance, IOSpaceTiming); - + /* Enable the PCCARD device */ - __FMC_PCCARD_ENABLE(hpccard->Instance); - + __FMC_PCCARD_ENABLE(hpccard->Instance); + /* Update the PCCARD state */ - hpccard->State = HAL_PCCARD_STATE_READY; - + hpccard->State = HAL_PCCARD_STATE_READY; + return HAL_OK; } @@ -222,7 +224,7 @@ HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_Ti HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard) { #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) - if(hpccard->MspDeInitCallback == NULL) + if (hpccard->MspDeInitCallback == NULL) { hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; } @@ -236,14 +238,14 @@ HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard) /* Configure the PCCARD registers with their reset values */ FMC_PCCARD_DeInit(hpccard->Instance); - + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_RESET; /* Release Lock */ __HAL_UNLOCK(hpccard); - return HAL_OK; + return HAL_OK; } /** @@ -258,7 +260,7 @@ __weak void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard) UNUSED(hpccard); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCCARD_MspInit could be implemented in the user file - */ + */ } /** @@ -273,90 +275,90 @@ __weak void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard) UNUSED(hpccard); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_PCCARD_MspDeInit could be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions +/** @defgroup PCCARD_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions * - @verbatim + @verbatim ============================================================================== ##### PCCARD Input and Output functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to use and control the PCCARD memory - + @endverbatim * @{ */ - + /** * @brief Read Compact Flash's ID. * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. - * @param CompactFlash_ID Compact flash ID structure. - * @param pStatus pointer to compact flash status + * @param CompactFlash_ID Compact flash ID structure. + * @param pStatus pointer to compact flash status * @retval HAL status - * - */ + * + */ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus) { uint32_t timeout = PCCARD_TIMEOUT_READ_ID, index = 0U; uint8_t status = 0; - + /* Process Locked */ - __HAL_LOCK(hpccard); - + __HAL_LOCK(hpccard); + /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; - + /* Initialize the PCCARD status */ - *pStatus = PCCARD_READY; - + *pStatus = PCCARD_READY; + /* Send the Identify Command */ - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = 0xECEC; - + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xECEC; + /* Read PCCARD IDs and timeout treatment */ - do + do { - /* Read the PCCARD status */ - status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); - - timeout--; - }while((status != PCCARD_STATUS_OK) && timeout); - - if(timeout == 0U) + /* Read the PCCARD status */ + status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); + + timeout--; + } while ((status != PCCARD_STATUS_OK) && timeout); + + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } else { - /* Read PCCARD ID bytes */ - for(index = 0U; index < 16U; index++) + /* Read PCCARD ID bytes */ + for (index = 0U; index < 16U; index++) { CompactFlash_ID[index] = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_DATA); - } + } } - + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hpccard); - + __HAL_UNLOCK(hpccard); + return HAL_OK; } - + /** * @brief Read sector from PCCARD memory * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains @@ -365,21 +367,22 @@ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t Comp * @param SectorAddress Sector address to read * @param pStatus pointer to PCCARD status * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) + */ +HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus) { uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U; uint8_t status = 0; /* Process Locked */ __HAL_LOCK(hpccard); - + /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; @@ -387,22 +390,22 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pStatus = PCCARD_READY; /* Set the parameters to write a sector */ - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00; + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x0000; *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress); - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0; + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0xE4A0; do { /* wait till the Status = 0x80 */ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - }while((status == 0x80) && timeout); - - if(timeout == 0U) + } while ((status == 0x80U) && timeout); + + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } - + timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR; do @@ -410,25 +413,25 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t /* wait till the Status = PCCARD_STATUS_OK */ status = *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - }while((status != PCCARD_STATUS_OK) && timeout); - - if(timeout == 0U) + } while ((status != PCCARD_STATUS_OK) && timeout); + + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } - + /* Read bytes */ - for(; index < PCCARD_SECTOR_SIZE; index++) + for (; index < PCCARD_SECTOR_SIZE; index++) { *(uint16_t *)pBuffer++ = *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR); - } + } /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_READY; - + /* Process unlocked */ __HAL_UNLOCK(hpccard); - + return HAL_OK; } @@ -442,45 +445,46 @@ HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t * @param pStatus pointer to PCCARD status * @retval HAL status */ -HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus) +HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus) { uint32_t timeout = PCCARD_TIMEOUT_READ_WRITE_SECTOR, index = 0U; uint8_t status = 0; /* Process Locked */ - __HAL_LOCK(hpccard); - + __HAL_LOCK(hpccard); + /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } - + /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; - + /* Initialize PCCARD status */ - *pStatus = PCCARD_READY; - + *pStatus = PCCARD_READY; + /* Set the parameters to write a sector */ - *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x00; + *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = (uint16_t)0x0000; *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = ((uint16_t)0x0100) | ((uint16_t)SectorAddress); *(__IO uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = (uint16_t)0x30A0; - + do { /* Wait till the Status = PCCARD_STATUS_OK */ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - }while((status != PCCARD_STATUS_OK) && timeout); - - if(timeout == 0U) + } while ((status != PCCARD_STATUS_OK) && timeout); + + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } - + /* Write bytes */ - for(; index < PCCARD_SECTOR_SIZE; index++) + for (; index < PCCARD_SECTOR_SIZE; index++) { *(uint16_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR) = *(uint16_t *)pBuffer++; } @@ -490,25 +494,25 @@ HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_ /* Wait till the Status = PCCARD_STATUS_WRITE_OK */ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - }while((status != PCCARD_STATUS_WRITE_OK) && timeout); + } while ((status != PCCARD_STATUS_WRITE_OK) && timeout); - if(timeout == 0U) + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; - } + } /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hpccard); - + __HAL_UNLOCK(hpccard); + return HAL_OK; } /** - * @brief Erase sector from PCCARD memory + * @brief Erase sector from PCCARD memory * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @param SectorAddress Sector address to erase @@ -519,22 +523,22 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16 { uint32_t timeout = PCCARD_TIMEOUT_ERASE_SECTOR; uint8_t status = 0; - + /* Process Locked */ - __HAL_LOCK(hpccard); - + __HAL_LOCK(hpccard); + /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Update the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; - - /* Initialize PCCARD status */ + + /* Initialize PCCARD status */ *pStatus = PCCARD_READY; - + /* Set the parameters to write a sector */ *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_LOW) = 0x00; *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CYLINDER_HIGH) = 0x00; @@ -542,32 +546,32 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16 *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_SECTOR_COUNT) = 0x01; *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_CARD_HEAD) = 0xA0; *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD) = ATA_ERASE_SECTOR_CMD; - + /* wait till the PCCARD is ready */ status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); - - while((status != PCCARD_STATUS_WRITE_OK) && timeout) + + while ((status != PCCARD_STATUS_WRITE_OK) && timeout) { status = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; - } - - if(timeout == 0U) + } + + if (timeout == 0U) { *pStatus = PCCARD_TIMEOUT_ERROR; } - + /* Check the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hpccard); - + __HAL_UNLOCK(hpccard); + return HAL_OK; } /** - * @brief Reset the PCCARD memory + * @brief Reset the PCCARD memory * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval HAL status @@ -575,12 +579,12 @@ HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16 HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard) { /* Process Locked */ - __HAL_LOCK(hpccard); - + __HAL_LOCK(hpccard); + /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_BUSY; + return HAL_BUSY; } /* Provide a SW reset and Read and verify the: @@ -592,15 +596,15 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard) /* Check the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_BUSY; - - *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION ) = 0x01; - + + *(__IO uint8_t *)(PCCARD_ATTRIBUTE_SPACE_ADDRESS | ATA_CARD_CONFIGURATION) = 0x01; + /* Check the PCCARD controller state */ hpccard->State = HAL_PCCARD_STATE_READY; - + /* Process unlocked */ - __HAL_UNLOCK(hpccard); - + __HAL_UNLOCK(hpccard); + return HAL_OK; } @@ -609,11 +613,11 @@ HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard) * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains * the configuration information for PCCARD module. * @retval HAL status -*/ + */ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) { /* Check PCCARD interrupt Rising edge flag */ - if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE)) + if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE)) { /* PCCARD interrupt callback*/ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) @@ -625,9 +629,9 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) /* Clear PCCARD interrupt Rising edge pending bit */ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_RISING_EDGE); } - + /* Check PCCARD interrupt Level flag */ - if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL)) + if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_LEVEL)) { /* PCCARD interrupt callback*/ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) @@ -641,7 +645,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) } /* Check PCCARD interrupt Falling edge flag */ - if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE)) + if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE)) { /* PCCARD interrupt callback*/ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) @@ -653,9 +657,9 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) /* Clear PCCARD interrupt Falling edge pending bit */ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FALLING_EDGE); } - + /* Check PCCARD interrupt FIFO empty flag */ - if(__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT)) + if (__FMC_PCCARD_GET_FLAG(hpccard->Instance, FMC_FLAG_FEMPT)) { /* PCCARD interrupt callback*/ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) @@ -666,7 +670,7 @@ void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard) /* Clear PCCARD interrupt FIFO empty pending bit */ __FMC_PCCARD_CLEAR_FLAG(hpccard->Instance, FMC_FLAG_FEMPT); - } + } } /** @@ -697,11 +701,12 @@ __weak void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard) * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, + pPCCARD_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -709,39 +714,39 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HA /* Process locked */ __HAL_LOCK(hpccard); - if(hpccard->State == HAL_PCCARD_STATE_READY) + if (hpccard->State == HAL_PCCARD_STATE_READY) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = pCallback; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = pCallback; - break; - case HAL_PCCARD_IT_CB_ID : - hpccard->ItCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = pCallback; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = pCallback; + break; + case HAL_PCCARD_IT_CB_ID : + hpccard->ItCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hpccard->State == HAL_PCCARD_STATE_RESET) + else if (hpccard->State == HAL_PCCARD_STATE_RESET) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = pCallback; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = pCallback; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -766,46 +771,46 @@ HAL_StatusTypeDef HAL_PCCARD_RegisterCallback (PCCARD_HandleTypeDef *hpccard, HA * @arg @ref HAL_PCCARD_IT_CB_ID PCCARD IT callback ID * @retval status */ -HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hpccard); - if(hpccard->State == HAL_PCCARD_STATE_READY) + if (hpccard->State == HAL_PCCARD_STATE_READY) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = HAL_PCCARD_MspInit; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; - break; - case HAL_PCCARD_IT_CB_ID : - hpccard->ItCallback = HAL_PCCARD_ITCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = HAL_PCCARD_MspInit; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; + break; + case HAL_PCCARD_IT_CB_ID : + hpccard->ItCallback = HAL_PCCARD_ITCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hpccard->State == HAL_PCCARD_STATE_RESET) + else if (hpccard->State == HAL_PCCARD_STATE_RESET) { switch (CallbackId) { - case HAL_PCCARD_MSP_INIT_CB_ID : - hpccard->MspInitCallback = HAL_PCCARD_MspInit; - break; - case HAL_PCCARD_MSP_DEINIT_CB_ID : - hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_PCCARD_MSP_INIT_CB_ID : + hpccard->MspInitCallback = HAL_PCCARD_MspInit; + break; + case HAL_PCCARD_MSP_DEINIT_CB_ID : + hpccard->MspDeInitCallback = HAL_PCCARD_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -824,21 +829,21 @@ HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, * @} */ -/** @defgroup PCCARD_Exported_Functions_Group3 State functions - * @brief Peripheral State functions - * -@verbatim +/** @defgroup PCCARD_Exported_Functions_Group3 State functions + * @brief Peripheral State functions + * +@verbatim ============================================================================== ##### PCCARD State functions ##### - ============================================================================== + ============================================================================== [..] - This subsection permits to get in run-time the status of the PCCARD controller + This subsection permits to get in run-time the status of the PCCARD controller and the data flow. @endverbatim * @{ - */ - + */ + /** * @brief return the PCCARD controller state * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains @@ -848,95 +853,94 @@ HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback (PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_StateTypeDef HAL_PCCARD_GetState(PCCARD_HandleTypeDef *hpccard) { return hpccard->State; -} - +} + /** * @brief Get the compact flash memory status * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains - * the configuration information for PCCARD module. + * the configuration information for PCCARD module. * @retval New status of the PCCARD operation. This parameter can be: - * - CompactFlash_TIMEOUT_ERROR: when the previous operation generate + * - CompactFlash_TIMEOUT_ERROR: when the previous operation generate * a Timeout error - * - CompactFlash_READY: when memory is ready for the next operation + * - CompactFlash_READY: when memory is ready for the next operation */ HAL_PCCARD_StatusTypeDef HAL_PCCARD_GetStatus(PCCARD_HandleTypeDef *hpccard) { - uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U; - + uint32_t timeout = PCCARD_TIMEOUT_STATUS, status_pccard = 0U; + /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_PCCARD_STATUS_ONGOING; + return HAL_PCCARD_STATUS_ONGOING; } status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); - - while((status_pccard == PCCARD_BUSY) && timeout) + + while ((status_pccard == PCCARD_BUSY) && timeout) { status_pccard = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); timeout--; } - if(timeout == 0U) - { - status_pccard = PCCARD_TIMEOUT_ERROR; - } + if (timeout == 0U) + { + status_pccard = PCCARD_TIMEOUT_ERROR; + } /* Return the operation status */ - return (HAL_PCCARD_StatusTypeDef) status_pccard; + return (HAL_PCCARD_StatusTypeDef) status_pccard; } - + /** * @brief Reads the Compact Flash memory status using the Read status command * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains - * the configuration information for PCCARD module. + * the configuration information for PCCARD module. * @retval The status of the Compact Flash memory. This parameter can be: * - CompactFlash_BUSY: when memory is busy - * - CompactFlash_READY: when memory is ready for the next operation - * - CompactFlash_ERROR: when the previous operation generates error + * - CompactFlash_READY: when memory is ready for the next operation + * - CompactFlash_ERROR: when the previous operation generates error */ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard) { uint8_t data = 0U, status_pccard = PCCARD_BUSY; - + /* Check the PCCARD controller state */ - if(hpccard->State == HAL_PCCARD_STATE_BUSY) + if (hpccard->State == HAL_PCCARD_STATE_BUSY) { - return HAL_PCCARD_STATUS_ONGOING; - } + return HAL_PCCARD_STATUS_ONGOING; + } /* Read status operation */ data = *(__IO uint8_t *)(PCCARD_IO_SPACE_PRIMARY_ADDR | ATA_STATUS_CMD_ALTERNATE); - if((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR) + if ((data & PCCARD_TIMEOUT_ERROR) == PCCARD_TIMEOUT_ERROR) { status_pccard = PCCARD_TIMEOUT_ERROR; - } - else if((data & PCCARD_READY) == PCCARD_READY) + } + else if ((data & PCCARD_READY) == PCCARD_READY) { status_pccard = PCCARD_READY; } - + return (HAL_PCCARD_StatusTypeDef) status_pccard; -} - +} + /** * @} */ - + /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ - STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -#endif /* HAL_PCCARD_MODULE_ENABLED */ /** * @} */ +#endif /* HAL_PCCARD_MODULE_ENABLED */ + /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* FMC_Bank4 || FSMC_Bank4 */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pccard.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pccard.h index 41d7824e063..47fbb262ff0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pccard.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pccard.h @@ -6,60 +6,56 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_PCCARD_H -#define __STM32F4xx_HAL_PCCARD_H +#ifndef STM32F4xx_HAL_PCCARD_H +#define STM32F4xx_HAL_PCCARD_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#if defined(FMC_Bank4) || defined(FSMC_Bank4) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +/* Includes ------------------------------------------------------------------*/ +#if defined(FSMC_Bank4) +#include "stm32f4xx_ll_fsmc.h" +#else +#include "stm32f4xx_ll_fmc.h" +#endif /* FSMC_Bank4 */ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /** @addtogroup PCCARD * @{ - */ + */ /* Exported typedef ----------------------------------------------------------*/ /** @defgroup PCCARD_Exported_Types PCCARD Exported Types * @{ */ -/** - * @brief HAL PCCARD State structures definition - */ +/** + * @brief HAL PCCARD State structures definition + */ typedef enum { HAL_PCCARD_STATE_RESET = 0x00U, /*!< PCCARD peripheral not yet initialized or disabled */ HAL_PCCARD_STATE_READY = 0x01U, /*!< PCCARD peripheral ready */ HAL_PCCARD_STATE_BUSY = 0x02U, /*!< PCCARD peripheral busy */ HAL_PCCARD_STATE_ERROR = 0x04U /*!< PCCARD peripheral error */ -}HAL_PCCARD_StateTypeDef; +} HAL_PCCARD_StateTypeDef; typedef enum { @@ -67,19 +63,19 @@ typedef enum HAL_PCCARD_STATUS_ONGOING, HAL_PCCARD_STATUS_ERROR, HAL_PCCARD_STATUS_TIMEOUT -}HAL_PCCARD_StatusTypeDef; +} HAL_PCCARD_StatusTypeDef; /** * @brief FMC_PCCARD handle Structure definition */ -#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) +#if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) typedef struct __PCCARD_HandleTypeDef #else typedef struct #endif /* USE_HAL_PCCARD_REGISTER_CALLBACKS */ { FMC_PCCARD_TypeDef *Instance; /*!< Register base address for PCCARD device */ - + FMC_PCCARD_InitTypeDef Init; /*!< PCCARD device control configuration parameters */ __IO HAL_PCCARD_StateTypeDef State; /*!< PCCARD device access state */ @@ -87,9 +83,9 @@ typedef struct HAL_LockTypeDef Lock; /*!< PCCARD Lock */ #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp Init callback */ - void (* MspDeInitCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD Msp DeInit callback */ - void (* ItCallback) ( struct __PCCARD_HandleTypeDef * hpccard); /*!< PCCARD IT callback */ + void (* MspInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp Init callback */ + void (* MspDeInitCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD Msp DeInit callback */ + void (* ItCallback)(struct __PCCARD_HandleTypeDef *hpccard); /*!< PCCARD IT callback */ #endif } PCCARD_HandleTypeDef; @@ -102,7 +98,7 @@ typedef enum HAL_PCCARD_MSP_INIT_CB_ID = 0x00U, /*!< PCCARD MspInit Callback ID */ HAL_PCCARD_MSP_DEINIT_CB_ID = 0x01U, /*!< PCCARD MspDeInit Callback ID */ HAL_PCCARD_IT_CB_ID = 0x02U /*!< PCCARD IT Callback ID */ -}HAL_PCCARD_CallbackIDTypeDef; +} HAL_PCCARD_CallbackIDTypeDef; /** * @brief HAL PCCARD Callback pointer definition @@ -133,18 +129,19 @@ typedef void (*pPCCARD_CallbackTypeDef)(PCCARD_HandleTypeDef *hpccard); #endif /** * @} - */ + */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCCARD_Exported_Functions +/** @addtogroup PCCARD_Exported_Functions * @{ */ -/** @addtogroup PCCARD_Exported_Functions_Group1 +/** @addtogroup PCCARD_Exported_Functions_Group1 * @{ */ /* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); +HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, + FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming); HAL_StatusTypeDef HAL_PCCARD_DeInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspInit(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); @@ -157,8 +154,10 @@ void HAL_PCCARD_MspDeInit(PCCARD_HandleTypeDef *hpccard); */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_PCCARD_Read_ID(PCCARD_HandleTypeDef *hpccard, uint8_t CompactFlash_ID[], uint8_t *pStatus); -HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus); -HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus); +HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus); +HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, + uint8_t *pStatus); HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus); HAL_StatusTypeDef HAL_PCCARD_Reset(PCCARD_HandleTypeDef *hpccard); void HAL_PCCARD_IRQHandler(PCCARD_HandleTypeDef *hpccard); @@ -166,8 +165,10 @@ void HAL_PCCARD_ITCallback(PCCARD_HandleTypeDef *hpccard); #if (USE_HAL_PCCARD_REGISTER_CALLBACKS == 1) /* PCCARD callback registering/unregistering */ -HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, pPCCARD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId); +HAL_StatusTypeDef HAL_PCCARD_RegisterCallback(PCCARD_HandleTypeDef *hpccard, HAL_PCCARD_CallbackIDTypeDef CallbackId, + pPCCARD_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_PCCARD_UnRegisterCallback(PCCARD_HandleTypeDef *hpccard, + HAL_PCCARD_CallbackIDTypeDef CallbackId); #endif /** * @} @@ -223,7 +224,7 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard); #define PCCARD_PROGR ((uint8_t)0x01) #define PCCARD_READY ((uint8_t)0x40) -#define PCCARD_SECTOR_SIZE 255U /* In half words */ +#define PCCARD_SECTOR_SIZE 255U /* In half words */ /** * @} @@ -254,14 +255,14 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard); #define CF_DEVICE_ADDRESS PCCARD_DEVICE_ADDRESS #define CF_ATTRIBUTE_SPACE_ADDRESS PCCARD_ATTRIBUTE_SPACE_ADDRESS -#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS -#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS -#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR +#define CF_COMMON_SPACE_ADDRESS PCCARD_COMMON_SPACE_ADDRESS +#define CF_IO_SPACE_ADDRESS PCCARD_IO_SPACE_ADDRESS +#define CF_IO_SPACE_PRIMARY_ADDR PCCARD_IO_SPACE_PRIMARY_ADDR #define CF_TIMEOUT_ERROR PCCARD_TIMEOUT_ERROR -#define CF_BUSY PCCARD_BUSY -#define CF_PROGR PCCARD_PROGR -#define CF_READY PCCARD_READY +#define CF_BUSY PCCARD_BUSY +#define CF_PROGR PCCARD_PROGR +#define CF_READY PCCARD_READY #define CF_SECTOR_SIZE PCCARD_SECTOR_SIZE @@ -270,18 +271,15 @@ HAL_PCCARD_StatusTypeDef HAL_PCCARD_ReadStatus(PCCARD_HandleTypeDef *hpccard); * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\ - STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - /** * @} */ - + +#endif /* FMC_Bank4 || FSMC_Bank4 */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_PCCARD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_PCCARD_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.c index 13aace25f3a..7e46592b31e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -41,17 +52,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -224,7 +224,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) hpcd->USB_Address = 0U; hpcd->State = HAL_PCD_STATE_READY; - #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) +#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) /* Activate LPM */ if (hpcd->Init.lpm_enable == 1U) { @@ -422,7 +422,7 @@ HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister an USB PCD Callback - * USB PCD callabck is redirected to the weak predefined callback + * USB PCD callback is redirected to the weak predefined callback * @param hpcd USB PCD handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -721,7 +721,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister the USB PCD Iso OUT incomplete Callback - * USB PCD Iso OUT incomplete Callback is redirected to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback + * USB PCD Iso OUT incomplete Callback is redirected + * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status */ @@ -795,7 +796,8 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, /** * @brief Unregister the USB PCD Iso IN incomplete Callback - * USB PCD Iso IN incomplete Callback is redirected to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback + * USB PCD Iso IN incomplete Callback is redirected + * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback * @param hpcd PCD handle * @retval HAL status */ @@ -1037,6 +1039,7 @@ HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) /* Disable USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); } + __HAL_UNLOCK(hpcd); return HAL_OK; @@ -1052,9 +1055,13 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i, ep_intr, epint, epnum; - uint32_t fifoemptymsk, temp; USB_OTG_EPTypeDef *ep; + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t RegVal; /* ensure that we are in device mode */ if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) @@ -1065,6 +1072,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) return; } + /* store current frame number */ + hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) { /* incorrect mode, acknowledge the interrupt */ @@ -1076,30 +1086,31 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - temp = USBx->GRXSTSP; + RegVal = USBx->GRXSTSP; - ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM]; + ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; - if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) { - if ((temp & USB_OTG_GRXSTSP_BCNT) != 0U) + if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) { (void)USB_ReadPacket(USBx, ep->xfer_buff, - (uint16_t)((temp & USB_OTG_GRXSTSP_BCNT) >> 4)); + (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); - ep->xfer_buff += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; } } - else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) { (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); - ep->xfer_count += (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; } else { /* ... */ } + USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); } @@ -1134,6 +1145,30 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); } + /* Clear OUT Endpoint disable interrupt */ + if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) + { + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; + } + + ep = &hpcd->OUT_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + + CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); + } + /* Clear Status Phase Received interrupt */ if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) { @@ -1203,6 +1238,21 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) } if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) { + (void)USB_FlushTxFifo(USBx, epnum); + + ep = &hpcd->IN_ep[epnum]; + + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#else + HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); } if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) @@ -1293,7 +1343,6 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) { USBx_INEP(i)->DIEPINT = 0xFB7FU; USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - USBx_INEP(i)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; USBx_OUTEP(i)->DOEPINT = 0xFB7FU; USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; @@ -1365,18 +1414,37 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); } + /* Handle Global OUT NAK effective Interrupt */ + if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) + { + USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; + + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + /* Handle Incomplete ISO IN Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) { - /* Keep application checking the corresponding Iso IN endpoint - causing the incomplete Interrupt */ - epnum = 0U; + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_INEP(epnum)->DIEPCTL; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); } @@ -1384,15 +1452,25 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Incomplete ISO OUT Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) { - /* Keep application checking the corresponding Iso OUT endpoint - causing the incomplete Interrupt */ - epnum = 0U; + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USBx_OUTEP(epnum)->DOEPCTL; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && + ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && + ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + + USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; + + if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) + { + USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; + break; + } + } + } __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); } @@ -1412,9 +1490,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) /* Handle Disconnection event Interrupt */ if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) { - temp = hpcd->Instance->GOTGINT; + RegVal = hpcd->Instance->GOTGINT; - if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) + if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DisconnectCallback(hpcd); @@ -1422,7 +1500,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) HAL_PCD_DisconnectCallback(hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - hpcd->Instance->GOTGINT |= temp; + hpcd->Instance->GOTGINT |= RegVal; } } } @@ -1651,19 +1729,16 @@ __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) { -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ __HAL_LOCK(hpcd); -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) + if ((hpcd->Init.battery_charging_enable == 1U) && (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) { /* Enable USB Transceiver */ USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; } -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ (void)USB_DevConnect(hpcd->Instance); __HAL_UNLOCK(hpcd); @@ -1677,21 +1752,17 @@ HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) */ HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) { -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ __HAL_LOCK(hpcd); (void)USB_DevDisconnect(hpcd->Instance); -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) if ((hpcd->Init.battery_charging_enable == 1U) && (hpcd->Init.phy_itface != USB_OTG_ULPI_PHY)) { /* Disable USB Transceiver */ USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); } -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ __HAL_UNLOCK(hpcd); @@ -1954,6 +2025,32 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) return HAL_OK; } +/** + * @brief Abort an USB EP transaction. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + HAL_StatusTypeDef ret; + PCD_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + ret = USB_EPStopXfer(hpcd->Instance, ep); + + return ret; +} + /** * @brief Flush an endpoint * @param hpcd PCD handle @@ -2027,6 +2124,33 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd) return hpcd->State; } +/** + * @brief Set the USB Device high speed test mode. + * @param hpcd PCD handle + * @param testmode USB Device high speed test mode + * @retval HAL status + */ +HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode) +{ + USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; + uint32_t USBx_BASE = (uint32_t)USBx; + + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + } + + return HAL_OK; +} /** * @} */ @@ -2108,6 +2232,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t */ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) { + USB_OTG_EPTypeDef *ep; USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t gSNPSiD = *(__IO uint32_t *)(&USBx->CID + 0x1U); @@ -2138,18 +2263,24 @@ static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint } else { - /* out data packet received over EP0 */ - hpcd->OUT_ep[epnum].xfer_count = - hpcd->OUT_ep[epnum].maxpacket - - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); + ep = &hpcd->OUT_ep[epnum]; - hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket; + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) + if (epnum == 0U) { - /* this is ZLP, so prepare EP0 for next setup */ - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } } + #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); #else @@ -2254,5 +2385,3 @@ static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.h index 87b9efa0a97..92488b2fe79 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -107,6 +106,7 @@ typedef struct uint32_t Setup[12]; /*!< Setup packet buffer */ PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ uint32_t BESL; + uint32_t FrameNumber; /*!< Store Current Frame number */ uint32_t lpm_active; /*!< Enable or disable the Link Power Management . @@ -194,16 +194,20 @@ typedef struct #define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) #define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ + ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) + #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) #define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) +#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) -#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) - -#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK +#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ + *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) +#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ + ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE) #define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) @@ -286,12 +290,10 @@ typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgType * @} */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback); @@ -313,14 +315,10 @@ HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, - pPCD_BcdCallbackTypeDef pCallback); - +HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, - pPCD_LpmCallbackTypeDef pCallback); - +HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ /** @@ -360,22 +358,17 @@ void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint16_t ep_mps, uint8_t ep_type); - +HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint8_t *pBuf, uint32_t len); - -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint8_t *pBuf, uint32_t len); - - +HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); +HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_SetTestMode(PCD_HandleTypeDef *hpcd, uint8_t testmode); uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); /** @@ -418,27 +411,27 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #if defined (USB_OTG_FS) || defined (USB_OTG_HS) #ifndef USB_OTG_DOEPINT_OTEPSPR #define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ -#endif +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ #ifndef USB_OTG_DOEPMSK_OTEPSPRM #define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ -#endif +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ #ifndef USB_OTG_DOEPINT_NAK #define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ -#endif +#endif /* defined USB_OTG_DOEPINT_NAK */ #ifndef USB_OTG_DOEPMSK_NAKM #define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ -#endif +#endif /* defined USB_OTG_DOEPMSK_NAKM */ #ifndef USB_OTG_DOEPINT_STPKTRX #define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ -#endif +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ #ifndef USB_OTG_DOEPMSK_NYETM #define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ -#endif +#endif /* defined USB_OTG_DOEPMSK_NYETM */ #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ /* Private macros ------------------------------------------------------------*/ @@ -464,5 +457,3 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #endif #endif /* STM32F4xx_HAL_PCD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd_ex.c index 51562ab8a19..292faf13bc2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd_ex.c @@ -10,13 +10,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -164,26 +163,10 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Enable DCD : Data Contact Detect */ USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - /* Wait Detect flag or a timeout is happen*/ - while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > 1000U) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - return; - } - } - - /* Right response got */ - HAL_Delay(200U); + /* Wait for Min DCD Timeout */ + HAL_Delay(300U); - /* Check Detect flag*/ + /* Check Detect flag */ if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) @@ -193,7 +176,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ } - /*Primary detection: checks if connected to Standard Downstream Port + /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ USBx->GCCFG &= ~ USB_OTG_GCCFG_DCDEN; HAL_Delay(50U); @@ -229,7 +212,7 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } else { - /* case Charging Downstream Port */ + /* case Charging Downstream Port */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); #else @@ -241,11 +224,23 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) /* Battery Charging capability discovery finished */ (void)HAL_PCDEx_DeActivateBCD(hpcd); + /* Check for the Timeout, else start USB Device */ + if ((HAL_GetTick() - tickstart) > 1000U) + { #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); #else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } + else + { +#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) + hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#else + HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); +#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ + } } /** @@ -344,5 +339,3 @@ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef m /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd_ex.h index 71e9a2c18b4..72ded2b6ca7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pcd_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -23,7 +22,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -83,9 +82,7 @@ void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32F4xx_HAL_PCD_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.c index 54896c9137b..f5863fa93fc 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.c @@ -11,14 +11,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -380,6 +378,9 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) */ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { + /* Prevent unused argument(s) compilation warning */ + UNUSED(Regulator); + /* Check the parameters */ assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); @@ -392,9 +393,6 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) { /* Request Wait For Interrupt */ __WFI(); - __NOP(); // Workaround for STM32F4 errata - __NOP(); // see chapter 2.1.3 - Debugging Sleep/Stop mode with WFE/WFI entry - __NOP(); // https://www.st.com/resource/en/errata_sheet/dm00037591-stm32f405-407xx-and-stm32f415-417xx-device-limitations-stmicroelectronics.pdf } else { @@ -574,5 +572,3 @@ void HAL_PWR_DisableSEVOnPend(void) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.h index 6f3bf7141c9..d97f255d9f0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -427,5 +425,3 @@ void HAL_PWR_DisableSEVOnPend(void); #endif /* __STM32F4xx_HAL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr_ex.c index 0d26083a4b1..77f9c35b160 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr_ex.c @@ -10,14 +10,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -600,5 +598,3 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr_ex.h index 10e017a1041..57fd4d93a7a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_pwr_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -340,5 +338,3 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t #endif /* __STM32F4xx_HAL_PWR_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.c index 02ab62a04ac..a3326f24f6e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.c @@ -14,6 +14,17 @@ * + Errors management and abort functionality * * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -111,7 +122,7 @@ ================================================= [..] (#) HAL_QSPI_GetError() function gives the error raised during the last operation. - (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and + (#) HAL_QSPI_Abort() and HAL_QSPI_Abort_IT() functions aborts any on-going operation and flushes the fifo : (++) In polling mode, the output of the function is done when the transfer complete bit is set and the busy bit cleared. @@ -133,7 +144,7 @@ The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_QSPI_RegisterCallback() to register a user callback, + Use Functions HAL_QSPI_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. @@ -150,7 +161,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_QSPI_UnRegisterCallback() to reset a callback to the default + Use function HAL_QSPI_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) ErrorCallback : callback when error occurs. (+) AbortCpltCallback : callback when abort is completed. @@ -166,12 +177,12 @@ (+) MspDeInitCallback : QSPI MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET + By default, after the HAL_QSPI_Init and if the state is HAL_QSPI_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_QSPI_Init - and @ref HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_QSPI_Init and @ref HAL_QSPI_DeInit + reset to the legacy weak (surcharged) functions in the HAL_QSPI_Init + and HAL_QSPI_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_QSPI_Init and HAL_QSPI_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -179,8 +190,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_QSPI_RegisterCallback before calling @ref HAL_QSPI_DeInit - or @ref HAL_QSPI_Init function. + using HAL_QSPI_RegisterCallback before calling HAL_QSPI_DeInit + or HAL_QSPI_Init function. When The compilation define USE_HAL_QSPI_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -194,17 +205,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -258,6 +258,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void QSPI_DMAError(DMA_HandleTypeDef *hdma); static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout); static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode); /* Exported functions --------------------------------------------------------*/ @@ -285,7 +286,7 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin /** * @brief Initialize the QSPI mode according to the specified parameters * in the QSPI_InitTypeDef and initialize the associated handle. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) @@ -386,7 +387,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) /** * @brief De-Initialize the QSPI peripheral. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) @@ -427,7 +428,7 @@ HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Initialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) @@ -442,7 +443,7 @@ __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) /** * @brief DeInitialize the QSPI MSP. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) @@ -481,7 +482,7 @@ __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) /** * @brief Handle QSPI interrupt request. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) @@ -726,7 +727,7 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; - + /* Error callback */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) hqspi->ErrorCallback(hqspi); @@ -771,9 +772,9 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) /** * @brief Set the command configuration. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @param cmd : structure that contains the command configuration information - * @param Timeout : Timeout duration + * @param Timeout Timeout duration * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ @@ -861,15 +862,14 @@ HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDe /** * @brief Set the command configuration in interrupt mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information * @note This function is used only in Indirect Read or Write Modes * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) { HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -908,7 +908,7 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp hqspi->State = HAL_QSPI_STATE_BUSY; /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); if (status == HAL_OK) { @@ -960,9 +960,9 @@ HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTyp /** * @brief Transmit an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1045,9 +1045,9 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u /** * @brief Receive an amount of data in blocking mode. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param pData pointer to data buffer + * @param Timeout Timeout duration * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1133,8 +1133,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui /** * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @retval HAL status */ @@ -1193,8 +1193,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Read Mode * @retval HAL status */ @@ -1257,8 +1257,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) /** * @brief Send an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer + * @param hqspi QSPI handle + * @param pData pointer to data buffer * @note This function is used only in Indirect Write Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1384,10 +1384,10 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat { /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Enable the QSPI transfer error Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } @@ -1424,8 +1424,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pDat /** * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hqspi : QSPI handle - * @param pData : pointer to data buffer. + * @param hqspi QSPI handle + * @param pData pointer to data buffer. * @note This function is used only in Indirect Read Mode * @note If DMA peripheral access is configured as halfword, the number * of data and the fifo threshold should be aligned on halfword @@ -1542,15 +1542,46 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* 4 Extra words (32-bits) are needed for read operation to guarantee the last data is transferred from DMA FIFO to RAM memory */ WRITE_REG(hqspi->Instance->DLR, (data_size - 1U + 16U)); + + /* Update direction mode bit */ + MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); + + /* Configure QSPI: CCR register with functional as indirect read */ + MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); + + /* Start the transfer by re-writing the address in AR register */ + WRITE_REG(hqspi->Instance->AR, addr_reg); + + /* Enable the DMA Channel */ + if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK) + { + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + + /* Enable the QSPI transfer error Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); + } + else + { + status = HAL_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; + hqspi->State = HAL_QSPI_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hqspi); + } #else /* Configure the direction of the DMA */ hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; -#endif + /* Update direction mode bit */ MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); /* Enable the DMA Channel */ - if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize) == HAL_OK) + if(HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSize)== HAL_OK) { /* Configure QSPI: CCR register with functional as indirect read */ MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); @@ -1560,10 +1591,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Process unlocked */ __HAL_UNLOCK(hqspi); - + /* Enable the QSPI transfer error Interrupt */ __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); - + /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */ SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); } @@ -1576,6 +1607,7 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /* Process unlocked */ __HAL_UNLOCK(hqspi); } +#endif /* QSPI1_V2_1L */ } } else @@ -1600,10 +1632,10 @@ HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData /** * @brief Configure the QSPI Automatic Polling Mode in blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. - * @param Timeout : Timeout duration + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. + * @param Timeout Timeout duration * @note This function is used only in Automatic Polling Mode * @retval HAL status */ @@ -1701,16 +1733,15 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTy /** * @brief Configure the QSPI Automatic Polling Mode in non-blocking mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the polling configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the polling configuration information. * @note This function is used only in Automatic Polling Mode * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg) { HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); /* Check the parameters */ assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode)); @@ -1754,7 +1785,7 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; /* Wait till BUSY flag reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); if (status == HAL_OK) { @@ -1805,9 +1836,9 @@ HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_Comman /** * @brief Configure the Memory Mapped mode. - * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information. - * @param cfg : structure that contains the memory mapped configuration information. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information. + * @param cfg structure that contains the memory mapped configuration information. * @note This function is used only in Memory mapped Mode * @retval HAL status */ @@ -1894,7 +1925,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandT /** * @brief Transfer Error callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) @@ -1909,7 +1940,7 @@ __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Abort completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1924,7 +1955,7 @@ __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Command completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1939,7 +1970,7 @@ __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1954,7 +1985,7 @@ __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1969,7 +2000,7 @@ __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Rx Half Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1984,7 +2015,7 @@ __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Tx Half Transfer completed callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) @@ -1999,7 +2030,7 @@ __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) /** * @brief FIFO Threshold callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) @@ -2014,7 +2045,7 @@ __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Status Match callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) @@ -2029,7 +2060,7 @@ __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Timeout callback. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval None */ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) @@ -2045,8 +2076,8 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) /** * @brief Register a User QSPI Callback * To be used instead of the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be registered + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2060,7 +2091,7 @@ __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) * @arg @ref HAL_QSPI_TIMEOUT_CB_ID QSPI Timeout Callback ID * @arg @ref HAL_QSPI_MSP_INIT_CB_ID QSPI MspInit callback ID * @arg @ref HAL_QSPI_MSP_DEINIT_CB_ID QSPI MspDeInit callback ID - * @param pCallback : pointer to the Callback function + * @param pCallback pointer to the Callback function * @retval status */ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback) @@ -2159,8 +2190,8 @@ HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI /** * @brief Unregister a User QSPI Callback * QSPI Callback is redirected to the weak (surcharged) predefined callback - * @param hqspi : QSPI handle - * @param CallbackId : ID of the callback to be unregistered + * @param hqspi QSPI handle + * @param CallbackId ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_QSPI_ERROR_CB_ID QSPI Error Callback ID * @arg @ref HAL_QSPI_ABORT_CB_ID QSPI Abort Callback ID @@ -2287,7 +2318,7 @@ HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QS /** * @brief Return the QSPI handle state. - * @param hqspi : QSPI handle + * @param hqspi QSPI handle * @retval HAL state */ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) @@ -2298,7 +2329,7 @@ HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi) /** * @brief Return the QSPI error code. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval QSPI Error Code */ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) @@ -2308,7 +2339,7 @@ uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission. -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) @@ -2335,25 +2366,33 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) } } - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); - - /* Wait until TC flag is set to go back in idle state */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); - - if (status == HAL_OK) + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) { - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + + /* Wait until TC flag is set to go back in idle state */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); + + if (status == HAL_OK) + { + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Wait until BUSY flag is reset */ + status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + } - /* Wait until BUSY flag is reset */ - status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); + if (status == HAL_OK) + { + /* Reset functional mode configuration to indirect write mode by default */ + CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); + + /* Update state */ + hqspi->State = HAL_QSPI_STATE_READY; + } } - - if (status == HAL_OK) + else { - /* Reset functional mode configuration to indirect write mode by default */ - CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); - /* Update state */ hqspi->State = HAL_QSPI_STATE_READY; } @@ -2364,7 +2403,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) /** * @brief Abort the current transmission (non-blocking function) -* @param hqspi : QSPI handle +* @param hqspi QSPI handle * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) @@ -2394,7 +2433,7 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) { /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; - + /* Abort Complete callback */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) hqspi->AbortCpltCallback(hqspi); @@ -2405,22 +2444,30 @@ HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) } else { - /* Clear interrupt */ - __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); - - /* Enable the QSPI Transfer Complete Interrupt */ - __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); - - /* Configure QSPI: CR register with Abort request */ - SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) + { + /* Clear interrupt */ + __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); + + /* Enable the QSPI Transfer Complete Interrupt */ + __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); + + /* Configure QSPI: CR register with Abort request */ + SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); + } + else + { + /* Change state of QSPI */ + hqspi->State = HAL_QSPI_STATE_READY; + } } } return status; } /** @brief Set QSPI timeout. - * @param hqspi : QSPI handle. - * @param Timeout : Timeout for the QSPI memory access. + * @param hqspi QSPI handle. + * @param Timeout Timeout for the QSPI memory access. * @retval None */ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) @@ -2429,8 +2476,8 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) } /** @brief Set QSPI Fifo threshold. - * @param hqspi : QSPI handle. - * @param Threshold : Threshold of the Fifo (value between 1 and 16). + * @param hqspi QSPI handle. + * @param Threshold Threshold of the Fifo (value between 1 and 16). * @retval HAL status */ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) @@ -2462,7 +2509,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t } /** @brief Get QSPI Fifo threshold. - * @param hqspi : QSPI handle. + * @param hqspi QSPI handle. * @retval Fifo threshold (value between 1 and 16) */ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) @@ -2471,8 +2518,8 @@ uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi) } /** @brief Set FlashID. - * @param hqspi : QSPI handle. - * @param FlashID : Index of the flash memory to be accessed. + * @param hqspi QSPI handle. + * @param FlashID Index of the flash memory to be accessed. * This parameter can be a value of @ref QSPI_Flash_Select. * @note The FlashID is ignored when dual flash mode is enabled. * @retval HAL status @@ -2521,7 +2568,7 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashI /** * @brief DMA QSPI receive process complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -2535,7 +2582,7 @@ static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) @@ -2549,7 +2596,7 @@ static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI receive process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2565,7 +2612,7 @@ static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI transmit process half complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -2581,7 +2628,7 @@ static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI communication error callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) @@ -2606,7 +2653,7 @@ static void QSPI_DMAError(DMA_HandleTypeDef *hdma) /** * @brief DMA QSPI abort complete callback. - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) @@ -2645,11 +2692,11 @@ static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) /** * @brief Wait for a flag state until timeout. - * @param hqspi : QSPI handle - * @param Flag : Flag checked - * @param State : Value of the flag expected - * @param Tickstart : Tick start value - * @param Timeout : Duration of the timeout + * @param hqspi QSPI handle + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Tickstart Tick start value + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, @@ -2674,10 +2721,35 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp } /** - * @brief Configure the communication registers. + * @brief Wait for a flag state until timeout using CPU cycle. * @param hqspi : QSPI handle - * @param cmd : structure that contains the command configuration information - * @param FunctionalMode : functional mode to configured + * @param Flag : Flag checked + * @param State : Value of the flag expected + * @param Timeout : Duration of the timeout + * @retval HAL status + */ +static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t Timeout) +{ + __IO uint32_t count = Timeout * (SystemCoreClock / 16U / 1000U); + do + { + if (count-- == 0U) + { + hqspi->State = HAL_QSPI_STATE_ERROR; + hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; + return HAL_TIMEOUT; + } + } + while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State); + + return HAL_OK; +} + +/** + * @brief Configure the communication registers. + * @param hqspi QSPI handle + * @param cmd structure that contains the command configuration information + * @param FunctionalMode functional mode to configured * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode @@ -2840,6 +2912,4 @@ static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uin * @} */ -#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* defined(QUADSPI) */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.h index 97e9324f34c..56287af6ceb 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_qspi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -457,7 +456,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); * @{ */ /** @brief Reset QSPI handle state. - * @param __HANDLE__ : QSPI handle. + * @param __HANDLE__ QSPI handle. * @retval None */ #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) @@ -471,20 +470,20 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #endif /** @brief Enable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable the QSPI peripheral. - * @param __HANDLE__ : specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -497,8 +496,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** @brief Disable the specified QSPI interrupt. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -510,8 +509,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Check whether the specified QSPI interrupt source is enabled or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -524,8 +523,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); /** * @brief Check whether the selected QSPI flag is set or not. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI flag to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Timeout flag @@ -538,8 +537,8 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__ : specifies the QSPI Handle. - * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Timeout flag * @arg QSPI_FLAG_SM: QSPI Status match flag @@ -742,12 +741,10 @@ HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint3 * @} */ -#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ +#endif /* defined(QUADSPI) */ #ifdef __cplusplus } #endif #endif /* STM32F4xx_HAL_QSPI_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.c index 552ef18ed80..8e494e630ef 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.c @@ -54,14 +54,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -481,7 +479,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -519,7 +517,7 @@ __weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruc /* Get Start Tick */ tickstart = HAL_GetTick(); - /* Wait till PLL is ready */ + /* Wait till PLL is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) @@ -1122,4 +1120,3 @@ __weak void HAL_RCC_CSSCallback(void) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.h index 2eeff3482eb..3dafcd16ddd 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -1409,7 +1407,7 @@ void HAL_RCC_CSSCallback(void); ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \ ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31)) -#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U) +#define IS_RCC_PLLM_VALUE(VALUE) ((2U <= (VALUE)) && ((VALUE) <= 63U)) #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U)) @@ -1459,4 +1457,3 @@ void HAL_RCC_CSSCallback(void); #endif /* __STM32F4xx_HAL_RCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc_ex.c index e42b850a62e..507662819c0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc_ex.c @@ -10,14 +10,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -3784,4 +3782,3 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc_ex.h index df6a66ab14d..bfba11f178e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rcc_ex.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -528,7 +526,7 @@ typedef struct * @{ */ #define RCC_I2SCLKSOURCE_PLLI2S 0x00000000U -#define RCC_I2SCLKSOURCE_EXT 0x00000001U +#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC /** * @} */ @@ -6103,7 +6101,7 @@ typedef struct * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin * used as I2S clock source. */ -#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__)) +#define __HAL_RCC_I2S_CONFIG(__SOURCE__) (MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (__SOURCE__))) /** @brief Macro to get the I2S clock source (I2SCLK). @@ -7111,4 +7109,3 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void); #endif /* __STM32F4xx_HAL_RCC_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.c index 47c313c89f8..bd50438df19 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.c @@ -9,6 +9,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -31,8 +42,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_RNG_RegisterCallback() to register a user callback. - Function @ref HAL_RNG_RegisterCallback() allows to register following callbacks: + Use Function HAL_RNG_RegisterCallback() to register a user callback. + Function HAL_RNG_RegisterCallback() allows to register following callbacks: (+) ErrorCallback : RNG Error Callback. (+) MspInitCallback : RNG MspInit. (+) MspDeInitCallback : RNG MspDeInit. @@ -40,9 +51,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_RNG_UnRegisterCallback() to reset a callback to the default + Use function HAL_RNG_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_RNG_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) ErrorCallback : RNG Error Callback. @@ -51,16 +62,16 @@ [..] For specific callback ReadyDataCallback, use dedicated register callbacks: - respectively @ref HAL_RNG_RegisterReadyDataCallback() , @ref HAL_RNG_UnRegisterReadyDataCallback(). + respectively HAL_RNG_RegisterReadyDataCallback() , HAL_RNG_UnRegisterReadyDataCallback(). [..] - By default, after the @ref HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET + By default, after the HAL_RNG_Init() and when the state is HAL_RNG_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - example @ref HAL_RNG_ErrorCallback(). + example HAL_RNG_ErrorCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_RNG_Init() - and @ref HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_RNG_Init() and @ref HAL_RNG_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_RNG_Init() + and HAL_RNG_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_RNG_Init() and HAL_RNG_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -69,8 +80,8 @@ in HAL_RNG_STATE_READY or HAL_RNG_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RNG_RegisterCallback() before calling @ref HAL_RNG_DeInit() - or @ref HAL_RNG_Init() function. + using HAL_RNG_RegisterCallback() before calling HAL_RNG_DeInit() + or HAL_RNG_Init() function. [..] When The compilation define USE_HAL_RNG_REGISTER_CALLBACKS is set to 0 or @@ -79,17 +90,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -129,8 +129,8 @@ */ /** @addtogroup RNG_Exported_Functions_Group1 - * @brief Initialization and configuration functions - * + * @brief Initialization and configuration functions + * @verbatim =============================================================================== ##### Initialization and configuration functions ##### @@ -296,7 +296,8 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -368,7 +369,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call /** * @brief Unregister an RNG Callback - * RNG callabck is redirected to the weak predefined callback + * RNG callback is redirected to the weak predefined callback * @param hrng RNG handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -515,8 +516,8 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng) */ /** @addtogroup RNG_Exported_Functions_Group2 - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -562,11 +563,15 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t { if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { - hrng->State = HAL_RNG_STATE_READY; - hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - return HAL_ERROR; + /* New check to avoid false timeout detection in case of preemption */ + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + hrng->State = HAL_RNG_STATE_READY; + hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + return HAL_ERROR; + } } } @@ -726,6 +731,8 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) /* Clear the clock error flag */ __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI | RNG_IT_SEI); + + return; } /* Check RNG data ready interrupt occurred */ @@ -803,8 +810,8 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) /** @addtogroup RNG_Exported_Functions_Group3 - * @brief Peripheral State functions - * + * @brief Peripheral State functions + * @verbatim =============================================================================== ##### Peripheral State functions ##### @@ -832,7 +839,7 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @brief Return the RNG handle error code. * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval RNG Error Code -*/ + */ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) { /* Return RNG Error Code */ @@ -858,4 +865,3 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.h index d2c9937c47a..7d4dca1ebd0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rng.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -77,7 +76,7 @@ typedef enum typedef struct __RNG_HandleTypeDef #else typedef struct -#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ { RNG_TypeDef *Instance; /*!< Register base address */ @@ -85,7 +84,7 @@ typedef struct __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ - __IO uint32_t ErrorCode; /*!< RNG Error code */ + __IO uint32_t ErrorCode; /*!< RNG Error code */ uint32_t RandomNumber; /*!< Last Generated RNG Data */ @@ -156,14 +155,14 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t /** @defgroup RNG_Error_Definition RNG Error Definition * @{ */ -#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ +#define HAL_RNG_ERROR_NONE 0x00000000U /*!< No error */ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) #define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ -#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ +#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ -#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ /** * @} */ @@ -189,7 +188,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t } while(0U) #else #define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET) -#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */ +#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ /** * @brief Enables the RNG peripheral. @@ -284,7 +283,8 @@ void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_RNG_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, + pRNG_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback); @@ -298,8 +298,10 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); /** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions * @{ */ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */ -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ +uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef + *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */ +uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef + *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); @@ -333,8 +335,8 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); ((IT) == RNG_IT_SEI)) #define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ - ((FLAG) == RNG_FLAG_CECS) || \ - ((FLAG) == RNG_FLAG_SECS)) + ((FLAG) == RNG_FLAG_CECS) || \ + ((FLAG) == RNG_FLAG_SECS)) /** * @} @@ -357,4 +359,3 @@ uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); #endif /* STM32F4xx_HAL_RNG_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.c index c12879e3076..f4d5dbc016a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.c @@ -4,21 +4,32 @@ * @author MCD Application Team * @brief RTC HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) peripheral: + * functionalities of the Real-Time Clock (RTC) peripheral: * + Initialization and de-initialization functions - * + RTC Time and Date functions - * + RTC Alarm functions + * + RTC Calendar (Time and Date) configuration functions + * + RTC Alarms (Alarm A and Alarm B) configuration functions * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== - ##### Backup Domain Operating Condition ##### + ##### RTC and Backup Domain Operating Condition ##### ============================================================================== [..] The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the VBAT voltage when the main VDD supply is powered off. - To retain the content of the RTC backup registers, backup SRAM, and supply + To retain the content of the RTC backup registers, BKP SRAM, and supply the RTC when VDD is turned off, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. @@ -26,7 +37,7 @@ off, the VBAT pin powers the following blocks: (#) The RTC (#) The LSE oscillator - (#) The backup SRAM when the low power backup regulator is enabled + (#) The BKP SRAM when the low power backup regulator is enabled (#) PC13 to PC15 I/Os, plus PI8 I/O (when available) [..] When the backup domain is supplied by VDD (analog switch connected to VDD), @@ -44,9 +55,10 @@ ##### Backup Domain Reset ##### ================================================================== [..] The backup domain reset sets all RTC registers and the RCC_BDCR register - to their reset values. The BKPSRAM is not affected by this reset. The only - way to reset the BKPSRAM is through the Flash interface by requesting - a protection level change from 1 to 0. + to their reset values. + The BKP SRAM is not affected by this reset. The only way to reset the BKP + SRAM is through the Flash interface by requesting a protection level + change from 1 to 0. [..] A backup domain reset is generated when one of the following events occurs: (#) Software reset, triggered by setting the BDRST bit in the RCC Backup domain control register (RCC_BDCR). @@ -54,19 +66,18 @@ ##### Backup Domain Access ##### ================================================================== - [..] After reset, the backup domain (RTC registers, RTC backup data - registers and backup SRAM) is protected against possible unwanted write - accesses. + [..] After reset, the backup domain (RTC registers, RTC backup data registers + and BKP SRAM) is protected against possible unwanted write accesses. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the - __HAL_RCC_PWR_CLK_ENABLE() function. + __HAL_RCC_PWR_CLK_ENABLE() macro. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. - (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. + (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() macro. + (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() macro. - - ##### How to use this driver ##### - ================================================================== + ============================================================================== + ##### How to use this driver ##### + ============================================================================== [..] (+) Enable the RTC domain access (see description in the section above). (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour @@ -77,13 +88,21 @@ [..] (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() and HAL_RTC_SetDate() functions. - (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. + (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() + functions. + (+) To manage the RTC summer or winter time change, use the following + functions: + (++) HAL_RTC_DST_Add1Hour() or HAL_RTC_DST_Sub1Hour to add or subtract + 1 hour from the calendar time. + (++) HAL_RTC_DST_SetStoreOperation() or HAL_RTC_DST_ClearStoreOperation + to memorize whether the time change has been performed or not. *** Alarm configuration *** =========================== [..] (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. + You can also configure the RTC Alarm with interrupt mode using the + HAL_RTC_SetAlarm_IT() function. (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. ##### RTC and low power modes ##### @@ -91,30 +110,28 @@ [..] The MCU can be woken up from a low power mode by an RTC alternate function. [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), - RTC wake-up, RTC tamper event detection and RTC time stamp event detection. + RTC wakeup, RTC tamper event detection and RTC timestamp event detection. These RTC alternate functions can wake up the system from the Stop and Standby low power modes. [..] The system can also wake up from low power modes without depending - on an external interrupt (Auto-wake-up mode), by using the RTC alarm - or the RTC wake-up events. + on an external interrupt (Auto-wakeup mode), by using the RTC alarm + or the RTC wakeup events. [..] The RTC provides a programmable time base for waking up from the Stop or Standby mode at regular intervals. - Wake-up from STOP and STANDBY modes is possible only when the RTC clock source - is LSE or LSI. + Wakeup from STOP and STANDBY modes is possible only when the RTC clock + source is LSE or LSI. *** Callback registration *** ============================================= - [..] The compilation define USE_HAL_RTC_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. - + Use Function HAL_RTC_RegisterCallback() to register an interrupt callback. [..] - Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: + Function HAL_RTC_RegisterCallback() allows to register following callbacks: (+) AlarmAEventCallback : RTC Alarm A Event callback. (+) AlarmBEventCallback : RTC Alarm B Event callback. - (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) TimeStampEventCallback : RTC Timestamp Event callback. (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. (+) Tamper1EventCallback : RTC Tamper 1 Event callback. (+) Tamper2EventCallback : RTC Tamper 2 Event callback. @@ -123,58 +140,44 @@ [..] This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - [..] - Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default + Use function HAL_RTC_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) AlarmAEventCallback : RTC Alarm A Event callback. (+) AlarmBEventCallback : RTC Alarm B Event callback. - (+) TimeStampEventCallback : RTC TimeStamp Event callback. + (+) TimeStampEventCallback : RTC Timestamp Event callback. (+) WakeUpTimerEventCallback : RTC WakeUpTimer Event callback. (+) Tamper1EventCallback : RTC Tamper 1 Event callback. (+) Tamper2EventCallback : RTC Tamper 2 Event callback. (+) MspInitCallback : RTC MspInit callback. (+) MspDeInitCallback : RTC MspDeInit callback. - [..] - By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, - all callbacks are set to the corresponding weak functions : - examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback(). - Exception done for MspInit and MspDeInit callbacks that are reset to the legacy weak function - in the @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() only when these callbacks are null - (not registered beforehand). - If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - + By default, after the HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, + all callbacks are set to the corresponding weak functions: + examples AlarmAEventCallback(), WakeUpTimerEventCallback(). + Exception done for MspInit() and MspDeInit() callbacks that are reset to the + legacy weak function in the HAL_RTC_Init()/HAL_RTC_DeInit() only + when these callbacks are null (not registered beforehand). + If not, MspInit() or MspDeInit() are not null, HAL_RTC_Init()/HAL_RTC_DeInit() + keep and use the user MspInit()/MspDeInit() callbacks (registered beforehand). [..] Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() - or @ref HAL_RTC_Init() function. - + Exception done MspInit()/MspDeInit() that can be registered/unregistered + in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state. + Thus registered (user) MspInit()/MspDeInit() callbacks can be used during the + Init/DeInit. + In that case first register the MspInit()/MspDeInit() user callbacks + using HAL_RTC_RegisterCallback() before calling HAL_RTC_DeInit() + or HAL_RTC_Init() functions. [..] When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - @endverbatim + not defined, the callback registration feature is not available and all + callbacks are set to the corresponding weak functions. - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * + @endverbatim ****************************************************************************** */ @@ -186,7 +189,7 @@ */ /** @defgroup RTC RTC - * @brief RTC HAL module driver + * @brief RTC HAL module driver * @{ */ @@ -204,8 +207,8 @@ */ /** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * + * @brief Initialization and Configuration functions + * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### @@ -216,7 +219,7 @@ RTC registers synchronization check and reference clock detection enable. (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. + (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. (++) When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize power consumption. (#) All RTC registers are Write protected. Writing to the RTC registers @@ -226,11 +229,11 @@ and its value can be updated. When the initialization sequence is complete, the calendar restarts counting after 4 RTCCLK cycles. (#) To read the calendar through the shadow registers after Calendar - initialization, calendar update or after wake-up from low power modes + initialization, calendar update or after wakeup from low power modes the software must first clear the RSF flag. The software must then wait until it is set again before reading the calendar, which means that the calendar registers have been correctly copied into the - RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function + RTC_TR and RTC_DR shadow registers. The HAL_RTC_WaitForSynchro() function implements the above software sequence (RSF clear and RSF check). @endverbatim @@ -245,22 +248,25 @@ */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { - /* Check the RTC peripheral state */ - if(hrtc == NULL) + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check RTC handler validity */ + if (hrtc == NULL) { - return HAL_ERROR; + return HAL_ERROR; } /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); - assert_param (IS_RTC_OUTPUT(hrtc->Init.OutPut)); - assert_param (IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); + assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut)); + assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity)); assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType)); #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if(hrtc->State == HAL_RTC_STATE_RESET) + if (hrtc->State == HAL_RTC_STATE_RESET) { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; @@ -270,22 +276,24 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ +#if defined(RTC_TAMPER2_SUPPORT) hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ +#endif /* RTC_TAMPER2_SUPPORT */ - if(hrtc->MspInitCallback == NULL) + if (hrtc->MspInitCallback == NULL) { hrtc->MspInitCallback = HAL_RTC_MspInit; } /* Init the low level hardware */ hrtc->MspInitCallback(hrtc); - if(hrtc->MspDeInitCallback == NULL) + if (hrtc->MspDeInitCallback == NULL) { hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; } } -#else - if(hrtc->State == HAL_RTC_STATE_RESET) +#else /* USE_HAL_RTC_REGISTER_CALLBACKS */ + if (hrtc->State == HAL_RTC_STATE_RESET) { /* Allocate lock resource and initialize it */ hrtc->Lock = HAL_UNLOCKED; @@ -293,76 +301,71 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); } -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) + /* Check whether the calendar needs to be initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - return HAL_ERROR; - } - else - { - /* Clear RTC_CR FMT, OSEL and POL Bits */ - hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); - /* Set RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - - /* Configure the RTC PRER */ - hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); - hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16U); - - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + if (status == HAL_OK) { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Clear RTC_CR FMT, OSEL and POL Bits */ + hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL)); + /* Set RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity); - hrtc->State = HAL_RTC_STATE_ERROR; + /* Configure the RTC PRER */ + hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv); + hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos); - return HAL_ERROR; - } + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); } - hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE; - hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); + if (status == HAL_OK) + { + hrtc->Instance->TAFCR &= (uint32_t)~RTC_OUTPUT_TYPE_PUSHPULL; + hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); + } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* The calendar is already initialized */ + status = HAL_OK; + } - /* Set RTC state */ + if (status == HAL_OK) + { hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; } + + return status; } /** * @brief DeInitializes the RTC peripheral * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @note This function doesn't reset the RTC Backup Data registers. + * @note This function does not reset the RTC Backup Data registers. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart = 0U; + HAL_StatusTypeDef status = HAL_ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; @@ -370,116 +373,76 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - return HAL_ERROR; - } - else + if (status == HAL_OK) { - /* Reset TR, DR and CR registers */ + /* Reset RTC registers */ hrtc->Instance->TR = 0x00000000U; - hrtc->Instance->DR = 0x00002101U; - /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= 0x00000007U; - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait till WUTWF flag is set and if Time out is reached exit */ - while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET) - { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - return HAL_TIMEOUT; - } - } - - /* Reset all RTC CR register bits */ - hrtc->Instance->CR &= 0x00000000U; - hrtc->Instance->WUTR = 0x0000FFFFU; - hrtc->Instance->PRER = 0x007F00FFU; + hrtc->Instance->DR = (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0); + hrtc->Instance->CR &= 0x00000000U; + hrtc->Instance->WUTR = RTC_WUTR_WUT; + hrtc->Instance->PRER = (uint32_t)(RTC_PRER_PREDIV_A | 0x000000FFU); hrtc->Instance->CALIBR = 0x00000000U; - hrtc->Instance->ALRMAR = 0x00000000U; - hrtc->Instance->ALRMBR = 0x00000000U; - hrtc->Instance->SHIFTR = 0x00000000U; - hrtc->Instance->CALR = 0x00000000U; + hrtc->Instance->ALRMAR = 0x00000000U; + hrtc->Instance->ALRMBR = 0x00000000U; + hrtc->Instance->CALR = 0x00000000U; + hrtc->Instance->SHIFTR = 0x00000000U; hrtc->Instance->ALRMASSR = 0x00000000U; hrtc->Instance->ALRMBSSR = 0x00000000U; - /* Reset ISR register and exit initialization mode */ - hrtc->Instance->ISR = 0x00000000U; - - /* Reset Tamper and alternate functions configuration register */ - hrtc->Instance->TAFCR = 0x00000000U; - - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - return HAL_ERROR; - } - } + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); -#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - if(hrtc->MspDeInitCallback == NULL) + if (status == HAL_OK) { - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - } + /* Reset Tamper and alternate functions configuration register */ + hrtc->Instance->TAFCR = 0x00000000U; - /* DeInit the low level hardware: CLOCK, NVIC.*/ - hrtc->MspDeInitCallback(hrtc); +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + if (hrtc->MspDeInitCallback == NULL) + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } -#else - /* De-Initialize RTC MSP */ - HAL_RTC_MspDeInit(hrtc); -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + /* DeInit the low level hardware: CLOCK, NVIC.*/ + hrtc->MspDeInitCallback(hrtc); +#else /* USE_HAL_RTC_REGISTER_CALLBACKS */ + /* De-Initialize RTC MSP */ + HAL_RTC_MspDeInit(hrtc); +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - hrtc->State = HAL_RTC_STATE_RESET; + hrtc->State = HAL_RTC_STATE_RESET; + } /* Release Lock */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /** - * @brief Register a User RTC Callback + * @brief Registers a User RTC Callback * To be used instead of the weak predefined callback - * @param hrtc RTC handle + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID - * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID - * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @note HAL_RTC_TAMPER2_EVENT_CB_ID is not applicable to all devices. * @param pCallback pointer to the Callback function * @retval HAL status */ @@ -487,7 +450,7 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -495,64 +458,66 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call /* Process locked */ __HAL_LOCK(hrtc); - if(HAL_RTC_STATE_READY == hrtc->State) + if (HAL_RTC_STATE_READY == hrtc->State) { switch (CallbackID) { - case HAL_RTC_ALARM_A_EVENT_CB_ID : - hrtc->AlarmAEventCallback = pCallback; - break; - - case HAL_RTC_ALARM_B_EVENT_CB_ID : - hrtc->AlarmBEventCallback = pCallback; - break; - - case HAL_RTC_TIMESTAMP_EVENT_CB_ID : - hrtc->TimeStampEventCallback = pCallback; - break; - - case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : - hrtc->WakeUpTimerEventCallback = pCallback; - break; - - case HAL_RTC_TAMPER1_EVENT_CB_ID : - hrtc->Tamper1EventCallback = pCallback; - break; - - case HAL_RTC_TAMPER2_EVENT_CB_ID : - hrtc->Tamper2EventCallback = pCallback; - break; - - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = pCallback; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = pCallback; + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = pCallback; + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = pCallback; + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = pCallback; + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = pCallback; + break; + +#if defined(RTC_TAMPER2_SUPPORT) + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = pCallback; + break; +#endif /* RTC_TAMPER2_SUPPORT */ + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(HAL_RTC_STATE_RESET == hrtc->State) + else if (HAL_RTC_STATE_RESET == hrtc->State) { switch (CallbackID) { - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = pCallback; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = pCallback; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = pCallback; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -568,19 +533,21 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call } /** - * @brief Unregister an RTC Callback + * @brief Unregisters an RTC Callback * RTC callabck is redirected to the weak predefined callback - * @param hrtc RTC handle + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: * @arg @ref HAL_RTC_ALARM_A_EVENT_CB_ID Alarm A Event Callback ID * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID - * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID - * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wake-Up Timer Event Callback ID + * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID Timestamp Event Callback ID + * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID Wakeup Timer Event Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID + * @note HAL_RTC_TAMPER2_EVENT_CB_ID is not applicable to all devices. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) @@ -590,64 +557,66 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca /* Process locked */ __HAL_LOCK(hrtc); - if(HAL_RTC_STATE_READY == hrtc->State) + if (HAL_RTC_STATE_READY == hrtc->State) { switch (CallbackID) { - case HAL_RTC_ALARM_A_EVENT_CB_ID : - hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ - break; - - case HAL_RTC_ALARM_B_EVENT_CB_ID : - hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ - break; - - case HAL_RTC_TIMESTAMP_EVENT_CB_ID : - hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ - break; - - case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : - hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ - break; - - case HAL_RTC_TAMPER1_EVENT_CB_ID : - hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ - break; - - case HAL_RTC_TAMPER2_EVENT_CB_ID : - hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ - break; - - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = HAL_RTC_MspInit; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RTC_ALARM_A_EVENT_CB_ID : + hrtc->AlarmAEventCallback = HAL_RTC_AlarmAEventCallback; /* Legacy weak AlarmAEventCallback */ + break; + + case HAL_RTC_ALARM_B_EVENT_CB_ID : + hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ + break; + + case HAL_RTC_TIMESTAMP_EVENT_CB_ID : + hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ + break; + + case HAL_RTC_WAKEUPTIMER_EVENT_CB_ID : + hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ + break; + + case HAL_RTC_TAMPER1_EVENT_CB_ID : + hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ + break; + +#if defined(RTC_TAMPER2_SUPPORT) + case HAL_RTC_TAMPER2_EVENT_CB_ID : + hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ + break; +#endif /* RTC_TAMPER2_SUPPORT */ + + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } - else if(HAL_RTC_STATE_RESET == hrtc->State) + else if (HAL_RTC_STATE_RESET == hrtc->State) { switch (CallbackID) { - case HAL_RTC_MSPINIT_CB_ID : - hrtc->MspInitCallback = HAL_RTC_MspInit; - break; - - case HAL_RTC_MSPDEINIT_CB_ID : - hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; + case HAL_RTC_MSPINIT_CB_ID : + hrtc->MspInitCallback = HAL_RTC_MspInit; + break; + + case HAL_RTC_MSPDEINIT_CB_ID : + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + break; + + default : + /* Return error status */ + status = HAL_ERROR; + break; } } else @@ -669,12 +638,13 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca * the configuration information for RTC. * @retval None */ -__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) +__weak void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspInit could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTC_MspInit could be implemented in the user file */ } @@ -684,12 +654,13 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) * the configuration information for RTC. * @retval None */ -__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) +__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_MspDeInit could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTC_MspDeInit could be implemented in the user file */ } @@ -698,8 +669,8 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) */ /** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions - * @brief RTC Time and Date functions - * + * @brief RTC Time and Date functions + * @verbatim =============================================================================== ##### RTC Time and Date functions ##### @@ -716,6 +687,8 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param sTime Pointer to Time structure + * @note DayLightSaving and StoreOperation interfaces are deprecated. + * To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions. * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format @@ -725,8 +698,9 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { uint32_t tmpreg = 0U; + HAL_StatusTypeDef status; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving)); assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation)); @@ -736,9 +710,9 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sTime->Hours)); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); @@ -751,14 +725,14 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim assert_param(IS_RTC_MINUTES(sTime->Minutes)); assert_param(IS_RTC_SECONDS(sTime->Seconds)); - tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ - (((uint32_t)sTime->TimeFormat) << 16U)); + tmpreg = (uint32_t)(( (uint32_t)RTC_ByteToBcd2(sTime->Hours) << RTC_TR_HU_Pos) | \ + ( (uint32_t)RTC_ByteToBcd2(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ( (uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \ + (((uint32_t)sTime->TimeFormat) << RTC_TR_PM_Pos)); } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sTime->Hours))); assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); @@ -770,69 +744,45 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim } assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds))); - tmpreg = (((uint32_t)(sTime->Hours) << 16U) | \ - ((uint32_t)(sTime->Minutes) << 8U) | \ - ((uint32_t)sTime->Seconds) | \ - ((uint32_t)(sTime->TimeFormat) << 16U)); + tmpreg = (((uint32_t)(sTime->Hours) << RTC_TR_HU_Pos) | \ + ((uint32_t)(sTime->Minutes) << RTC_TR_MNU_Pos) | \ + ((uint32_t) sTime->Seconds) | \ + ((uint32_t)(sTime->TimeFormat) << RTC_TR_PM_Pos)); } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + if (status == HAL_OK) { /* Set the RTC_TR register */ hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); - /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; + /* Clear the bits to be configured (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_BKP; - /* This interface is deprecated. To manage Daylight Saving Time, please use HAL_RTC_DST_xxx functions */ + /* Configure the RTC_CR register (Deprecated. Use HAL_RTC_DST_xxx functions instead) */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } + status = RTC_ExitInitMode(hrtc); + } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } - hrtc->State = HAL_RTC_STATE_READY; + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_OK; - } + return status; } /** @@ -844,13 +794,19 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format - * @note You can use SubSeconds and SecondFraction (sTime structure fields returned) to convert SubSeconds - * value in second fraction ratio with time unit following generic formula: - * Second fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit - * This conversion can be performed only if no shift operation is pending (ie. SHFP=0) when PREDIV_S >= SS - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until current date is read. + * @note You can use SubSeconds and SecondFraction (sTime structure fields + * returned) to convert SubSeconds value in second fraction ratio with + * time unit following generic formula: + * Second fraction ratio * time_unit = + * [(SecondFraction - SubSeconds) / (SecondFraction + 1)] * time_unit + * This conversion can be performed only if no shift operation is pending + * (ie. SHFP=0) when PREDIV_S >= SS + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the + * values in the higher-order calendar shadow registers to ensure + * consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers + * until current date is read to ensure consistency between the time and + * date values. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) @@ -860,7 +816,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - /* Get subseconds structure field from the corresponding register */ + /* Get subseconds value from the corresponding register */ sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR); /* Get SecondFraction structure field from the corresponding register field*/ @@ -870,13 +826,13 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16U); - sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); - sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); - sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16U); + sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> RTC_TR_HU_Pos); + sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); + sTime->Seconds = (uint8_t)( tmpreg & (RTC_TR_ST | RTC_TR_SU)); + sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> RTC_TR_PM_Pos); /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { /* Convert the time structure parameters to Binary format */ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); @@ -901,32 +857,33 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { uint32_t datetmpreg = 0U; + HAL_StatusTypeDef status; - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - /* Process Locked */ - __HAL_LOCK(hrtc); + /* Process Locked */ + __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; - if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) + if ((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U)) { sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU); } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { assert_param(IS_RTC_YEAR(sDate->Year)); assert_param(IS_RTC_MONTH(sDate->Month)); assert_param(IS_RTC_DATE(sDate->Date)); - datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ - ((uint32_t)sDate->WeekDay << 13U)); + datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << RTC_DR_YU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \ + ((uint32_t)sDate->WeekDay << RTC_DR_WDU_Pos)); } else { @@ -934,64 +891,39 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(sDate->Month))); assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(sDate->Date))); - datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \ - (((uint32_t)sDate->Month) << 8U) | \ - ((uint32_t)sDate->Date) | \ - (((uint32_t)sDate->WeekDay) << 13U)); + datetmpreg = ((((uint32_t)sDate->Year) << RTC_DR_YU_Pos) | \ + (((uint32_t)sDate->Month) << RTC_DR_MU_Pos) | \ + ((uint32_t) sDate->Date) | \ + (((uint32_t)sDate->WeekDay) << RTC_DR_WDU_Pos)); } /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + if (status == HAL_OK) { /* Set the RTC_DR register */ hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - - /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - } + status = RTC_ExitInitMode(hrtc); + } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; + } - hrtc->State = HAL_RTC_STATE_READY ; + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_OK; - } + return status; } /** @@ -1003,9 +935,12 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format - * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers to ensure consistency between the time and date values. - * Reading RTC current time locks the values in calendar shadow registers until Current date is read. + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the + * values in the higher-order calendar shadow registers to ensure + * consistency between the time and date values. + * Reading RTC current time locks the values in calendar shadow registers + * until current date is read to ensure consistency between the time and + * date values. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) @@ -1019,18 +954,18 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); /* Fill the structure fields with the read parameters */ - sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16U); - sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8U); - sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU)); - sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13U); + sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos); + sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos); + sDate->Date = (uint8_t) (datetmpreg & (RTC_DR_DT | RTC_DR_DU)); + sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> RTC_DR_WDU_Pos); /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { /* Convert the date structure parameters to Binary format */ - sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); + sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month); - sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); + sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date); } return HAL_OK; } @@ -1040,8 +975,8 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ /** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions - * @brief RTC Alarm functions - * + * @brief RTC Alarm functions + * @verbatim =============================================================================== ##### RTC Alarm functions ##### @@ -1061,12 +996,16 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { uint32_t tickstart = 0U; - uint32_t tmpreg = 0U, subsecondtmpreg = 0U; + uint32_t tmpreg = 0U; + uint32_t subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1079,11 +1018,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state to BUSY */ hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == RTC_FORMAT_BIN) + /* Check the data format (binary or BCD) and store the Alarm time and date + configuration accordingly */ + if (Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); @@ -1096,7 +1038,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); } @@ -1105,17 +1047,17 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); @@ -1129,7 +1071,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } @@ -1138,37 +1080,41 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t) sAlarm->AlarmMask)); } - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + /* Store the Alarm subseconds configuration */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | \ + (uint32_t)(sAlarm->AlarmSubSecondMask)); /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) + if (sAlarm->Alarm == RTC_ALARM_A) { - /* Disable the Alarm A interrupt */ + /* Disable the Alarm A */ __HAL_RTC_ALARMA_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ + /* In case interrupt mode is used, the interrupt source must be disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); + /* Clear the Alarm flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); + /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1183,26 +1129,29 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ + /* Configure the Alarm A Subseconds register */ hrtc->Instance->ALRMASSR = subsecondtmpreg; /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMA_ENABLE(hrtc); } else { - /* Disable the Alarm B interrupt */ + /* Disable the Alarm B */ __HAL_RTC_ALARMB_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ + /* In case interrupt mode is used, the interrupt source must be disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); + /* Clear the Alarm flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1217,7 +1166,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Sub Second register */ + /* Configure the Alarm B Subseconds register */ hrtc->Instance->ALRMBSSR = subsecondtmpreg; /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMB_ENABLE(hrtc); @@ -1226,7 +1175,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ + /* Change RTC state back to READY */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1236,7 +1185,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } /** - * @brief Sets the specified RTC Alarm with Interrupt + * @brief Sets the specified RTC Alarm with Interrupt. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param sAlarm Pointer to Alarm structure @@ -1244,12 +1193,16 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format * @arg RTC_FORMAT_BCD: BCD data format + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tmpreg = 0U, subsecondtmpreg = 0U; - __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U) ; + __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + uint32_t tmpreg = 0U; + uint32_t subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); @@ -1262,11 +1215,14 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state to BUSY */ hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == RTC_FORMAT_BIN) + /* Check the data format (binary or BCD) and store the Alarm time and date + configuration accordingly */ + if (Format == RTC_FORMAT_BIN) { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); @@ -1279,7 +1235,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay)); } @@ -1287,17 +1243,18 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); } - tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ ((uint32_t)sAlarm->AlarmMask)); } else { - if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) + if ((hrtc->Instance->CR & RTC_CR_FMT) != 0U) { assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); @@ -1311,7 +1268,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes))); assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds))); - if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) + if (sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE) { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } @@ -1319,30 +1276,33 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef { assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); } - tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \ - ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \ - ((uint32_t) sAlarm->AlarmTime.Seconds) | \ - ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \ - ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \ - ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ - ((uint32_t)sAlarm->AlarmMask)); + + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + ((uint32_t) sAlarm->AlarmTime.Seconds) | \ + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_TR_PM_Pos) | \ + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + ((uint32_t) sAlarm->AlarmDateWeekDaySel) | \ + ((uint32_t) sAlarm->AlarmMask)); } - /* Configure the Alarm A or Alarm B Sub Second registers */ - subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask)); + + /* Store the Alarm subseconds configuration */ + subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | \ + (uint32_t)(sAlarm->AlarmSubSecondMask)); /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* Configure the Alarm register */ - if(sAlarm->Alarm == RTC_ALARM_A) + if (sAlarm->Alarm == RTC_ALARM_A) { - /* Disable the Alarm A interrupt */ + /* Disable the Alarm A */ __HAL_RTC_ALARMA_DISABLE(hrtc); - /* Clear flag alarm A */ + /* Clear the Alarm flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); - /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */ + /* Wait till RTC ALRAWF flag is set and if timeout is reached exit */ do { if (count-- == 0U) @@ -1357,26 +1317,28 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef return HAL_TIMEOUT; } - } - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET); + } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U); hrtc->Instance->ALRMAR = (uint32_t)tmpreg; - /* Configure the Alarm A Sub Second register */ + /* Configure the Alarm A Subseconds register */ hrtc->Instance->ALRMASSR = subsecondtmpreg; /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMA_ENABLE(hrtc); /* Configure the Alarm interrupt */ - __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA); + __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRA); } else { - /* Disable the Alarm B interrupt */ + /* Disable the Alarm B */ __HAL_RTC_ALARMB_DISABLE(hrtc); - /* Clear flag alarm B */ + /* Clear the Alarm flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); - /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */ + /* Reload the counter */ + count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + + /* Wait till RTC ALRBWF flag is set and if timeout is reached exit */ do { if (count-- == 0U) @@ -1391,11 +1353,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef return HAL_TIMEOUT; } - } - while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET); + } while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U); hrtc->Instance->ALRMBR = (uint32_t)tmpreg; - /* Configure the Alarm B Sub Second register */ + /* Configure the Alarm B Subseconds register */ hrtc->Instance->ALRMBSSR = subsecondtmpreg; /* Configure the Alarm state: Enable Alarm */ __HAL_RTC_ALARMB_ENABLE(hrtc); @@ -1405,12 +1366,12 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /* RTC Alarm Interrupt Configuration: EXTI configuration */ __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state back to READY */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1420,13 +1381,13 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } /** - * @brief Deactivate the specified RTC Alarm + * @brief Deactivates the specified RTC Alarm. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB + * @arg RTC_ALARM_A: Alarm A + * @arg RTC_ALARM_B: Alarm B * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) @@ -1444,21 +1405,21 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - if(Alarm == RTC_ALARM_A) + if (Alarm == RTC_ALARM_A) { - /* AlarmA */ + /* Disable Alarm A */ __HAL_RTC_ALARMA_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ + /* In case interrupt mode is used, the interrupt source must be disabled */ __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET) + /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1474,19 +1435,19 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar } else { - /* AlarmB */ + /* Disable Alarm B */ __HAL_RTC_ALARMB_DISABLE(hrtc); - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB); + /* In case interrupt mode is used, the interrupt source must be disabled */ + __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET) + /* Wait till RTC ALRxWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1500,6 +1461,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar } } } + /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1518,8 +1480,8 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @param sAlarm Pointer to Date structure * @param Alarm Specifies the Alarm. * This parameter can be one of the following values: - * @arg RTC_ALARM_A: AlarmA - * @arg RTC_ALARM_B: AlarmB + * @arg RTC_ALARM_A: Alarm A + * @arg RTC_ALARM_B: Alarm B * @param Format Specifies the format of the entered parameters. * This parameter can be one of the following values: * @arg RTC_FORMAT_BIN: Binary data format @@ -1528,19 +1490,19 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { - uint32_t tmpreg = 0U, subsecondtmpreg = 0U; + uint32_t tmpreg = 0U; + uint32_t subsecondtmpreg = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); assert_param(IS_RTC_ALARM(Alarm)); - if(Alarm == RTC_ALARM_A) + if (Alarm == RTC_ALARM_A) { - /* AlarmA */ sAlarm->Alarm = RTC_ALARM_A; tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); - subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); + subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS); } else { @@ -1551,67 +1513,67 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA } /* Fill the structure with the read parameters */ - sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16U); - sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8U); - sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); - sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16U); + sAlarm->AlarmTime.Hours = (uint8_t) ((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> RTC_ALRMAR_HU_Pos); + sAlarm->AlarmTime.Minutes = (uint8_t) ((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> RTC_ALRMAR_MNU_Pos); + sAlarm->AlarmTime.Seconds = (uint8_t) ( tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); + sAlarm->AlarmTime.TimeFormat = (uint8_t) ((tmpreg & RTC_ALRMAR_PM) >> RTC_TR_PM_Pos); sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; - sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24U); - sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); - sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); + sAlarm->AlarmDateWeekDay = (uint8_t) ((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> RTC_ALRMAR_DU_Pos); + sAlarm->AlarmDateWeekDaySel = (uint32_t) (tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t) (tmpreg & RTC_ALARMMASK_ALL); - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { - sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); + sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds); - sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); + sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay); } return HAL_OK; } /** - * @brief This function handles Alarm interrupt request. + * @brief Handles Alarm interrupt request. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Get the AlarmA interrupt source enable status */ - if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != (uint32_t)RESET) + /* Get the Alarm A interrupt source enable status */ + if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRA) != 0U) { - /* Get the pending status of the AlarmA Interrupt */ - if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != (uint32_t)RESET) + /* Get the pending status of the Alarm A Interrupt */ + if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) != 0U) { - /* AlarmA callback */ - #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Alarm A callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->AlarmAEventCallback(hrtc); - #else +#else HAL_RTC_AlarmAEventCallback(hrtc); - #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the AlarmA interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF); + /* Clear the Alarm A interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); } } - /* Get the AlarmB interrupt source enable status */ - if(__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != (uint32_t)RESET) + /* Get the Alarm B interrupt source enable status */ + if (__HAL_RTC_ALARM_GET_IT_SOURCE(hrtc, RTC_IT_ALRB) != 0U) { - /* Get the pending status of the AlarmB Interrupt */ - if(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != (uint32_t)RESET) + /* Get the pending status of the Alarm B Interrupt */ + if (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) != 0U) { - /* AlarmB callback */ - #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Alarm B callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->AlarmBEventCallback(hrtc); - #else +#else HAL_RTCEx_AlarmBEventCallback(hrtc); - #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the AlarmB interrupt pending bit */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF); + /* Clear the Alarm B interrupt pending bit */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); } } @@ -1632,13 +1594,14 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RTC_AlarmAEventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTC_AlarmAEventCallback could be implemented in the user file */ } /** - * @brief This function handles AlarmA Polling request. + * @brief Handles Alarm A Polling request. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -1648,14 +1611,15 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T { uint32_t tickstart = 0U; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) + /* Wait till RTC ALRAF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1663,7 +1627,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T } } - /* Clear the Alarm interrupt pending bit */ + /* Clear the Alarm flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF); /* Change RTC state */ @@ -1677,8 +1641,8 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T */ /** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions - * @brief Peripheral Control functions - * + * @brief Peripheral Control functions + * @verbatim =============================================================================== ##### Peripheral Control functions ##### @@ -1686,6 +1650,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T [..] This subsection provides functions allowing to (+) Wait for RTC Time and Date Synchronization + (+) Manage RTC Summer or Winter time change @endverbatim * @{ @@ -1697,7 +1662,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * @note The RTC Resynchronization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. * @note To read the calendar through the shadow registers after Calendar - * initialization, calendar update or after wake-up from low power modes + * initialization, calendar update or after wakeup from low power modes * the software must first clear the RSF flag. * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been @@ -1706,20 +1671,20 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) { uint32_t tickstart = 0U; /* Clear RSF flag */ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); /* Wait the registers to be synchronised */ - while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET) + while ((hrtc->Instance->ISR & RTC_ISR_RSF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -1729,104 +1694,112 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) } /** - * @} - */ - -/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection provides functions allowing to - (+) Get RTC state - -@endverbatim - * @{ - */ -/** - * @brief Returns the RTC state. + * @brief Daylight Saving Time, adds one hour to the calendar in one + * single operation without going through the initialization procedure. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @retval HAL state - */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) -{ - return hrtc->State; -} - -/** - * @brief Daylight Saving Time, Add one hour to the calendar in one single operation - * without going through the initialization procedure. - * @param hrtc RTC handle * @retval None */ void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) { - UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - SET_BIT(RTC->CR, RTC_CR_ADD1H); + SET_BIT(hrtc->Instance->CR, RTC_CR_ADD1H); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /** - * @brief Daylight Saving Time, Substract one hour from the calendar in one + * @brief Daylight Saving Time, subtracts one hour from the calendar in one * single operation without going through the initialization procedure. - * @param hrtc RTC handle + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) { - UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - SET_BIT(RTC->CR, RTC_CR_SUB1H); + SET_BIT(hrtc->Instance->CR, RTC_CR_SUB1H); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /** - * @brief Daylight Saving Time, Set the store operation bit. + * @brief Daylight Saving Time, sets the store operation bit. * @note It can be used by the software in order to memorize the DST status. - * @param hrtc RTC handle + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) { - UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - SET_BIT(RTC->CR, RTC_CR_BKP); + SET_BIT(hrtc->Instance->CR, RTC_CR_BKP); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /** - * @brief Daylight Saving Time, Clear the store operation bit. - * @param hrtc RTC handle + * @brief Daylight Saving Time, clears the store operation bit. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. * @retval None */ void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) { - UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - CLEAR_BIT(RTC->CR, RTC_CR_BKP); + CLEAR_BIT(hrtc->Instance->CR, RTC_CR_BKP); __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); } /** - * @brief Daylight Saving Time, Read the store operation bit. + * @brief Daylight Saving Time, reads the store operation bit. * @param hrtc RTC handle * @retval operation see RTC_StoreOperation_Definitions */ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) { - UNUSED(hrtc); - return READ_BIT(RTC->CR, RTC_CR_BKP); + return READ_BIT(hrtc->Instance->CR, RTC_CR_BKP); +} + +/** + * @} + */ + +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Get RTC state + +@endverbatim + * @{ + */ +/** + * @brief Returns the RTC state. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL state + */ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +{ + return hrtc->State; } /** * @} */ + +/** + * @} + */ + +/** @addtogroup RTC_Private_Functions + * @{ + */ + /** * @brief Enters the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the @@ -1835,61 +1808,90 @@ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) { uint32_t tickstart = 0U; + HAL_StatusTypeDef status = HAL_OK; - /* Check if the Initialization mode is set */ - if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + /* Check that Initialization mode is not already set */ + if (READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) { - /* Set the Initialization mode */ - hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK; + /* Set INIT bit to enter Initialization mode */ + SET_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC is in INIT state and if Time out is reached exit */ - while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) + /* Wait till RTC is in INIT state and if timeout is reached exit */ + while ((READ_BIT(hrtc->Instance->ISR, RTC_ISR_INITF) == 0U) && (status != HAL_ERROR)) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - return HAL_TIMEOUT; + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + status = HAL_ERROR; } } } - return HAL_OK; + return status; } +/** + * @brief Exits the RTC Initialization mode. + * @param hrtc pointer to a RTC_HandleTypeDef structure that contains + * the configuration information for RTC. + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Clear INIT bit to exit Initialization mode */ + CLEAR_BIT(hrtc->Instance->ISR, RTC_ISR_INIT); + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(hrtc->Instance->CR, RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + status = HAL_ERROR; + } + } + + return status; +} /** - * @brief Converts a 2 digit decimal to BCD format. - * @param Value Byte to be converted + * @brief Converts a 2-digit number from decimal to BCD format. + * @param number decimal-formatted number (from 0 to 99) to be converted * @retval Converted byte */ -uint8_t RTC_ByteToBcd2(uint8_t Value) +uint8_t RTC_ByteToBcd2(uint8_t number) { - uint32_t bcdhigh = 0U; + uint8_t bcdhigh = 0U; - while(Value >= 10U) + while (number >= 10U) { bcdhigh++; - Value -= 10U; + number -= 10U; } - return ((uint8_t)(bcdhigh << 4U) | Value); + return ((uint8_t)(bcdhigh << 4U) | number); } /** - * @brief Converts from 2 digit BCD to Binary. - * @param Value BCD value to be converted + * @brief Converts a 2-digit number from BCD to decimal format. + * @param number BCD-formatted number (from 00 to 99) to be converted * @retval Converted word */ -uint8_t RTC_Bcd2ToByte(uint8_t Value) +uint8_t RTC_Bcd2ToByte(uint8_t number) { - uint32_t tmp = 0U; - tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; - return (tmp + (Value & (uint8_t)0x0F)); + uint8_t tmp = 0U; + tmp = ((uint8_t)(number & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (number & (uint8_t)0x0F)); } /** @@ -1904,5 +1906,3 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.h index 9afa8a14073..6254ad62e17 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc.h @@ -6,26 +6,26 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_RTC_H -#define __STM32F4xx_HAL_RTC_H +#ifndef STM32F4xx_HAL_RTC_H +#define STM32F4xx_HAL_RTC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ + #include "stm32f4xx_hal_def.h" /** @addtogroup STM32F4xx_HAL_Driver @@ -37,6 +37,7 @@ */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup RTC_Exported_Types RTC Exported Types * @{ */ @@ -51,7 +52,7 @@ typedef enum HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */ HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */ HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */ -}HAL_RTCStateTypeDef; +} HAL_RTCStateTypeDef; /** * @brief RTC Configuration Structure definition @@ -65,7 +66,7 @@ typedef struct This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */ uint32_t SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFFU */ + This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FFF */ uint32_t OutPut; /*!< Specifies which signal will be routed to the RTC output. This parameter can be a value of @ref RTC_Output_selection_Definitions */ @@ -75,7 +76,7 @@ typedef struct uint32_t OutPutType; /*!< Specifies the RTC Output Pin mode. This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */ -}RTC_InitTypeDef; +} RTC_InitTypeDef; /** * @brief RTC Time structure definition @@ -83,8 +84,8 @@ typedef struct typedef struct { uint8_t Hours; /*!< Specifies the RTC Time Hour. - This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected. - This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ + This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected + This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */ uint8_t Minutes; /*!< Specifies the RTC Time Minutes. This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ @@ -95,22 +96,22 @@ typedef struct uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ - uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. + uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content. This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity */ uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content - corresponding to Synchronous pre-scaler factor value (PREDIV_S) + corresponding to Synchronous prescaler factor value (PREDIV_S) This parameter corresponds to a time unit range between [0-1] Second with [1 Sec / SecondFraction +1] granularity. This field will be used only by HAL_RTC_GetTime function */ - uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight Saving Time, - please use HAL_RTC_DST_xxx functions */ + uint32_t DayLightSaving; /*!< This interface is deprecated. To manage Daylight + Saving Time, please use HAL_RTC_DST_xxx functions */ - uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight Saving Time, - please use HAL_RTC_DST_xxx functions */ -}RTC_TimeTypeDef; + uint32_t StoreOperation; /*!< This interface is deprecated. To manage Daylight + Saving Time, please use HAL_RTC_DST_xxx functions */ +} RTC_TimeTypeDef; /** * @brief RTC Date structure definition @@ -129,7 +130,7 @@ typedef struct uint8_t Year; /*!< Specifies the RTC Date Year. This parameter must be a number between Min_Data = 0 and Max_Data = 99 */ -}RTC_DateTypeDef; +} RTC_DateTypeDef; /** * @brief RTC Alarm structure definition @@ -145,7 +146,7 @@ typedef struct This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. - This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ uint8_t AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range. @@ -153,7 +154,7 @@ typedef struct uint32_t Alarm; /*!< Specifies the alarm . This parameter can be a value of @ref RTC_Alarms_Definitions */ -}RTC_AlarmTypeDef; +} RTC_AlarmTypeDef; /** * @brief RTC Handle Structure definition @@ -162,7 +163,7 @@ typedef struct typedef struct __RTC_HandleTypeDef #else typedef struct -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ { RTC_TypeDef *Instance; /*!< Register base address */ @@ -173,25 +174,27 @@ typedef struct __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) - void (* AlarmAEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm A Event callback */ + void (* AlarmAEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm A Event callback */ - void (* AlarmBEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Alarm B Event callback */ + void (* AlarmBEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Alarm B Event callback */ - void (* TimeStampEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC TimeStamp Event callback */ + void (* TimeStampEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Timestamp Event callback */ - void (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC WakeUpTimer Event callback */ + void (* WakeUpTimerEventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC WakeUpTimer Event callback */ - void (* Tamper1EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 1 Event callback */ + void (* Tamper1EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 1 Event callback */ - void (* Tamper2EventCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Tamper 2 Event callback */ +#if defined(RTC_TAMPER2_SUPPORT) + void (* Tamper2EventCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Tamper 2 Event callback */ +#endif /* RTC_TAMPER2_SUPPORT */ - void (* MspInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp Init callback */ + void (* MspInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp Init callback */ - void (* MspDeInitCallback) ( struct __RTC_HandleTypeDef * hrtc); /*!< RTC Msp DeInit callback */ + void (* MspDeInitCallback) (struct __RTC_HandleTypeDef *hrtc); /*!< RTC Msp DeInit callback */ -#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ -}RTC_HandleTypeDef; +} RTC_HandleTypeDef; #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) /** @@ -199,20 +202,22 @@ typedef struct */ typedef enum { - HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00u, /*!< RTC Alarm A Event Callback ID */ - HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01u, /*!< RTC Alarm B Event Callback ID */ - HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02u, /*!< RTC TimeStamp Event Callback ID */ - HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03u, /*!< RTC Wake-Up Timer Event Callback ID */ - HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04u, /*!< RTC Tamper 1 Callback ID */ - HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05u, /*!< RTC Tamper 2 Callback ID */ - HAL_RTC_MSPINIT_CB_ID = 0x0Eu, /*!< RTC Msp Init callback ID */ - HAL_RTC_MSPDEINIT_CB_ID = 0x0Fu /*!< RTC Msp DeInit callback ID */ -}HAL_RTC_CallbackIDTypeDef; + HAL_RTC_ALARM_A_EVENT_CB_ID = 0x00U, /*!< RTC Alarm A Event Callback ID */ + HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */ + HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC Timestamp Event Callback ID */ + HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC Wakeup Timer Event Callback ID */ + HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */ +#if defined(RTC_TAMPER2_SUPPORT) + HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */ +#endif /* RTC_TAMPER2_SUPPORT */ + HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */ + HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */ +} HAL_RTC_CallbackIDTypeDef; /** * @brief HAL RTC Callback pointer definition */ -typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */ +typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to an RTC callback function */ #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /** @@ -220,6 +225,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup RTC_Exported_Constants RTC Exported Constants * @{ */ @@ -228,7 +234,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_HOURFORMAT_24 0x00000000U -#define RTC_HOURFORMAT_12 0x00000040U +#define RTC_HOURFORMAT_12 RTC_CR_FMT /** * @} */ @@ -237,9 +243,9 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_OUTPUT_DISABLE 0x00000000U -#define RTC_OUTPUT_ALARMA 0x00200000U -#define RTC_OUTPUT_ALARMB 0x00400000U -#define RTC_OUTPUT_WAKEUP 0x00600000U +#define RTC_OUTPUT_ALARMA RTC_CR_OSEL_0 +#define RTC_OUTPUT_ALARMB RTC_CR_OSEL_1 +#define RTC_OUTPUT_WAKEUP RTC_CR_OSEL /** * @} */ @@ -248,7 +254,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_OUTPUT_POLARITY_HIGH 0x00000000U -#define RTC_OUTPUT_POLARITY_LOW 0x00100000U +#define RTC_OUTPUT_POLARITY_LOW RTC_CR_POL /** * @} */ @@ -257,7 +263,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_OUTPUT_TYPE_OPENDRAIN 0x00000000U -#define RTC_OUTPUT_TYPE_PUSHPULL 0x00040000U +#define RTC_OUTPUT_TYPE_PUSHPULL RTC_TAFCR_ALARMOUTTYPE /** * @} */ @@ -266,7 +272,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_HOURFORMAT12_AM ((uint8_t)0x00) -#define RTC_HOURFORMAT12_PM ((uint8_t)0x40) +#define RTC_HOURFORMAT12_PM ((uint8_t)0x01) /** * @} */ @@ -274,8 +280,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_SUB1H 0x00020000U -#define RTC_DAYLIGHTSAVING_ADD1H 0x00010000U +#define RTC_DAYLIGHTSAVING_SUB1H RTC_CR_SUB1H +#define RTC_DAYLIGHTSAVING_ADD1H RTC_CR_ADD1H #define RTC_DAYLIGHTSAVING_NONE 0x00000000U /** * @} @@ -285,7 +291,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_STOREOPERATION_RESET 0x00000000U -#define RTC_STOREOPERATION_SET 0x00040000U +#define RTC_STOREOPERATION_SET RTC_CR_BKP /** * @} */ @@ -293,16 +299,15 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions * @{ */ -#define RTC_FORMAT_BIN 0x00000000U -#define RTC_FORMAT_BCD 0x00000001U +#define RTC_FORMAT_BIN 0x00000000U +#define RTC_FORMAT_BCD 0x00000001U /** * @} */ -/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format) * @{ */ -/* Coded in BCD format */ #define RTC_MONTH_JANUARY ((uint8_t)0x01) #define RTC_MONTH_FEBRUARY ((uint8_t)0x02) #define RTC_MONTH_MARCH ((uint8_t)0x03) @@ -337,7 +342,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @{ */ #define RTC_ALARMDATEWEEKDAYSEL_DATE 0x00000000U -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY 0x40000000U +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL /** * @} */ @@ -350,7 +355,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to #define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 #define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 #define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL 0x80808080U +#define RTC_ALARMMASK_ALL (RTC_ALARMMASK_DATEWEEKDAY | \ + RTC_ALARMMASK_HOURS | \ + RTC_ALARMMASK_MINUTES | \ + RTC_ALARMMASK_SECONDS) /** * @} */ @@ -367,39 +375,38 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 0x01000000U /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 0x02000000U /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 0x03000000U /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 0x04000000U /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 0x05000000U /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 0x06000000U /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 0x07000000U /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 0x08000000U /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 0x09000000U /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 0x0A000000U /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 0x0B000000U /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 0x0C000000U /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 0x0D000000U /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 0x0E000000U /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_NONE 0x0F000000U /*!< SS[14:0] are compared and must match - to activate alarm. */ +/*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */ +#define RTC_ALARMSUBSECONDMASK_ALL 0x00000000U +/*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 +/*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 +/*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1) +/*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 +/*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2) +/*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) +/*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2) +/*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 +/*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14 (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3) +/*!< SS[14:0] are compared and must match to activate alarm. */ +#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /** * @} */ @@ -407,13 +414,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions * @{ */ -#define RTC_IT_TS 0x00008000U -#define RTC_IT_WUT 0x00004000U -#define RTC_IT_ALRB 0x00002000U -#define RTC_IT_ALRA 0x00001000U -#define RTC_IT_TAMP 0x00000004U /* Used only to Enable the Tamper Interrupt */ -#define RTC_IT_TAMP1 0x00020000U -#define RTC_IT_TAMP2 0x00040000U +#define RTC_IT_TS RTC_CR_TSIE /*!< Enable Timestamp Interrupt */ +#define RTC_IT_WUT RTC_CR_WUTIE /*!< Enable Wakeup timer Interrupt */ +#define RTC_IT_ALRB RTC_CR_ALRBIE /*!< Enable Alarm B Interrupt */ +#define RTC_IT_ALRA RTC_CR_ALRAIE /*!< Enable Alarm A Interrupt */ /** * @} */ @@ -421,21 +425,23 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /** @defgroup RTC_Flags_Definitions RTC Flags Definitions * @{ */ -#define RTC_FLAG_RECALPF 0x00010000U -#define RTC_FLAG_TAMP2F 0x00004000U -#define RTC_FLAG_TAMP1F 0x00002000U -#define RTC_FLAG_TSOVF 0x00001000U -#define RTC_FLAG_TSF 0x00000800U -#define RTC_FLAG_WUTF 0x00000400U -#define RTC_FLAG_ALRBF 0x00000200U -#define RTC_FLAG_ALRAF 0x00000100U -#define RTC_FLAG_INITF 0x00000040U -#define RTC_FLAG_RSF 0x00000020U -#define RTC_FLAG_INITS 0x00000010U -#define RTC_FLAG_SHPF 0x00000008U -#define RTC_FLAG_WUTWF 0x00000004U -#define RTC_FLAG_ALRBWF 0x00000002U -#define RTC_FLAG_ALRAWF 0x00000001U +#define RTC_FLAG_RECALPF RTC_ISR_RECALPF /*!< Recalibration pending flag */ +#if defined(RTC_TAMPER2_SUPPORT) +#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F /*!< Tamper 2 event flag */ +#endif /* RTC_TAMPER2_SUPPORT */ +#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F /*!< Tamper 1 event flag */ +#define RTC_FLAG_TSOVF RTC_ISR_TSOVF /*!< Timestamp overflow flag */ +#define RTC_FLAG_TSF RTC_ISR_TSF /*!< Timestamp event flag */ +#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Wakeup timer event flag */ +#define RTC_FLAG_ALRBF RTC_ISR_ALRBF /*!< Alarm B event flag */ +#define RTC_FLAG_ALRAF RTC_ISR_ALRAF /*!< Alarm A event flag */ +#define RTC_FLAG_INITF RTC_ISR_INITF /*!< RTC in initialization mode flag */ +#define RTC_FLAG_RSF RTC_ISR_RSF /*!< Register synchronization flag */ +#define RTC_FLAG_INITS RTC_ISR_INITS /*!< RTC initialization status flag */ +#define RTC_FLAG_SHPF RTC_ISR_SHPF /*!< Shift operation pending flag */ +#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< WUTR register write allowance flag */ +#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF /*!< ALRMBR register write allowance flag */ +#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF /*!< ALRMAR register write allowance flag */ /** * @} */ @@ -444,7 +450,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ + /** @defgroup RTC_Exported_Macros RTC Exported Macros * @{ */ @@ -454,11 +461,11 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @retval None */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_RTC_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL;\ - (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0u) +#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do { \ + (__HANDLE__)->State = HAL_RTC_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) #else #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ @@ -468,21 +475,27 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xCAU; \ - (__HANDLE__)->Instance->WPR = 0x53U; \ - } while(0U) +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) do { \ + (__HANDLE__)->Instance->WPR = 0xCAU; \ + (__HANDLE__)->Instance->WPR = 0x53U; \ + } while(0U) /** * @brief Enable the write protection for RTC registers. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ - do{ \ - (__HANDLE__)->Instance->WPR = 0xFFU; \ - } while(0U) +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) do { \ + (__HANDLE__)->Instance->WPR = 0xFFU; \ + } while(0U) + + +/** + * @brief Check whether the RTC Calendar is initialized. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) (((((__HANDLE__)->Instance->ISR) & (RTC_FLAG_INITS)) == RTC_FLAG_INITS) ? 1U : 0U) /** * @brief Enable the RTC ALARMA peripheral. @@ -527,9 +540,9 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @brief Disable the RTC Alarm interrupt. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. - * This parameter can be any combination of the following values: - * @arg RTC_IT_ALRA: Alarm A interrupt - * @arg RTC_IT_ALRB: Alarm B interrupt + * This parameter can be any combination of the following values: + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) @@ -543,25 +556,25 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) /** * @brief Get the selected RTC Alarm's flag status. * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC Alarm Flag to check. * This parameter can be: - * @arg RTC_FLAG_ALRAF - * @arg RTC_FLAG_ALRBF - * @arg RTC_FLAG_ALRAWF - * @arg RTC_FLAG_ALRBWF + * @arg RTC_FLAG_ALRAF: Alarm A interrupt flag + * @arg RTC_FLAG_ALRAWF: Alarm A 'write allowed' flag + * @arg RTC_FLAG_ALRBF: Alarm B interrupt flag + * @arg RTC_FLAG_ALRBWF: Alarm B 'write allowed' flag * @retval None */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) /** * @brief Clear the RTC Alarm's pending flags. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. + * @param __FLAG__ specifies the RTC Alarm flag to be cleared. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF @@ -569,7 +582,6 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to */ #define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) - /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. @@ -579,86 +591,88 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** - * @brief Enable interrupt on the RTC Alarm associated Exti line. + * @brief Enable interrupt on the RTC Alarm associated EXTI line. * @retval None */ #define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable interrupt on the RTC Alarm associated Exti line. + * @brief Disable interrupt on the RTC Alarm associated EXTI line. * @retval None */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Enable event on the RTC Alarm associated Exti line. + * @brief Enable event on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable event on the RTC Alarm associated Exti line. + * @brief Disable event on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. + * @brief Enable falling edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ #define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. + * @brief Disable falling edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. + * @brief Enable rising edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ #define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. + * @brief Disable rising edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @brief Enable rising & falling edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE();\ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \ } while(0U) /** - * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @brief Disable rising & falling edge trigger on the RTC Alarm associated EXTI line. * @retval None. */ -#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();\ - __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE();\ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \ } while(0U) /** - * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. + * @brief Check whether the RTC Alarm associated EXTI line interrupt flag is set or not. * @retval Line Status. */ #define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Clear the RTC Alarm associated Exti line flag. + * @brief Clear the RTC Alarm associated EXTI line flag. * @retval None. */ #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Generate a Software interrupt on RTC Alarm associated Exti line. + * @brief Generate a Software interrupt on RTC Alarm associated EXTI line. * @retval None. */ #define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) @@ -666,10 +680,11 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to * @} */ -/* Include RTC HAL Extension module */ +/* Include RTC HAL Extended module */ #include "stm32f4xx_hal_rtc_ex.h" /* Exported functions --------------------------------------------------------*/ + /** @addtogroup RTC_Exported_Functions * @{ */ @@ -680,8 +695,8 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); -void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); +void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -700,11 +715,6 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); /** * @} */ @@ -717,9 +727,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); /** * @} */ @@ -728,7 +738,14 @@ void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); + +/* RTC Daylight Saving Time functions *****************************************/ +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); /** * @} */ @@ -749,28 +766,38 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ + /** @defgroup RTC_Private_Constants RTC Private Constants * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK 0x007F7F7FU -#define RTC_DR_RESERVED_MASK 0x00FFFF3FU +#define RTC_TR_RESERVED_MASK ((uint32_t)(RTC_TR_HT | RTC_TR_HU | \ + RTC_TR_MNT | RTC_TR_MNU | \ + RTC_TR_ST | RTC_TR_SU | \ + RTC_TR_PM)) +#define RTC_DR_RESERVED_MASK ((uint32_t)(RTC_DR_YT | RTC_DR_YU | \ + RTC_DR_MT | RTC_DR_MU | \ + RTC_DR_DT | RTC_DR_DU | \ + RTC_DR_WDU)) #define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK 0xFFFFFF5FU -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ - RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \ - RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F | \ - RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) +#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_INITF | RTC_FLAG_INITS | \ + RTC_FLAG_ALRAF | RTC_FLAG_ALRAWF | \ + RTC_FLAG_ALRBF | RTC_FLAG_ALRBWF | \ + RTC_FLAG_WUTF | RTC_FLAG_WUTWF | \ + RTC_FLAG_RECALPF | RTC_FLAG_SHPF | \ + RTC_FLAG_TSF | RTC_FLAG_TSOVF | \ + RTC_FLAG_RSF | RTC_TAMPER_FLAGS_MASK)) -#define RTC_TIMEOUT_VALUE 1000 +#define RTC_TIMEOUT_VALUE 1000U -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_ALARM_EVENT EXTI_IMR_MR17 /*!< External interrupt line 17 Connected to the RTC Alarm event */ /** * @} */ /* Private macros ------------------------------------------------------------*/ + /** @defgroup RTC_Private_Macros RTC Private Macros * @{ */ @@ -780,31 +807,42 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); */ #define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ ((FORMAT) == RTC_HOURFORMAT_24)) + #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ ((OUTPUT) == RTC_OUTPUT_WAKEUP)) + #define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ ((POL) == RTC_OUTPUT_POLARITY_LOW)) + #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) -#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) + #define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FU) #define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFFU) + +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0U) && ((HOUR) <= 12U)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23U) #define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59U) #define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59U) -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) +#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || \ + ((PM) == RTC_HOURFORMAT12_PM)) + #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) + #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ ((OPERATION) == RTC_STOREOPERATION_SET)) + #define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD)) + #define IS_RTC_YEAR(YEAR) ((YEAR) <= 99U) #define IS_RTC_MONTH(MONTH) (((MONTH) >= 1U) && ((MONTH) <= 12U)) #define IS_RTC_DATE(DATE) (((DATE) >= 1U) && ((DATE) <= 31U)) + #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ @@ -812,7 +850,9 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + #define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0U) && ((DATE) <= 31U)) + #define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ @@ -820,27 +860,31 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) + #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) -#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7FU) == (uint32_t)RESET) + +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & ((uint32_t)~RTC_ALARMMASK_ALL)) == 0U) + #define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFFU) - -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ + +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) + +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ + ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ ((MASK) == RTC_ALARMSUBSECONDMASK_NONE)) /** * @} @@ -851,12 +895,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); */ /* Private functions ---------------------------------------------------------*/ + /** @defgroup RTC_Private_Functions RTC Private Functions * @{ */ -HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); -uint8_t RTC_ByteToBcd2(uint8_t Value); -uint8_t RTC_Bcd2ToByte(uint8_t Value); +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc); +uint8_t RTC_ByteToBcd2(uint8_t number); +uint8_t RTC_Bcd2ToByte(uint8_t number); /** * @} */ @@ -873,6 +919,4 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value); } #endif -#endif /* __STM32F4xx_HAL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_RTC_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc_ex.c index 8e07b4e22e1..eb5708fa0d6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc_ex.c @@ -2,58 +2,76 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc_ex.c * @author MCD Application Team - * @brief RTC HAL module driver. + * @brief Extended RTC HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) Extension peripheral: - * + RTC Time Stamp functions + * functionalities of the Real-Time Clock (RTC) Extended peripheral: + * + RTC Timestamp functions * + RTC Tamper functions - * + RTC Wake-up functions - * + Extension Control functions - * + Extension RTC features functions + * + RTC Wakeup functions + * + Extended Control functions + * + Extended RTC features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== - ##### How to use this driver ##### + ##### How to use this driver ##### ============================================================================== [..] (+) Enable the RTC domain access. (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour format using the HAL_RTC_Init() function. - *** RTC Wake-up configuration *** + *** RTC Wakeup configuration *** ================================ [..] - (+) To configure the RTC Wake-up Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() - function. You can also configure the RTC Wake-up timer in interrupt mode - using the HAL_RTCEx_SetWakeUpTimer_IT() function. - (+) To read the RTC Wake-up Counter register, use the HAL_RTCEx_GetWakeUpTimer() + (+) To configure the RTC Wakeup Clock source and Counter use the + HAL_RTCEx_SetWakeUpTimer() function. + You can also configure the RTC Wakeup timer in interrupt mode using the + HAL_RTCEx_SetWakeUpTimer_IT() function. + (+) To read the RTC Wakeup Counter register, use the HAL_RTCEx_GetWakeUpTimer() function. - *** TimeStamp configuration *** + *** Timestamp configuration *** =============================== [..] - (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the - HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with - interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function. - (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp() - function. - (+) The TIMESTAMP alternate function can be mapped either to RTC_AF1 (PC13) - or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TSINSEL bit in - RTC_TAFCR register. The corresponding pin is also selected by HAL_RTCEx_SetTimeStamp() - or HAL_RTCEx_SetTimeStamp_IT() function. + (+) To configure the RTC Timestamp use the HAL_RTCEx_SetTimeStamp() function. + You can also configure the RTC Timestamp with interrupt mode using the + HAL_RTCEx_SetTimeStamp_IT() function. + (+) To read the RTC Timestamp Time and Date register, use the + HAL_RTCEx_GetTimeStamp() function. + (+) The Timestamp alternate function can be mapped either to RTC_AF1 (PC13) + or RTC_AF2 (PI8) depending on the value of TSINSEL bit in RTC_TAFCR + register. + For STM32F446xx devices RTC_AF2 corresponds to pin PA0 and not to pin PI8. + The corresponding pin is also selected by HAL_RTCEx_SetTimeStamp() + or HAL_RTCEx_SetTimeStamp_IT() functions. *** Tamper configuration *** ============================ [..] - (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge - or Level according to the Tamper filter (if equal to 0 Edge else Level) - value, sampling frequency, precharge or discharge and Pull-UP using the - HAL_RTCEx_SetTamper() function. You can configure RTC Tamper in interrupt - mode using HAL_RTCEx_SetTamper_IT() function. + (+) To Enable the RTC Tamper and configure the Tamper filter count, trigger + Edge or Level according to the Tamper filter value (if equal to 0 Edge + else Level), sampling frequency, precharge or discharge and Pull-UP use + the HAL_RTCEx_SetTamper() function. + You can configure RTC Tamper in interrupt mode using HAL_RTCEx_SetTamper_IT() + function. (+) The TAMPER1 alternate function can be mapped either to RTC_AF1 (PC13) - or RTC_AF2 (PI8 or PA0 only for STM32F446xx devices) depending on the value of TAMP1INSEL bit in - RTC_TAFCR register. The corresponding pin is also selected by HAL_RTCEx_SetTamper() - or HAL_RTCEx_SetTamper_IT() function. + or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in RTC_TAFCR + register. + The corresponding pin is also selected by HAL_RTCEx_SetTamper() + or HAL_RTCEx_SetTamper_IT() functions. + (+) The TAMPER2 alternate function is mapped to RTC_AF2 (PI8). + For STM32F446xx devices RTC_AF2 corresponds to pin PA0 and not to pin PI8. *** Backup Data Registers configuration *** =========================================== @@ -63,18 +81,44 @@ (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead() function. - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * + *** Coarse Digital Calibration configuration *** + ================================================ + [..] + (+) The Coarse Digital Calibration can be used to compensate crystal inaccuracy + by setting the DCS bit in RTC_CALIBR register. + (+) When positive calibration is enabled (DCS = ‘0’), 2 asynchronous prescaler + clock cycles are added every minute during 2xDC minutes. + This causes the calendar to be updated sooner, thereby adjusting the + effective RTC frequency to be a bit higher. + (+) When negative calibration is enabled (DCS = ‘1’), 1 asynchronous prescaler + clock cycle is removed every minute during 2xDC minutes. + This causes the calendar to be updated later, thereby adjusting the + effective RTC frequency to be a bit lower. + (+) DC is configured through bits DC[4:0] of RTC_CALIBR register. This number + ranges from 0 to 31 corresponding to a time interval (2xDC) ranging from + 0 to 62. + (+) In order to measure the clock deviation, a 512 Hz clock is output for + calibration. + (+) The RTC Coarse Digital Calibration value and sign can be calibrated using + the HAL_RTCEx_SetCoarseCalib() function. + + *** Smooth Digital Calibration configuration *** + ================================================ + [..] + (+) RTC frequency can be digitally calibrated with a resolution of about + 0.954 ppm with a range from -487.1 ppm to +488.5 ppm. + The correction of the frequency is performed using a series of small + adjustments (adding and/or subtracting individual RTCCLK pulses). + (+) The smooth digital calibration is performed during a cycle of about 2^20 + RTCCLK pulses (or 32 seconds) when the input frequency is 32,768 Hz. + This cycle is maintained by a 20-bit counter clocked by RTCCLK. + (+) The smooth calibration register (RTC_CALR) specifies the number of RTCCLK + clock cycles to be masked during the 32-second cycle. + (+) The RTC Smooth Digital Calibration value and the corresponding calibration + cycle period (32s, 16s, or 8s) can be calibrated using the + HAL_RTCEx_SetSmoothCalib() function. + + @endverbatim ****************************************************************************** */ @@ -86,7 +130,7 @@ */ /** @defgroup RTCEx RTCEx - * @brief RTC HAL module driver + * @brief RTC Extended HAL module driver * @{ */ @@ -97,80 +141,90 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions * @{ */ -/** @defgroup RTCEx_Exported_Functions_Group1 RTC TimeStamp and Tamper functions - * @brief RTC TimeStamp and Tamper functions - * +/** @defgroup RTCEx_Exported_Functions_Group1 RTC Timestamp and Tamper functions + * @brief RTC Timestamp and Tamper functions + * @verbatim =============================================================================== - ##### RTC TimeStamp and Tamper functions ##### + ##### RTC Timestamp and Tamper functions ##### =============================================================================== - [..] This section provides functions allowing to configure TimeStamp feature + [..] This section provides functions allowing to configure Timestamp feature @endverbatim * @{ */ /** - * @brief Sets TimeStamp. - * @note This API must be called before enabling the TimeStamp feature. + * @brief Sets Timestamp. + * @note This API must be called before enabling the Timestamp feature. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * @param RTC_TimeStampEdge Specifies the pin edge on which the Timestamp is * activated. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPEDGE_RISING: the Timestamp event occurs on + * the rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Timestamp event occurs on + * the falling edge of the related pin. + * @param RTC_TimeStampPin Specifies the RTC Timestamp Pin. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TIMESTAMPPIN_POS1: PI8/PA0 is selected as RTC TimeStamp Pin. - * (not applicable in the case of STM32F412xx, STM32F413xx and STM32F423xx devices) - * (PI8 for all STM32 devices except for STM32F446xx devices the PA0 is used) - * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC Timestamp Pin. + * @arg RTC_TIMESTAMPPIN_POS1: PI8 is selected as RTC Timestamp Pin. + * @note RTC_TIMESTAMPPIN_POS1 corresponds to pin PA0 in the case of + * STM32F446xx devices. + * @note RTC_TIMESTAMPPIN_POS1 is not applicable to the following list of devices: + * STM32F412xx, STM32F413xx and STM32F423xx. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin) { uint32_t tmpreg = 0U; /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_TIMESTAMP_EDGE(RTC_TimeStampEdge)); assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state to BUSY */ hrtc->State = HAL_RTC_STATE_BUSY; + hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL; + hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); + /* Get the RTC_CR register and clear the bits to be configured */ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - tmpreg|= TimeStampEdge; + /* Configure the Timestamp TSEDGE bit */ + tmpreg |= RTC_TimeStampEdge; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL; - hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); - - /* Configure the Time Stamp TSEDGE and Enable bits */ + /* Copy the desired configuration into the CR register */ hrtc->Instance->CR = (uint32_t)tmpreg; + /* Clear RTC Timestamp flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); + + /* Clear RTC Timestamp overrun Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); + + /* Enable the Timestamp saving */ __HAL_RTC_TIMESTAMP_ENABLE(hrtc); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ + /* Change RTC state back to READY */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -180,67 +234,76 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS } /** - * @brief Sets TimeStamp with Interrupt. + * @brief Sets Timestamp with Interrupt. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @note This API must be called before enabling the TimeStamp feature. - * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is + * @note This API must be called before enabling the Timestamp feature. + * @param RTC_TimeStampEdge Specifies the pin edge on which the Timestamp is * activated. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the - * rising edge of the related pin. - * @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the - * falling edge of the related pin. - * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin. + * @arg RTC_TIMESTAMPEDGE_RISING: the Timestamp event occurs on + * the rising edge of the related pin. + * @arg RTC_TIMESTAMPEDGE_FALLING: the Timestamp event occurs on + * the falling edge of the related pin. + * @param RTC_TimeStampPin Specifies the RTC Timestamp Pin. * This parameter can be one of the following values: - * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin. - * @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx, STM32F412xx, STM32F413xx and STM32F423xx devices) - * @arg RTC_TIMESTAMPPIN_PA0: PA0 is selected as RTC TimeStamp Pin only for STM32F446xx devices + * @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC Timestamp Pin. + * @arg RTC_TIMESTAMPPIN_POS1: PI8 is selected as RTC Timestamp Pin. + * @note RTC_TIMESTAMPPIN_POS1 corresponds to pin PA0 in the case of + * STM32F446xx devices. + * @note RTC_TIMESTAMPPIN_POS1 is not applicable to the following list of devices: + * STM32F412xx, STM32F413xx and STM32F423xx. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin) +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin) { uint32_t tmpreg = 0U; /* Check the parameters */ - assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge)); + assert_param(IS_TIMESTAMP_EDGE(RTC_TimeStampEdge)); assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin)); /* Process Locked */ __HAL_LOCK(hrtc); + /* Change RTC state to BUSY */ hrtc->State = HAL_RTC_STATE_BUSY; + hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL; + hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); + /* Get the RTC_CR register and clear the bits to be configured */ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - tmpreg |= TimeStampEdge; + /* Configure the Timestamp TSEDGE bit */ + tmpreg |= RTC_TimeStampEdge; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Configure the Time Stamp TSEDGE and Enable bits */ + /* Copy the desired configuration into the CR register */ hrtc->Instance->CR = (uint32_t)tmpreg; - hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_TSINSEL; - hrtc->Instance->TAFCR |= (uint32_t)(RTC_TimeStampPin); - /* Clear RTC Timestamp flag */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); - __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - - /* Enable IT timestamp */ - __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); + /* Clear RTC Timestamp overrun Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + /* Enable the Timestamp saving */ + __HAL_RTC_TIMESTAMP_ENABLE(hrtc); - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + /* Enable IT Timestamp */ + __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc, RTC_IT_TS); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* RTC Timestamp Interrupt Configuration: EXTI configuration */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); + + /* Change RTC state back to READY */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -250,7 +313,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti } /** - * @brief Deactivates TimeStamp. + * @brief Deactivates Timestamp. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status @@ -273,7 +336,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) /* Get the RTC_CR register and clear the bits to be configured */ tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); - /* Configure the Time Stamp TSEDGE and Enable bits */ + /* Configure the Timestamp TSEDGE and Enable bits */ hrtc->Instance->CR = (uint32_t)tmpreg; /* Enable the write protection for RTC registers */ @@ -288,70 +351,71 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) } /** - * @brief Gets the RTC TimeStamp value. + * @brief Gets the RTC Timestamp value. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param sTimeStamp Pointer to Time structure * @param sTimeStampDate Pointer to Date structure * @param Format specifies the format of the entered parameters. * This parameter can be one of the following values: - * RTC_FORMAT_BIN: Binary data format - * RTC_FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format) { - uint32_t tmptime = 0U, tmpdate = 0U; + uint32_t tmptime = 0U; + uint32_t tmpdate = 0U; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - /* Get the TimeStamp time and date registers values */ + /* Get the Timestamp time and date registers values */ tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK); tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK); /* Fill the Time structure fields with the read parameters */ - sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U); - sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U); - sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU)); - sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U); + sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> RTC_TSTR_HU_Pos); + sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> RTC_TSTR_MNU_Pos); + sTimeStamp->Seconds = (uint8_t)((tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)) >> RTC_TSTR_SU_Pos); + sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> RTC_TSTR_PM_Pos); sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR; /* Fill the Date structure fields with the read parameters */ - sTimeStampDate->Year = 0U; - sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U); - sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU)); - sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U); + sTimeStampDate->Year = 0U; + sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> RTC_TSDR_MU_Pos); + sTimeStampDate->Date = (uint8_t)((tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)) >> RTC_TSDR_DU_Pos); + sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> RTC_TSDR_WDU_Pos); /* Check the input parameters format */ - if(Format == RTC_FORMAT_BIN) + if (Format == RTC_FORMAT_BIN) { - /* Convert the TimeStamp structure parameters to Binary format */ - sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); + /* Convert the Timestamp structure parameters to Binary format */ + sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes); sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds); /* Convert the DateTimeStamp structure parameters to Binary format */ - sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); - sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); + sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month); + sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date); sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay); } - /* Clear the TIMESTAMP Flag */ + /* Clear the Timestamp Flag */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); return HAL_OK; } /** - * @brief Sets Tamper - * @note By calling this API we disable the tamper interrupt for all tampers. + * @brief Sets Tamper. + * @note By calling this API the tamper global interrupt will be disabled. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) { uint32_t tmpreg = 0U; @@ -360,6 +424,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection)); assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger)); assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); @@ -370,20 +435,46 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef hrtc->State = HAL_RTC_STATE_BUSY; - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) + /* Copy control register into temporary variable */ + tmpreg = hrtc->Instance->TAFCR; + + /* Enable selected tamper */ + tmpreg |= (sTamper->Tamper); + + /* Configure the tamper trigger bit (this bit is just on the right of the + tamper enable bit, hence the one-time right shift before updating it) */ + if (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE) { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); + /* Set the tamper trigger bit (case of falling edge or high level) */ + tmpreg |= (uint32_t)(sTamper->Tamper << 1U); } + else + { + /* Clear the tamper trigger bit (case of rising edge or low level) */ + tmpreg &= (uint32_t)~(sTamper->Tamper << 1U); + } + + /* Clear remaining fields before setting them */ + tmpreg &= ~(RTC_TAMPERFILTER_MASK | \ + RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \ + RTC_TAMPERPRECHARGEDURATION_MASK | \ + RTC_TAMPER_PULLUP_MASK | \ + RTC_TAFCR_TAMP1INSEL | \ + RTC_TIMESTAMPONTAMPERDETECTION_MASK); - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger |\ - (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ - (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + /* Set remaining parameters of desired configuration into temporary variable */ + tmpreg |= ((uint32_t)sTamper->Filter | \ + (uint32_t)sTamper->SamplingFrequency | \ + (uint32_t)sTamper->PrechargeDuration | \ + (uint32_t)sTamper->TamperPullUp | \ + (uint32_t)sTamper->PinSelection | \ + (uint32_t)sTamper->TimeStampOnTamperDetection); - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\ - (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ - (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL | (uint32_t)RTC_TAFCR_TAMPIE); + /* Disable tamper global interrupt in case it is enabled */ + tmpreg &= (uint32_t)~RTC_TAFCR_TAMPIE; - hrtc->Instance->TAFCR |= tmpreg; + /* Copy desired configuration into configuration register */ + hrtc->Instance->TAFCR = tmpreg; hrtc->State = HAL_RTC_STATE_READY; @@ -395,13 +486,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /** * @brief Sets Tamper with interrupt. - * @note By calling this API we force the tamper interrupt for all tampers. + * @note By calling this API the tamper global interrupt will be enabled. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param sTamper Pointer to RTC Tamper. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) { uint32_t tmpreg = 0U; @@ -410,6 +501,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType assert_param(IS_RTC_TAMPER_PIN(sTamper->PinSelection)); assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(sTamper->Filter, sTamper->Trigger)); assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); @@ -420,40 +512,50 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType hrtc->State = HAL_RTC_STATE_BUSY; - /* Configure the tamper trigger */ - if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE) - { - sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U); - } - - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->PinSelection | (uint32_t)sTamper->Trigger |\ - (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\ - (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + /* Copy control register into temporary variable */ + tmpreg = hrtc->Instance->TAFCR; - hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1U) | (uint32_t)RTC_TAFCR_TAMPTS |\ - (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\ - (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPINSEL); + /* Enable selected tamper */ + tmpreg |= (sTamper->Tamper); - hrtc->Instance->TAFCR |= tmpreg; - - /* Configure the Tamper Interrupt in the RTC_TAFCR */ - hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE; - - if(sTamper->Tamper == RTC_TAMPER_1) + /* Configure the tamper trigger bit (this bit is just on the right of the + tamper enable bit, hence the one-time right shift before updating it) */ + if (sTamper->Trigger == RTC_TAMPERTRIGGER_FALLINGEDGE) { - /* Clear RTC Tamper 1 flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); + /* Set the tamper trigger bit (case of falling edge or high level) */ + tmpreg |= (uint32_t)(sTamper->Tamper << 1U); } else { - /* Clear RTC Tamper 2 flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + /* Clear the tamper trigger bit (case of rising edge or low level) */ + tmpreg &= (uint32_t)~(sTamper->Tamper << 1U); } + /* Clear remaining fields before setting them */ + tmpreg &= ~(RTC_TAMPERFILTER_MASK | \ + RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK | \ + RTC_TAMPERPRECHARGEDURATION_MASK | \ + RTC_TAMPER_PULLUP_MASK | \ + RTC_TAFCR_TAMP1INSEL | \ + RTC_TIMESTAMPONTAMPERDETECTION_MASK); + + /* Set remaining parameters of desired configuration into temporary variable */ + tmpreg |= ((uint32_t)sTamper->Filter | \ + (uint32_t)sTamper->SamplingFrequency | \ + (uint32_t)sTamper->PrechargeDuration | \ + (uint32_t)sTamper->TamperPullUp | \ + (uint32_t)sTamper->PinSelection | \ + (uint32_t)sTamper->TimeStampOnTamperDetection); + + /* Enable global tamper interrupt */ + tmpreg |= (uint32_t)RTC_TAFCR_TAMPIE; + + /* Copy desired configuration into configuration register */ + hrtc->Instance->TAFCR = tmpreg; + /* RTC Tamper Interrupt Configuration: EXTI configuration */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); hrtc->State = HAL_RTC_STATE_READY; @@ -465,10 +567,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /** * @brief Deactivates Tamper. + * @note The tamper global interrupt bit will remain unchanged. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Tamper Selected tamper pin. - * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2. + * This parameter can be any combination of the following values: + * @arg RTC_TAMPER_1: Tamper 1 + * @arg RTC_TAMPER_2: Tamper 2 + * @note RTC_TAMPER_2 is not applicable to all devices. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) @@ -492,36 +598,36 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T } /** - * @brief This function handles TimeStamp interrupt request. + * @brief Handles Timestamp and Tamper interrupt request. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None */ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Get the TimeStamp interrupt source enable status */ - if(__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != (uint32_t)RESET) + /* Get the Timestamp interrupt source enable status */ + if (__HAL_RTC_TIMESTAMP_GET_IT_SOURCE(hrtc, RTC_IT_TS) != 0U) { - /* Get the pending status of the TIMESTAMP Interrupt */ - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != (uint32_t)RESET) + /* Get the pending status of the Timestamp Interrupt */ + if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) != 0U) { - /* TIMESTAMP callback */ + /* Timestamp callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->TimeStampEventCallback(hrtc); #else HAL_RTCEx_TimeStampEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the TIMESTAMP interrupt pending bit */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); + /* Clear the Timestamp interrupt pending bit */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF); } } - /* Get the Tamper1 interrupt source enable status */ - if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != (uint32_t)RESET) + /* Get the Tamper 1 interrupt source enable status */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U) { - /* Get the pending status of the Tamper1 Interrupt */ - if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != (uint32_t)RESET) + /* Get the pending status of the Tamper 1 Interrupt */ + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) != 0U) { /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -531,15 +637,16 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); } } - /* Get the Tamper2 interrupt source enable status */ - if(__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != (uint32_t)RESET) +#if defined(RTC_TAMPER2_SUPPORT) + /* Get the Tamper 2 interrupt source enable status */ + if (__HAL_RTC_TAMPER_GET_IT_SOURCE(hrtc, RTC_IT_TAMP) != 0U) { - /* Get the pending status of the Tamper2 Interrupt */ - if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != (uint32_t)RESET) + /* Get the pending status of the Tamper 2 Interrupt */ + if (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) != 0U) { /* Tamper callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) @@ -552,8 +659,9 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); } } +#endif /* RTC_TAMPER2_SUPPORT */ - /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ + /* Clear the EXTI's Flag for RTC Timestamp and Tamper */ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); /* Change RTC state */ @@ -561,7 +669,7 @@ void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) } /** - * @brief TimeStamp callback. + * @brief Timestamp callback. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None @@ -570,8 +678,9 @@ __weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_TimeStampEventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file */ } @@ -585,11 +694,13 @@ __weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_Tamper1EventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file */ } +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Tamper 2 callback. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains @@ -600,13 +711,15 @@ __weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_Tamper2EventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file */ } +#endif /* RTC_TAMPER2_SUPPORT */ /** - * @brief This function handles TimeStamp polling request. + * @brief Handles Timestamp polling request. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -619,27 +732,27 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) + while (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == 0U) { - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) + if (Timeout != HAL_MAX_DELAY) + { + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + + if (__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != 0U) { - /* Clear the TIMESTAMP Overrun Flag */ + /* Clear the Timestamp Overrun Flag */ __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - /* Change TIMESTAMP state */ + /* Change Timestamp state */ hrtc->State = HAL_RTC_STATE_ERROR; return HAL_ERROR; } - - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } } /* Change RTC state */ @@ -649,7 +762,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint3 } /** - * @brief This function handles Tamper1 Polling. + * @brief Handles Tamper 1 Polling. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -663,11 +776,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ tickstart = HAL_GetTick(); /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) + while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -676,7 +789,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ } /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP1F); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -684,8 +797,9 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_ return HAL_OK; } +#if defined(RTC_TAMPER2_SUPPORT) /** - * @brief This function handles Tamper2 Polling. + * @brief Handles Tamper 2 Polling. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -699,11 +813,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ tickstart = HAL_GetTick(); /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) + while (__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -712,38 +826,39 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ } /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F); + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; return HAL_OK; } +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ -/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wake-up functions - * @brief RTC Wake-up functions - * +/** @defgroup RTCEx_Exported_Functions_Group2 RTC Wakeup functions + * @brief RTC Wakeup functions + * @verbatim =============================================================================== - ##### RTC Wake-up functions ##### + ##### RTC Wakeup functions ##### =============================================================================== - [..] This section provides functions allowing to configure Wake-up feature + [..] This section provides functions allowing to configure Wakeup feature @endverbatim * @{ */ /** - * @brief Sets wake up timer. + * @brief Sets wakeup timer. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param WakeUpCounter Wake up counter - * @param WakeUpClock Wake up clock + * @param WakeUpCounter Wakeup counter + * @param WakeUpClock Wakeup clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) @@ -762,15 +877,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + /* Check RTC WUTWF flag is reset only when wakeup timer enabled*/ + if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) { tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) + /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -785,14 +900,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } } + /* Disable the Wakeup timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); + /* Clear the Wakeup flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -806,16 +926,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } } - /* Clear the Wake-up Timer clock source bits in CR register */ + /* Clear the Wakeup Timer clock source bits in CR register */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; /* Configure the clock source */ hrtc->Instance->CR |= (uint32_t)WakeUpClock; - /* Configure the Wake-up Timer counter */ + /* Configure the Wakeup Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - /* Enable the Wake-up Timer */ + /* Enable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); /* Enable the write protection for RTC registers */ @@ -830,16 +950,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t Wak } /** - * @brief Sets wake up timer with interrupt + * @brief Sets wakeup timer with interrupt. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param WakeUpCounter Wake up counter - * @param WakeUpClock Wake up clock + * @param WakeUpCounter Wakeup counter + * @param WakeUpClock Wakeup clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - __IO uint32_t count; + __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); @@ -853,14 +973,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Check RTC WUTWF flag is reset only when wake up timer enabled */ - if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) + /* Check RTC WUTWF flag is reset only when wakeup timer enabled */ + if ((hrtc->Instance->CR & RTC_CR_WUTE) != 0U) { - /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ - count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + /* Wait till RTC WUTWF flag is reset and if timeout is reached exit */ do { - if(count-- == 0U) + if (count-- == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -872,17 +991,22 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t return HAL_TIMEOUT; } - } - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET); + } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) != 0U); } + /* Disable the Wakeup timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + /* Clear the Wakeup flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + + /* Reload the counter */ + count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U); + + /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ do { - if(count-- == 0U) + if (count-- == 0U) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -894,30 +1018,25 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t return HAL_TIMEOUT; } - } - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET); + } while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U); - /* Configure the Wake-up Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Clear the Wake-up Timer clock source bits in CR register */ + /* Clear the Wakeup Timer clock source bits in CR register */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; /* Configure the clock source */ hrtc->Instance->CR |= (uint32_t)WakeUpClock; - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - - EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - /* Clear RTC Wake Up timer Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + /* RTC wakeup timer Interrupt Configuration: EXTI configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); + /* Configure the interrupt in the RTC_CR register */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc, RTC_IT_WUT); - /* Enable the Wake-up Timer */ + /* Enable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); /* Enable the write protection for RTC registers */ @@ -932,12 +1051,12 @@ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t } /** - * @brief Deactivates wake up timer counter. + * @brief Deactivates wakeup timer counter. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval HAL status */ -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { uint32_t tickstart = 0U; @@ -949,19 +1068,19 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Disable the Wake-up Timer */ + /* Disable the Wakeup Timer */ __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc, RTC_IT_WUT); /* Get tick */ tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + /* Wait till RTC WUTWF flag is set and if timeout is reached exit */ + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -987,7 +1106,7 @@ uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) } /** - * @brief Gets wake up timer counter. + * @brief Gets wakeup timer counter. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval Counter value @@ -999,8 +1118,8 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) } /** - * @brief This function handles Wake Up Timer interrupt request. - * @note Unlike alarm interrupt line (shared by AlarmA and AlarmB) and tamper + * @brief Handles Wakeup Timer interrupt request. + * @note Unlike alarm interrupt line (shared by Alarms A and B) or tamper * interrupt line (shared by timestamp and tampers) wakeup timer * interrupt line is exclusive to the wakeup timer. * There is no need in this case to check on the interrupt enable @@ -1011,17 +1130,17 @@ uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) */ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) { - /* Get the pending status of the WAKEUPTIMER Interrupt */ - if(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != (uint32_t)RESET) + /* Get the pending status of the Wakeup timer Interrupt */ + if (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) != 0U) { - /* WAKEUPTIMER callback */ + /* Wakeup timer callback */ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) hrtc->WakeUpTimerEventCallback(hrtc); #else HAL_RTCEx_WakeUpTimerEventCallback(hrtc); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ - /* Clear the WAKEUPTIMER interrupt pending bit */ + /* Clear the Wakeup timer interrupt pending bit */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); } @@ -1033,7 +1152,7 @@ void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) } /** - * @brief Wake Up Timer callback. + * @brief Wakeup Timer callback. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @retval None @@ -1042,13 +1161,14 @@ __weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file */ } /** - * @brief This function handles Wake Up Timer Polling. + * @brief Handles Wakeup Timer Polling. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -1061,20 +1181,19 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) + while (__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; } } } - /* Clear the WAKEUPTIMER Flag */ + /* Clear the Wakeup timer Flag */ __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); /* Change RTC state */ @@ -1087,13 +1206,12 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @} */ - -/** @defgroup RTCEx_Exported_Functions_Group3 Extension Peripheral Control functions - * @brief Extension Peripheral Control functions - * +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @brief Extended Peripheral Control functions + * @verbatim =============================================================================== - ##### Extension Peripheral Control functions ##### + ##### Extended Peripheral Control functions ##### =============================================================================== [..] This subsection provides functions allowing to @@ -1119,8 +1237,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param BackupRegister RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. + * This parameter can be: RTC_BKP_DRx (where x can be from 0 to 19) + * to specify the register. * @param Data Data to be written in the specified RTC Backup data register. * @retval None */ @@ -1131,7 +1249,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); - tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp = (uint32_t) & (hrtc->Instance->BKP0R); tmp += (BackupRegister * 4U); /* Write the specified register */ @@ -1143,8 +1261,8 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param BackupRegister RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. + * This parameter can be: RTC_BKP_DRx (where x can be from 0 to 19) + * to specify the register. * @retval Read value */ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) @@ -1154,7 +1272,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) /* Check the parameters */ assert_param(IS_RTC_BKP(BackupRegister)); - tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp = (uint32_t) & (hrtc->Instance->BKP0R); tmp += (BackupRegister * 4U); /* Read the specified register */ @@ -1166,7 +1284,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param CalibSign Specifies the sign of the coarse calibration value. - * This parameter can be one of the following values : + * This parameter can be one of the following values: * @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive * @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative * @param Value value of coarse calibration expressed in ppm (coded on 5 bits). @@ -1178,8 +1296,10 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) * sign with a 4-ppm step. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t CalibSign, uint32_t Value) +HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value) { + HAL_StatusTypeDef status; + /* Check the parameters */ assert_param(IS_RTC_CALIB_SIGN(CalibSign)); assert_param(IS_RTC_CALIB_VALUE(Value)); @@ -1192,42 +1312,33 @@ HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t Cal /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - return HAL_ERROR; - } - else + if (status == HAL_OK) { /* Enable the Coarse Calibration */ __HAL_RTC_COARSE_CALIB_ENABLE(hrtc); /* Set the coarse calibration value */ - hrtc->Instance->CALIBR = (uint32_t)(CalibSign|Value); + hrtc->Instance->CALIBR = (uint32_t)(CalibSign | Value); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + status = RTC_ExitInitMode(hrtc); + } + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change state */ - hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** @@ -1236,8 +1347,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t Cal * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status; + /* Process Locked */ __HAL_LOCK(hrtc); @@ -1246,39 +1359,30 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + if (status == HAL_OK) { - /* Enable the Coarse Calibration */ + /* Disable the Coarse Calibration */ __HAL_RTC_COARSE_CALIB_DISABLE(hrtc); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + status = RTC_ExitInitMode(hrtc); + } + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change state */ - hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** @@ -1286,7 +1390,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param SmoothCalibPeriod Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : + * This parameter can be can be one of the following values: * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s. * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s. * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s. @@ -1294,21 +1398,21 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc) * This parameter can be one of the following values: * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses. * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmouthCalibMinusPulsesValue Select the value of CALM[80] bits. + * @param SmoothCalibMinusPulsesValue Select the value of CALM[8:0] bits. * This parameter can be one any value from 0 to 0x000001FF. * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmouthCalibMinusPulsesValue must be equal to 0. + * SmoothCalibMinusPulsesValue must be equal to 0. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) { uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -1319,15 +1423,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /* check if a calibration is pending*/ - if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + if ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) { - /* Get tick */ - tickstart = HAL_GetTick(); + /* Get tick */ + tickstart = HAL_GetTick(); /* check if a calibration is pending*/ - while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + while ((hrtc->Instance->ISR & RTC_ISR_RECALPF) != 0U) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1344,7 +1448,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo } /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue); + hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | \ + (uint32_t)SmoothCalibPlusPulses | \ + (uint32_t)SmoothCalibMinusPulsesValue); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1364,14 +1470,14 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param ShiftAdd1S Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values : + * This parameter can be one of the following values: * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. * @arg RTC_SHIFTADD1S_RESET: No effect. * @param ShiftSubFS Select the number of Second Fractions to substitute. * This parameter can be one any value from 0 to 0x7FFF. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) { uint32_t tickstart = 0U; @@ -1390,59 +1496,59 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /* Get tick */ tickstart = HAL_GetTick(); - /* Wait until the shift is completed*/ - while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) + /* Wait until the shift is completed */ + while ((hrtc->Instance->ISR & RTC_ISR_SHPF) != 0U) + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } + } - /* Check if the reference clock detection is disabled */ - if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); + /* Check if the reference clock detection is disabled */ + if ((hrtc->Instance->CR & RTC_CR_REFCKON) == 0U) + { + /* Configure the Shift settings */ + hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if ((hrtc->Instance->CR & RTC_CR_BYPSHAD) == 0U) + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_ERROR; + hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_ERROR; - } + return HAL_ERROR; } } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_ERROR; - } + return HAL_ERROR; + } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1460,13 +1566,13 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. - * @param CalibOutput Select the Calibration output Selection . + * @param CalibOutput Select the Calibration output Selection. * This parameter can be one of the following values: * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput) { /* Check the parameters */ assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); @@ -1505,7 +1611,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc) { /* Process Locked */ __HAL_LOCK(hrtc); @@ -1535,8 +1641,10 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status; + /* Process Locked */ __HAL_LOCK(hrtc); @@ -1545,38 +1653,30 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_ERROR; - } - else + if (status == HAL_OK) { + /* Enable the reference clock detection */ __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + status = RTC_ExitInitMode(hrtc); + } + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** @@ -1585,8 +1685,10 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) * the configuration information for RTC. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc) { + HAL_StatusTypeDef status; + /* Process Locked */ __HAL_LOCK(hrtc); @@ -1595,38 +1697,30 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); - return HAL_ERROR; - } - else + if (status == HAL_OK) { + /* Disable the reference clock detection */ __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + status = RTC_ExitInitMode(hrtc); + } + + if (status == HAL_OK) + { + hrtc->State = HAL_RTC_STATE_READY; } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ __HAL_UNLOCK(hrtc); - return HAL_OK; + return status; } /** @@ -1637,7 +1731,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) * directly from the Calendar counter. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) { /* Process Locked */ __HAL_LOCK(hrtc); @@ -1670,7 +1764,7 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) * directly from the Calendar counter. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) { /* Process Locked */ __HAL_LOCK(hrtc); @@ -1699,9 +1793,9 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) * @} */ - /** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions - * @brief Extended features functions - * +/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions + * @brief Extended features functions + * @verbatim =============================================================================== ##### Extended features functions ##### @@ -1724,13 +1818,14 @@ __weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_AlarmBEventCallback could be implemented in the user file + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file */ } /** - * @brief This function handles AlarmB Polling request. + * @brief Handles Alarm B Polling request. * @param hrtc pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param Timeout Timeout duration @@ -1743,11 +1838,12 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /* Get tick */ tickstart = HAL_GetTick(); - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) + /* Wait till RTC ALRBF flag is set and if timeout is reached exit */ + while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == 0U) { - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1755,7 +1851,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t } } - /* Clear the Alarm Flag */ + /* Clear the Alarm flag */ __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); /* Change RTC state */ @@ -1780,5 +1876,3 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc_ex.h index 76859eeb263..ff5f14d4989 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_rtc_ex.h @@ -2,30 +2,30 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc_ex.h * @author MCD Application Team - * @brief Header file of RTC HAL Extension module. + * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_RTC_EX_H -#define __STM32F4xx_HAL_RTC_EX_H +#ifndef STM32F4xx_HAL_RTC_EX_H +#define STM32F4xx_HAL_RTC_EX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ + #include "stm32f4xx_hal_def.h" /** @addtogroup STM32F4xx_HAL_Driver @@ -34,26 +34,27 @@ /** @addtogroup RTCEx * @{ - */ + */ + +/* Exported types ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ /** @defgroup RTCEx_Exported_Types RTCEx Exported Types * @{ */ -/** - * @brief RTC Tamper structure definition +/** + * @brief RTC Tamper structure definition */ -typedef struct +typedef struct { uint32_t Tamper; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Pin_Definitions */ uint32_t PinSelection; /*!< Specifies the Tamper Pin. - This parameter can be a value of @ref RTCEx_Tamper_Pins_Selection */ + This parameter can be a value of @ref RTCEx_Tamper_Pin_Selection */ uint32_t Trigger; /*!< Specifies the Tamper Trigger. - This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */ uint32_t Filter; /*!< Specifies the RTC Filter Tamper. This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */ @@ -62,24 +63,25 @@ typedef struct This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */ uint32_t PrechargeDuration; /*!< Specifies the Precharge Duration . - This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . - This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ -}RTC_TamperTypeDef; +} RTC_TamperTypeDef; /** * @} */ /* Exported constants --------------------------------------------------------*/ + /** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants * @{ - */ + */ -/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions +/** @defgroup RTCEx_Backup_Registers_Definitions RTCEx Backup Registers Definitions * @{ */ #define RTC_BKP_DR0 0x00000000U @@ -104,213 +106,226 @@ typedef struct #define RTC_BKP_DR19 0x00000013U /** * @} - */ + */ -/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC TimeStamp Edges Definitions +/** @defgroup RTCEx_Timestamp_Edges_Definitions RTCEx Timestamp Edges Definitions * @{ - */ + */ #define RTC_TIMESTAMPEDGE_RISING 0x00000000U -#define RTC_TIMESTAMPEDGE_FALLING 0x00000008U +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE /** * @} */ - -/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions + +/** @defgroup RTCEx_Timestamp_Pin_Selection RTC Timestamp Pin Selection * @{ */ -#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E +#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U +#if defined(RTC_AF2_SUPPORT) +#define RTC_TIMESTAMPPIN_POS1 RTC_TAFCR_TSINSEL +#endif /* RTC_AF2_SUPPORT */ +/** + * @} + */ -#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx) +/** @defgroup RTCEx_Tamper_Pin_Definitions RTCEx Tamper Pins Definitions + * @{ + */ +#define RTC_TAMPER_1 RTC_TAFCR_TAMP1E +#if defined(RTC_TAMPER2_SUPPORT) #define RTC_TAMPER_2 RTC_TAFCR_TAMP2E -#endif +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ -/** @defgroup RTCEx_Tamper_Pins_Selection RTC tamper Pins Selection +/** @defgroup RTCEx_Tamper_Pin_Selection RTC tamper Pins Selection * @{ */ - #define RTC_TAMPERPIN_DEFAULT 0x00000000U - -#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx) -#define RTC_TAMPERPIN_POS1 0x00010000U -#endif +#if defined(RTC_AF2_SUPPORT) +#define RTC_TAMPERPIN_POS1 RTC_TAFCR_TAMP1INSEL +#endif /* RTC_AF2_SUPPORT */ /** * @} - */ + */ -/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pins Selection +/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTCEx Tamper Interrupt Definitions * @{ - */ -#define RTC_TIMESTAMPPIN_DEFAULT 0x00000000U - -#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx) -#define RTC_TIMESTAMPPIN_POS1 0x00020000U -#endif + */ +#define RTC_IT_TAMP RTC_TAFCR_TAMPIE /*!< Enable global Tamper Interrupt */ /** * @} - */ + */ -/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions +/** @defgroup RTCEx_Tamper_Trigger_Definitions RTCEx Tamper Triggers Definitions * @{ - */ + */ #define RTC_TAMPERTRIGGER_RISINGEDGE 0x00000000U -#define RTC_TAMPERTRIGGER_FALLINGEDGE 0x00000002U +#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAFCR_TAMP1TRG #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE /** * @} - */ + */ -/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions +/** @defgroup RTCEx_Tamper_Filter_Definitions RTCEx Tamper Filter Definitions * @{ - */ -#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ + */ +#define RTC_TAMPERFILTER_DISABLE 0x00000000U /*!< Tamper filter is disabled */ -#define RTC_TAMPERFILTER_2SAMPLE 0x00000800U /*!< Tamper is activated after 2 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE 0x00001000U /*!< Tamper is activated after 4 - consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE 0x00001800U /*!< Tamper is activated after 8 - consecutive samples at the active level. */ +#define RTC_TAMPERFILTER_2SAMPLE RTC_TAFCR_TAMPFLT_0 /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_4SAMPLE RTC_TAFCR_TAMPFLT_1 /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_8SAMPLE RTC_TAFCR_TAMPFLT /*!< Tamper is activated after 8 + consecutive samples at the active level */ +#define RTC_TAMPERFILTER_MASK RTC_TAFCR_TAMPFLT /*!< Masking all bits except those of + field TAMPFLT */ /** * @} */ -/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions +/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTCEx Tamper Sampling Frequencies Definitions * @{ - */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 0x00000100U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 0x00000200U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 0x00000300U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 0x00000400U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 0x00000500U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 0x00000600U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 0x00000700U /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ + */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 0x00000000U /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAFCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAFCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAFCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 (RTC_TAFCR_TAMPFREQ_0 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (RTC_TAFCR_TAMPFREQ_1 | RTC_TAFCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 RTC_TAFCR_TAMPFREQ /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK RTC_TAFCR_TAMPFREQ /*!< Masking all bits except those of + field TAMPFREQ */ /** * @} */ -/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTCEx Tamper Pin Precharge Duration Definitions * @{ - */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK 0x00002000U /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK 0x00004000U /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK 0x00006000U /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ + */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK 0x00000000U /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAFCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAFCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK RTC_TAFCR_TAMPPRCH /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_MASK RTC_TAFCR_TAMPPRCH /*!< Masking all bits except those of + field TAMPPRCH */ /** * @} */ - -/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions + +/** @defgroup RTCEx_Tamper_Pull_Up_Definitions RTCEx Tamper Pull Up Definitions * @{ - */ -#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAFCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */ + */ +#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_DISABLE RTC_TAFCR_TAMPPUDIS /*!< Tamper pins are not pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_MASK RTC_TAFCR_TAMPPUDIS /*!< Masking all bits except bit TAMPPUDIS */ /** * @} */ - -/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions + +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTCEx Tamper TimeStamp On Tamper Detection Definitions * @{ - */ -#define RTC_TAMPER_PULLUP_ENABLE 0x00000000U /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ + */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAFCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE 0x00000000U /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_MASK RTC_TAFCR_TAMPTS /*!< Masking all bits except bit TAMPTS */ /** * @} */ -/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wake-up Timer Definitions +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTCEx Wakeup Timer Definitions * @{ - */ + */ #define RTC_WAKEUPCLOCK_RTCCLK_DIV16 0x00000000U -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 0x00000001U -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 0x00000002U -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 0x00000003U -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS 0x00000004U -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS 0x00000006U +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2) /** * @} - */ + */ -/** @defgroup RTCEx_Digital_Calibration_Definitions RTC Digital Calib Definitions +/** @defgroup RTCEx_Coarse_Calibration_Definitions RTCEx Coarse Calib Definitions * @{ - */ -#define RTC_CALIBSIGN_POSITIVE 0x00000000U -#define RTC_CALIBSIGN_NEGATIVE 0x00000080U + */ +#define RTC_CALIBSIGN_POSITIVE 0x00000000U +#define RTC_CALIBSIGN_NEGATIVE RTC_CALIBR_DCS /** * @} */ -/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTCEx Smooth Calib Period Definitions * @{ - */ -#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC 0x00002000U /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC 0x00004000U /*!< If RTCCLK = 32768 Hz, Smooth calibration - period is 8s, else 2exp18 RTCCLK seconds */ + */ +#define RTC_SMOOTHCALIB_PERIOD_32SEC 0x00000000U /*!< If RTCCLK = 32768 Hz, smooth calibration + period is 32s, otherwise 2^20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CALR_CALW16 /*!< If RTCCLK = 32768 Hz, smooth calibration + period is 16s, otherwise 2^19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CALR_CALW8 /*!< If RTCCLK = 32768 Hz, smooth calibration + period is 8s, otherwise 2^18 RTCCLK pulses */ /** * @} - */ + */ -/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus Pulses Definitions +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTCEx Smooth Calib Plus Pulses Definitions * @{ - */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET 0x00008000U /*!< The number of RTCCLK pulses added - during a X -second window = Y - CALM[8:0] - with Y = 512, 256, 128 when X = 32, 16, 8 */ -#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited - during a 32-second window = CALM[8:0] */ + */ +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CALR_CALP /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0] + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SMOOTHCALIB_PLUSPULSES_RESET 0x00000000U /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0] */ /** * @} */ -/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions +/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTCEx Add 1 Second Parameter Definitions * @{ - */ + */ #define RTC_SHIFTADD1S_RESET 0x00000000U -#define RTC_SHIFTADD1S_SET 0x80000000U +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S /** * @} - */ - + */ - /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions +/** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output Selection Definitions * @{ - */ -#define RTC_CALIBOUTPUT_512HZ 0x00000000U -#define RTC_CALIBOUTPUT_1HZ 0x00080000U + */ +#define RTC_CALIBOUTPUT_512HZ 0x00000000U +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL /** * @} - */ + */ /** * @} - */ - -/* Exported macro ------------------------------------------------------------*/ + */ + +/* Exported macros -----------------------------------------------------------*/ + /** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros * @{ */ -/* ---------------------------------WAKEUPTIMER---------------------------------*/ -/** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer +/* ---------------------------------WAKEUPTIMER-------------------------------*/ + +/** @defgroup RTCEx_WakeUp_Timer RTCEx WakeUp Timer * @{ */ @@ -322,152 +337,154 @@ typedef struct #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) /** - * @brief Disable the RTC Wake-up Timer peripheral. + * @brief Disable the RTC Wakeup Timer peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) /** - * @brief Enable the RTC WakeUpTimer interrupt. + * @brief Enable the RTC Wakeup Timer interrupt. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @arg RTC_IT_WUT: Wakeup Timer interrupt * @retval None */ #define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** - * @brief Disable the RTC WakeUpTimer interrupt. + * @brief Disable the RTC Wakeup Timer interrupt. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt sources to be enabled or disabled. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @arg RTC_IT_WUT: Wakeup Timer interrupt * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** - * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. + * @brief Check whether the specified RTC Wakeup Timer interrupt has occurred or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check. + * @param __INTERRUPT__ specifies the RTC Wakeup Timer interrupt to check. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @arg RTC_IT_WUT: Wakeup Timer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) /** - * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. + * @brief Check whether the specified RTC Wakeup timer interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. + * @param __INTERRUPT__ specifies the RTC Wakeup timer interrupt sources to check. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer interrupt + * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** - * @brief Get the selected RTC WakeUpTimer's flag status. + * @brief Get the selected RTC Wakeup Timer's flag status. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC WakeUpTimer Flag to check. + * @param __FLAG__ specifies the RTC Wakeup Timer flag to check. * This parameter can be: - * @arg RTC_FLAG_WUTF - * @arg RTC_FLAG_WUTWF + * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt flag + * @arg RTC_FLAG_WUTWF: Wakeup Timer 'write allowed' flag * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) /** - * @brief Clear the RTC Wake Up timer's pending flags. + * @brief Clear the RTC Wakeup timer's pending flags. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled. + * @param __FLAG__ specifies the RTC Wakeup Timer Flag to clear. * This parameter can be: - * @arg RTC_FLAG_WUTF + * @arg RTC_FLAG_WUTF: Wakeup Timer interrupt Flag * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) /** - * @brief Enable interrupt on the RTC Wake-up Timer associated Exti line. + * @brief Enable interrupt on the RTC Wakeup Timer associated EXTI line. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable interrupt on the RTC Wake-up Timer associated Exti line. + * @brief Disable interrupt on the RTC Wakeup Timer associated EXTI line. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Enable event on the RTC Wake-up Timer associated Exti line. + * @brief Enable event on the RTC Wakeup Timer associated EXTI line. * @retval None. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable event on the RTC Wake-up Timer associated Exti line. + * @brief Disable event on the RTC Wakeup Timer associated EXTI line. * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Enable falling edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Enable falling edge trigger on the RTC Wakeup Timer associated EXTI line. * @retval None. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable falling edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Disable falling edge trigger on the RTC Wakeup Timer associated EXTI line. * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Enable rising edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Enable rising edge trigger on the RTC Wakeup Timer associated EXTI line. * @retval None. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Disable rising edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Disable rising edge trigger on the RTC Wakeup Timer associated EXTI line. * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Enable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Enable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line. * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\ - __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\ - } while(0U) +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0U) /** - * @brief Disable rising & falling edge trigger on the RTC Wake-up Timer associated Exti line. + * @brief Disable rising & falling edge trigger on the RTC Wakeup Timer associated EXTI line. * This parameter can be: * @retval None. */ -#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\ - __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\ - } while(0U) +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** - * @brief Check whether the RTC Wake-up Timer associated Exti line interrupt flag is set or not. + * @brief Check whether the RTC Wakeup Timer associated EXTI line interrupt flag is set or not. * @retval Line Status. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Clear the RTC Wake-up Timer associated Exti line flag. + * @brief Clear the RTC Wakeup Timer associated EXTI line flag. * @retval None. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) /** - * @brief Generate a Software interrupt on the RTC Wake-up Timer associated Exti line. + * @brief Generate a Software interrupt on the RTC Wakeup Timer associated EXTI line. * @retval None. */ #define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) @@ -477,28 +494,29 @@ typedef struct */ /* ---------------------------------TIMESTAMP---------------------------------*/ -/** @defgroup RTCEx_Timestamp RTC Timestamp + +/** @defgroup RTCEx_Timestamp RTCEx Timestamp * @{ */ /** - * @brief Enable the RTC TimeStamp peripheral. + * @brief Enable the RTC Timestamp peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) /** - * @brief Disable the RTC TimeStamp peripheral. + * @brief Disable the RTC Timestamp peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) /** - * @brief Enable the RTC TimeStamp interrupt. + * @brief Enable the RTC Timestamp interrupt. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -506,9 +524,9 @@ typedef struct #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** - * @brief Disable the RTC TimeStamp interrupt. + * @brief Disable the RTC Timestamp interrupt. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __INTERRUPT__ specifies the RTC Timestamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -516,42 +534,43 @@ typedef struct #define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** - * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. + * @brief Check whether the specified RTC Timestamp interrupt has occurred or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check. + * @param __INTERRUPT__ specifies the RTC Timestamp interrupt to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) /** - * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. + * @brief Check whether the specified RTC Timestamp interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. - * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. + * @param __INTERRUPT__ specifies the RTC Timestamp interrupt source to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** - * @brief Get the selected RTC TimeStamp's flag status. + * @brief Get the selected RTC Timestamp's flag status. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC TimeStamp flag to check. + * @param __FLAG__ specifies the RTC Timestamp flag to check. * This parameter can be: - * @arg RTC_FLAG_TSF - * @arg RTC_FLAG_TSOVF + * @arg RTC_FLAG_TSF: Timestamp interrupt flag + * @arg RTC_FLAG_TSOVF: Timestamp overflow flag * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) /** - * @brief Clear the RTC Time Stamp's pending flags. + * @brief Clear the RTC Timestamp's pending flags. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_FLAG_TSF + * @param __FLAG__ specifies the RTC Timestamp flag to clear. + * This parameter can be: + * @arg RTC_FLAG_TSF: Timestamp interrupt flag + * @arg RTC_FLAG_TSOVF: Timestamp overflow flag * @retval None */ #define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) @@ -561,7 +580,8 @@ typedef struct */ /* ---------------------------------TAMPER------------------------------------*/ -/** @defgroup RTCEx_Tamper RTC Tamper + +/** @defgroup RTCEx_Tamper RTCEx Tamper * @{ */ @@ -578,8 +598,8 @@ typedef struct * @retval None */ #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E)) - -#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx) + +#if defined(RTC_TAMPER2_SUPPORT) /** * @brief Enable the RTC Tamper2 input detection. * @param __HANDLE__ specifies the RTC handle. @@ -593,47 +613,70 @@ typedef struct * @retval None */ #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E)) -#endif - +#endif /* RTC_TAMPER2_SUPPORT */ + +/** + * @brief Enable the RTC Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP: Tamper global interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR |= (__INTERRUPT__)) + +/** + * @brief Disable the RTC Tamper interrupt. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TAMP: Tamper global interrupt + * @retval None + */ +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAFCR &= ~(__INTERRUPT__)) + /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * This parameter can be: - * @arg RTC_IT_TAMP1 - * @arg RTC_IT_TAMP2 + * @arg RTC_IT_TAMP1: Tamper 1 interrupt + * @arg RTC_IT_TAMP2: Tamper 2 interrupt + * @note RTC_IT_TAMP2 is not applicable to all devices. * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4U)) != RESET)? SET : RESET) +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__) >> 4U)) != 0U) ? 1U : 0U) /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. * This parameter can be: - * @arg RTC_IT_TAMP: Tamper interrupt + * @arg RTC_IT_TAMP: Tamper global interrupt * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != RESET) ? SET : RESET) +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAFCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) /** * @brief Get the selected RTC Tamper's flag status. * @param __HANDLE__ specifies the RTC handle. - * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled. + * @param __FLAG__ specifies the RTC Tamper flag to be checked. * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @arg RTC_FLAG_TAMP2F + * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag + * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag + * @note RTC_FLAG_TAMP2F is not applicable to all devices. * @retval None */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) /** * @brief Clear the RTC Tamper's pending flags. * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC Tamper Flag to clear. * This parameter can be: - * @arg RTC_FLAG_TAMP1F - * @arg RTC_FLAG_TAMP2F + * @arg RTC_FLAG_TAMP1F: Tamper 1 interrupt flag + * @arg RTC_FLAG_TAMP2F: Tamper 2 interrupt flag + * @note RTC_FLAG_TAMP2F is not applicable to all devices. * @retval None */ #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) @@ -647,84 +690,86 @@ typedef struct */ /** - * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable interrupt on the RTC Tamper and Timestamp associated EXTI line. * @retval None */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @brief Disable interrupt on the RTC Tamper and Timestamp associated EXTI line. * @retval None */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Enable event on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable event on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Disable event on the RTC Tamper and Timestamp associated Exti line. + * @brief Disable event on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();\ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); \ __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0U) + } while(0U) /** - * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated EXTI line. * This parameter can be: * @retval None. */ -#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();\ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE();\ - } while(0U) +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0U) /** - * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not. + * @brief Check whether the RTC Tamper and Timestamp associated EXTI line interrupt flag is set or not. * @retval Line Status. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Clear the RTC Tamper and Timestamp associated Exti line flag. + * @brief Clear the RTC Tamper and Timestamp associated EXTI line flag. * @retval None. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) /** - * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line + * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated EXTI line * @retval None. */ #define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) @@ -732,8 +777,9 @@ typedef struct * @} */ -/* ------------------------------Calibration----------------------------------*/ -/** @defgroup RTCEx_Calibration RTC Calibration +/* ------------------------------CALIBRATION----------------------------------*/ + +/** @defgroup RTCEx_Calibration RTCEx Calibration * @{ */ @@ -784,10 +830,10 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: - * @arg RTC_FLAG_SHPF + * @arg RTC_FLAG_SHPF: Shift pending flag * @retval None */ -#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U)? 1U : 0U) /** * @} */ @@ -797,6 +843,7 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ + /** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions * @{ */ @@ -804,23 +851,27 @@ typedef struct /** @addtogroup RTCEx_Exported_Functions_Group1 * @{ */ -/* RTC TimeStamp and Tamper functions *****************************************/ -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); -HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); +/* RTC Timestamp and Tamper functions *****************************************/ +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin); +HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t RTC_TimeStampEdge, uint32_t RTC_TimeStampPin); HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +#if defined(RTC_TAMPER2_SUPPORT) +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); +#endif /* RTC_TAMPER2_SUPPORT */ +void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#if defined(RTC_TAMPER2_SUPPORT) HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ @@ -828,13 +879,13 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_ /** @addtogroup RTCEx_Exported_Functions_Group2 * @{ */ -/* RTC Wake-up functions ******************************************************/ +/* RTC Wakeup functions ******************************************************/ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** * @} @@ -843,13 +894,13 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /** @addtogroup RTCEx_Exported_Functions_Group3 * @{ */ -/* Extension Control functions ************************************************/ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +/* Extended Control functions ************************************************/ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value); HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue); +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc); @@ -864,8 +915,8 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); /** @addtogroup RTCEx_Exported_Functions_Group4 * @{ */ -/* Extension RTC features functions *******************************************/ -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); +/* Extended RTC features functions *******************************************/ +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); /** * @} @@ -878,73 +929,83 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ + +/** @defgroup RTCEx_Private_Constants RTCEx Private Constants + * @{ + */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT EXTI_IMR_MR21 /*!< External interrupt line 21 Connected to the RTC Tamper and Timestamp event */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT EXTI_IMR_MR22 /*!< External interrupt line 22 Connected to the RTC Wakeup event */ +/** + * @} + */ + /** @defgroup RTCEx_Private_Constants RTCEx Private Constants * @{ */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ +/* Masks Definition */ +#if defined(RTC_TAMPER2_SUPPORT) +#define RTC_TAMPER_ENABLE_BITS_MASK ((uint32_t) (RTC_TAMPER_1 | \ + RTC_TAMPER_2)) + +#define RTC_TAMPER_FLAGS_MASK ((uint32_t) (RTC_FLAG_TAMP1F | \ + RTC_FLAG_TAMP2F)) +#else /* RTC_TAMPER2_SUPPORT */ +#define RTC_TAMPER_ENABLE_BITS_MASK RTC_TAMPER_1 + +#define RTC_TAMPER_FLAGS_MASK RTC_FLAG_TAMP1F +#endif /* RTC_TAMPER2_SUPPORT */ /** * @} */ /* Private macros ------------------------------------------------------------*/ + /** @defgroup RTCEx_Private_Macros RTCEx Private Macros * @{ */ /** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters * @{ - */ -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4) || \ - ((BKP) == RTC_BKP_DR5) || \ - ((BKP) == RTC_BKP_DR6) || \ - ((BKP) == RTC_BKP_DR7) || \ - ((BKP) == RTC_BKP_DR8) || \ - ((BKP) == RTC_BKP_DR9) || \ - ((BKP) == RTC_BKP_DR10) || \ - ((BKP) == RTC_BKP_DR11) || \ - ((BKP) == RTC_BKP_DR12) || \ - ((BKP) == RTC_BKP_DR13) || \ - ((BKP) == RTC_BKP_DR14) || \ - ((BKP) == RTC_BKP_DR15) || \ - ((BKP) == RTC_BKP_DR16) || \ - ((BKP) == RTC_BKP_DR17) || \ - ((BKP) == RTC_BKP_DR18) || \ - ((BKP) == RTC_BKP_DR19)) + */ +#define IS_RTC_BKP(BKP) ((BKP) < (uint32_t) RTC_BKP_NUMBER) + #define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E ))) == 0x00U) && ((TAMPER) != (uint32_t)RESET)) -#else -#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)!(RTC_TAFCR_TAMP1E | RTC_TAFCR_TAMP2E))) == 0x00U) && ((TAMPER) != (uint32_t)RESET)) -#endif +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & ((uint32_t)~RTC_TAMPER_ENABLE_BITS_MASK)) == 0x00U) && ((TAMPER) != 0U)) -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -#define IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT) -#else +#if defined(RTC_AF2_SUPPORT) #define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TAMPERPIN_DEFAULT) || \ ((PIN) == RTC_TAMPERPIN_POS1)) -#endif +#else /* RTC_AF2_SUPPORT */ +#define IS_RTC_TAMPER_PIN(PIN) ((PIN) == RTC_TAMPERPIN_DEFAULT) +#endif /* RTC_AF2_SUPPORT */ -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) -#define IS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_DEFAULT) -#else +#if defined(RTC_AF2_SUPPORT) #define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT) || \ ((PIN) == RTC_TIMESTAMPPIN_POS1)) -#endif -#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ +#else /* RTC_AF2_SUPPORT */ +#define IS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_DEFAULT) +#endif /* RTC_AF2_SUPPORT */ + +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) + #define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) + +#define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER) \ + ( ( ((FILTER) != RTC_TAMPERFILTER_DISABLE) \ + && ( ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) \ + || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))) \ + || ( ((FILTER) == RTC_TAMPERFILTER_DISABLE) \ + && ( ((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) \ + || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE)))) + #define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ @@ -953,14 +1014,18 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) + #define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) -#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + #define IS_RTC_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) + +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) + #define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ @@ -968,7 +1033,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) -#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFFU) +#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= RTC_WUTR_WUT) + #define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \ ((SIGN) == RTC_CALIBSIGN_NEGATIVE)) @@ -976,14 +1042,18 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t #define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) + ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) + #define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FFU) +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM) + #define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ - ((SEL) == RTC_SHIFTADD1S_SET)) -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFFU) + ((SEL) == RTC_SHIFTADD1S_SET)) + +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS) + #define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) /** @@ -996,16 +1066,14 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /** * @} - */ + */ /** * @} - */ - + */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_RTC_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_RTC_EX_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.c index 7d157ccbca3..eda41dd3c98 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -199,18 +210,6 @@ and weak (surcharged) callbacks are used. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -261,7 +260,7 @@ typedef enum * @{ */ static void SAI_FillFifo(SAI_HandleTypeDef *hsai); -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode); +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, uint32_t mode); static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); @@ -1244,6 +1243,9 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + SAI_Disable(hsai); + /* Disable the SAI DMA request */ hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN; @@ -1275,9 +1277,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai) } } - /* Disable SAI peripheral */ - SAI_Disable(hsai); - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1303,6 +1302,9 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) /* Process Locked */ __HAL_LOCK(hsai); + /* Disable SAI peripheral */ + SAI_Disable(hsai); + /* Check SAI DMA is enabled or not */ if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN) { @@ -1342,9 +1344,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai) hsai->Instance->IMR = 0U; hsai->Instance->CLRFR = 0xFFFFFFFFU; - /* Disable SAI peripheral */ - SAI_Disable(hsai); - /* Flush the fifo */ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH); @@ -1910,7 +1909,7 @@ __weak void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai) * the configuration information for SAI module. * @retval HAL state */ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai) { return hsai->State; } @@ -1921,7 +1920,7 @@ HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai) * the configuration information for the specified SAI Block. * @retval SAI Error Code */ -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai) +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai) { return hsai->ErrorCode; } @@ -2139,7 +2138,7 @@ static void SAI_FillFifo(SAI_HandleTypeDef *hsai) * @param mode SAI_MODE_DMA or SAI_MODE_IT * @retval the list of the IT flag to enable */ -static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode) +static uint32_t SAI_InterruptFlag(const SAI_HandleTypeDef *hsai, uint32_t mode) { uint32_t tmpIT = SAI_IT_OVRUDR; @@ -2553,4 +2552,3 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.h index 0307f92333a..368316d20a4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -118,7 +117,7 @@ typedef struct uint32_t TriState; /*!< Specifies the companding mode type. This parameter can be a value of @ref SAI_TRIState_Management */ - /* This part of the structure is automatically filled if your are using the high level intialisation + /* This part of the structure is automatically filled if your are using the high level initialisation function HAL_SAI_InitProtocol */ uint32_t Protocol; /*!< Specifies the SAI Block protocol. @@ -749,8 +748,8 @@ void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); * @{ */ /* Peripheral State functions ************************************************/ -HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai); -uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); +HAL_SAI_StateTypeDef HAL_SAI_GetState(const SAI_HandleTypeDef *hsai); +uint32_t HAL_SAI_GetError(const SAI_HandleTypeDef *hsai); /** * @} */ @@ -894,4 +893,3 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); #endif /* __STM32F4xx_HAL_SAI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai_ex.c index 120a2777473..2d5e8c4d670 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai_ex.c @@ -7,6 +7,17 @@ * functionalities of SAI extension peripheral: * + Extension features functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### SAI peripheral extension features ##### @@ -23,17 +34,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -95,7 +95,7 @@ * the configuration information for SAI module. * @retval SAI Clock Input */ -void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai) +void SAI_BlockSynchroConfig(const SAI_HandleTypeDef *hsai) { uint32_t tmpregisterGCR; @@ -158,7 +158,7 @@ void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai) * the configuration information for SAI module. * @retval SAI Clock Input */ -uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai) +uint32_t SAI_GetInputClock(const SAI_HandleTypeDef *hsai) { /* This variable used to store the SAI_CK_x (value in Hz) */ uint32_t saiclocksource = 0U; @@ -308,4 +308,3 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai_ex.h index fbd44979dee..75ba6d20f58 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sai_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -72,8 +71,8 @@ extern "C" { */ /* Extended features functions ************************************************/ -void SAI_BlockSynchroConfig(SAI_HandleTypeDef *hsai); -uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai); +void SAI_BlockSynchroConfig(const SAI_HandleTypeDef *hsai); +uint32_t SAI_GetInputClock(const SAI_HandleTypeDef *hsai); /** * @} */ @@ -113,4 +112,3 @@ uint32_t SAI_GetInputClock(SAI_HandleTypeDef *hsai); #endif /* __STM32F4xx_HAL_SAI_EX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.c index ea36feb53bd..f4145e9edbb 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -199,7 +210,7 @@ The compilation define USE_HAL_SD_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SD_RegisterCallback() to register a user callback, + Use Functions HAL_SD_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -210,7 +221,7 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_SD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) TxCpltCallback : callback when a transmission transfer is completed. (+) RxCpltCallback : callback when a reception transfer is completed. @@ -220,12 +231,12 @@ (+) MspDeInitCallback : SD MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_SD_Init and if the state is HAL_SD_STATE_RESET + By default, after the HAL_SD_Init and if the state is HAL_SD_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SD_Init - and @ref HAL_SD_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SD_Init and @ref HAL_SD_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SD_Init + and HAL_SD_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SD_Init and HAL_SD_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -233,8 +244,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SD_RegisterCallback before calling @ref HAL_SD_DeInit - or @ref HAL_SD_Init function. + using HAL_SD_RegisterCallback before calling HAL_SD_DeInit + or HAL_SD_Init function. When The compilation define USE_HAL_SD_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -242,17 +253,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -430,6 +430,9 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) /* Enable SDIO Clock */ __HAL_SD_ENABLE(hsd); + /* Required power up waiting time before starting the SD initialization sequence */ + HAL_Delay(2); + /* Identify card operating voltage */ errorstate = SD_PowerON(hsd); if(errorstate != HAL_SD_ERROR_NONE) @@ -3272,5 +3275,3 @@ static void SD_Write_IT(SD_HandleTypeDef *hsd) */ #endif /* SDIO */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.h index e82e7e0ce0a..73fc7de6981 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sd.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -757,5 +756,3 @@ HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd); #endif /* STM32F4xx_HAL_SD_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sdram.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sdram.c index da34f47a843..31633a2b4ef 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sdram.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sdram.c @@ -3,57 +3,68 @@ * @file stm32f4xx_hal_sdram.c * @author MCD Application Team * @brief SDRAM HAL module driver. - * This file provides a generic firmware to drive SDRAM memories mounted + * This file provides a generic firmware to drive SDRAM memories mounted * as external device. - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] - This driver is a generic layered driver which contains a set of APIs used to - control SDRAM memories. It uses the FMC layer functions to interface - with SDRAM devices. + This driver is a generic layered driver which contains a set of APIs used to + control SDRAM memories. It uses the FMC layer functions to interface + with SDRAM devices. The following sequence should be followed to configure the FMC to interface - with SDRAM memories: - + with SDRAM memories: + (#) Declare a SDRAM_HandleTypeDef handle structure, for example: - SDRAM_HandleTypeDef hdsram - - (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed + SDRAM_HandleTypeDef hsdram + + (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed values of the structure member. - - (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined - base register instance for NOR or SDRAM device - + + (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SDRAM device + (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: FMC_SDRAM_TimingTypeDef Timing; and fill its fields with the allowed values of the structure member. - + (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function performs the following sequence: - + (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() - (##) Control register configuration using the FMC SDRAM interface function + (##) Control register configuration using the FMC SDRAM interface function FMC_SDRAM_Init() - (##) Timing register configuration using the FMC SDRAM interface function + (##) Timing register configuration using the FMC SDRAM interface function FMC_SDRAM_Timing_Init() (##) Program the SDRAM external device by applying its initialization sequence according to the device plugged in your hardware. This step is mandatory - for accessing the SDRAM device. + for accessing the SDRAM device. - (#) At this stage you can perform read/write accesses from/to the memory connected + (#) At this stage you can perform read/write accesses from/to the memory connected to the SDRAM Bank. You can perform either polling or DMA transfer using the following APIs: (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer - + (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ - HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or + HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM - device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef - structure. - + device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef + structure. + (#) You can continuously monitor the SDRAM device HAL state by calling the function HAL_SDRAM_GetState() @@ -63,25 +74,25 @@ The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SDRAM_RegisterCallback() to register a user callback, + Use Functions HAL_SDRAM_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : SDRAM MspInit. (+) MspDeInitCallback : SDRAM MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_SDRAM_UnRegisterCallback() to reset a callback to the default + Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : SDRAM MspInit. (+) MspDeInitCallback : SDRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET + By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SDRAM_Init - and @ref HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SDRAM_Init and @ref HAL_SDRAM_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init + and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -89,8 +100,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SDRAM_RegisterCallback before calling @ref HAL_SDRAM_DeInit - or @ref HAL_SDRAM_Init function. + using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit + or HAL_SDRAM_Init function. When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -98,80 +109,74 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(FMC_Bank5_6) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#ifdef HAL_SDRAM_MODULE_ENABLED + /** @defgroup SDRAM SDRAM * @brief SDRAM driver modules * @{ */ -#ifdef HAL_SDRAM_MODULE_ENABLED -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma); +static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma); +static void SDRAM_DMAError(DMA_HandleTypeDef *hdma); + /* Exported functions --------------------------------------------------------*/ /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions * @{ */ - -/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + +/** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim ============================================================================== ##### SDRAM Initialization and de_initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to initialize/de-initialize the SDRAM memory - + @endverbatim * @{ */ - + /** * @brief Performs the SDRAM device initialization sequence. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @param Timing Pointer to SDRAM control timing structure + * @param Timing Pointer to SDRAM control timing structure * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) -{ +{ /* Check the SDRAM handle parameter */ - if(hsdram == NULL) + if (hsdram == NULL) { return HAL_ERROR; } - - if(hsdram->State == HAL_SDRAM_STATE_RESET) - { + + if (hsdram->State == HAL_SDRAM_STATE_RESET) + { /* Allocate lock resource and initialize it */ hsdram->Lock = HAL_UNLOCKED; #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - if(hsdram->MspInitCallback == NULL) + if (hsdram->MspInitCallback == NULL) { hsdram->MspInitCallback = HAL_SDRAM_MspInit; } @@ -184,21 +189,20 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy #else /* Initialize the low level hardware (MSP) */ HAL_SDRAM_MspInit(hsdram); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } - + /* Initialize the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_BUSY; - + /* Initialize SDRAM control Interface */ - FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); - + (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); + /* Initialize SDRAM timing Interface */ - FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); - + (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); /* Update the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_READY; - + return HAL_OK; } @@ -211,7 +215,7 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) { #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - if(hsdram->MspDeInitCallback == NULL) + if (hsdram->MspDeInitCallback == NULL) { hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; } @@ -221,10 +225,10 @@ HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) #else /* Initialize the low level hardware (MSP) */ HAL_SDRAM_MspDeInit(hsdram); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /* Configure the SDRAM registers with their reset values */ - FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); + (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); /* Reset the SDRAM controller state */ hsdram->State = HAL_SDRAM_STATE_RESET; @@ -245,9 +249,10 @@ __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsdram); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_SDRAM_MspInit could be implemented in the user file - */ + */ } /** @@ -260,9 +265,10 @@ __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsdram); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_SDRAM_MspDeInit could be implemented in the user file - */ + */ } /** @@ -270,18 +276,18 @@ __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @retval HAL status -*/ + */ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) { /* Check SDRAM interrupt Rising edge flag */ - if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) + if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) { /* SDRAM refresh error interrupt callback */ #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) hsdram->RefreshErrorCallback(hsdram); #else HAL_SDRAM_RefreshErrorCallback(hsdram); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /* Clear SDRAM refresh error interrupt pending bit */ __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); @@ -291,16 +297,17 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) /** * @brief SDRAM Refresh error callback. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. + * the configuration information for SDRAM module. * @retval None */ __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsdram); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file - */ + */ } /** @@ -313,9 +320,10 @@ __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file - */ + */ } /** @@ -327,24 +335,26 @@ __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma); + /* NOTE: This function Should not be modified, when the callback is needed, the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file - */ + */ } + /** * @} */ -/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions +/** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions + * @brief Input Output and memory control functions * - @verbatim + @verbatim ============================================================================== ##### SDRAM Input and Output functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to use and control the SDRAM memory - + @endverbatim * @{ */ @@ -354,289 +364,377 @@ __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer + * @param pDstBuffer Pointer to destination buffer * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) { + uint32_t size; __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsdram); - + uint8_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { - return HAL_ERROR; - } - - /* Read data from source */ - for(; BufferSize != 0U; BufferSize--) + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from source */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *(__IO uint8_t *)pSdramAddress; + pdestbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else { - *pDstBuffer = *(__IO uint8_t *)pSdramAddress; - pDstBuffer++; - pSdramAddress++; + return HAL_ERROR; } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; + + return HAL_OK; } - + /** * @brief Writes 8-bit data buffer to SDRAM memory. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write + * @param pSrcBuffer Pointer to source buffer to write * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) { + uint32_t size; __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; - uint32_t tmp = 0U; - - /* Process Locked */ - __HAL_LOCK(hsdram); - + uint8_t *psrcbuff = pSrcBuffer; + /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + else if (hsdram->State == HAL_SDRAM_STATE_READY) { - return HAL_ERROR; + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *(__IO uint8_t *)pSdramAddress = *psrcbuff; + psrcbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); } - - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + else { - *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; - pSrcBuffer++; - pSdramAddress++; + return HAL_ERROR; } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Reads 16-bit data buffer from the SDRAM memory. + * @brief Reads 16-bit data buffer from the SDRAM memory. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer + * @param pDstBuffer Pointer to destination buffer * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) { - __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsdram); - + uint32_t size; + __IO uint32_t *pSdramAddress = pAddress; + uint16_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { - return HAL_ERROR; - } - - /* Read data from source */ - for(; BufferSize != 0U; BufferSize--) + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size >= 2U ; size -= 2U) + { + *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); + pdestbuff++; + *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U); + pdestbuff++; + pSdramAddress++; + } + + /* Read last 16-bits if size is not 32-bits multiple */ + if ((BufferSize % 2U) != 0U) + { + *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else { - *pDstBuffer = *(__IO uint16_t *)pSdramAddress; - pDstBuffer++; - pSdramAddress++; + return HAL_ERROR; } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Writes 16-bit data buffer to SDRAM memory. + * @brief Writes 16-bit data buffer to SDRAM memory. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write + * @param pSrcBuffer Pointer to source buffer to write * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) { - __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; - uint32_t tmp = 0U; - - /* Process Locked */ - __HAL_LOCK(hsdram); - + uint32_t size; + __IO uint32_t *psdramaddress = pAddress; + uint16_t *psrcbuff = pSrcBuffer; + /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + else if (hsdram->State == HAL_SDRAM_STATE_READY) { - return HAL_ERROR; + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size >= 2U ; size -= 2U) + { + *psdramaddress = (uint32_t)(*psrcbuff); + psrcbuff++; + *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U); + psrcbuff++; + psdramaddress++; + } + + /* Write last 16-bits if size is not 32-bits multiple */ + if ((BufferSize % 2U) != 0U) + { + *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U); + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); } - - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + else { - *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; - pSrcBuffer++; - pSdramAddress++; + return HAL_ERROR; } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Reads 32-bit data buffer from the SDRAM memory. + * @brief Reads 32-bit data buffer from the SDRAM memory. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer + * @param pDstBuffer Pointer to destination buffer * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { + uint32_t size; __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsdram); - + uint32_t *pdestbuff = pDstBuffer; + HAL_SDRAM_StateTypeDef state = hsdram->State; + /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { - return HAL_ERROR; - } - - /* Read data from source */ - for(; BufferSize != 0U; BufferSize--) + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Read data from source */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *(__IO uint32_t *)pSdramAddress; + pdestbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = state; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else { - *pDstBuffer = *(__IO uint32_t *)pSdramAddress; - pDstBuffer++; - pSdramAddress++; + return HAL_ERROR; } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Writes 32-bit data buffer to SDRAM memory. + * @brief Writes 32-bit data buffer to SDRAM memory. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write + * @param pSrcBuffer Pointer to source buffer to write * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { - __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; - uint32_t tmp = 0U; - - /* Process Locked */ - __HAL_LOCK(hsdram); - + uint32_t size; + __IO uint32_t *pSdramAddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; + /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + else if (hsdram->State == HAL_SDRAM_STATE_READY) { - return HAL_ERROR; + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *pSdramAddress = *psrcbuff; + psrcbuff++; + pSdramAddress++; + } + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); } - - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + else { - *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; - pSrcBuffer++; - pSdramAddress++; + return HAL_ERROR; } - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; + + return HAL_OK; } /** - * @brief Reads a Words data from the SDRAM memory using DMA transfer. + * @brief Reads a Words data from the SDRAM memory using DMA transfer. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer + * @param pDstBuffer Pointer to destination buffer * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { - uint32_t tmp = 0U; - - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) + HAL_StatusTypeDef status; + HAL_SDRAM_StateTypeDef state = hsdram->State; + + /* Check the SDRAM controller state */ + if (state == HAL_SDRAM_STATE_BUSY) { - return HAL_BUSY; + status = HAL_BUSY; + } + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + if (state == HAL_SDRAM_STATE_READY) + { + hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; + } + else + { + hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt; + } + hsdram->hdma->XferErrorCallback = SDRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); } - else if(tmp == HAL_SDRAM_STATE_PRECHARGED) + else { - return HAL_ERROR; - } - - /* Configure DMA user callbacks */ - hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; + status = HAL_ERROR; + } + + return status; } /** @@ -644,40 +742,44 @@ HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAdd * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write + * @param pSrcBuffer Pointer to source buffer to write * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { - uint32_t tmp = 0U; - - /* Process Locked */ - __HAL_LOCK(hsdram); - - /* Check the SDRAM controller state */ - tmp = hsdram->State; - - if(tmp == HAL_SDRAM_STATE_BUSY) + HAL_StatusTypeDef status; + + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { - return HAL_BUSY; + status = HAL_BUSY; } - else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) + else if (hsdram->State == HAL_SDRAM_STATE_READY) { - return HAL_ERROR; - } - - /* Configure DMA user callbacks */ - hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); - - /* Process Unlocked */ - __HAL_UNLOCK(hsdram); - - return HAL_OK; + /* Process Locked */ + __HAL_LOCK(hsdram); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; + hsdram->hdma->XferErrorCallback = SDRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + + /* Process Unlocked */ + __HAL_UNLOCK(hsdram); + } + else + { + status = HAL_ERROR; + } + + return status; } #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) @@ -693,53 +795,54 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - - if(pCallback == NULL) + + if (pCallback == NULL) { return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hsdram); - + state = hsdram->State; - if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = pCallback; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = pCallback; - break; - case HAL_SDRAM_REFRESH_ERR_CB_ID : - hsdram->RefreshErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hsdram->State == HAL_SDRAM_STATE_RESET) + else if (hsdram->State == HAL_SDRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = pCallback; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = pCallback; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -766,54 +869,54 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_S * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID * @retval status */ -HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - + /* Process locked */ __HAL_LOCK(hsdram); - + state = hsdram->State; - if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = HAL_SDRAM_MspInit; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; - break; - case HAL_SDRAM_REFRESH_ERR_CB_ID : - hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; - break; - case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : - hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; - break; - case HAL_SDRAM_DMA_XFER_ERR_CB_ID : - hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + case HAL_SDRAM_REFRESH_ERR_CB_ID : + hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; + break; + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(hsdram->State == HAL_SDRAM_STATE_RESET) + else if (hsdram->State == HAL_SDRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SDRAM_MSP_INIT_CB_ID : - hsdram->MspInitCallback = HAL_SDRAM_MspInit; - break; - case HAL_SDRAM_MSP_DEINIT_CB_ID : - hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_MSP_INIT_CB_ID : + hsdram->MspInitCallback = HAL_SDRAM_MspInit; + break; + case HAL_SDRAM_MSP_DEINIT_CB_ID : + hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -838,34 +941,35 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback (SDRAM_HandleTypeDef *hsdram, HAL * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SDRAM_StateTypeDef state; - - if(pCallback == NULL) + + if (pCallback == NULL) { return HAL_ERROR; } /* Process locked */ __HAL_LOCK(hsdram); - + state = hsdram->State; - if((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) + if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) { switch (CallbackId) { - case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : - hsdram->DmaXferCpltCallback = pCallback; - break; - case HAL_SDRAM_DMA_XFER_ERR_CB_ID : - hsdram->DmaXferErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : + hsdram->DmaXferCpltCallback = pCallback; + break; + case HAL_SDRAM_DMA_XFER_ERR_CB_ID : + hsdram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -878,19 +982,19 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL __HAL_UNLOCK(hsdram); return status; } -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} */ - -/** @defgroup SDRAM_Exported_Functions_Group3 Control functions - * @brief management functions - * -@verbatim + +/** @defgroup SDRAM_Exported_Functions_Group3 Control functions + * @brief management functions + * +@verbatim ============================================================================== ##### SDRAM Control functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to control dynamically the SDRAM interface. @@ -906,23 +1010,29 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) -{ - /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) +{ + /* Check the SDRAM controller state */ + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Enable write protection */ - FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; - - return HAL_OK; + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Enable write protection */ + (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; } /** @@ -933,21 +1043,29 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) */ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) { + HAL_SDRAM_StateTypeDef state = hsdram->State; + /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Disable write protection */ - FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; - + else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Disable write protection */ + (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + return HAL_OK; } @@ -958,85 +1076,106 @@ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) * @param Command SDRAM command structure * @param Timeout Timeout duration * @retval HAL status - */ -HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) + */ +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout) { + HAL_SDRAM_StateTypeDef state = hsdram->State; + /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (state == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; } - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Send SDRAM command */ - FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); - - /* Update the SDRAM controller state */ - if(Command->CommandMode == FMC_SDRAM_CMD_PALL) + else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) { - hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Send SDRAM command */ + (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); + + /* Update the SDRAM controller state state */ + if (Command->CommandMode == FMC_SDRAM_CMD_PALL) + { + hsdram->State = HAL_SDRAM_STATE_PRECHARGED; + } + else + { + hsdram->State = HAL_SDRAM_STATE_READY; + } } else { - hsdram->State = HAL_SDRAM_STATE_READY; + return HAL_ERROR; } - - return HAL_OK; + + return HAL_OK; } /** * @brief Programs the SDRAM Memory Refresh rate. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param RefreshRate The SDRAM refresh rate value + * the configuration information for SDRAM module. + * @param RefreshRate The SDRAM refresh rate value * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) { /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; - } - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Program the refresh rate */ - FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; - - return HAL_OK; + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Program the refresh rate */ + (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + + return HAL_OK; } /** * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains - * the configuration information for SDRAM module. - * @param AutoRefreshNumber The SDRAM auto Refresh number + * the configuration information for SDRAM module. + * @param AutoRefreshNumber The SDRAM auto Refresh number * @retval HAL status */ HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) { /* Check the SDRAM controller state */ - if(hsdram->State == HAL_SDRAM_STATE_BUSY) + if (hsdram->State == HAL_SDRAM_STATE_BUSY) { return HAL_BUSY; - } - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_BUSY; - - /* Set the Auto-Refresh number */ - FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); - - /* Update the SDRAM state */ - hsdram->State = HAL_SDRAM_STATE_READY; - + } + else if (hsdram->State == HAL_SDRAM_STATE_READY) + { + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_BUSY; + + /* Set the Auto-Refresh number */ + (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber); + + /* Update the SDRAM state */ + hsdram->State = HAL_SDRAM_STATE_READY; + } + else + { + return HAL_ERROR; + } + return HAL_OK; } @@ -1044,27 +1183,27 @@ HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, ui * @brief Returns the SDRAM memory current mode. * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains * the configuration information for SDRAM module. - * @retval The SDRAM memory mode. + * @retval The SDRAM memory mode. */ uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) { /* Return the SDRAM memory current mode */ - return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); + return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); } /** * @} */ - -/** @defgroup SDRAM_Exported_Functions_Group4 State functions - * @brief Peripheral State functions - * -@verbatim + +/** @defgroup SDRAM_Exported_Functions_Group4 State functions + * @brief Peripheral State functions + * +@verbatim ============================================================================== ##### SDRAM State functions ##### - ============================================================================== + ============================================================================== [..] - This subsection permits to get in run-time the status of the SDRAM controller + This subsection permits to get in run-time the status of the SDRAM controller and the data flow. @endverbatim @@ -1084,19 +1223,86 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) /** * @} - */ + */ /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ -#endif /* HAL_SDRAM_MODULE_ENABLED */ + +/** + * @brief DMA SDRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_READY; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferCpltCallback(hdma); +#else + HAL_SDRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferCpltCallback(hdma); +#else + HAL_SDRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SDRAM error callback. + * @param hdma : DMA handle + * @retval None + */ +static void SDRAM_DMAError(DMA_HandleTypeDef *hdma) +{ + SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SDRAM controller state */ + hsdram->State = HAL_SDRAM_STATE_ERROR; + +#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) + hsdram->DmaXferErrorCallback(hdma); +#else + HAL_SDRAM_DMA_XferErrorCallback(hdma); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ +} + /** * @} */ +#endif /* HAL_SDRAM_MODULE_ENABLED */ + /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* FMC_Bank5_6 */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sdram.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sdram.h index 3dd78027af2..3d450a0387a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sdram.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sdram.h @@ -6,27 +6,25 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_SDRAM_H -#define __STM32F4xx_HAL_SDRAM_H +#ifndef STM32F4xx_HAL_SDRAM_H +#define STM32F4xx_HAL_SDRAM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(FMC_Bank5_6) /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_ll_fmc.h" @@ -37,16 +35,17 @@ /** @addtogroup SDRAM * @{ - */ + */ + +/* Exported typedef ----------------------------------------------------------*/ -/* Exported typedef ----------------------------------------------------------*/ /** @defgroup SDRAM_Exported_Types SDRAM Exported Types * @{ */ -/** - * @brief HAL SDRAM State structure definition - */ +/** + * @brief HAL SDRAM State structure definition + */ typedef enum { HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */ @@ -68,22 +67,22 @@ typedef struct #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ { FMC_SDRAM_TypeDef *Instance; /*!< Register base address */ - + FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */ - + __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */ - - HAL_LockTypeDef Lock; /*!< SDRAM locking object */ + + HAL_LockTypeDef Lock; /*!< SDRAM locking object */ DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp Init callback */ - void (* MspDeInitCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Msp DeInit callback */ - void (* RefreshErrorCallback) ( struct __SDRAM_HandleTypeDef * hsdram); /*!< SDRAM Refresh Error callback */ - void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SDRAM DMA Xfer Error callback */ -#endif + void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */ + void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */ + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ } SDRAM_HandleTypeDef; #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) @@ -97,20 +96,21 @@ typedef enum HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */ HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */ HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */ -}HAL_SDRAM_CallbackIDTypeDef; +} HAL_SDRAM_CallbackIDTypeDef; /** * @brief HAL SDRAM Callback pointer definition */ typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram); typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} */ /* Exported constants --------------------------------------------------------*/ /* Exported macro ------------------------------------------------------------*/ + /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros * @{ */ @@ -127,17 +127,18 @@ typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); } while(0) #else #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) -#endif +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} */ /* Exported functions --------------------------------------------------------*/ + /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions * @{ */ -/** @addtogroup SDRAM_Exported_Functions_Group1 +/** @addtogroup SDRAM_Exported_Functions_Group1 * @{ */ @@ -151,50 +152,63 @@ void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram); void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram); void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + /** * @} */ -/** @addtogroup SDRAM_Exported_Functions_Group2 +/** @addtogroup SDRAM_Exported_Functions_Group2 * @{ */ /* I/O operation functions ****************************************************/ -HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); - -HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); + +HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) /* SDRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback); -#endif +HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, + pSDRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ /** * @} */ - -/** @addtogroup SDRAM_Exported_Functions_Group3 + +/** @addtogroup SDRAM_Exported_Functions_Group3 * @{ */ /* SDRAM Control functions *****************************************************/ HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); -HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, + uint32_t Timeout); HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); + /** * @} */ -/** @addtogroup SDRAM_Exported_Functions_Group4 +/** @addtogroup SDRAM_Exported_Functions_Group4 * @{ */ /* SDRAM State functions ********************************************************/ @@ -211,16 +225,14 @@ HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ - /** * @} */ +#endif /* FMC_Bank5_6 */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_SDRAM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_SDRAM_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smartcard.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smartcard.c index 71a6c154c85..9d165cde3d8 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smartcard.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smartcard.c @@ -10,6 +10,17 @@ * + Peripheral Control functions * + Peripheral State and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -105,8 +116,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_SMARTCARD_RegisterCallback() to register a user callback. - Function @ref HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: + Use Function HAL_SMARTCARD_RegisterCallback() to register a user callback. + Function HAL_SMARTCARD_RegisterCallback() allows to register following callbacks: (+) TxCpltCallback : Tx Complete Callback. (+) RxCpltCallback : Rx Complete Callback. (+) ErrorCallback : Error Callback. @@ -119,9 +130,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default + Use function HAL_SMARTCARD_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_SMARTCARD_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxCpltCallback : Tx Complete Callback. @@ -134,13 +145,13 @@ (+) MspDeInitCallback : SMARTCARD MspDeInit. [..] - By default, after the @ref HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET + By default, after the HAL_SMARTCARD_Init() and when the state is HAL_SMARTCARD_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_SMARTCARD_TxCpltCallback(), @ref HAL_SMARTCARD_RxCpltCallback(). + examples HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SMARTCARD_Init() - and @ref HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SMARTCARD_Init() and @ref HAL_SMARTCARD_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_SMARTCARD_Init() + and HAL_SMARTCARD_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SMARTCARD_Init() and HAL_SMARTCARD_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -149,8 +160,8 @@ in HAL_SMARTCARD_STATE_READY or HAL_SMARTCARD_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SMARTCARD_RegisterCallback() before calling @ref HAL_SMARTCARD_DeInit() - or @ref HAL_SMARTCARD_Init() function. + using HAL_SMARTCARD_RegisterCallback() before calling HAL_SMARTCARD_DeInit() + or HAL_SMARTCARD_Init() function. [..] When The compilation define USE_HAL_SMARTCARD_REGISTER_CALLBACKS is set to 0 or @@ -159,17 +170,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -756,9 +756,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *tmp = pData; + const uint8_t *tmp = pData; uint32_t tickstart = 0U; if(hsc->gState == HAL_SMARTCARD_STATE_READY) @@ -876,7 +876,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if(hsc->gState == HAL_SMARTCARD_STATE_READY) @@ -969,9 +969,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t * @param Size Amount of data to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size) { - uint32_t *tmp; + const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if(hsc->gState == HAL_SMARTCARD_STATE_READY) @@ -1001,8 +1001,8 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 hsc->hdmatx->XferAbortCallback = NULL; /* Enable the SMARTCARD transmit DMA stream */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size); + tmp = (const uint32_t*)&pData; + HAL_DMA_Start_IT(hsc->hdmatx, *(const uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC); @@ -1780,7 +1780,7 @@ __weak void HAL_SMARTCARD_AbortReceiveCpltCallback (SMARTCARD_HandleTypeDef *hsc * the configuration information for SMARTCARD module. * @retval HAL state */ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc) { uint32_t temp1= 0x00U, temp2 = 0x00U; temp1 = hsc->gState; @@ -1795,7 +1795,7 @@ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc) * the configuration information for the specified SMARTCARD. * @retval SMARTCARD Error Code */ -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc) +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc) { return hsc->ErrorCode; } @@ -1921,11 +1921,12 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles SMARTCARD Communication Timeout. + * @brief This function handles SMARTCARD Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param hsc Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for SMARTCARD module. * @param Flag Specifies the SMARTCARD flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Timeout Timeout duration * @param Tickstart Tick start value * @retval HAL status @@ -2360,4 +2361,4 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smartcard.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smartcard.h index c3d1544455b..7aa4ce34b8d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smartcard.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smartcard.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -99,7 +98,7 @@ typedef struct * 01 : (Not Used) * 10 : Timeout * 11 : Error - * b5 IP initilisation status + * b5 IP initialization status * 0 : Reset (IP not initialized) * 1 : Init done (IP initialized. HAL SMARTCARD Init function already called) * b4-b3 (not used) @@ -116,7 +115,7 @@ typedef struct * RxState value coding follow below described bitmap : * b7-b6 (not used) * xx : Should be set to 00 - * b5 IP initilisation status + * b5 IP initialization status * 0 : Reset (IP not initialized) * 1 : Init done (IP initialized) * b4-b2 (not used) @@ -157,7 +156,7 @@ typedef struct __SMARTCARD_HandleTypeDef SMARTCARD_InitTypeDef Init; /*!< SmartCard communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SmartCard Tx transfer Buffer */ uint16_t TxXferSize; /*!< SmartCard Tx Transfer size */ @@ -643,11 +642,11 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsc, * @{ */ /* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); /* Transfer Abort functions */ HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsc); @@ -672,8 +671,8 @@ void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsc); * @{ */ /* Peripheral State functions **************************************************/ -HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc); -uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); +HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(const SMARTCARD_HandleTypeDef *hsc); +uint32_t HAL_SMARTCARD_GetError(const SMARTCARD_HandleTypeDef *hsc); /** * @} */ @@ -754,4 +753,3 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); #endif /* __STM32F4xx_HAL_SMARTCARD_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smbus.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smbus.c index cc6258ca815..84d5d89c617 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smbus.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smbus.c @@ -10,6 +10,17 @@ * + IO operation functions * + Peripheral State, Mode and Error functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -20,7 +31,7 @@ (#) Declare a SMBUS_HandleTypeDef handle structure, for example: SMBUS_HandleTypeDef hsmbus; - (#)Initialize the SMBUS low level resources by implementing the @ref HAL_SMBUS_MspInit() API: + (#)Initialize the SMBUS low level resources by implementing the HAL_SMBUS_MspInit() API: (##) Enable the SMBUSx interface clock (##) SMBUS pins configuration (+++) Enable the clock for the SMBUS GPIOs @@ -32,10 +43,10 @@ (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, Dual Addressing mode, Own Address2, General call and Nostretch mode in the hsmbus Init structure. - (#) Initialize the SMBUS registers by calling the @ref HAL_SMBUS_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_SMBUS_MspInit(&hsmbus) API. + (#) Initialize the SMBUS registers by calling the HAL_SMBUS_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_SMBUS_MspInit(&hsmbus) API. - (#) To check if target device is ready for communication, use the function @ref HAL_SMBUS_IsDeviceReady() + (#) To check if target device is ready for communication, use the function HAL_SMBUS_IsDeviceReady() (#) For SMBUS IO operations, only one mode of operations is available within this driver : @@ -44,35 +55,35 @@ =================================== [..] - (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Master_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_MasterTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterTxCpltCallback() - (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Master_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_MasterRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_MasterRxCpltCallback() - (+) Abort a master/Host SMBUS process communication with Interrupt using @ref HAL_SMBUS_Master_Abort_IT() - (++) End of abort process, @ref HAL_SMBUS_AbortCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_AbortCpltCallback() + (+) Transmit in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_MasterTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_MasterTxCpltCallback() + (+) Receive in master/host SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Master_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_MasterRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_MasterRxCpltCallback() + (+) Abort a master/Host SMBUS process communication with Interrupt using HAL_SMBUS_Master_Abort_IT() + (++) End of abort process, HAL_SMBUS_AbortCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_AbortCpltCallback() (+) Enable/disable the Address listen mode in slave/device or host/slave SMBUS mode - using @ref HAL_SMBUS_EnableListen_IT() @ref HAL_SMBUS_DisableListen_IT() - (++) When address slave/device SMBUS match, @ref HAL_SMBUS_AddrCallback() is executed and user can + using HAL_SMBUS_EnableListen_IT() HAL_SMBUS_DisableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback() is executed and user can add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end @ref HAL_SMBUS_ListenCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ListenCpltCallback() - (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Slave_Transmit_IT() - (++) At transmission end of transfer @ref HAL_SMBUS_SlaveTxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveTxCpltCallback() - (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using @ref HAL_SMBUS_Slave_Receive_IT() - (++) At reception end of transfer @ref HAL_SMBUS_SlaveRxCpltCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_SlaveRxCpltCallback() - (+) Enable/Disable the SMBUS alert mode using @ref HAL_SMBUS_EnableAlert_IT() and @ref HAL_SMBUS_DisableAlert_IT() - (++) When SMBUS Alert is generated @ref HAL_SMBUS_ErrorCallback() is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() - to check the Alert Error Code using function @ref HAL_SMBUS_GetError() - (+) Get HAL state machine or error values using @ref HAL_SMBUS_GetState() or HAL_SMBUS_GetError() - (+) In case of transfer Error, @ref HAL_SMBUS_ErrorCallback() function is executed and user can - add his own code by customization of function pointer @ref HAL_SMBUS_ErrorCallback() - to check the Error Code using function @ref HAL_SMBUS_GetError() + (++) At Listen mode end HAL_SMBUS_ListenCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback() + (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT() + (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback() + (+) Receive in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Receive_IT() + (++) At reception end of transfer HAL_SMBUS_SlaveRxCpltCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_SlaveRxCpltCallback() + (+) Enable/Disable the SMBUS alert mode using HAL_SMBUS_EnableAlert_IT() and HAL_SMBUS_DisableAlert_IT() + (++) When SMBUS Alert is generated HAL_SMBUS_ErrorCallback() is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Alert Error Code using function HAL_SMBUS_GetError() + (+) Get HAL state machine or error values using HAL_SMBUS_GetState() or HAL_SMBUS_GetError() + (+) In case of transfer Error, HAL_SMBUS_ErrorCallback() function is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ErrorCallback() + to check the Error Code using function HAL_SMBUS_GetError() *** SMBUS HAL driver macros list *** @@ -80,12 +91,12 @@ [..] Below the list of most used macros in SMBUS HAL driver. - (+) @ref __HAL_SMBUS_ENABLE : Enable the SMBUS peripheral - (+) @ref __HAL_SMBUS_DISABLE : Disable the SMBUS peripheral - (+) @ref __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not - (+) @ref __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag - (+) @ref __HAL_SMBUS_ENABLE_IT : Enable the specified SMBUS interrupt - (+) @ref __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt + (+) __HAL_SMBUS_ENABLE : Enable the SMBUS peripheral + (+) __HAL_SMBUS_DISABLE : Disable the SMBUS peripheral + (+) __HAL_SMBUS_GET_FLAG : Checks whether the specified SMBUS flag is set or not + (+) __HAL_SMBUS_CLEAR_FLAG: Clear the specified SMBUS pending flag + (+) __HAL_SMBUS_ENABLE_IT : Enable the specified SMBUS interrupt + (+) __HAL_SMBUS_DISABLE_IT: Disable the specified SMBUS interrupt [..] (@) You can refer to the SMBUS HAL driver header file for more useful macros @@ -95,10 +106,10 @@ [..] The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterXXXCallback() + Use Functions HAL_SMBUS_RegisterCallback() or HAL_SMBUS_RegisterXXXCallback() to register an interrupt callback. - Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: + Function HAL_SMBUS_RegisterCallback() allows to register following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. @@ -111,11 +122,11 @@ This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback(). + For specific callback AddrCallback use dedicated register callbacks : HAL_SMBUS_RegisterAddrCallback(). [..] - Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default + Use function HAL_SMBUS_UnRegisterCallback to reset a callback to the default weak function. - @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) MasterTxCpltCallback : callback for Master transmission end of transfer. @@ -128,42 +139,30 @@ (+) MspInitCallback : callback for Msp Init. (+) MspDeInitCallback : callback for Msp DeInit. [..] - For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback(). + For callback AddrCallback use dedicated register callbacks : HAL_SMBUS_UnRegisterAddrCallback(). [..] - By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_SMBUS_STATE_RESET + By default, after the HAL_SMBUS_Init() and when the state is HAL_SMBUS_STATE_RESET all callbacks are set to the corresponding weak functions: - examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). + examples HAL_SMBUS_MasterTxCpltCallback(), HAL_SMBUS_MasterRxCpltCallback(). Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() only when + reset to the legacy weak functions in the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() only when these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() + If MspInit or MspDeInit are not null, the HAL_SMBUS_Init()/ HAL_SMBUS_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. [..] - Callbacks can be registered/unregistered in @ref HAL_SMBUS_STATE_READY state only. + Callbacks can be registered/unregistered in HAL_SMBUS_STATE_READY state only. Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_SMBUS_STATE_READY or @ref HAL_SMBUS_STATE_RESET state, + in HAL_SMBUS_STATE_READY or HAL_SMBUS_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() - or @ref HAL_SMBUS_Init() function. + using HAL_SMBUS_RegisterCallback() before calling HAL_SMBUS_DeInit() + or HAL_SMBUS_Init() function. [..] When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or not defined, the callback registration feature is not available and all callbacks are set to the corresponding weak functions. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -214,6 +213,7 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbus, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); static void SMBUS_ITError(SMBUS_HandleTypeDef *hsmbus); +static void SMBUS_Flush_DR(SMBUS_HandleTypeDef *hsmbus); /* Private functions for SMBUS transfer IRQ handler */ static HAL_StatusTypeDef SMBUS_MasterTransmit_TXE(SMBUS_HandleTypeDef *hsmbus); @@ -359,7 +359,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) /*---------------------------- SMBUSx CR1 Configuration ----------------------*/ /* Configure SMBUSx: Generalcall , PEC , Peripheral mode and NoStretch mode */ - MODIFY_REG(hsmbus->Instance->CR1, (I2C_CR1_NOSTRETCH | I2C_CR1_ENGC | I2C_CR1_PEC | I2C_CR1_ENARP | I2C_CR1_SMBTYPE | I2C_CR1_SMBUS), (hsmbus->Init.NoStretchMode | hsmbus->Init.GeneralCallMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode)); + MODIFY_REG(hsmbus->Instance->CR1, (I2C_CR1_NOSTRETCH | I2C_CR1_ENGC | I2C_CR1_ENPEC | I2C_CR1_ENARP | I2C_CR1_SMBTYPE | I2C_CR1_SMBUS), (hsmbus->Init.NoStretchMode | hsmbus->Init.GeneralCallMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode)); /*---------------------------- SMBUSx OAR1 Configuration ---------------------*/ /* Configure SMBUSx: Own Address1 and addressing mode */ @@ -846,6 +846,18 @@ HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus) #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ +/** + * @brief SMBUS data register flush process. + * @param hsmbus SMBUS handle. + * @retval None + */ +static void SMBUS_Flush_DR(SMBUS_HandleTypeDef *hsmbus) +{ + /* Write a dummy data in DR to clear it */ + hsmbus->Instance->DR = 0x00U; + +} + /** * @} */ @@ -1681,6 +1693,13 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) /* Clear AF flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); + + /* Disable EVT, BUF and ERR interrupt */ + __HAL_SMBUS_DISABLE_IT(hsmbus, SMBUS_IT_EVT | SMBUS_IT_BUF | SMBUS_IT_ERR); + + /* Flush data register */ + SMBUS_Flush_DR(hsmbus); + } } @@ -1706,7 +1725,7 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/ if (((sr1itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERR) != RESET)) { - hsmbus->ErrorCode |= SMBUS_FLAG_PECERR; + hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR; /* Clear PEC error flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR); @@ -2037,7 +2056,7 @@ static HAL_StatusTypeDef SMBUS_MasterTransmit_BTF(SMBUS_HandleTypeDef *hsmbus) /* Generate Stop */ SET_BIT(hsmbus->Instance->CR1, I2C_CR1_STOP); - hsmbus->PreviousState = HAL_SMBUS_STATE_READY; + hsmbus->PreviousState = SMBUS_STATE_NONE; hsmbus->State = HAL_SMBUS_STATE_READY; hsmbus->Mode = HAL_SMBUS_MODE_NONE; #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) @@ -2783,4 +2802,3 @@ static HAL_StatusTypeDef SMBUS_WaitOnFlagUntilTimeout(SMBUS_HandleTypeDef *hsmbu * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smbus.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smbus.h index 056a600d175..ea92afa30c4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smbus.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_smbus.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -730,4 +729,3 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); #endif /* __STM32F4xx_HAL_SMBUS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spdifrx.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spdifrx.c index 50fac5e027a..da7c302189d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spdifrx.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spdifrx.c @@ -8,6 +8,18 @@ * + Data transfers functions * + DMA transfers management * + Interrupts and flags management + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim =============================================================================== ##### How to use this driver ##### @@ -142,18 +154,6 @@ are set to the corresponding weak functions. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -188,7 +188,8 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma); static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma); static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif); static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif); -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart); +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, + FlagStatus Status, uint32_t Timeout, uint32_t tickstart); /** * @} */ @@ -238,7 +239,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) uint32_t tmpreg; /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) + if (hspdif == NULL) { return HAL_ERROR; } @@ -256,7 +257,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) assert_param(IS_PARITY_ERROR_MASK(hspdif->Init.ParityErrorMask)); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - if(hspdif->State == HAL_SPDIFRX_STATE_RESET) + if (hspdif->State == HAL_SPDIFRX_STATE_RESET) { /* Allocate lock resource and initialize it */ hspdif->Lock = HAL_UNLOCKED; @@ -267,7 +268,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) hspdif->CxCpltCallback = HAL_SPDIFRX_CxCpltCallback; /* Legacy weak CxCpltCallback */ hspdif->ErrorCallback = HAL_SPDIFRX_ErrorCallback; /* Legacy weak ErrorCallback */ - if(hspdif->MspInitCallback == NULL) + if (hspdif->MspInitCallback == NULL) { hspdif->MspInitCallback = HAL_SPDIFRX_MspInit; /* Legacy weak MspInit */ } @@ -276,7 +277,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) hspdif->MspInitCallback(hspdif); } #else - if(hspdif->State == HAL_SPDIFRX_STATE_RESET) + if (hspdif->State == HAL_SPDIFRX_STATE_RESET) { /* Allocate lock resource and initialize it */ hspdif->Lock = HAL_UNLOCKED; @@ -310,7 +311,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) hspdif->Init.ChannelStatusMask | hspdif->Init.ValidityBitMask | hspdif->Init.ParityErrorMask - ); + ); hspdif->Instance->CR = tmpreg; @@ -331,7 +332,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) { /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) + if (hspdif == NULL) { return HAL_ERROR; } @@ -345,7 +346,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) __HAL_SPDIFRX_IDLE(hspdif); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - if(hspdif->MspDeInitCallback == NULL) + if (hspdif->MspDeInitCallback == NULL) { hspdif->MspDeInitCallback = HAL_SPDIFRX_MspDeInit; /* Legacy weak MspDeInit */ } @@ -415,11 +416,12 @@ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, + pSPDIFRX_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; - if(pCallback == NULL) + if (pCallback == NULL) { /* Update the error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; @@ -428,7 +430,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA /* Process locked */ __HAL_LOCK(hspdif); - if(HAL_SPDIFRX_STATE_READY == hspdif->State) + if (HAL_SPDIFRX_STATE_READY == hspdif->State) { switch (CallbackID) { @@ -468,7 +470,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA break; } } - else if(HAL_SPDIFRX_STATE_RESET == hspdif->State) + else if (HAL_SPDIFRX_STATE_RESET == hspdif->State) { switch (CallbackID) { @@ -483,7 +485,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA default : /* Update the error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ + /* Return error status */ status = HAL_ERROR; break; } @@ -503,7 +505,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA /** * @brief Unregister a SPDIFRX Callback - * SPDIFRX callabck is redirected to the weak predefined callback + * SPDIFRX callback is redirected to the weak predefined callback * @param hspdif SPDIFRX handle * @param CallbackID ID of the callback to be unregistered * This parameter can be one of the following values: @@ -516,14 +518,15 @@ HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HA * @arg @ref HAL_SPDIFRX_MSPDEINIT_CB_ID MspDeInit callback ID * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID) +HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, + HAL_SPDIFRX_CallbackIDTypeDef CallbackID) { -HAL_StatusTypeDef status = HAL_OK; + HAL_StatusTypeDef status = HAL_OK; /* Process locked */ __HAL_LOCK(hspdif); - if(HAL_SPDIFRX_STATE_READY == hspdif->State) + if (HAL_SPDIFRX_STATE_READY == hspdif->State) { switch (CallbackID) { @@ -550,12 +553,12 @@ HAL_StatusTypeDef status = HAL_OK; default : /* Update the error code */ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_INVALID_CALLBACK; - /* Return error status */ + /* Return error status */ status = HAL_ERROR; break; } } - else if(HAL_SPDIFRX_STATE_RESET == hspdif->State) + else if (HAL_SPDIFRX_STATE_RESET == hspdif->State) { switch (CallbackID) { @@ -601,7 +604,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF uint32_t tmpreg; /* Check the SPDIFRX handle allocation */ - if(hspdif == NULL) + if (hspdif == NULL) { return HAL_ERROR; } @@ -617,9 +620,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF /* Reset the old SPDIFRX CR configuration */ tmpreg = hspdif->Instance->CR; - if(((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && - (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || - ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) + if (((tmpreg & SPDIFRX_STATE_RCV) == SPDIFRX_STATE_RCV) && + (((tmpreg & SPDIFRX_CR_DRFMT) != sDataFormat.DataFormat) || + ((tmpreg & SPDIFRX_CR_RXSTEO) != sDataFormat.StereoMode))) { return HAL_ERROR; } @@ -683,8 +686,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF (++) HAL_SPDIFRX_CxCpltCallback() @endverbatim -* @{ -*/ + * @{ + */ /** * @brief Receives an amount of data (Data Flow) in blocking mode. @@ -695,18 +698,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIF * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint16_t sizeCounter = Size; uint32_t *pTmpBuf = pData; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(hspdif->State == HAL_SPDIFRX_STATE_READY) + if (hspdif->State == HAL_SPDIFRX_STATE_READY) { /* Process Locked */ __HAL_LOCK(hspdif); @@ -720,7 +724,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin tickstart = HAL_GetTick(); /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -729,13 +733,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin __HAL_SPDIFRX_RCV(hspdif); /* Receive data flow */ - while(sizeCounter > 0U) + while (sizeCounter > 0U) { /* Get tick */ tickstart = HAL_GetTick(); /* Wait until RXNE flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -768,18 +772,19 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uin * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout) { uint32_t tickstart; uint16_t sizeCounter = Size; uint32_t *pTmpBuf = pData; - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if(hspdif->State == HAL_SPDIFRX_STATE_READY) + if (hspdif->State == HAL_SPDIFRX_STATE_READY) { /* Process Locked */ __HAL_LOCK(hspdif); @@ -793,7 +798,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, tickstart = HAL_GetTick(); /* Wait until SYNCD flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -802,13 +807,13 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, __HAL_SPDIFRX_RCV(hspdif); /* Receive control flow */ - while(sizeCounter > 0U) + while (sizeCounter > 0U) { /* Get tick */ tickstart = HAL_GetTick(); /* Wait until CSRNE flag is set */ - if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) + if (SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_CSRNE, RESET, Timeout, tickstart) != HAL_OK) { return HAL_TIMEOUT; } @@ -845,9 +850,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) { - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -873,7 +878,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, /* Enable the SPDIFRX RXNE interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_RXNE); - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -892,7 +897,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -930,9 +935,9 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) { - if((pData == NULL ) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } @@ -958,7 +963,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi /* Enable the SPDIFRX CSRNE interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE); - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -977,7 +982,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdi __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1015,12 +1020,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_CX)) { /* Process Locked */ __HAL_LOCK(hspdif); @@ -1042,7 +1047,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, hspdif->hdmaDrRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ - if(HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hspdif->hdmaDrRx, (uint32_t)&hspdif->Instance->DR, (uint32_t)hspdif->pRxBuffPtr, Size) != HAL_OK) { /* Set SPDIFRX error */ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; @@ -1059,7 +1064,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, /* Enable RXDMAEN bit in SPDIFRX CR register for data flow reception*/ hspdif->Instance->CR |= SPDIFRX_CR_RXDMAEN; - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -1078,7 +1083,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1116,12 +1121,12 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd const HAL_SPDIFRX_StateTypeDef tempState = hspdif->State; - if((pData == NULL) || (Size == 0U)) + if ((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } - if((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) + if ((tempState == HAL_SPDIFRX_STATE_READY) || (tempState == HAL_SPDIFRX_STATE_BUSY_RX)) { hspdif->pCsBuffPtr = pData; hspdif->CsXferSize = Size; @@ -1143,7 +1148,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ - if(HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK) + if (HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size) != HAL_OK) { /* Set SPDIFRX error */ hspdif->ErrorCode = HAL_SPDIFRX_ERROR_DMA; @@ -1160,7 +1165,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN; - if((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) + if ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_RCV) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); @@ -1179,7 +1184,7 @@ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspd __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1244,21 +1249,21 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) uint32_t itSource = hspdif->Instance->IMR; /* SPDIFRX in mode Data Flow Reception */ - if(((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE)) + if (((itFlag & SPDIFRX_FLAG_RXNE) == SPDIFRX_FLAG_RXNE) && ((itSource & SPDIFRX_IT_RXNE) == SPDIFRX_IT_RXNE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_RXNE); SPDIFRX_ReceiveDataFlow_IT(hspdif); } /* SPDIFRX in mode Control Flow Reception */ - if(((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE)) + if (((itFlag & SPDIFRX_FLAG_CSRNE) == SPDIFRX_FLAG_CSRNE) && ((itSource & SPDIFRX_IT_CSRNE) == SPDIFRX_IT_CSRNE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_CSRNE); SPDIFRX_ReceiveControlFlow_IT(hspdif); } /* SPDIFRX Overrun error interrupt occurred */ - if(((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE)) + if (((itFlag & SPDIFRX_FLAG_OVR) == SPDIFRX_FLAG_OVR) && ((itSource & SPDIFRX_IT_OVRIE) == SPDIFRX_IT_OVRIE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_OVRIE); @@ -1270,7 +1275,7 @@ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) } /* SPDIFRX Parity error interrupt occurred */ - if(((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE)) + if (((itFlag & SPDIFRX_FLAG_PERR) == SPDIFRX_FLAG_PERR) && ((itSource & SPDIFRX_IT_PERRIE) == SPDIFRX_IT_PERRIE)) { __HAL_SPDIFRX_CLEAR_IT(hspdif, SPDIFRX_IT_PERRIE); @@ -1381,7 +1386,7 @@ and the data flow. * @param hspdif SPDIFRX handle * @retval HAL state */ -HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif) +HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif) { return hspdif->State; } @@ -1391,7 +1396,7 @@ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * cons * @param hspdif SPDIFRX handle * @retval SPDIFRX Error Code */ -uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif) +uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif) { return hspdif->ErrorCode; } @@ -1407,10 +1412,10 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif) */ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Rx DMA Request */ - if(hdma->Init.Mode != DMA_CIRCULAR) + if (hdma->Init.Mode != DMA_CIRCULAR) { hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_RXDMAEN); hspdif->RxXferCount = 0; @@ -1430,7 +1435,7 @@ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) hspdif->RxHalfCpltCallback(hspdif); @@ -1447,7 +1452,7 @@ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Cb DMA Request */ hspdif->Instance->CR &= (uint16_t)(~SPDIFRX_CR_CBDMAEN); @@ -1468,7 +1473,7 @@ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = (SPDIFRX_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) hspdif->CxHalfCpltCallback(hspdif); @@ -1484,13 +1489,13 @@ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) */ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) { - SPDIFRX_HandleTypeDef* hspdif = ( SPDIFRX_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + SPDIFRX_HandleTypeDef *hspdif = (SPDIFRX_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Disable Rx and Cb DMA Request */ hspdif->Instance->CR &= (uint16_t)(~(SPDIFRX_CR_RXDMAEN | SPDIFRX_CR_CBDMAEN)); hspdif->RxXferCount = 0; - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Set the error code and execute error callback*/ hspdif->ErrorCode |= HAL_SPDIFRX_ERROR_DMA; @@ -1516,7 +1521,7 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) hspdif->pRxBuffPtr++; hspdif->RxXferCount--; - if(hspdif->RxXferCount == 0U) + if (hspdif->RxXferCount == 0U) { /* Disable RXNE/PE and OVR interrupts */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE | SPDIFRX_IT_PERRIE | SPDIFRX_IT_RXNE); @@ -1527,9 +1532,9 @@ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) __HAL_UNLOCK(hspdif); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->RxCpltCallback(hspdif); + hspdif->RxCpltCallback(hspdif); #else - HAL_SPDIFRX_RxCpltCallback(hspdif); + HAL_SPDIFRX_RxCpltCallback(hspdif); #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } } @@ -1546,7 +1551,7 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) hspdif->pCsBuffPtr++; hspdif->CsXferCount--; - if(hspdif->CsXferCount == 0U) + if (hspdif->CsXferCount == 0U) { /* Disable CSRNE interrupt */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); @@ -1557,9 +1562,9 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) __HAL_UNLOCK(hspdif); #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) - hspdif->CxCpltCallback(hspdif); + hspdif->CxCpltCallback(hspdif); #else - HAL_SPDIFRX_CxCpltCallback(hspdif); + HAL_SPDIFRX_CxCpltCallback(hspdif); #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } } @@ -1573,15 +1578,16 @@ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) * @param tickstart Tick start value * @retval HAL status */ -static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart) +static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, + uint32_t Timeout, uint32_t tickstart) { /* Wait until flag is set */ - while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status) + while (__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == Status) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if(((HAL_GetTick() - tickstart ) > Timeout) || (Timeout == 0U)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); @@ -1592,7 +1598,7 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); - hspdif->State= HAL_SPDIFRX_STATE_READY; + hspdif->State = HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); @@ -1619,5 +1625,3 @@ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *h /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spdifrx.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spdifrx.h index 73e30d22835..7ea04aa9004 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spdifrx.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spdifrx.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -22,7 +21,7 @@ #define STM32F4xx_HAL_SPDIFRX_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -124,7 +123,7 @@ typedef enum typedef struct __SPDIFRX_HandleTypeDef #else typedef struct -#endif +#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ { SPDIFRX_TypeDef *Instance; /* SPDIFRX registers base address */ @@ -168,8 +167,8 @@ typedef struct void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow half completed callback */ void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Control flow completed callback */ void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX error callback */ - void (* MspInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp Init callback */ - void (* MspDeInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp DeInit callback */ + void (* MspInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp Init callback */ + void (* MspDeInitCallback)(struct __SPDIFRX_HandleTypeDef *hspdif); /*!< SPDIFRX Msp DeInit callback */ #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ } SPDIFRX_HandleTypeDef; @@ -190,12 +189,12 @@ typedef enum HAL_SPDIFRX_ERROR_CB_ID = 0x04U, /*!< SPDIFRX error callback */ HAL_SPDIFRX_MSPINIT_CB_ID = 0x05U, /*!< SPDIFRX Msp Init callback ID */ HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U /*!< SPDIFRX Msp DeInit callback ID */ -}HAL_SPDIFRX_CallbackIDTypeDef; +} HAL_SPDIFRX_CallbackIDTypeDef; /** * @brief HAL SPDIFRX Callback pointer definition */ -typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< pointer to an SPDIFRX callback function */ +typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef *hspdif); /*!< pointer to an SPDIFRX callback function */ #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ /* Exported constants --------------------------------------------------------*/ @@ -268,8 +267,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< */ /** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask -* @{ -*/ + * @{ + */ #define SPDIFRX_VALIDITYMASK_OFF ((uint32_t)0x00000000U) #define SPDIFRX_VALIDITYMASK_ON ((uint32_t)SPDIFRX_CR_VMSK) /** @@ -369,10 +368,10 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< */ #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\ - (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\ - (__HANDLE__)->MspInitCallback = NULL;\ - (__HANDLE__)->MspDeInitCallback = NULL;\ - }while(0) + (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\ + (__HANDLE__)->MspInitCallback = NULL;\ + (__HANDLE__)->MspDeInitCallback = NULL;\ + }while(0) #else #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET) #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ @@ -411,7 +410,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< * @retval None */ #define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) -#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__))) +#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR\ + &= (uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. * @param __HANDLE__ specifies the SPDIFRX Handle. @@ -426,7 +426,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< * @arg SPDIFRX_IT_IFEIE * @retval The new state of __IT__ (TRUE or FALSE). */ -#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR\ + & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified SPDIFRX flag is set or not. * @param __HANDLE__ specifies the SPDIFRX Handle. @@ -443,7 +444,8 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< * @arg SPDIFRX_FLAG_TERR * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET) +#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR)\ + & (__FLAG__)) == (__FLAG__)) ? SET : RESET) /** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. * @param __HANDLE__ specifies the USART Handle. @@ -472,15 +474,17 @@ typedef void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< */ /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif); -HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif); +HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif); void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif); void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif); HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, + pSPDIFRX_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, + HAL_SPDIFRX_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */ /** * @} @@ -490,9 +494,11 @@ HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, * @{ */ /* I/O operation functions ***************************************************/ - /* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout); +/* Blocking mode: Polling */ +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout); +HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout); /* Non-Blocking mode: Interrupt */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size); @@ -518,8 +524,8 @@ void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif); -uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif); +HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const *const hspdif); +uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const *const hspdif); /** * @} */ @@ -535,39 +541,39 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif); * @{ */ #define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_INPUT_IN1) || \ - ((INPUT) == SPDIFRX_INPUT_IN2) || \ - ((INPUT) == SPDIFRX_INPUT_IN3) || \ - ((INPUT) == SPDIFRX_INPUT_IN0)) + ((INPUT) == SPDIFRX_INPUT_IN2) || \ + ((INPUT) == SPDIFRX_INPUT_IN3) || \ + ((INPUT) == SPDIFRX_INPUT_IN0)) #define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_MAXRETRIES_NONE) || \ - ((RET) == SPDIFRX_MAXRETRIES_3) || \ - ((RET) == SPDIFRX_MAXRETRIES_15) || \ - ((RET) == SPDIFRX_MAXRETRIES_63)) + ((RET) == SPDIFRX_MAXRETRIES_3) || \ + ((RET) == SPDIFRX_MAXRETRIES_15) || \ + ((RET) == SPDIFRX_MAXRETRIES_63)) #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \ - ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) + ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF)) #define IS_PREAMBLE_TYPE_MASK(VAL) (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \ - ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) + ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF)) #define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \ - ((VAL) == SPDIFRX_VALIDITYMASK_ON)) + ((VAL) == SPDIFRX_VALIDITYMASK_ON)) #define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \ - ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) + ((VAL) == SPDIFRX_PARITYERRORMASK_ON)) #define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_CHANNEL_A) || \ - ((CHANNEL) == SPDIFRX_CHANNEL_B)) + ((CHANNEL) == SPDIFRX_CHANNEL_B)) #define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \ - ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ - ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) + ((FORMAT) == SPDIFRX_DATAFORMAT_MSB) || \ + ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS)) #define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \ - ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) + ((MODE) == SPDIFRX_STEREOMODE_ENABLE)) #define IS_CHANNEL_STATUS_MASK(VAL) (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \ - ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) + ((VAL) == SPDIFRX_CHANNELSTATUS_OFF)) /** * @} @@ -595,6 +601,4 @@ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif); #endif -#endif /* __STM32F4xx_HAL_SPDIFRX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_SPDIFRX_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.c index 8afa6e7088b..416b1eca2e3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.c @@ -9,7 +9,17 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -184,18 +194,6 @@ (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -858,6 +856,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -887,6 +886,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -916,9 +916,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error: - hspi->State = HAL_SPI_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspi); return errorcode; @@ -941,6 +944,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 uint32_t tickstart; HAL_StatusTypeDef errorcode = HAL_OK; + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -954,12 +963,6 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -1025,6 +1028,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1048,6 +1052,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1114,9 +1119,12 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { errorcode = HAL_ERROR; } + else + { + hspi->State = HAL_SPI_STATE_READY; + } error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1134,13 +1142,13 @@ error : HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { -#if (USE_SPI_CRC != 0U) - __IO uint32_t tmpreg = 0U; -#endif /* USE_SPI_CRC */ uint16_t initial_TxXferCount; uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; uint32_t tickstart; +#if (USE_SPI_CRC != 0U) + __IO uint32_t tmpreg = 0U; +#endif /* USE_SPI_CRC */ /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; @@ -1248,6 +1256,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1293,6 +1302,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { errorcode = HAL_TIMEOUT; + hspi->State = HAL_SPI_STATE_READY; goto error; } } @@ -1341,8 +1351,16 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD __HAL_SPI_CLEAR_OVRFLAG(hspi); } + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + errorcode = HAL_ERROR; + } + else + { + hspi->State = HAL_SPI_STATE_READY; + } + error : - hspi->State = HAL_SPI_STATE_READY; __HAL_UNLOCK(hspi); return errorcode; } @@ -1362,8 +1380,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); if ((pData == NULL) || (Size == 0U)) { @@ -1377,6 +1393,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1416,10 +1435,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); - - /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { @@ -1427,8 +1442,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } -error : + /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1444,6 +1463,13 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { HAL_StatusTypeDef errorcode = HAL_OK; + + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1451,14 +1477,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); } - /* Process Locked */ - __HAL_LOCK(hspi); - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } if ((pData == NULL) || (Size == 0U)) { @@ -1466,6 +1484,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui goto error; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -1505,9 +1526,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } #endif /* USE_SPI_CRC */ - /* Enable TXE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); - /* Note : The SPI must be enabled after unlocking current process to avoid the risk of SPI interrupt handle execution before current process unlock */ @@ -1519,9 +1537,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1543,9 +1564,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; @@ -1563,6 +1581,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p goto error; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1598,8 +1619,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p } #endif /* USE_SPI_CRC */ - /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); /* Check if the SPI is already enabled */ if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) @@ -1608,9 +1627,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_SPI_ENABLE(hspi); } -error : /* Process Unlocked */ __HAL_UNLOCK(hspi); + /* Enable TXE, RXNE and ERR interrupt */ + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + +error : return errorcode; } @@ -1697,7 +1719,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1737,6 +1758,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); + if (hspi->State != HAL_SPI_STATE_READY) + { + errorcode = HAL_BUSY; + goto error; + } + if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1751,12 +1778,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - goto error; - } - if ((pData == NULL) || (Size == 0U)) { errorcode = HAL_ERROR; @@ -1812,7 +1833,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1934,7 +1954,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -1956,7 +1975,6 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); errorcode = HAL_ERROR; - hspi->State = HAL_SPI_STATE_READY; goto error; } @@ -3156,12 +3174,15 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; /* To avoid GCC warning */ - UNUSED(tmpreg); + UNUSED(tmpreg8); /* Disable RXNE and ERR interrupt */ __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); @@ -3256,7 +3277,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) /* Read 16bit CRC to flush Data Register */ tmpreg = READ_REG(hspi->Instance->DR); /* To avoid GCC warning */ - UNUSED(tmpreg); + UNUSED(tmpreg); /* Disable RXNE interrupt */ __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); @@ -3311,12 +3332,15 @@ static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) { - __IO uint32_t tmpreg = 0U; + __IO uint8_t *ptmpreg8; + __IO uint8_t tmpreg8 = 0; + /* Initialize the 8bit temporary pointer */ + ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR; /* Read 8bit CRC to flush Data Register */ - tmpreg = READ_REG(*(__IO uint8_t *)&hspi->Instance->DR); + tmpreg8 = *ptmpreg8; /* To avoid GCC warning */ - UNUSED(tmpreg); + UNUSED(tmpreg8); SPI_CloseRx_ISR(hspi); } @@ -3520,7 +3544,7 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, return HAL_TIMEOUT; } /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */ - if(count == 0U) + if (count == 0U) { tmp_timeout = 0U; } @@ -3909,4 +3933,3 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.h index f2e07c2c0f6..d7997a317b2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_spi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -656,7 +655,8 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, + pSPI_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ /** @@ -727,4 +727,3 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #endif /* STM32F4xx_HAL_SPI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.c index 752056982b7..ef2eaf092eb 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.c @@ -3,58 +3,69 @@ * @file stm32f4xx_hal_sram.c * @author MCD Application Team * @brief SRAM HAL module driver. - * This file provides a generic firmware to drive SRAM memories + * This file provides a generic firmware to drive SRAM memories * mounted as external device. - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### - ============================================================================== + ============================================================================== [..] - This driver is a generic layered driver which contains a set of APIs used to - control SRAM memories. It uses the FMC layer functions to interface - with SRAM devices. + This driver is a generic layered driver which contains a set of APIs used to + control SRAM memories. It uses the FMC layer functions to interface + with SRAM devices. The following sequence should be followed to configure the FMC/FSMC to interface - with SRAM/PSRAM memories: - + with SRAM/PSRAM memories: + (#) Declare a SRAM_HandleTypeDef handle structure, for example: - SRAM_HandleTypeDef hsram; and: - - (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed + SRAM_HandleTypeDef hsram; and: + + (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed values of the structure member. - - (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined - base register instance for NOR or SRAM device - + + (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined + base register instance for NOR or SRAM device + (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined - base register instance for NOR or SRAM extended mode - - (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended + base register instance for NOR or SRAM extended mode + + (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended mode timings; for example: FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming; and fill its fields with the allowed values of the structure member. - + (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function performs the following sequence: - + (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() - (##) Control register configuration using the FMC NORSRAM interface function + (##) Control register configuration using the FMC NORSRAM interface function FMC_NORSRAM_Init() - (##) Timing register configuration using the FMC NORSRAM interface function + (##) Timing register configuration using the FMC NORSRAM interface function FMC_NORSRAM_Timing_Init() - (##) Extended mode Timing register configuration using the FMC NORSRAM interface function + (##) Extended mode Timing register configuration using the FMC NORSRAM interface function FMC_NORSRAM_Extended_Timing_Init() - (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() + (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() - (#) At this stage you can perform read/write accesses from/to the memory connected + (#) At this stage you can perform read/write accesses from/to the memory connected to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the following APIs: (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer - + (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ - HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation - + HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation + (#) You can continuously monitor the SRAM device HAL state by calling the function HAL_SRAM_GetState() @@ -64,25 +75,25 @@ The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS when set to 1 allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_SRAM_RegisterCallback() to register a user callback, + Use Functions HAL_SRAM_RegisterCallback() to register a user callback, it allows to register following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. - Use function @ref HAL_SRAM_UnRegisterCallback() to reset a callback to the default + Use function HAL_SRAM_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. It allows to reset following callbacks: (+) MspInitCallback : SRAM MspInit. (+) MspDeInitCallback : SRAM MspDeInit. This function) takes as parameters the HAL peripheral handle and the Callback ID. - By default, after the @ref HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET + By default, after the HAL_SRAM_Init and if the state is HAL_SRAM_STATE_RESET all callbacks are reset to the corresponding legacy weak (surcharged) functions. Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_SRAM_Init - and @ref HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_SRAM_Init and @ref HAL_SRAM_DeInit + reset to the legacy weak (surcharged) functions in the HAL_SRAM_Init + and HAL_SRAM_DeInit only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_SRAM_Init and HAL_SRAM_DeInit keep and use the user MspInit/MspDeInit callbacks (registered beforehand) Callbacks can be registered/unregistered in READY state only. @@ -90,8 +101,8 @@ in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_SRAM_RegisterCallback before calling @ref HAL_SRAM_DeInit - or @ref HAL_SRAM_Init function. + using HAL_SRAM_RegisterCallback before calling HAL_SRAM_DeInit + or HAL_SRAM_Init function. When The compilation define USE_HAL_SRAM_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available @@ -99,57 +110,49 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" +#if defined(FMC_Bank1) || defined(FSMC_Bank1) + /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#ifdef HAL_SRAM_MODULE_ENABLED + /** @defgroup SRAM SRAM * @brief SRAM driver modules * @{ */ -#ifdef HAL_SRAM_MODULE_ENABLED - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma); +static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma); +static void SRAM_DMAError(DMA_HandleTypeDef *hdma); /* Exported functions --------------------------------------------------------*/ + /** @defgroup SRAM_Exported_Functions SRAM Exported Functions * @{ */ -/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions + +/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions. * - @verbatim + @verbatim ============================================================================== ##### SRAM Initialization and de_initialization functions ##### ============================================================================== [..] This section provides functions allowing to initialize/de-initialize the SRAM memory - + @endverbatim * @{ */ @@ -158,25 +161,26 @@ * @brief Performs the SRAM device initialization sequence * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. - * @param Timing Pointer to SRAM control timing structure - * @param ExtTiming Pointer to SRAM extended mode timing structure + * @param Timing Pointer to SRAM control timing structure + * @param ExtTiming Pointer to SRAM extended mode timing structure * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) -{ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming) +{ /* Check the SRAM handle parameter */ - if(hsram == NULL) + if (hsram == NULL) { - return HAL_ERROR; + return HAL_ERROR; } - - if(hsram->State == HAL_SRAM_STATE_RESET) - { + + if (hsram->State == HAL_SRAM_STATE_RESET) + { /* Allocate lock resource and initialize it */ hsram->Lock = HAL_UNLOCKED; #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if(hsram->MspInitCallback == NULL) + if (hsram->MspInitCallback == NULL) { hsram->MspInitCallback = HAL_SRAM_MspInit; } @@ -188,21 +192,25 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp #else /* Initialize the low level hardware (MSP) */ HAL_SRAM_MspInit(hsram); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } - + /* Initialize SRAM control Interface */ - FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); + (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); /* Initialize SRAM timing Interface */ - FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); + (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); /* Initialize SRAM extended mode timing Interface */ - FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); - + (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, + hsram->Init.ExtendedMode); + /* Enable the NORSRAM device */ - __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); - + __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); + + /* Initialize the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + return HAL_OK; } @@ -212,10 +220,10 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp * the configuration information for SRAM module. * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) -{ +HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) +{ #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - if(hsram->MspDeInitCallback == NULL) + if (hsram->MspDeInitCallback == NULL) { hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; } @@ -225,13 +233,14 @@ HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) #else /* De-Initialize the low level hardware (MSP) */ HAL_SRAM_MspDeInit(hsram); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /* Configure the SRAM registers with their reset values */ - FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); + (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); + /* Reset the SRAM controller state */ hsram->State = HAL_SRAM_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hsram); @@ -248,9 +257,10 @@ __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsram); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_MspInit could be implemented in the user file - */ + */ } /** @@ -263,9 +273,10 @@ __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) { /* Prevent unused argument(s) compilation warning */ UNUSED(hsram); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_MspDeInit could be implemented in the user file - */ + */ } /** @@ -278,9 +289,10 @@ __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma); + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file - */ + */ } /** @@ -293,257 +305,337 @@ __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) { /* Prevent unused argument(s) compilation warning */ UNUSED(hdma); - /* NOTE : This function Should not be modified, when the callback is needed, + + /* NOTE : This function Should not be modified, when the callback is needed, the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file - */ + */ } /** * @} */ -/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions - * @brief Input Output and memory control functions +/** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions + * @brief Input Output and memory control functions * - @verbatim + @verbatim ============================================================================== ##### SRAM Input and Output functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to use and control the SRAM memory - + @endverbatim * @{ */ /** - * @brief Reads 8-bit buffer from SRAM memory. + * @brief Reads 8-bit buffer from SRAM memory. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer + * @param pDstBuffer Pointer to destination buffer * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize) { - __IO uint8_t * pSramAddress = (uint8_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0U; BufferSize--) + uint32_t size; + __IO uint8_t *psramaddress = (uint8_t *)pAddress; + uint8_t *pdestbuff = pDstBuffer; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { - *pDstBuffer = *(__IO uint8_t *)pSramAddress; - pDstBuffer++; - pSramAddress++; + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *psramaddress; + pdestbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; + return HAL_OK; } /** - * @brief Writes 8-bit buffer to SRAM memory. + * @brief Writes 8-bit buffer to SRAM memory. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write + * @param pSrcBuffer Pointer to source buffer to write * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize) { - __IO uint8_t * pSramAddress = (uint8_t *)pAddress; - + uint32_t size; + __IO uint8_t *psramaddress = (uint8_t *)pAddress; + uint8_t *psrcbuff = pSrcBuffer; + /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_READY) { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Process Locked */ + __HAL_LOCK(hsram); - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *psramaddress = *psrcbuff; + psrcbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else { - *(__IO uint8_t *)pSramAddress = *pSrcBuffer; - pSrcBuffer++; - pSramAddress++; - } + return HAL_ERROR; + } - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; + return HAL_OK; } /** - * @brief Reads 16-bit buffer from SRAM memory. + * @brief Reads 16-bit buffer from SRAM memory. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer + * @param pDstBuffer Pointer to destination buffer * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize) { - __IO uint16_t * pSramAddress = (uint16_t *)pAddress; - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0U; BufferSize--) + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint16_t *pdestbuff = pDstBuffer; + uint8_t limit; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { - *pDstBuffer = *(__IO uint16_t *)pSramAddress; - pDstBuffer++; - pSramAddress++; + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Check if the size is a 32-bits multiple */ + limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); + + /* Read data from memory */ + for (size = BufferSize; size != limit; size -= 2U) + { + *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); + pdestbuff++; + *pdestbuff = (uint16_t)(((*psramaddress) & 0xFFFF0000U) >> 16U); + pdestbuff++; + psramaddress++; + } + + /* Read last 16-bits if size is not 32-bits multiple */ + if (limit != 0U) + { + *pdestbuff = (uint16_t)((*psramaddress) & 0x0000FFFFU); + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; + return HAL_OK; } /** - * @brief Writes 16-bit buffer to SRAM memory. + * @brief Writes 16-bit buffer to SRAM memory. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write + * @param pSrcBuffer Pointer to source buffer to write * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize) { - __IO uint16_t * pSramAddress = (uint16_t *)pAddress; - + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint16_t *psrcbuff = pSrcBuffer; + uint8_t limit; + /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_READY) { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Process Locked */ + __HAL_LOCK(hsram); - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Check if the size is a 32-bits multiple */ + limit = (((BufferSize % 2U) != 0U) ? 1U : 0U); + + /* Write data to memory */ + for (size = BufferSize; size != limit; size -= 2U) + { + *psramaddress = (uint32_t)(*psrcbuff); + psrcbuff++; + *psramaddress |= ((uint32_t)(*psrcbuff) << 16U); + psrcbuff++; + psramaddress++; + } + + /* Write last 16-bits if size is not 32-bits multiple */ + if (limit != 0U) + { + *psramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psramaddress) & 0xFFFF0000U); + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else { - *(__IO uint16_t *)pSramAddress = *pSrcBuffer; - pSrcBuffer++; - pSramAddress++; - } + return HAL_ERROR; + } - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; + return HAL_OK; } /** - * @brief Reads 32-bit buffer from SRAM memory. + * @brief Reads 32-bit buffer from SRAM memory. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer + * @param pDstBuffer Pointer to destination buffer * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Read data from memory */ - for(; BufferSize != 0U; BufferSize--) + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint32_t *pdestbuff = pDstBuffer; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { - *pDstBuffer = *(__IO uint32_t *)pAddress; - pDstBuffer++; - pAddress++; + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Read data from memory */ + for (size = BufferSize; size != 0U; size--) + { + *pdestbuff = *psramaddress; + pdestbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = state; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; } - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; + return HAL_OK; } /** - * @brief Writes 32-bit buffer to SRAM memory. + * @brief Writes 32-bit buffer to SRAM memory. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write + * @param pSrcBuffer Pointer to source buffer to write * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { + uint32_t size; + __IO uint32_t *psramaddress = pAddress; + uint32_t *psrcbuff = pSrcBuffer; + /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_READY) { - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; + /* Process Locked */ + __HAL_LOCK(hsram); - /* Write data to memory */ - for(; BufferSize != 0U; BufferSize--) + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Write data to memory */ + for (size = BufferSize; size != 0U; size--) + { + *psramaddress = *psrcbuff; + psrcbuff++; + psramaddress++; + } + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else { - *(__IO uint32_t *)pAddress = *pSrcBuffer; - pSrcBuffer++; - pAddress++; - } + return HAL_ERROR; + } - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; + return HAL_OK; } /** @@ -551,32 +643,48 @@ HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress Pointer to read start address - * @param pDstBuffer Pointer to destination buffer + * @param pDstBuffer Pointer to destination buffer * @param BufferSize Size of the buffer to read from memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize) { - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; + HAL_StatusTypeDef status; + HAL_SRAM_StateTypeDef state = hsram->State; + + /* Check the SRAM controller state */ + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + { + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + if (state == HAL_SRAM_STATE_READY) + { + hsram->hdma->XferCpltCallback = SRAM_DMACplt; + } + else + { + hsram->hdma->XferCpltCallback = SRAM_DMACpltProt; + } + hsram->hdma->XferErrorCallback = SRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + status = HAL_ERROR; + } + + return status; } /** @@ -584,38 +692,40 @@ HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddres * @param hsram pointer to a SRAM_HandleTypeDef structure that contains * the configuration information for SRAM module. * @param pAddress Pointer to write start address - * @param pSrcBuffer Pointer to source buffer to write + * @param pSrcBuffer Pointer to source buffer to write * @param BufferSize Size of the buffer to write to memory * @retval HAL status */ -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize) { + HAL_StatusTypeDef status; + /* Check the SRAM controller state */ - if(hsram->State == HAL_SRAM_STATE_PROTECTED) + if (hsram->State == HAL_SRAM_STATE_READY) { - return HAL_ERROR; + /* Process Locked */ + __HAL_LOCK(hsram); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Configure DMA user callbacks */ + hsram->hdma->XferCpltCallback = SRAM_DMACplt; + hsram->hdma->XferErrorCallback = SRAM_DMAError; + + /* Enable the DMA Stream */ + status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); + + /* Process unlocked */ + __HAL_UNLOCK(hsram); } - - /* Process Locked */ - __HAL_LOCK(hsram); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Configure DMA user callbacks */ - hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; + else + { + status = HAL_ERROR; + } + + return status; } #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) @@ -630,12 +740,13 @@ HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddre * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -644,20 +755,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_RESET) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = pCallback; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = pCallback; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -683,7 +794,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM * @arg @ref HAL_SRAM_DMA_XFER_ERR_CB_ID SRAM DMA Xfer Error callback ID * @retval status */ -HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) +HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; @@ -692,42 +803,42 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } - else if(state == HAL_SRAM_STATE_RESET) + else if (state == HAL_SRAM_STATE_RESET) { switch (CallbackId) { - case HAL_SRAM_MSP_INIT_CB_ID : - hsram->MspInitCallback = HAL_SRAM_MspInit; - break; - case HAL_SRAM_MSP_DEINIT_CB_ID : - hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_MSP_INIT_CB_ID : + hsram->MspInitCallback = HAL_SRAM_MspInit; + break; + case HAL_SRAM_MSP_DEINIT_CB_ID : + hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -752,12 +863,13 @@ HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback (SRAM_HandleTypeDef *hsram, HAL_SR * @param pCallback : pointer to the Callback function * @retval status */ -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; HAL_SRAM_StateTypeDef state; - if(pCallback == NULL) + if (pCallback == NULL) { return HAL_ERROR; } @@ -766,20 +878,20 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR __HAL_LOCK(hsram); state = hsram->State; - if((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) + if ((state == HAL_SRAM_STATE_READY) || (state == HAL_SRAM_STATE_PROTECTED)) { switch (CallbackId) { - case HAL_SRAM_DMA_XFER_CPLT_CB_ID : - hsram->DmaXferCpltCallback = pCallback; - break; - case HAL_SRAM_DMA_XFER_ERR_CB_ID : - hsram->DmaXferErrorCallback = pCallback; - break; - default : - /* update return status */ - status = HAL_ERROR; - break; + case HAL_SRAM_DMA_XFER_CPLT_CB_ID : + hsram->DmaXferCpltCallback = pCallback; + break; + case HAL_SRAM_DMA_XFER_ERR_CB_ID : + hsram->DmaXferErrorCallback = pCallback; + break; + default : + /* update return status */ + status = HAL_ERROR; + break; } } else @@ -792,18 +904,19 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR __HAL_UNLOCK(hsram); return status; } -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + /** * @} */ - -/** @defgroup SRAM_Exported_Functions_Group3 Control functions - * @brief management functions - * -@verbatim + +/** @defgroup SRAM_Exported_Functions_Group3 Control functions + * @brief Control functions + * +@verbatim ============================================================================== ##### SRAM Control functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to control dynamically the SRAM interface. @@ -811,7 +924,7 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR @endverbatim * @{ */ - + /** * @brief Enables dynamically SRAM write operation. * @param hsram pointer to a SRAM_HandleTypeDef structure that contains @@ -820,19 +933,30 @@ HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SR */ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) { - /* Process Locked */ - __HAL_LOCK(hsram); + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_PROTECTED) + { + /* Process Locked */ + __HAL_LOCK(hsram); - /* Enable write operation */ - FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Enable write operation */ + (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; } /** @@ -843,43 +967,51 @@ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) */ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) { - /* Process Locked */ - __HAL_LOCK(hsram); + /* Check the SRAM controller state */ + if (hsram->State == HAL_SRAM_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(hsram); - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_BUSY; - - /* Disable write operation */ - FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); - - /* Update the SRAM controller state */ - hsram->State = HAL_SRAM_STATE_PROTECTED; - - /* Process unlocked */ - __HAL_UNLOCK(hsram); - - return HAL_OK; + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_BUSY; + + /* Disable write operation */ + (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; + + /* Process unlocked */ + __HAL_UNLOCK(hsram); + } + else + { + return HAL_ERROR; + } + + return HAL_OK; } /** * @} */ -/** @defgroup SRAM_Exported_Functions_Group4 State functions - * @brief Peripheral State functions - * -@verbatim +/** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim ============================================================================== ##### SRAM State functions ##### - ============================================================================== + ============================================================================== [..] - This subsection permits to get in run-time the status of the SRAM controller + This subsection permits to get in run-time the status of the SRAM controller and the data flow. @endverbatim * @{ */ - + /** * @brief Returns the SRAM controller state * @param hsram pointer to a SRAM_HandleTypeDef structure that contains @@ -890,6 +1022,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) { return hsram->State; } + /** * @} */ @@ -897,16 +1030,81 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ -#endif /* HAL_SRAM_MODULE_ENABLED */ + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_READY; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferCpltCallback(hdma); +#else + HAL_SRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM process complete callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_PROTECTED; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferCpltCallback(hdma); +#else + HAL_SRAM_DMA_XferCpltCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA SRAM error callback. + * @param hdma : DMA handle + * @retval None + */ +static void SRAM_DMAError(DMA_HandleTypeDef *hdma) +{ + SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); + + /* Disable the DMA channel */ + __HAL_DMA_DISABLE(hdma); + + /* Update the SRAM controller state */ + hsram->State = HAL_SRAM_STATE_ERROR; + +#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) + hsram->DmaXferErrorCallback(hdma); +#else + HAL_SRAM_DMA_XferErrorCallback(hdma); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +} + /** * @} */ +#endif /* HAL_SRAM_MODULE_ENABLED */ + /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* FMC_Bank1 || FSMC_Bank1 */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.h index 0c7b08dba72..e135aa13782 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_sram.h @@ -6,58 +6,48 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_HAL_SRAM_H -#define __STM32F4xx_HAL_SRAM_H +#ifndef STM32F4xx_HAL_SRAM_H +#define STM32F4xx_HAL_SRAM_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif -/* Includes ------------------------------------------------------------------*/ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - #include "stm32f4xx_ll_fsmc.h" -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #include "stm32f4xx_ll_fmc.h" -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +#if defined(FMC_Bank1) || defined(FSMC_Bank1) +/* Includes ------------------------------------------------------------------*/ +#if defined(FSMC_Bank1) +#include "stm32f4xx_ll_fsmc.h" +#else +#include "stm32f4xx_ll_fmc.h" +#endif /* FSMC_Bank1 */ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\ - defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - /** @addtogroup SRAM * @{ - */ + */ /* Exported typedef ----------------------------------------------------------*/ /** @defgroup SRAM_Exported_Types SRAM Exported Types * @{ - */ -/** - * @brief HAL SRAM State structures definition - */ + */ +/** + * @brief HAL SRAM State structures definition + */ typedef enum { HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ @@ -75,26 +65,26 @@ typedef enum typedef struct __SRAM_HandleTypeDef #else typedef struct -#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ { - FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ - + FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ + FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ - + FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ - HAL_LockTypeDef Lock; /*!< SRAM locking object */ - + HAL_LockTypeDef Lock; /*!< SRAM locking object */ + __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ - + DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) - void (* MspInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp Init callback */ - void (* MspDeInitCallback) ( struct __SRAM_HandleTypeDef * hsram); /*!< SRAM Msp DeInit callback */ - void (* DmaXferCpltCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Complete callback */ - void (* DmaXferErrorCallback) ( DMA_HandleTypeDef * hdma); /*!< SRAM DMA Xfer Error callback */ -#endif + void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp Init callback */ + void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram); /*!< SRAM Msp DeInit callback */ + void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Complete callback */ + void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SRAM DMA Xfer Error callback */ +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ } SRAM_HandleTypeDef; #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) @@ -107,14 +97,14 @@ typedef enum HAL_SRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SRAM MspDeInit Callback ID */ HAL_SRAM_DMA_XFER_CPLT_CB_ID = 0x02U, /*!< SRAM DMA Xfer Complete Callback ID */ HAL_SRAM_DMA_XFER_ERR_CB_ID = 0x03U /*!< SRAM DMA Xfer Complete Callback ID */ -}HAL_SRAM_CallbackIDTypeDef; +} HAL_SRAM_CallbackIDTypeDef; /** * @brief HAL SRAM Callback pointer definition */ typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram); typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ @@ -125,6 +115,7 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); /** @defgroup SRAM_Exported_Macros SRAM Exported Macros * @{ */ + /** @brief Reset SRAM handle state * @param __HANDLE__ SRAM handle * @retval None @@ -137,69 +128,89 @@ typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); } while(0) #else #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) -#endif +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ /** * @} */ + /* Exported functions --------------------------------------------------------*/ +/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions + * @{ + */ -/** @addtogroup SRAM_Exported_Functions - * @{ - */ +/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ -/** @addtogroup SRAM_Exported_Functions_Group1 - * @{ - */ -/* Initialization/de-initialization functions **********************************/ -HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); +/* Initialization/de-initialization functions ********************************/ +HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, + FMC_NORSRAM_TimingTypeDef *ExtTiming); HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); +void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); -void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); -void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); /** * @} - */ - -/** @addtogroup SRAM_Exported_Functions_Group2 - * @{ - */ -/* I/O operation functions *****************************************************/ -HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); -HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); + */ + +/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions + * @{ + */ + +/* I/O operation functions ***************************************************/ +HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, + uint32_t BufferSize); +HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, + uint32_t BufferSize); + +void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); +void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); + #if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1) /* SRAM callback registering/unregistering */ -HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId); -HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback); -#endif +HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, + pSRAM_DmaCallbackTypeDef pCallback); +#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS */ + /** * @} - */ + */ -/** @addtogroup SRAM_Exported_Functions_Group3 - * @{ - */ -/* SRAM Control functions ******************************************************/ +/** @addtogroup SRAM_Exported_Functions_Group3 Control functions + * @{ + */ + +/* SRAM Control functions ****************************************************/ HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); + /** * @} - */ + */ + +/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions + * @{ + */ -/** @addtogroup SRAM_Exported_Functions_Group4 - * @{ - */ -/* SRAM State functions *********************************************************/ +/* SRAM State functions ******************************************************/ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); + /** * @} */ @@ -208,25 +219,18 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); * @} */ -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ /** * @} - */ + */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ - STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\ - STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ /** * @} */ + +#endif /* FMC_Bank1 || FSMC_Bank1 */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_HAL_SRAM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_HAL_SRAM_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.c index 451c62d1e7f..e35049bf559 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.c @@ -29,6 +29,17 @@ * + Commutation Event configuration with Interruption and DMA * + TIM OCRef clear configuration * + TIM External Clock configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### TIMER Generic features ##### @@ -103,14 +114,14 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_TIM_RegisterCallback() to register a callback. - @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, + Use Function HAL_TIM_RegisterCallback() to register a callback. + HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, the Callback ID and a pointer to the user callback function. [..] - Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default + Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default weak function. - @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, + HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, and the Callback ID. [..] @@ -146,7 +157,7 @@ [..] By default, after the Init and when the state is HAL_TIM_STATE_RESET all interrupt callbacks are set to the corresponding weak functions: - examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). + examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). [..] Exception done for MspInit and MspDeInit functions that are reset to the legacy weak @@ -160,7 +171,7 @@ all interrupt callbacks are set to the corresponding weak functions: in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. + using HAL_TIM_RegisterCallback() before calling DeInit or Init function. [..] When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or @@ -169,17 +180,6 @@ all interrupt callbacks are set to the corresponding weak functions: @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -204,9 +204,9 @@ all interrupt callbacks are set to the corresponding weak functions: /** @addtogroup TIM_Private_Functions * @{ */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); @@ -222,7 +222,7 @@ static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig); + const TIM_SlaveConfigTypeDef *sSlaveConfig); /** * @} */ @@ -522,7 +522,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) { uint32_t tmpsmcr; @@ -558,7 +558,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -874,6 +875,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -919,34 +921,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -962,6 +968,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -996,26 +1004,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1031,8 +1043,10 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1071,7 +1085,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1092,7 +1107,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1113,7 +1129,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1133,7 +1150,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1144,34 +1162,38 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1187,6 +1209,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1225,26 +1249,30 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1511,7 +1539,9 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1555,34 +1585,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1598,6 +1632,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1632,26 +1668,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1667,8 +1707,10 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1707,7 +1749,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1728,7 +1771,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1748,7 +1792,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1768,7 +1813,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1779,34 +1825,38 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Enable the main output */ + __HAL_TIM_MOE_ENABLE(htim); + } + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1822,6 +1872,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe */ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -1860,26 +1912,30 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + if (status == HAL_OK) { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } + /* Disable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) + { + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); + } - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2139,7 +2195,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); @@ -2188,27 +2246,32 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + if (status == HAL_OK) { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2224,6 +2287,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); @@ -2258,21 +2323,25 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + if (status == HAL_OK) + { + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2290,7 +2359,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; + HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); @@ -2322,6 +2393,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel return HAL_ERROR; } + /* Enable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + switch (Channel) { case TIM_CHANNEL_1: @@ -2334,7 +2408,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2354,7 +2429,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2374,7 +2450,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2394,7 +2471,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -2405,12 +2483,10 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } default: + status = HAL_ERROR; break; } - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) { @@ -2426,7 +2502,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel } /* Return function status */ - return HAL_OK; + return status; } /** @@ -2442,6 +2518,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel */ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); @@ -2484,18 +2562,22 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) } default: + status = HAL_ERROR; break; } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + if (status == HAL_OK) + { + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM channel state */ + TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** * @} @@ -2681,8 +2763,8 @@ __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) * @brief Starts the TIM One Pulse signal generation. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status @@ -2738,8 +2820,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu * @brief Stops the TIM One Pulse signal generation. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status @@ -2781,8 +2863,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output * @brief Starts the TIM One Pulse signal generation in interrupt mode. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status @@ -2844,8 +2926,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou * @brief Stops the TIM One Pulse signal generation in interrupt mode. * @note Though OutputChannel parameter is deprecated and ignored by the function * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note The pulse output channel is determined when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel See note above * @retval HAL status @@ -3548,7 +3630,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3556,11 +3639,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); break; } @@ -3573,7 +3657,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Set the DMA error callback */ htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3581,15 +3666,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); break; } - case TIM_CHANNEL_ALL: + default: { /* Set the DMA capture callbacks */ htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; @@ -3599,7 +3685,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -3613,27 +3700,27 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); /* Enable the TIM Input Capture DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - default: + /* Enable the Capture compare channel */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + break; + } } /* Return function status */ @@ -3943,9 +4030,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); @@ -3997,12 +4086,13 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4018,8 +4108,10 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel) +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); @@ -4076,7 +4168,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Set the IC3PSC value */ htim->Instance->CCMR2 |= sConfig->ICPrescaler; } - else + else if (Channel == TIM_CHANNEL_4) { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); @@ -4092,10 +4184,14 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); } + else + { + status = HAL_ERROR; + } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4112,9 +4208,11 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - TIM_OC_InitTypeDef *sConfig, + const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); @@ -4195,12 +4293,13 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -4225,6 +4324,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) { + HAL_StatusTypeDef status = HAL_OK; TIM_OC_InitTypeDef temp1; /* Check the parameters */ @@ -4255,6 +4355,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_OC1_SetConfig(htim->Instance, &temp1); break; } + case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); @@ -4262,60 +4363,67 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_OC2_SetConfig(htim->Instance, &temp1); break; } + default: + status = HAL_ERROR; break; } - switch (InputChannel) + if (status == HAL_OK) { - case TIM_CHANNEL_1: + switch (InputChannel) { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + case TIM_CHANNEL_1: + { + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; + /* Reset the IC1PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI1FP1; - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); + case TIM_CHANNEL_2: + { + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, + sConfig->ICSelection, sConfig->ICFilter); - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; + /* Reset the IC2PSC Bits */ + htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } + /* Select the Trigger source */ + htim->Instance->SMCR &= ~TIM_SMCR_TS; + htim->Instance->SMCR |= TIM_TS_TI2FP2; - default: - break; + /* Select the Slave Mode */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; + break; + } + + default: + status = HAL_ERROR; + break; + } } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } else { @@ -4362,10 +4470,16 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength) { - return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + + return status; } /** @@ -4408,9 +4522,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); @@ -4437,6 +4553,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint { /* nothing to do */ } + switch (BurstRequestSrc) { case TIM_DMA_UPDATE: @@ -4450,7 +4567,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4468,7 +4585,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4486,7 +4603,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4504,7 +4621,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4522,7 +4639,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4540,7 +4657,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4558,7 +4675,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) + (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4566,16 +4683,20 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint break; } default: + status = HAL_ERROR; break; } - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4586,6 +4707,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4628,17 +4751,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B break; } default: + status = HAL_ERROR; break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4682,8 +4809,13 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) { - return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - ((BurstLength) >> 8U) + 1U); + HAL_StatusTypeDef status; + + status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, + ((BurstLength) >> 8U) + 1U); + + + return status; } /** @@ -4729,6 +4861,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); @@ -4768,7 +4902,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4786,7 +4920,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4804,7 +4938,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4822,7 +4956,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4840,7 +4974,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4858,7 +4992,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4876,7 +5010,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 /* Enable the DMA stream */ if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) + DataLength) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -4884,17 +5018,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 break; } default: + status = HAL_ERROR; break; } - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength); + if (status == HAL_OK) + { + /* Configure the DMA Burst Mode */ + htim->Instance->DCR = (BurstBaseAddress | BurstLength); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + /* Enable the TIM DMA Request */ + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -4905,6 +5043,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint3 */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); @@ -4947,17 +5087,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu break; } default: + status = HAL_ERROR; break; } - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); + if (status == HAL_OK) + { + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + /* Change the DMA burst operation state */ + htim->DMABurstState = HAL_DMA_BURST_STATE_READY; + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -5018,9 +5162,11 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - TIM_ClearInputConfigTypeDef *sClearInputConfig, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); @@ -5062,76 +5208,80 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, } default: + status = HAL_ERROR; break; } - switch (Channel) + if (status == HAL_OK) { - case TIM_CHANNEL_1: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 1 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - break; - } - case TIM_CHANNEL_2: + switch (Channel) { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 2 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - break; - } - case TIM_CHANNEL_3: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_1: { - /* Enable the OCREF clear feature for Channel 3 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 1 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + else + { + /* Disable the OCREF clear feature for Channel 1 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); + } + break; } - else + case TIM_CHANNEL_2: { - /* Disable the OCREF clear feature for Channel 3 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 2 */ + SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + else + { + /* Disable the OCREF clear feature for Channel 2 */ + CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); + } + break; } - break; - } - case TIM_CHANNEL_4: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + case TIM_CHANNEL_3: { - /* Enable the OCREF clear feature for Channel 4 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 3 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + else + { + /* Disable the OCREF clear feature for Channel 3 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); + } + break; } - else + case TIM_CHANNEL_4: { - /* Disable the OCREF clear feature for Channel 4 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) + { + /* Enable the OCREF clear feature for Channel 4 */ + SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + else + { + /* Disable the OCREF clear feature for Channel 4 */ + CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); + } + break; } - break; + default: + break; } - default: - break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -5141,8 +5291,9 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, * contains the clock source information for the TIM peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig) +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Process Locked */ @@ -5263,22 +5414,23 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo case TIM_CLOCKSOURCE_ITR1: case TIM_CLOCKSOURCE_ITR2: case TIM_CLOCKSOURCE_ITR3: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); + { + /* Check whether or not the timer instance supports internal trigger input */ + assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } + TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); + break; + } default: + status = HAL_ERROR; break; } htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); - return HAL_OK; + return status; } /** @@ -5325,7 +5477,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S * (Disable, Reset, Gated, Trigger, External clock mode 1). * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig) +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5366,7 +5518,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { /* Check the parameters */ assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); @@ -5408,7 +5560,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval Captured value */ -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) { uint32_t tmpreg = 0U; @@ -5799,7 +5951,7 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } @@ -5865,14 +6017,14 @@ HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Call default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } /* Release Lock */ @@ -5928,116 +6080,143 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */ + /* Legacy weak Period Elapsed Callback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; break; case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */ + /* Legacy weak Period Elapsed half complete Callback */ + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; break; case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */ + /* Legacy weak Trigger Callback */ + htim->TriggerCallback = HAL_TIM_TriggerCallback; break; case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */ + /* Legacy weak Trigger half complete Callback */ + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; break; case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */ + /* Legacy weak IC Capture Callback */ + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; break; case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */ + /* Legacy weak IC Capture half complete Callback */ + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; break; case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */ + /* Legacy weak OC Delay Elapsed Callback */ + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */ + /* Legacy weak PWM Pulse Finished Callback */ + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; break; case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */ + /* Legacy weak PWM Pulse Finished half complete Callback */ + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; break; case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */ + /* Legacy weak Error Callback */ + htim->ErrorCallback = HAL_TIM_ErrorCallback; break; case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */ + /* Legacy weak Commutation Callback */ + htim->CommutationCallback = HAL_TIMEx_CommutCallback; break; case HAL_TIM_COMMUTATION_HALF_CB_ID : - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */ + /* Legacy weak Commutation half complete Callback */ + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; break; case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */ + /* Legacy weak Break Callback */ + htim->BreakCallback = HAL_TIMEx_BreakCallback; break; default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } @@ -6046,71 +6225,85 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca switch (CallbackID) { case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */ + /* Legacy weak Base MspInit Callback */ + htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; break; case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */ + /* Legacy weak Base Msp DeInit Callback */ + htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; break; case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */ + /* Legacy weak IC Msp Init Callback */ + htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; break; case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */ + /* Legacy weak IC Msp DeInit Callback */ + htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; break; case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */ + /* Legacy weak OC Msp Init Callback */ + htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; break; case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */ + /* Legacy weak OC Msp DeInit Callback */ + htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; break; case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */ + /* Legacy weak PWM Msp Init Callback */ + htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; break; case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */ + /* Legacy weak PWM Msp DeInit Callback */ + htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; break; case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */ + /* Legacy weak One Pulse Msp Init Callback */ + htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; break; case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */ + /* Legacy weak One Pulse Msp DeInit Callback */ + htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; break; case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */ + /* Legacy weak Encoder Msp Init Callback */ + htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; break; case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */ + /* Legacy weak Encoder Msp DeInit Callback */ + htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; break; case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */ + /* Legacy weak Hall Sensor Msp Init Callback */ + htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; break; case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */ + /* Legacy weak Hall Sensor Msp DeInit Callback */ + htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; break; default : /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; break; } } else { /* Return error status */ - status = HAL_ERROR; + status = HAL_ERROR; } /* Release Lock */ @@ -6144,7 +6337,7 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @param htim TIM Base handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6154,7 +6347,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Output Compare handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6164,7 +6357,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6174,7 +6367,7 @@ HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) * @param htim TIM IC handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6184,7 +6377,7 @@ HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) * @param htim TIM OPM handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6194,7 +6387,7 @@ HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) * @param htim TIM Encoder Interface handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -6204,7 +6397,7 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) * @param htim TIM handle * @retval Active channel */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) { return htim->Channel; } @@ -6222,7 +6415,7 @@ HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_6: TIM Channel 6 * @retval TIM Channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel) +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -6239,7 +6432,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, ui * @param htim TIM handle * @retval DMA burst state */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim) +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); @@ -6582,7 +6775,7 @@ static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) * @param Structure TIM Base configuration structure * @retval None */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { uint32_t tmpcr1; tmpcr1 = TIMx->CR1; @@ -6630,7 +6823,7 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -6705,7 +6898,7 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -6781,7 +6974,7 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -6855,7 +7048,7 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @param OC_Config The output configuration structure * @retval None */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) +static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { uint32_t tmpccmrx; uint32_t tmpccer; @@ -6916,8 +7109,9 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) * @retval None */ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - TIM_SlaveConfigTypeDef *sSlaveConfig) + const TIM_SlaveConfigTypeDef *sSlaveConfig) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; @@ -7014,16 +7208,18 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, case TIM_TS_ITR1: case TIM_TS_ITR2: case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - break; - } + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + break; + } default: + status = HAL_ERROR; break; } - return HAL_OK; + + return status; } /** @@ -7397,19 +7593,19 @@ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelStat void TIM_ResetCallback(TIM_HandleTypeDef *htim) { /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */ - htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */ - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */ + htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; + htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; + htim->TriggerCallback = HAL_TIM_TriggerCallback; + htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; + htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; + htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; + htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; + htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; + htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; + htim->ErrorCallback = HAL_TIM_ErrorCallback; + htim->CommutationCallback = HAL_TIMEx_CommutCallback; + htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; + htim->BreakCallback = HAL_TIMEx_BreakCallback; } #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ @@ -7425,4 +7621,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim) /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.h index 7ec73103800..3a1da9df232 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -65,8 +64,10 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. */ uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. This parameter can be a value of @ref TIM_AutoReloadPreload */ @@ -218,7 +219,8 @@ typedef struct uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity This parameter can be a value of @ref TIM_ClearInput_Polarity */ uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ + This parameter must be 0: When OCRef clear feature is used with ETR source, + ETR prescaler must be off */ uint32_t ClearInputFilter; /*!< TIM Clear Input filter This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_ClearInputConfigTypeDef; @@ -264,22 +266,22 @@ typedef struct */ typedef struct { - uint32_t OffStateRunMode; /*!< TIM off state in run mode - This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode - This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - uint32_t LockLevel; /*!< TIM Lock level - This parameter can be a value of @ref TIM_Lock_level */ - uint32_t DeadTime; /*!< TIM dead Time - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - uint32_t BreakState; /*!< TIM Break State - This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - uint32_t BreakPolarity; /*!< TIM Break input polarity - This parameter can be a value of @ref TIM_Break_Polarity */ - uint32_t BreakFilter; /*!< Specifies the break input filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state - This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ + + uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + } TIM_BreakDeadTimeConfigTypeDef; /** @@ -628,10 +630,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection * @{ */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be - connected to IC2, IC1, IC4 or IC3, respectively */ +#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ /** * @} @@ -705,6 +705,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @} */ +/** @defgroup TIM_CC_DMA_Request CCx DMA request selection + * @{ + */ +#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ +#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ +/** + * @} + */ + /** @defgroup TIM_Flag_definition TIM Flag Definition * @{ */ @@ -739,16 +748,16 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to /** @defgroup TIM_Clock_Source TIM Clock Source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ +#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ +#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ +#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ +#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ +#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ /** * @} */ @@ -846,8 +855,7 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @{ */ #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event - (if none of the break inputs BRK and BRK2 is active) */ +#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ /** * @} */ @@ -1091,7 +1099,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Disable the TIM main Output. * @param __HANDLE__ TIM handle * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled + * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been + * disabled */ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ do { \ @@ -1252,8 +1261,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to * @brief Indicates whether or not the TIM Counter is used as downcounter. * @param __HANDLE__ TIM handle. * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder -mode. + * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode + * or Encoder mode. */ #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) @@ -1327,7 +1336,8 @@ mode. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. + * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() + * function. * @param __HANDLE__ TIM handle. * @param __CHANNEL__ TIM Channels to be configured. * This parameter can be one of the following values: @@ -1525,6 +1535,17 @@ mode. TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ }while(0) +/** @brief Select the Capture/compare DMA request source. + * @param __HANDLE__ specifies the TIM Handle. + * @param __CCDMA__ specifies Capture/compare DMA request source + * This parameter can be one of the following values: + * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event + * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event + * @retval None + */ +#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ + MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) + /** * @} */ @@ -1638,15 +1659,15 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3)) #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)) #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ @@ -1722,13 +1743,13 @@ mode. ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) -#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ ((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ ((__SELECTION__) == TIM_TS_ETRF)) #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ @@ -1817,11 +1838,11 @@ mode. ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ - } while(0) + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ @@ -1836,11 +1857,15 @@ mode. ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ - } while(0) + (__HANDLE__)->ChannelNState[0] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = \ + (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = \ + (__CHANNEL_STATE__); \ + } while(0) /** * @} @@ -1871,7 +1896,7 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); /** * @} @@ -1893,7 +1918,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -1915,7 +1941,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -2000,31 +2027,35 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); * @{ */ /* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, + uint32_t Channel); +HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, + uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, +HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, + const TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); +HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, - uint32_t DataLength); + uint32_t BurstRequestSrc, uint32_t *BurstBuffer, + uint32_t BurstLength, uint32_t DataLength); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} */ @@ -2061,17 +2092,17 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca * @{ */ /* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); /* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); +HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); +HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); /** * @} */ @@ -2085,9 +2116,9 @@ HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); /** @defgroup TIM_Private_Functions TIM Private Functions * @{ */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); +void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); +void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); @@ -2119,5 +2150,3 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim); #endif #endif /* STM32F4xx_HAL_TIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim_ex.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim_ex.c index 438dc44e909..98f26f56e87 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim_ex.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim_ex.c @@ -10,6 +10,17 @@ * + Time Complementary signal break and dead time configuration * + Time Master and Slave synchronization configuration * + Timer remapping capabilities configuration + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### TIMER Extended features ##### @@ -54,24 +65,16 @@ the commutation event). (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT() + (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), + HAL_TIMEx_OCN_Start_IT() + (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), + HAL_TIMEx_PWMN_Start_IT() (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT(). + (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), + HAL_TIMEx_HallSensor_Start_IT(). @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -132,7 +135,7 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig) +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) { TIM_OC_InitTypeDef OC_Config; @@ -335,7 +338,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -367,7 +371,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the Peripheral */ @@ -418,7 +423,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ @@ -450,7 +456,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); /* Disable the capture compare Interrupts event */ @@ -510,7 +517,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32 } /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); /* Set the DMA Input Capture 1 Callbacks */ @@ -557,7 +565,8 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */ + (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, + TIM_CHANNEL_2 and TIM_CHANNEL_3) */ TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); @@ -697,6 +706,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -736,34 +746,38 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann default: + status = HAL_ERROR; break; } - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -779,7 +793,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -807,30 +823,34 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if (status == HAL_OK) { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -846,8 +866,10 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -886,7 +908,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -906,7 +929,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -926,7 +950,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -937,31 +962,35 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + if (status == HAL_OK) + { + /* Enable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -977,6 +1006,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1007,23 +1038,27 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + if (status == HAL_OK) + { + /* Disable the Capture compare channel N */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1154,6 +1189,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1192,34 +1228,38 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); + if (status == HAL_OK) + { + /* Enable the TIM Break interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1235,6 +1275,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chan */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpccer; /* Check the parameters */ @@ -1264,30 +1305,34 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann } default: + status = HAL_ERROR; break; } - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + if (status == HAL_OK) { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the TIM Break interrupt (only if no more channel is active) */ + tmpccer = htim->Instance->CCER; + if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET) + { + __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); + } - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1303,8 +1348,10 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length) { + HAL_StatusTypeDef status = HAL_OK; uint32_t tmpsmcr; /* Check the parameters */ @@ -1343,7 +1390,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1363,7 +1411,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1383,7 +1432,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; /* Enable the DMA stream */ - if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK) + if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, + Length) != HAL_OK) { /* Return error status */ return HAL_ERROR; @@ -1394,31 +1444,35 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha } default: + status = HAL_ERROR; break; } - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); + if (status == HAL_OK) + { + /* Enable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); + /* Enable the Main Output */ + __HAL_TIM_MOE_ENABLE(htim); - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ + if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) + { + tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; + if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) + { + __HAL_TIM_ENABLE(htim); + } + } + else { __HAL_TIM_ENABLE(htim); } } - else - { - __HAL_TIM_ENABLE(htim); - } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1434,6 +1488,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { + HAL_StatusTypeDef status = HAL_OK; + /* Check the parameters */ assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); @@ -1464,23 +1520,27 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan } default: + status = HAL_ERROR; break; } - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); + if (status == HAL_OK) + { + /* Disable the complementary PWM output */ + TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); + /* Disable the Main Output */ + __HAL_TIM_MOE_DISABLE(htim); - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + /* Set the TIM complementary channel state */ + TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); + } /* Return function status */ - return HAL_OK; + return status; } /** @@ -1508,8 +1568,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: @@ -1529,7 +1589,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) @@ -1557,8 +1617,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t Ou /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: @@ -1596,8 +1656,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t Out /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to enable * This parameter can be one of the following values: @@ -1617,7 +1677,7 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) + if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) @@ -1651,8 +1711,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). + * @note OutputChannel must match the pulse output channel chosen when calling + * @ref HAL_TIM_OnePulse_ConfigChannel(). * @param htim TIM One Pulse handle * @param OutputChannel pulse output channel to disable * This parameter can be one of the following values: @@ -1902,7 +1962,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint3 * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig) + const TIM_MasterConfigTypeDef *sMasterConfig) { uint32_t tmpcr2; uint32_t tmpsmcr; @@ -1963,7 +2023,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; @@ -2040,11 +2100,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, */ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { - __HAL_LOCK(htim); /* Check parameters */ assert_param(IS_TIM_REMAP(htim->Instance, Remap)); + __HAL_LOCK(htim); + #if defined(LPTIM_OR_TIM1_ITR2_RMP) && defined(LPTIM_OR_TIM5_ITR1_RMP) && defined(LPTIM_OR_TIM9_ITR1_RMP) if ((Remap & LPTIM_REMAP_MASK) == LPTIM_REMAP_MASK) { @@ -2156,7 +2217,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) * @param htim TIM Hall Sensor handle * @retval HAL state */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) { return htim->State; } @@ -2171,7 +2232,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim) * @arg TIM_CHANNEL_3: TIM Channel 3 * @retval TIM Complementary channel state */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN) +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) { HAL_TIM_ChannelStateTypeDef channel_state; @@ -2191,7 +2252,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIMEx Private Functions +/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ @@ -2367,5 +2428,3 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim_ex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim_ex.h index 737fdc4e5e1..561e9bbe878 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim_ex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_tim_ex.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -75,9 +74,8 @@ typedef struct #if defined (TIM2) #if defined(TIM8) #define TIM_TIM2_TIM8_TRGO 0x00000000U /*!< TIM2 ITR1 is connected to TIM8 TRGO */ -#else -#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ #endif /* TIM8 */ +#define TIM_TIM2_ETH_PTP TIM_OR_ITR1_RMP_0 /*!< TIM2 ITR1 is connected to PTP trigger output */ #define TIM_TIM2_USBFS_SOF TIM_OR_ITR1_RMP_1 /*!< TIM2 ITR1 is connected to OTG FS SOF */ #define TIM_TIM2_USBHS_SOF (TIM_OR_ITR1_RMP_1 | TIM_OR_ITR1_RMP_0) /*!< TIM2 ITR1 is connected to OTG HS SOF */ #endif /* TIM2 */ @@ -206,7 +204,7 @@ typedef struct * @{ */ /* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); @@ -239,7 +237,8 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Chann HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -258,7 +257,8 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); +HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, + uint16_t Length); HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); /** * @} @@ -292,9 +292,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - TIM_MasterConfigTypeDef *sMasterConfig); + const TIM_MasterConfigTypeDef *sMasterConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); + const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); /** * @} @@ -317,8 +317,8 @@ void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); * @{ */ /* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); +HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); +HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); /** * @} */ @@ -329,7 +329,7 @@ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, /* End of exported functions -------------------------------------------------*/ /* Private functions----------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions +/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions * @{ */ void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); @@ -353,5 +353,3 @@ void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); #endif /* STM32F4xx_HAL_TIM_EX_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.c index 640ee1265b4..e2af5385ef1 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.c @@ -9,6 +9,18 @@ * + IO operation functions * + Peripheral Control functions * + Peripheral State and Errors functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -21,7 +33,7 @@ (##) Enable the USARTx interface clock. (##) UART pins configuration: (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins (TX as alternate function pull-up, RX as alternate function Input). + (+++) Configure the UART TX/RX pins as alternate function pull-up. (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() and HAL_UART_Receive_IT() APIs): (+++) Configure the USARTx interrupt priority. @@ -72,8 +84,8 @@ allows the user to configure dynamically the driver callbacks. [..] - Use Function @ref HAL_UART_RegisterCallback() to register a user callback. - Function @ref HAL_UART_RegisterCallback() allows to register following callbacks: + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. (+) TxCpltCallback : Tx Complete Callback. (+) RxHalfCpltCallback : Rx Half Complete Callback. @@ -88,9 +100,9 @@ and a pointer to the user callback function. [..] - Use function @ref HAL_UART_UnRegisterCallback() to reset a callback to the default + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default weak (surcharged) function. - @ref HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, and the Callback ID. This function allows to reset following callbacks: (+) TxHalfCpltCallback : Tx Half Complete Callback. @@ -106,16 +118,16 @@ [..] For specific callback RxEventCallback, use dedicated registration/reset functions: - respectively @ref HAL_UART_RegisterRxEventCallback() , @ref HAL_UART_UnRegisterRxEventCallback(). + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). [..] - By default, after the @ref HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET all callbacks are set to the corresponding weak (surcharged) functions: - examples @ref HAL_UART_TxCpltCallback(), @ref HAL_UART_RxHalfCpltCallback(). + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak (surcharged) functions in the @ref HAL_UART_Init() - and @ref HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the @ref HAL_UART_Init() and @ref HAL_UART_DeInit() + reset to the legacy weak (surcharged) functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() keep and use the user MspInit/MspDeInit callbacks (registered beforehand). [..] @@ -124,8 +136,8 @@ in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. In that case first register the MspInit/MspDeInit user callbacks - using @ref HAL_UART_RegisterCallback() before calling @ref HAL_UART_DeInit() - or @ref HAL_UART_Init() function. + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. [..] When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or @@ -240,17 +252,6 @@ | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+ ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -299,7 +300,8 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); static void UART_SetConfig(UART_HandleTypeDef *huart); /** @@ -418,6 +420,7 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -487,6 +490,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -567,6 +571,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -650,6 +655,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; return HAL_OK; } @@ -692,6 +698,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_RESET; huart->RxState = HAL_UART_STATE_RESET; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Process Unlock */ __HAL_UNLOCK(huart); @@ -749,7 +756,8 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) * @param pCallback pointer to the Callback function * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -1130,10 +1138,10 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; uint32_t tickstart = 0U; /* Check that a Tx process is not already ongoing */ @@ -1144,9 +1152,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; @@ -1160,7 +1165,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; + pdata16bits = (const uint16_t *) pData; } else { @@ -1168,9 +1173,6 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u pdata16bits = NULL; } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - while (huart->TxXferCount > 0U) { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) @@ -1232,9 +1234,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; @@ -1257,9 +1256,6 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui pdata16bits = NULL; } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - /* Check the remain data to be received */ while (huart->RxXferCount > 0U) { @@ -1309,7 +1305,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1319,9 +1315,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1329,9 +1322,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData huart->ErrorCode = HAL_UART_ERROR_NONE; huart->gState = HAL_UART_STATE_BUSY_TX; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - /* Enable the UART Transmit data register empty Interrupt */ __HAL_UART_ENABLE_IT(huart, UART_IT_TXE); @@ -1364,13 +1354,10 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - return(UART_Start_Receive_IT(huart, pData, Size)); + return (UART_Start_Receive_IT(huart, pData, Size)); } else { @@ -1389,9 +1376,9 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, * @param Size Amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) { - uint32_t *tmp; + const uint32_t *tmp; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) @@ -1401,9 +1388,6 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - huart->pTxBuffPtr = pData; huart->TxXferSize = Size; huart->TxXferCount = Size; @@ -1424,18 +1408,15 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat huart->hdmatx->XferAbortCallback = NULL; /* Enable the UART transmit DMA stream */ - tmp = (uint32_t *)&pData; - HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); + tmp = (const uint32_t *)&pData; + HAL_DMA_Start_IT(huart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&huart->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); - /* Process Unlocked */ - __HAL_UNLOCK(huart); - /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); return HAL_OK; } @@ -1467,13 +1448,10 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData return HAL_ERROR; } - /* Process Locked */ - __HAL_LOCK(huart); - /* Set Reception type to Standard reception */ huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - return(UART_Start_Receive_DMA(huart, pData, Size)); + return (UART_Start_Receive_DMA(huart, pData, Size)); } else { @@ -1491,30 +1469,24 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) { uint32_t dmarequest = 0x00U; - /* Process Locked */ - __HAL_LOCK(huart); - dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) { /* Disable the UART DMA Tx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); } dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the UART DMA Rx request */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -1526,13 +1498,11 @@ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) { - /* Process Locked */ - __HAL_LOCK(huart); if (huart->gState == HAL_UART_STATE_BUSY_TX) { /* Enable the UART DMA Tx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); } if (huart->RxState == HAL_UART_STATE_BUSY_RX) @@ -1541,16 +1511,16 @@ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) __HAL_UART_CLEAR_OREFLAG(huart); /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the UART DMA Rx request */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); } - /* Process Unlocked */ - __HAL_UNLOCK(huart); - return HAL_OK; } @@ -1573,7 +1543,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT); if ((huart->gState == HAL_UART_STATE_BUSY_TX) && dmarequest) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx stream */ if (huart->hdmatx != NULL) @@ -1587,7 +1557,7 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) dmarequest = HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR); if ((huart->RxState == HAL_UART_STATE_BUSY_RX) && dmarequest) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) @@ -1615,7 +1585,8 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). * @retval HAL status */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout) +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) { uint8_t *pdata8bits; uint16_t *pdata16bits; @@ -1629,11 +1600,10 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p return HAL_ERROR; } - __HAL_LOCK(huart); - huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); @@ -1653,8 +1623,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p pdata16bits = NULL; } - __HAL_UNLOCK(huart); - /* Initialize output number of received elements */ *RxLen = 0U; @@ -1671,6 +1639,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p /* If Set, and data has already been received, this means Idle Event is valid : End reception */ if (*RxLen > 0U) { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; huart->RxState = HAL_UART_STATE_READY; return HAL_OK; @@ -1687,14 +1656,14 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p } else { - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); - } + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) || ((huart->Init.WordLength == UART_WORDLENGTH_8B) && (huart->Init.Parity == UART_PARITY_NONE))) + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF); + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F); + } pdata8bits++; } @@ -1753,10 +1722,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_IT(huart, pData, Size); @@ -1766,7 +1734,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_IDLEFLAG(huart); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { @@ -1814,10 +1782,9 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ return HAL_ERROR; } - __HAL_LOCK(huart); - /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; status = UART_Start_Receive_DMA(huart, pData, Size); @@ -1827,7 +1794,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { __HAL_UART_CLEAR_IDLEFLAG(huart); - SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } else { @@ -1847,6 +1814,36 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ } } +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value : + * In Interrupt Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one) + * In DMA Mode : + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of + * received data is lower than expected one). + * In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (returned value will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return(huart->RxEventType); +} + /** * @brief Abort ongoing transfers (blocking mode). * @param huart UART handle. @@ -1858,23 +1855,23 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx stream: use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1899,7 +1896,7 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream: use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -1947,16 +1944,16 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -1998,23 +1995,23 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -2059,19 +2056,19 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) { uint32_t AbortCplt = 0x01U; /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised @@ -2109,7 +2106,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { /* Disable DMA Tx at UART level */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx stream : use non blocking DMA Abort API (callback) */ if (huart->hdmatx != NULL) @@ -2132,7 +2129,7 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream : use non blocking DMA Abort API (callback) */ if (huart->hdmarx != NULL) @@ -2194,16 +2191,16 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); /* Disable the UART DMA Tx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Abort the UART DMA Tx stream : use blocking DMA Abort API (no callback) */ if (huart->hdmatx != NULL) @@ -2271,23 +2268,23 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); } /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream : use blocking DMA Abort API (no callback) */ if (huart->hdmarx != NULL) @@ -2371,7 +2368,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* If some errors occur */ - if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) + if ((errorflags != RESET) && (((cr3its & USART_CR3_EIE) != RESET) + || ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE)) != RESET))) { /* UART parity error interrupt occurred ----------------------------------*/ if (((isrflags & USART_SR_PE) != RESET) && ((cr1its & USART_CR1_PEIE) != RESET)) @@ -2392,7 +2390,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) } /* UART Over-Run interrupt occurred --------------------------------------*/ - if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) || ((cr3its & USART_CR3_EIE) != RESET))) + if (((isrflags & USART_SR_ORE) != RESET) && (((cr1its & USART_CR1_RXNEIE) != RESET) + || ((cr3its & USART_CR3_EIE) != RESET))) { huart->ErrorCode |= HAL_UART_ERROR_ORE; } @@ -2419,7 +2418,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Disable the UART DMA Rx request if enabled */ if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* Abort the UART DMA Rx stream */ if (huart->hdmarx != NULL) @@ -2477,9 +2476,9 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Check current reception Mode : If Reception till IDLE event has been selected : */ - if ( (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - &&((isrflags & USART_SR_IDLE) != 0U) - &&((cr1its & USART_SR_IDLE) != 0U)) + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_SR_IDLE) != 0U) + && ((cr1its & USART_SR_IDLE) != 0U)) { __HAL_UART_CLEAR_IDLEFLAG(huart); @@ -2491,8 +2490,8 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) (DMA cplt callback will be called). Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - if ( (nb_remaining_rx_data > 0U) - &&(nb_remaining_rx_data < huart->RxXferSize)) + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) { /* Reception is not complete */ huart->RxXferCount = nb_remaining_rx_data; @@ -2501,29 +2500,34 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) if (huart->hdmarx->Init.Mode != DMA_CIRCULAR) { /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); /* Last bytes received, so no need as the abort is immediate */ (void)HAL_DMA_Abort(huart->hdmarx); } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#endif +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; } @@ -2533,27 +2537,32 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* Check received length : If all expected data are received, do nothing. Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - if ( (huart->RxXferCount > 0U) - &&(nb_rx_data > 0U) ) + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) { /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx complete callback*/ huart->RxEventCallback(huart, nb_rx_data); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, nb_rx_data); -#endif +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } return; } @@ -2752,7 +2761,7 @@ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Send break characters */ - SET_BIT(huart->Instance->CR1, USART_CR1_SBK); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_SBK); huart->gState = HAL_UART_STATE_READY; @@ -2779,9 +2788,10 @@ HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Enable the USART mute mode by setting the RWU bit in the CR1 register */ - SET_BIT(huart->Instance->CR1, USART_CR1_RWU); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RWU); huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -2806,9 +2816,10 @@ HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart) huart->gState = HAL_UART_STATE_BUSY; /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RWU); huart->gState = HAL_UART_STATE_READY; + huart->RxEventType = HAL_UART_RXEVENT_TC; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -2914,7 +2925,7 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) * the configuration information for the specified UART module. * @retval HAL state */ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) { uint32_t temp1 = 0x00U, temp2 = 0x00U; temp1 = huart->gState; @@ -2929,7 +2940,7 @@ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) * the configuration information for the specified UART. * @retval UART Error Code */ -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) { return huart->ErrorCode; } @@ -2984,10 +2995,10 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* Disable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); /* Enable the UART Transmit Complete Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); } /* DMA Circular mode */ @@ -3031,18 +3042,19 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* DMA Normal mode*/ if ((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) { huart->RxXferCount = 0U; /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Disable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; @@ -3050,14 +3062,18 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } } + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { + { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, huart->RxXferSize); @@ -3089,16 +3105,20 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize/2U); + huart->RxEventCallback(huart, huart->RxXferSize / 2U); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize/2U); + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3152,16 +3172,18 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles UART Communication Timeout. + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param huart Pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @param Flag specifies the UART flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Tickstart Tick start value * @param Timeout Timeout duration * @retval HAL status */ -static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) @@ -3172,8 +3194,8 @@ static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_TXEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); huart->gState = HAL_UART_STATE_READY; huart->RxState = HAL_UART_STATE_READY; @@ -3208,11 +3230,11 @@ HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pDat huart->ErrorCode = HAL_UART_ERROR_NONE; huart->RxState = HAL_UART_STATE_BUSY_RX; - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_PE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ __HAL_UART_ENABLE_IT(huart, UART_IT_ERR); @@ -3263,18 +3285,18 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa /* Clear the Overrun flag just before enabling the DMA Rx request: can be mandatory for the second transfer */ __HAL_UART_CLEAR_OREFLAG(huart); - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - /* Enable the UART Parity Error Interrupt */ - SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + if (huart->Init.Parity != UART_PARITY_NONE) + { + /* Enable the UART Parity Error Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); return HAL_OK; } @@ -3287,7 +3309,7 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { /* Disable TXEIE and TCIE interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE | USART_CR1_TCIE)); /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; @@ -3301,13 +3323,13 @@ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); - CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); } /* At end of Rx process, restore huart->RxState to Ready */ @@ -3494,14 +3516,14 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) { - uint16_t *tmp; + const uint16_t *tmp; /* Check that a Tx process is ongoing */ if (huart->gState == HAL_UART_STATE_BUSY_TX) { if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) { - tmp = (uint16_t *) huart->pTxBuffPtr; + tmp = (const uint16_t *) huart->pTxBuffPtr; huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); huart->pTxBuffPtr += 2U; } @@ -3512,7 +3534,7 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) if (--huart->TxXferCount == 0U) { - /* Disable the UART Transmit Complete Interrupt */ + /* Disable the UART Transmit Data Register Empty Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); /* Enable the UART Transmit Complete Interrupt */ @@ -3602,12 +3624,25 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) /* Rx process is completed, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + /* Check current reception Mode : If Reception till IDLE event has been selected : */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + /* Disable IDLE interrupt */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_IDLEFLAG(huart); + } #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ @@ -3615,20 +3650,20 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else { - /* Standard reception API called */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); #else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + return HAL_OK; } return HAL_OK; @@ -3722,4 +3757,3 @@ static void UART_SetConfig(UART_HandleTypeDef *huart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.h index 24a41147bb8..e6ce82fca7d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_uart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -138,12 +137,23 @@ typedef enum /** * @brief HAL UART Reception type definition * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * It is expected to admit following values : + * This parameter can be a value of @ref UART_Reception_Type_Values : * HAL_UART_RECEPTION_STANDARD = 0x00U, * HAL_UART_RECEPTION_TOIDLE = 0x01U, */ typedef uint32_t HAL_UART_RxTypeTypeDef; +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + /** * @brief UART handle Structure definition */ @@ -153,7 +163,7 @@ typedef struct __UART_HandleTypeDef UART_InitTypeDef Init; /*!< UART communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ uint16_t TxXferSize; /*!< UART Tx Transfer size */ @@ -167,6 +177,8 @@ typedef struct __UART_HandleTypeDef __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ @@ -382,7 +394,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @} */ -/** @defgroup UART_RECEPTION_TYPE_Values UART Reception type values +/** @defgroup UART_Reception_Type_Values UART Reception type values * @{ */ #define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ @@ -391,6 +403,16 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @} */ +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) +/** + * @} + */ + /** * @} */ @@ -573,7 +595,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == UART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == UART_CR2_REG_INDEX)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK)) /** @brief Enable CTS flow control * @note This macro allows to enable CTS hardware flow control for a given UART instance, @@ -591,7 +613,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart */ #define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ } while(0U) @@ -611,7 +633,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart */ #define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ } while(0U) @@ -631,7 +653,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart */ #define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ do{ \ - SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ } while(0U) @@ -651,7 +673,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart */ #define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ do{ \ - CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ } while(0U) @@ -665,7 +687,8 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart * @param __HANDLE__ specifies the UART Handle. * @retval None */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) /** @brief Enable UART * @param __HANDLE__ specifies the UART Handle. @@ -702,7 +725,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); @@ -718,20 +742,23 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); */ /* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); + /* Transfer Abort functions */ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); @@ -773,8 +800,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); * @{ */ /* Peripheral State functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); /** * @} */ @@ -832,7 +859,8 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); #define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(4U*((uint64_t)(_BAUD_))))) #define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_) (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U) + 50U) / 100U) +#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100U)) * 16U)\ + + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0FU) */ #define UART_BRR_SAMPLING16(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4U) + \ @@ -841,7 +869,8 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); #define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((uint32_t)((((uint64_t)(_PCLK_))*25U)/(2U*((uint64_t)(_BAUD_))))) #define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_) (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100U) -#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U) + 50U) / 100U) +#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_) ((((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100U)) * 8U)\ + + 50U) / 100U) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ #define UART_BRR_SAMPLING8(_PCLK_, _BAUD_) ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4U) + \ @@ -878,4 +907,3 @@ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pDa #endif /* __STM32F4xx_HAL_UART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_usart.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_usart.c index 41c1fb792f7..b6df8e7fc72 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_usart.c @@ -9,6 +9,18 @@ * + Initialization and de-initialization functions * + IO operation functions * + Peripheral Control functions + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -182,17 +194,6 @@ | 1 | 1 | | SB | 8 bit data | PB | STB | | +-------------------------------------------------------------+ ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -243,7 +244,8 @@ static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma); static void USART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout); +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); /** * @} */ @@ -440,7 +442,8 @@ __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart) * @param pCallback pointer to the Callback function * @retval HAL status + */ -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback) +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback) { HAL_StatusTypeDef status = HAL_OK; @@ -744,10 +747,10 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ * @param Timeout Timeout duration. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout) { - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint32_t tickstart; if (husart->State == HAL_USART_STATE_READY) @@ -773,7 +776,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; } else { @@ -934,12 +937,13 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint8_t *prxdata8bits; uint16_t *prxdata16bits; - uint8_t *ptxdata8bits; - uint16_t *ptxdata16bits; + const uint8_t *ptxdata8bits; + const uint16_t *ptxdata16bits; uint16_t rxdatacount; uint32_t tickstart; @@ -979,7 +983,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t { prxdata8bits = NULL; ptxdata8bits = NULL; - ptxdata16bits = (uint16_t *) pTxData; + ptxdata16bits = (const uint16_t *) pTxData; prxdata16bits = (uint16_t *) pRxData; } else @@ -1011,14 +1015,14 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t else { husart->Instance->DR = (uint8_t)(*ptxdata8bits & (uint8_t)0xFF); - ptxdata8bits++; + ptxdata8bits++; } husart->TxXferCount--; } if (husart->RxXferCount > 0U) - { + { /* Wait for RXNE Flag */ if (USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) { @@ -1073,7 +1077,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t * @retval HAL status * @note The USART errors are not managed to avoid the overrun error. */ -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) { @@ -1147,8 +1151,16 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error and Data Register not empty Interrupts */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error and Data Register not empty Interrupts */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE); + } + else + { + /* Enable the USART Data Register not empty Interrupts */ + SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1176,7 +1188,8 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx * @param Size Amount of data elements (u8 or u16) to be sent (same amount to be received). * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { if (husart->State == HAL_USART_STATE_READY) { @@ -1203,8 +1216,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint /* Enable the USART Data Register not empty Interrupt */ SET_BIT(husart->Instance->CR1, USART_CR1_RXNEIE); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1231,9 +1247,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint * @param Size Amount of data elements (u8 or u16) to be sent. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size) { - uint32_t *tmp; + const uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) { @@ -1264,8 +1280,8 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p husart->hdmatx->XferAbortCallback = NULL; /* Enable the USART transmit DMA stream */ - tmp = (uint32_t *)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size); + tmp = (const uint32_t *)&pTxData; + HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC); @@ -1358,8 +1374,11 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1393,9 +1412,10 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR * @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit. * @retval HAL status */ -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { - uint32_t *tmp; + const uint32_t *tmp; if (husart->State == HAL_USART_STATE_READY) { @@ -1437,11 +1457,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Enable the USART receive DMA stream */ tmp = (uint32_t *)&pRxData; - HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t *)tmp, Size); + HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(const uint32_t *)tmp, Size); /* Enable the USART transmit DMA stream */ - tmp = (uint32_t *)&pTxData; - HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size); + tmp = (const uint32_t *)&pTxData; + HAL_DMA_Start_IT(husart->hdmatx, *(const uint32_t *)tmp, (uint32_t)&husart->Instance->DR, Size); /* Clear the TC flag in the SR register by writing 0 to it */ __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC); @@ -1452,8 +1472,11 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Process Unlocked */ __HAL_UNLOCK(husart); - /* Enable the USART Parity Error Interrupt */ - SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + if (husart->Init.Parity != USART_PARITY_NONE) + { + /* Enable the USART Parity Error Interrupt */ + SET_BIT(husart->Instance->CR1, USART_CR1_PEIE); + } /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */ SET_BIT(husart->Instance->CR3, USART_CR3_EIE); @@ -1576,7 +1599,7 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) * - Set handle State to READY * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) { /* Disable TXEIE, TCIE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ @@ -1642,7 +1665,7 @@ HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart) * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * considered as completed only when user abort complete callback is executed (not when exiting function). * @retval HAL status -*/ + */ HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart) { uint32_t AbortCplt = 0x01U; @@ -2052,7 +2075,7 @@ __weak void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart) * the configuration information for the specified USART module. * @retval HAL state */ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart) { return husart->State; } @@ -2063,7 +2086,7 @@ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart) * the configuration information for the specified USART. * @retval USART Error Code */ -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart) +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart) { return husart->ErrorCode; } @@ -2286,16 +2309,18 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) } /** - * @brief This function handles USART Communication Timeout. + * @brief This function handles USART Communication Timeout. It waits + * until a flag is no longer in the specified status. * @param husart Pointer to a USART_HandleTypeDef structure that contains * the configuration information for the specified USART module. * @param Flag specifies the USART flag to check. - * @param Status The new Flag status (SET or RESET). + * @param Status The actual Flag status (SET or RESET). * @param Tickstart Tick start value. * @param Timeout Timeout duration. * @retval HAL status */ -static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) +static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) { /* Wait until flag is set */ while ((__HAL_USART_GET_FLAG(husart, Flag) ? SET : RESET) == Status) @@ -2474,13 +2499,13 @@ static void USART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) { - uint16_t *tmp; + const uint16_t *tmp; if (husart->State == HAL_USART_STATE_BUSY_TX) { if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - tmp = (uint16_t *) husart->pTxBuffPtr; + tmp = (const uint16_t *) husart->pTxBuffPtr; husart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF); husart->pTxBuffPtr += 2U; } @@ -2616,8 +2641,8 @@ static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart) */ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { - uint8_t *pdata8bits; - uint16_t *pdata16bits; + const uint16_t *pdatatx16bits; + uint16_t *pdatarx16bits; if (husart->State == HAL_USART_STATE_BUSY_TX_RX) { @@ -2627,9 +2652,8 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - pdata8bits = NULL; - pdata16bits = (uint16_t *) husart->pTxBuffPtr; - husart->Instance->DR = (uint16_t)(*pdata16bits & (uint16_t)0x01FF); + pdatatx16bits = (const uint16_t *) husart->pTxBuffPtr; + husart->Instance->DR = (uint16_t)(*pdatatx16bits & (uint16_t)0x01FF); husart->pTxBuffPtr += 2U; } else @@ -2653,22 +2677,19 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart) { if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { - pdata8bits = NULL; - pdata16bits = (uint16_t *) husart->pRxBuffPtr; - *pdata16bits = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); - husart->pRxBuffPtr += 2U; + pdatarx16bits = (uint16_t *) husart->pRxBuffPtr; + *pdatarx16bits = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF); + husart->pRxBuffPtr += 2U; } else { - pdata8bits = (uint8_t *) husart->pRxBuffPtr; - pdata16bits = NULL; if ((husart->Init.WordLength == USART_WORDLENGTH_9B) || ((husart->Init.WordLength == USART_WORDLENGTH_8B) && (husart->Init.Parity == USART_PARITY_NONE))) { - *pdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF); } else { - *pdata8bits = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); + *husart->pRxBuffPtr = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F); } husart->pRxBuffPtr += 1U; } @@ -2815,4 +2836,3 @@ static void USART_SetConfig(USART_HandleTypeDef *husart) * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_usart.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_usart.h index 8664355c664..e4bfcf3796a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_usart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -102,7 +101,7 @@ typedef struct __USART_HandleTypeDef USART_InitTypeDef Init; /*!< Usart communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to Usart Tx transfer Buffer */ uint16_t TxXferSize; /*!< Usart Tx Transfer size */ @@ -430,10 +429,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \ (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & USART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK))) + ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK))) #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((((__INTERRUPT__) >> 28U) == USART_CR1_REG_INDEX)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ (((__INTERRUPT__) >> 28U) == USART_CR2_REG_INDEX)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) + ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK))) /** @brief Checks whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -449,7 +448,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == USART_CR1_REG_INDEX)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28U) == USART_CR2_REG_INDEX)? \ - (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK)) + (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK)) /** @brief Macro to enable the USART's one bit sample method * @param __HANDLE__ specifies the USART Handle. @@ -461,7 +460,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @param __HANDLE__ specifies the USART Handle. * @retval None */ -#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\ + &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) /** @brief Enable USART * @param __HANDLE__ specifies the USART Handle. @@ -496,7 +496,8 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, + pUSART_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ @@ -508,15 +509,18 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ * @{ */ /* IO operation functions *******************************************************/ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); +HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size); HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); +HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size); HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart); @@ -540,8 +544,8 @@ void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart); * @{ */ /* Peripheral State functions ************************************************/ -HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); -uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); +HAL_USART_StateTypeDef HAL_USART_GetState(const USART_HandleTypeDef *husart); +uint32_t HAL_USART_GetError(const USART_HandleTypeDef *husart); /** * @} */ @@ -559,7 +563,7 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); * */ #define USART_IT_MASK ((uint32_t) USART_CR1_PEIE | USART_CR1_TXEIE | USART_CR1_TCIE | USART_CR1_RXNEIE | \ - USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) + USART_CR1_IDLEIE | USART_CR2_LBDIE | USART_CR3_CTSIE | USART_CR3_EIE ) #define USART_CR1_REG_INDEX 1U #define USART_CR2_REG_INDEX 2U @@ -613,8 +617,8 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07U) */ #define USART_BRR(_PCLK_, _BAUD_) (((USART_DIVMANT((_PCLK_), (_BAUD_)) << 4U) + \ - ((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ - (USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x07U)) + ((USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF8U) << 1U)) + \ + (USART_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x07U)) /** * @} */ @@ -642,4 +646,3 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); #endif /* __STM32F4xx_HAL_USART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c index e853ba2d113..216ea2b92c5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.c @@ -7,6 +7,17 @@ * functionalities of the Window Watchdog (WWDG) peripheral: * + Initialization and Configuration functions * + IO operation functions + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### WWDG Specific features ##### @@ -55,7 +66,7 @@ (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). (+) Configure the WWDG prescaler, refresh window value, counter value and early interrupt status using HAL_WWDG_Init() function. This will automatically - enable WWDG and start its downcounter. Time reference can be taken from + enable WWDG and start its downcounter. Time reference can be taken from function exit. Care must be taken to provide a counter value greater than 0x40 to prevent generation of immediate reset. (+) If the Early Wakeup Interrupt (EWI) feature is enabled, an interrupt is @@ -112,17 +123,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -418,5 +418,3 @@ __weak void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.h index 017b34df4bf..ab8b1ead410 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_hal_wwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -184,7 +183,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt @@ -297,5 +296,3 @@ void HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg); #endif #endif /* STM32F4xx_HAL_WWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.c index c53c1478965..cdb750fe6f5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -23,9 +22,9 @@ #include "stm32f4xx_ll_bus.h" #ifdef USE_FULL_ASSERT - #include "stm32_assert.h" +#include "stm32_assert.h" #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /** @addtogroup STM32F4xx_LL_Driver @@ -291,14 +290,14 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) { /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - + /* Force reset of ADC clock (core clock) */ LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC); - + /* Release reset of ADC clock (core clock) */ LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC); - + return SUCCESS; } @@ -320,14 +319,14 @@ ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); - + #if defined(ADC_MULTIMODE_SUPPORT) assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode)); - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer)); assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay)); @@ -339,7 +338,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* On this STM32 series, setting of these features is conditioned to */ /* ADC state: */ /* All ADC instances of the ADC common group must be disabled. */ - if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) + if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - common to several ADC */ @@ -351,16 +350,16 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* - Set ADC multimode DMA transfer */ /* - Set ADC multimode: delay between 2 sampling phases */ #if defined(ADC_MULTIMODE_SUPPORT) - if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) + if (ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT) { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_ADCPRE + ADC_CCR_ADCPRE | ADC_CCR_MULTI | ADC_CCR_DMA | ADC_CCR_DDS | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | ADC_CommonInitStruct->Multimode | ADC_CommonInitStruct->MultiDMATransfer | ADC_CommonInitStruct->MultiTwoSamplingDelay @@ -369,13 +368,13 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni else { MODIFY_REG(ADCxy_COMMON->CCR, - ADC_CCR_ADCPRE + ADC_CCR_ADCPRE | ADC_CCR_MULTI | ADC_CCR_DMA | ADC_CCR_DDS | ADC_CCR_DELAY - , - ADC_CommonInitStruct->CommonClock + , + ADC_CommonInitStruct->CommonClock | LL_ADC_MULTI_INDEPENDENT ); } @@ -389,7 +388,7 @@ ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonIni /* the same ADC common instance are not disabled. */ status = ERROR; } - + return status; } @@ -405,11 +404,11 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) /* Set fields of ADC common */ /* (all ADC instances belonging to the same ADC common instance) */ ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; - + #if defined(ADC_MULTIMODE_SUPPORT) /* Set fields of ADC multimode */ ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT; - ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; + ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC; ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES; #endif /* ADC_MULTIMODE_SUPPORT */ } @@ -427,76 +426,76 @@ void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - + /* Disable ADC instance if not already disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 1UL) + if (LL_ADC_IsEnabled(ADCx) == 1UL) { /* Set ADC group regular trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - + /* Set ADC group injected trigger source to SW start to ensure to not */ /* have an external trigger event occurring during the conversion stop */ /* ADC disable process. */ LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); - + /* Disable the ADC instance */ LL_ADC_Disable(ADCx); } - + /* Check whether ADC state is compliant with expected state */ /* (hardware requirements of bits state to reset registers below) */ - if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL) + if (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0UL) { /* ========== Reset ADC registers ========== */ /* Reset register SR */ CLEAR_BIT(ADCx->SR, - ( LL_ADC_FLAG_STRT + (LL_ADC_FLAG_STRT | LL_ADC_FLAG_JSTRT | LL_ADC_FLAG_EOCS | LL_ADC_FLAG_OVR | LL_ADC_FLAG_JEOS - | LL_ADC_FLAG_AWD1 ) + | LL_ADC_FLAG_AWD1) ); - + /* Reset register CR1 */ CLEAR_BIT(ADCx->CR1, - ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN + (ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE - | ADC_CR1_AWDCH ) + | ADC_CR1_AWDCH) ); - + /* Reset register CR2 */ CLEAR_BIT(ADCx->CR2, - ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL + (ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DMA - | ADC_CR2_CONT | ADC_CR2_ADON ) + | ADC_CR2_CONT | ADC_CR2_ADON) ); - + /* Reset register SMPR1 */ CLEAR_BIT(ADCx->SMPR1, - ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 + (ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10) ); - + /* Reset register SMPR2 */ CLEAR_BIT(ADCx->SMPR2, - ( ADC_SMPR2_SMP9 + (ADC_SMPR2_SMP9 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0) ); - + /* Reset register JOFR1 */ CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); /* Reset register JOFR2 */ @@ -505,43 +504,48 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); /* Reset register JOFR4 */ CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); - + /* Reset register HTR */ SET_BIT(ADCx->HTR, ADC_HTR_HT); /* Reset register LTR */ CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); - + /* Reset register SQR1 */ CLEAR_BIT(ADCx->SQR1, - ( ADC_SQR1_L + (ADC_SQR1_L | ADC_SQR1_SQ16 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13) ); - + /* Reset register SQR2 */ CLEAR_BIT(ADCx->SQR2, - ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 + (ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7) ); - - + + /* Reset register SQR3 */ + CLEAR_BIT(ADCx->SQR3, + (ADC_SQR3_SQ6 | ADC_SQR3_SQ5 | ADC_SQR3_SQ4 + | ADC_SQR3_SQ3 | ADC_SQR3_SQ2 | ADC_SQR3_SQ1) + ); + /* Reset register JSQR */ CLEAR_BIT(ADCx->JSQR, - ( ADC_JSQR_JL + (ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 - | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) + | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1) ); - + /* Reset register DR */ /* bits in access mode read only, no direct reset applicable */ - + /* Reset registers JDR1, JDR2, JDR3, JDR4 */ /* bits in access mode read only, no direct reset applicable */ - + /* Reset register CCR */ CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); } - + return status; } @@ -581,34 +585,34 @@ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - + assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC instance */ /* - Set ADC data resolution */ /* - Set ADC conversion data alignment */ MODIFY_REG(ADCx->CR1, - ADC_CR1_RES + ADC_CR1_RES | ADC_CR1_SCAN - , - ADC_InitStruct->Resolution + , + ADC_InitStruct->Resolution | ADC_InitStruct->SequencersScanMode ); - + MODIFY_REG(ADCx->CR2, - ADC_CR2_ALIGN - , - ADC_InitStruct->DataAlignment + ADC_CR2_ALIGN + , + ADC_InitStruct->DataAlignment ); } @@ -632,13 +636,13 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) /* Set fields of ADC instance */ ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; - + /* Enable scan mode to have a generic behavior with ADC of other */ /* STM32 families, without this setting available: */ /* ADC group regular sequencer and ADC group injected sequencer depend */ /* only of their own configuration. */ ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; - + } /** @@ -676,26 +680,26 @@ void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); } assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); - + /* ADC group regular continuous mode and discontinuous mode */ /* can not be enabled simultenaeously */ assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group regular */ @@ -708,33 +712,33 @@ ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_I /* Note: On this STM32 series, ADC trigger edge is set when starting */ /* ADC conversion. */ /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ - if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CR1, - ADC_CR1_DISCEN + ADC_CR1_DISCEN | ADC_CR1_DISCNUM - , - ADC_REG_InitStruct->SequencerDiscont + , + ADC_REG_InitStruct->SequencerDiscont ); } else { MODIFY_REG(ADCx->CR1, - ADC_CR1_DISCEN + ADC_CR1_DISCEN | ADC_CR1_DISCNUM - , - LL_ADC_REG_SEQ_DISCONT_DISABLE + , + LL_ADC_REG_SEQ_DISCONT_DISABLE ); } - + MODIFY_REG(ADCx->CR2, - ADC_CR2_EXTSEL + ADC_CR2_EXTSEL | ADC_CR2_EXTEN | ADC_CR2_CONT | ADC_CR2_DMA | ADC_CR2_DDS - , - (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) + , + (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) | ADC_REG_InitStruct->ContinuousMode | ADC_REG_InitStruct->DMATransfer ); @@ -811,20 +815,20 @@ void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) { ErrorStatus status = SUCCESS; - + /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(ADCx)); assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) { assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); } assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); - + /* Note: Hardware constraint (refer to description of this function): */ /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0UL) + if (LL_ADC_IsEnabled(ADCx) == 0UL) { /* Configuration of ADC hierarchical scope: */ /* - ADC group injected */ @@ -836,34 +840,34 @@ ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_I /* Note: On this STM32 series, ADC trigger edge is set when starting */ /* ADC conversion. */ /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ - if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) + if (ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) { MODIFY_REG(ADCx->CR1, - ADC_CR1_JDISCEN + ADC_CR1_JDISCEN | ADC_CR1_JAUTO - , - ADC_INJ_InitStruct->SequencerDiscont + , + ADC_INJ_InitStruct->SequencerDiscont | ADC_INJ_InitStruct->TrigAuto ); } else { MODIFY_REG(ADCx->CR1, - ADC_CR1_JDISCEN + ADC_CR1_JDISCEN | ADC_CR1_JAUTO - , - LL_ADC_REG_SEQ_DISCONT_DISABLE + , + LL_ADC_REG_SEQ_DISCONT_DISABLE | ADC_INJ_InitStruct->TrigAuto ); } - + MODIFY_REG(ADCx->CR2, - ADC_CR2_JEXTSEL + ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN - , - (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) + , + (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) ); - + /* Note: Hardware constraint (refer to description of this function): */ /* Note: If ADC instance feature scan mode is disabled */ /* (refer to ADC instance initialization structure */ @@ -916,4 +920,3 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.h index 93489114209..43b4a1ed544 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_adc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -322,23 +321,23 @@ typedef struct { uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */ #if defined(ADC_MULTIMODE_SUPPORT) uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances). This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */ uint32_t MultiDMATransfer; /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA. This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */ uint32_t MultiTwoSamplingDelay; /*!< Set ADC multimode delay between 2 sampling phases. This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */ #endif /* ADC_MULTIMODE_SUPPORT */ @@ -368,17 +367,17 @@ typedef struct { uint32_t Resolution; /*!< Set ADC resolution. This parameter can be a value of @ref ADC_LL_EC_RESOLUTION - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ uint32_t DataAlignment; /*!< Set ADC conversion data alignment. This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ uint32_t SequencersScanMode; /*!< Set ADC scan selection. This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION - + This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */ } LL_ADC_InitTypeDef; @@ -408,31 +407,31 @@ typedef struct This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE @note On this STM32 series, setting of external trigger edge is performed using function @ref LL_ADC_REG_StartConversionExtTrig(). - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE @note This parameter has an effect only if group regular sequencer is enabled (scan length of 2 ranks or more). - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER - + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ } LL_ADC_REG_InitTypeDef; @@ -462,26 +461,26 @@ typedef struct This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE @note On this STM32 series, setting of external trigger edge is performed using function @ref LL_ADC_INJ_StartConversionExtTrig(). - + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group injected sequencer length. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode'). - + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE @note This parameter has an effect only if group injected sequencer is enabled (scan length of 2 ranks or more). - + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */ uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular. This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO - Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. - + Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger. + This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */ } LL_ADC_INJ_InitTypeDef; @@ -510,7 +509,7 @@ typedef struct #define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1 /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ #define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2 /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ #define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3 /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */ -#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */ +#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1 /*!< ADC flag ADC multimode master group regular overrun */ #define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2 /*!< ADC flag ADC multimode slave 1 group regular overrun */ #define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3 /*!< ADC flag ADC multimode slave 2 group regular overrun */ #define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1 /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 series, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */ @@ -685,8 +684,8 @@ typedef struct */ /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode -* @{ -*/ + * @{ + */ #define LL_ADC_REG_CONV_SINGLE 0x00000000UL /*!< ADC conversions are performed in single mode: one conversion per trigger */ #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ /** @@ -809,8 +808,8 @@ typedef struct */ /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode -* @{ -*/ + * @{ + */ #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */ #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */ /** @@ -1046,7 +1045,7 @@ typedef struct * above each literal definition. * @{ */ - + /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ /* not timeout values. */ /* Timeout values for ADC operations are dependent to device clock */ @@ -1146,7 +1145,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. * @retval Value between Min_Data=0 and Max_Data=18 @@ -1184,7 +1183,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n * (1) For ADC channel read back from ADC register, @@ -1244,7 +1243,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). @@ -1289,7 +1288,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. * @retval Returned value can be one of the following values: @@ -1334,7 +1333,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1. * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. @@ -1378,7 +1377,7 @@ typedef struct * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n * (1) For ADC channel read back from ADC register, @@ -1393,35 +1392,35 @@ typedef struct * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ @@ -1459,7 +1458,7 @@ typedef struct * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ @@ -1497,7 +1496,7 @@ typedef struct /** * @brief Helper macro to get the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is + * or low in function of ADC resolution, when ADC resolution is * different of 12 bits. * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). * Example, with a ADC resolution of 8 bits, to get the value of @@ -1606,7 +1605,7 @@ typedef struct /** * @brief Helper macro to convert the ADC conversion data from * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted + * @param __DATA__ ADC conversion data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -1855,7 +1854,7 @@ typedef struct * @param Register This parameter can be one of the following values: * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1) - * + * * (1) Available on devices with several ADC instances. * @retval ADC register address */ @@ -1863,25 +1862,28 @@ typedef struct __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { uint32_t data_reg_addr = 0UL; - + if (Register == LL_ADC_DMA_REG_REGULAR_DATA) { /* Retrieve address of register DR */ - data_reg_addr = (uint32_t)&(ADCx->DR); + data_reg_addr = (uint32_t) & (ADCx->DR); } else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */ { /* Retrieve address of register CDR */ - data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); + data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR); } - + return data_reg_addr; } #else __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) { + /* Prevent unused argument compilation warning */ + (void)Register; + /* Retrieve address of register DR */ - return (uint32_t)&(ADCx->DR); + return (uint32_t) & (ADCx->DR); } #endif @@ -2119,7 +2121,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) * external interrupt line). * @note On this STM32 series, setting of external trigger edge is performed * using function @ref LL_ADC_REG_StartConversionExtTrig(). - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource\n * CR2 EXTEN LL_ADC_REG_SetTriggerSource @@ -2146,11 +2148,11 @@ __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { -/* Note: On this STM32 series, ADC group regular external trigger edge */ -/* is used to perform a ADC conversion start. */ -/* This function does not set external trigger edge. */ -/* This feature is set using function */ -/* @ref LL_ADC_REG_StartConversionExtTrig(). */ + /* Note: On this STM32 series, ADC group regular external trigger edge */ + /* is used to perform a ADC conversion start. */ + /* This function does not set external trigger edge. */ + /* This feature is set using function */ + /* @ref LL_ADC_REG_StartConversionExtTrig(). */ MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL)); } @@ -2161,10 +2163,10 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @note To determine whether group regular trigger source is * internal (SW start) or external, without detail * of which peripheral is selected as external trigger, - * (equivalent to + * (equivalent to * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource\n * CR2 EXTEN LL_ADC_REG_GetTriggerSource @@ -2191,11 +2193,11 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) { uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN); - + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */ uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); - + /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */ /* to match with triggers literals definition. */ return ((TriggerSource @@ -2363,7 +2365,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) * @brief Set ADC group regular sequencer discontinuous mode: * sequence subdivided and scan conversions interrupted every selected * number of ranks. - * @note It is not possible to enable both ADC group regular + * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. * @note It is not possible to enable both ADC auto-injected mode * and ADC group regular sequencer discontinuous mode. @@ -2483,7 +2485,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. * @retval None @@ -2495,7 +2497,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); - + MODIFY_REG(*preg, ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK), (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); @@ -2578,7 +2580,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n * (1) For ADC channel read back from ADC register, @@ -2588,11 +2590,11 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK)); - - return (uint32_t) (READ_BIT(*preg, - ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) - >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) - ); + + return (uint32_t)(READ_BIT(*preg, + ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) + >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) + ); } /** @@ -2601,7 +2603,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * - single mode: one conversion per trigger * - continuous mode: after the first trigger, following * conversions launched successively automatically. - * @note It is not possible to enable both ADC group regular + * @note It is not possible to enable both ADC group regular * continuous mode and sequencer discontinuous mode. * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode * @param ADCx ADC instance @@ -2754,7 +2756,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) * external interrupt line). * @note On this STM32 series, setting of external trigger edge is performed * using function @ref LL_ADC_INJ_StartConversionExtTrig(). - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource\n * CR2 JEXTEN LL_ADC_INJ_SetTriggerSource @@ -2781,11 +2783,11 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx) */ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) { -/* Note: On this STM32 series, ADC group injected external trigger edge */ -/* is used to perform a ADC conversion start. */ -/* This function does not set external trigger edge. */ -/* This feature is set using function */ -/* @ref LL_ADC_INJ_StartConversionExtTrig(). */ + /* Note: On this STM32 series, ADC group injected external trigger edge */ + /* is used to perform a ADC conversion start. */ + /* This function does not set external trigger edge. */ + /* This feature is set using function */ + /* @ref LL_ADC_INJ_StartConversionExtTrig(). */ MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL)); } @@ -2796,10 +2798,10 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @note To determine whether group injected trigger source is * internal (SW start) or external, without detail * of which peripheral is selected as external trigger, - * (equivalent to + * (equivalent to * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)") * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer + * @note Availability of parameters of trigger sources from timer * depends on timers availability on the selected device. * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource\n * CR2 JEXTEN LL_ADC_INJ_GetTriggerSource @@ -2826,11 +2828,11 @@ __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx) { uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN); - + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */ uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL)); - + /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */ /* to match with triggers literals definition. */ return ((TriggerSource @@ -3000,7 +3002,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. * @retval None @@ -3012,7 +3014,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra /* Parameters "Rank" and "Channel" are used with masks because containing */ /* other bits reserved for other purpose. */ uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL; - + MODIFY_REG(ADCx->JSQR, ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))), (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))); @@ -3067,7 +3069,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n * (1) For ADC channel read back from ADC register, @@ -3077,7 +3079,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) { uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL; - + return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))) >> (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))) @@ -3088,18 +3090,18 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_ * @brief Set ADC group injected conversion trigger: * independent or from ADC group regular. * @note This mode can be used to extend number of data registers - * updated after one ADC conversion trigger and with data + * updated after one ADC conversion trigger and with data * permanently kept (not erased by successive conversions of scan of * ADC sequencer ranks), up to 5 data registers: * 1 data register on ADC group regular, 4 data registers - * on ADC group injected. + * on ADC group injected. * @note If ADC group injected injected trigger source is set to an * external trigger, this feature must be must be set to * independent trigger. - * ADC group injected automatic trigger is compliant only with - * group injected trigger source set to SW start, without any - * further action on ADC group injected conversion start or stop: - * in this case, ADC group injected is controlled only + * ADC group injected automatic trigger is compliant only with + * group injected trigger source set to SW start, without any + * further action on ADC group injected conversion start or stop: + * in this case, ADC group injected is controlled only * from ADC group regular. * @note It is not possible to enable both ADC group injected * auto-injected mode and sequencer discontinuous mode. @@ -3157,7 +3159,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx) __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); - + MODIFY_REG(*preg, ADC_JOFR1_JOFFSET1, OffsetLevel); @@ -3184,7 +3186,7 @@ __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK)); - + return (uint32_t)(READ_BIT(*preg, ADC_JOFR1_JOFFSET1) ); @@ -3260,7 +3262,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank) * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. * @param SamplingTime This parameter can be one of the following values: @@ -3281,7 +3283,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C /* Parameter "Channel" is used with masks because containing */ /* other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); - + MODIFY_REG(*preg, ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK), SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)); @@ -3338,7 +3340,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_CHANNEL_VREFINT (1) * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)(2) * @arg @ref LL_ADC_CHANNEL_VBAT (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. * @retval Returned value can be one of the following values: @@ -3354,7 +3356,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK)); - + return (uint32_t)(READ_BIT(*preg, ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)) >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK) @@ -3394,35 +3396,35 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ @@ -3460,7 +3462,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32 * @arg @ref LL_ADC_AWD_CH_VBAT_REG (1) * @arg @ref LL_ADC_AWD_CH_VBAT_INJ (1) * @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ (1) - * + * * (1) On STM32F4, parameter available only on ADC instance: ADC1.\n * (2) On devices STM32F42x and STM32F43x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. * @retval None @@ -3503,35 +3505,35 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ * @arg @ref LL_ADC_AWD_CHANNEL_10_REG * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ @@ -3591,7 +3593,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); - + MODIFY_REG(*preg, ADC_HTR_HT, AWDThresholdValue); @@ -3614,7 +3616,7 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow); - + return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT)); } @@ -3857,7 +3859,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADC /** * @brief Enable the selected ADC instance. - * @note On this STM32 series, after ADC enable, a delay for + * @note On this STM32 series, after ADC enable, a delay for * ADC internal analog stabilization is required before performing a * ADC conversion start. * Refer to device datasheet, parameter tSTAB. @@ -3907,9 +3909,9 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion - * start must be performed using function + * start must be performed using function * @ref LL_ADC_REG_StartConversionExtTrig(). - * (if external trigger edge would have been set during ADC other + * (if external trigger edge would have been set during ADC other * settings, ADC conversion would start at trigger event * as soon as ADC is enabled). * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart @@ -3925,7 +3927,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx) * @brief Start ADC group regular conversion from external trigger. * @note ADC conversion will start at next trigger event (on the selected * trigger edge) following the ADC start conversion command. - * @note On this STM32 series, this function is relevant for + * @note On this STM32 series, this function is relevant for * ADC conversion start from external trigger. * If internal trigger (SW start) is needed, perform ADC conversion * start using function @ref LL_ADC_REG_StartConversionSWStart(). @@ -4016,7 +4018,7 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) { - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } /** @@ -4031,7 +4033,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) { - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } #if defined(ADC_MULTIMODE_SUPPORT) @@ -4080,9 +4082,9 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef * - If ADC trigger has been set to software start, ADC conversion * starts immediately. * - If ADC trigger has been set to external trigger, ADC conversion - * start must be performed using function + * start must be performed using function * @ref LL_ADC_INJ_StartConversionExtTrig(). - * (if external trigger edge would have been set during ADC other + * (if external trigger edge would have been set during ADC other * settings, ADC conversion would start at trigger event * as soon as ADC is enabled). * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart @@ -4098,7 +4100,7 @@ __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx) * @brief Start ADC group injected conversion from external trigger. * @note ADC conversion will start at next trigger event (on the selected * trigger edge) following the ADC start conversion command. - * @note On this STM32 series, this function is relevant for + * @note On this STM32 series, this function is relevant for * ADC conversion start from external trigger. * If internal trigger (SW start) is needed, perform ADC conversion * start using function @ref LL_ADC_INJ_StartConversionSWStart(). @@ -4153,7 +4155,7 @@ __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx) __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - + return (uint32_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -4180,7 +4182,7 @@ __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - + return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -4207,7 +4209,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - + return (uint16_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -4234,7 +4236,7 @@ __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - + return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -4261,7 +4263,7 @@ __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32 __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank) { __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK)); - + return (uint8_t)(READ_BIT(*preg, ADC_JDR1_JDATA) ); @@ -4395,7 +4397,7 @@ __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS)); + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_MST) == (LL_ADC_FLAG_EOCS_MST)); } /** @@ -4468,7 +4470,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_ /** * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master. - * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_EOCS + * @rmtoll CSR JEOC LL_ADC_IsActiveFlag_MST_JEOS * @param ADCxy_COMMON ADC common instance * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) * @retval State of bit (1 or 0). @@ -4547,7 +4549,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy */ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON) { - return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); + return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2)); } #endif /* ADC_MULTIMODE_SUPPORT */ @@ -4778,4 +4780,3 @@ void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct); #endif /* __STM32F4xx_LL_ADC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_bus.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_bus.h index 66da28fe241..5083c10dc19 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_bus.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_bus.h @@ -23,14 +23,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -2105,4 +2103,3 @@ __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs) #endif /* __STM32F4xx_LL_BUS_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_cortex.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_cortex.h index cfa8fbe7a89..d478e130192 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_cortex.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_cortex.h @@ -10,7 +10,7 @@ [..] The LL CORTEX driver contains a set of generic APIs that can be used by user: - (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick + (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick functions (+) Low power mode configuration (SCB register of Cortex-MCU) (+) MPU API to configure and enable regions @@ -22,14 +22,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -637,4 +635,3 @@ __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) #endif /* __STM32F4xx_LL_CORTEX_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.c index 821b281e8ae..113879301f0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -26,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ @@ -102,6 +101,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.h index 2d05b679495..0a280062b8b 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_crc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -200,5 +199,3 @@ ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); #endif #endif /* STM32F4xx_LL_CRC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.c index 1316504b4fc..0a5c2ffde48 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -279,4 +278,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.h index 42031307fa0..ea1500ba586 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dac.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1288,7 +1287,6 @@ __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t D * @{ */ - /** * @brief Get DAC underrun flag for DAC channel 1 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 @@ -1455,4 +1453,3 @@ void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); #endif /* STM32F4xx_LL_DAC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.c index e4cbae4c98b..a83c086430a 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -422,4 +421,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.h index 63264e614d0..76444fc604c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -2730,7 +2729,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) } /** - * @brief Check if Half transfer interrup is enabled. + * @brief Check if Half transfer interrupt is enabled. * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -2770,7 +2769,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Strea } /** - * @brief Check if Transfer complete interrup is enabled. + * @brief Check if Transfer complete interrupt is enabled. * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -2810,7 +2809,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stre } /** - * @brief Check if FIFO error interrup is enabled. + * @brief Check if FIFO error interrupt is enabled. * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE * @param DMAx DMAx Instance * @param Stream This parameter can be one of the following values: @@ -2867,4 +2866,3 @@ void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); #endif /* __STM32F4xx_LL_DMA_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.c index 92941c4fb63..9f6c8f51c82 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -593,6 +592,3 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.h index a783d058aff..64c57b0ee4d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_dma2d.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1900,5 +1899,3 @@ void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t Nb #endif #endif /* STM32F4xx_LL_DMA2D_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.c index 31d70ac6819..ce2f7b054b6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause * ****************************************************************************** */ @@ -211,4 +210,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.h index c816e266efa..65ab6918408 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_exti.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS.Clause * ****************************************************************************** */ @@ -953,4 +952,3 @@ void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); #endif /* __STM32F4xx_LL_EXTI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.c index 2e4dadb32e6..1bdf9dea7af 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.c @@ -3,27 +3,38 @@ * @file stm32f4xx_ll_fmc.c * @author MCD Application Team * @brief FMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following + * + * This file provides firmware functions to manage the following * functionalities of the Flexible Memory Controller (FMC) peripheral memories: * + Initialization/de-initialization functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### FMC peripheral features ##### ============================================================================== - [..] The Flexible memory controller (FMC) includes three memory controllers: + [..] The Flexible memory controller (FMC) includes following memory controllers: (+) The NOR/PSRAM memory controller (+) The NAND/PC Card memory controller - (+) The Synchronous DRAM (SDRAM) controller - + (+) The Synchronous DRAM (SDRAM) controller + [..] The FMC functional block makes the interface with synchronous and asynchronous static memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: (+) to translate AHB transactions into the appropriate external device protocol (+) to meet the access time requirements of the external memory devices - + [..] All external memories share the addresses, data and control signals with the controller. Each external device is accessed by means of a unique Chip Select. The FMC performs only one access at a time to an external device. @@ -39,21 +50,10 @@ (+) Interface with synchronous DRAM (SDRAM) memories (+) Independent Chip Select control for each memory bank (+) Independent configuration for each memory bank - + @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -61,79 +61,187 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules * @{ */ -#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + +/** @defgroup FMC_LL_Private_Constants FMC Low Layer Private Constants + * @{ + */ + +/* ----------------------- FMC registers bit mask --------------------------- */ + +#if defined(FMC_Bank1) +/* --- BCR Register ---*/ +/* BCR register clear mask */ + +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\ + FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\ + FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\ + FMC_BTR1_ACCMOD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\ + FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\ + FMC_BWTR1_ACCMOD)) +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) + +#if defined (FMC_PCR_PWAITEN) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \ + FMC_PCR_PTYP | FMC_PCR_PWID | \ + FMC_PCR_ECCEN | FMC_PCR_TCLR | \ + FMC_PCR_TAR | FMC_PCR_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 |\ + FMC_PMEM_MEMHOLD2 | FMC_PMEM_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 |\ + FMC_PATT_ATTHOLD2 | FMC_PATT_ATTHIZ2)) +#else +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | \ + FMC_PCR2_PTYP | FMC_PCR2_PWID | \ + FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ + FMC_PCR2_TAR | FMC_PCR2_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 |\ + FMC_PMEM2_MEMHOLD2 | FMC_PMEM2_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 |\ + FMC_PATT2_ATTHOLD2 | FMC_PATT2_ATTHIZ2)) + +#endif /* FMC_PCR_PWAITEN */ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ +#if defined(FMC_Bank4) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR4_CLEAR_MASK ((uint32_t)(FMC_PCR4_PWAITEN | FMC_PCR4_PBKEN | \ + FMC_PCR4_PTYP | FMC_PCR4_PWID | \ + FMC_PCR4_ECCEN | FMC_PCR4_TCLR | \ + FMC_PCR4_TAR | FMC_PCR4_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM4_CLEAR_MASK ((uint32_t)(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 |\ + FMC_PMEM4_MEMHOLD4 | FMC_PMEM4_MEMHIZ4)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT4_CLEAR_MASK ((uint32_t)(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 |\ + FMC_PATT4_ATTHOLD4 | FMC_PATT4_ATTHIZ4)) + +/* --- PIO4 Register ---*/ +/* PIO4 register clear mask */ +#define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \ + FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4)) + +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) + +/* --- SDCR Register ---*/ +/* SDCR register clear mask */ +#define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \ + FMC_SDCR1_MWID | FMC_SDCR1_NB | \ + FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \ + FMC_SDCR1_RPIPE)) + +/* --- SDTR Register ---*/ +/* SDTR register clear mask */ +#define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \ + FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \ + FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)) +#endif /* FMC_Bank5_6 */ + +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup FMC_LL_Private_Functions +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_Functions FMC Low Layer Exported Functions * @{ */ -/** @addtogroup FMC_LL_NORSRAM - * @brief NORSRAM Controller functions +#if defined(FMC_Bank1) + +/** @defgroup FMC_LL_Exported_Functions_NORSRAM FMC Low Layer NOR SRAM Exported Functions + * @brief NORSRAM Controller functions * - @verbatim - ============================================================================== + @verbatim + ============================================================================== ##### How to use NORSRAM device driver ##### ============================================================================== - - [..] + + [..] This driver contains a set of APIs to interface with the FMC NORSRAM banks in order to run the NORSRAM external devices. - - (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() + + (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() - (+) FMC NORSRAM bank extended timing configuration using the function + (+) FMC NORSRAM bank extended timing configuration using the function FMC_NORSRAM_Extended_Timing_Init() (+) FMC NORSRAM bank enable/disable write operation using the functions FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() - @endverbatim * @{ */ - -/** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1 - * @brief Initialization and Configuration functions + +/** @defgroup FMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim ============================================================================== ##### Initialization and de_initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: (+) Initialize and configure the FMC NORSRAM interface - (+) De-initialize the FMC NORSRAM interface - (+) Configure the FMC clock and associated GPIOs - + (+) De-initialize the FMC NORSRAM interface + (+) Configure the FMC clock and associated GPIOs + @endverbatim * @{ */ - + /** * @brief Initialize the FMC_NORSRAM device according to the specified * control parameters in the FMC_NORSRAM_InitTypeDef * @param Device Pointer to NORSRAM device instance - * @param Init Pointer to NORSRAM Initialization structure + * @param Init Pointer to NORSRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) -{ - uint32_t tmpr = 0U; - +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init) +{ + uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; + /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); @@ -142,131 +250,139 @@ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_Ini assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#if defined(FMC_BCR1_WRAPMOD) assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* FMC_BCR1_WRAPMOD */ assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); +#if defined(FMC_BCR1_CCLKEN) assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); - assert_param(IS_FMC_PAGESIZE(Init->PageSize)); -#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#endif +#if defined(FMC_BCR1_WFDIS) assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Init->NSBank]; - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CPSIZE, CBURSTRW and CCLKEN bits */ - tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ - FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ - FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \ - FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ - FMC_BCR1_ASYNCWAIT | FMC_BCR1_CPSIZE | FMC_BCR1_CBURSTRW | \ - FMC_BCR1_CCLKEN)); - - /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WrapMode |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->PageSize |\ - Init->WriteBurst |\ - Init->ContinuousClock); -#else /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */ - tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ - FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ - FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \ - FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ - FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \ - FMC_BCR1_WFDIS)); - +#endif /* FMC_BCR1_WFDIS */ + assert_param(IS_FMC_PAGESIZE(Init->PageSize)); + + /* Disable NORSRAM Device */ + __FMC_NORSRAM_DISABLE(Device, Init->NSBank); + /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->WriteBurst |\ - Init->ContinuousClock |\ - Init->PageSize |\ - Init->WriteFifo); -#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ - - if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) + if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + else { - tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; + flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; } - - Device->BTCR[Init->NSBank] = tmpr; + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + +#if defined(FMC_BCR1_WRAPMOD) + btcr_reg |= Init->WrapMode; +#endif /* FMC_BCR1_WRAPMOD */ +#if defined(FMC_BCR1_CCLKEN) + btcr_reg |= Init->ContinuousClock; +#endif /* FMC_BCR1_CCLKEN */ +#if defined(FMC_BCR1_WFDIS) + btcr_reg |= Init->WriteFifo; +#endif /* FMC_BCR1_WFDIS */ + btcr_reg |= Init->PageSize; + + mask = (FMC_BCR1_MBKEN | + FMC_BCR1_MUXEN | + FMC_BCR1_MTYP | + FMC_BCR1_MWID | + FMC_BCR1_FACCEN | + FMC_BCR1_BURSTEN | + FMC_BCR1_WAITPOL | + FMC_BCR1_WAITCFG | + FMC_BCR1_WREN | + FMC_BCR1_WAITEN | + FMC_BCR1_EXTMOD | + FMC_BCR1_ASYNCWAIT | + FMC_BCR1_CBURSTRW); + +#if defined(FMC_BCR1_WRAPMOD) + mask |= FMC_BCR1_WRAPMOD; +#endif /* FMC_BCR1_WRAPMOD */ +#if defined(FMC_BCR1_CCLKEN) + mask |= FMC_BCR1_CCLKEN; +#endif +#if defined(FMC_BCR1_WFDIS) + mask |= FMC_BCR1_WFDIS; +#endif /* FMC_BCR1_WFDIS */ + mask |= FMC_BCR1_CPSIZE; + + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); + +#if defined(FMC_BCR1_CCLKEN) /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ - if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) - { - Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); + if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) + { + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); } +#endif +#if defined(FMC_BCR1_WFDIS) -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - if(Init->NSBank != FMC_NORSRAM_BANK1) + if (Init->NSBank != FMC_NORSRAM_BANK1) { - Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); + /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ + SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); } -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ - +#endif /* FMC_BCR1_WFDIS */ + return HAL_OK; } /** - * @brief DeInitialize the FMC_NORSRAM peripheral + * @brief DeInitialize the FMC_NORSRAM peripheral * @param Device Pointer to NORSRAM device instance - * @param ExDevice Pointer to NORSRAM extended mode device instance - * @param Bank NORSRAM bank number + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); - + /* Disable the FMC_NORSRAM device */ __FMC_NORSRAM_DISABLE(Device, Bank); - + /* De-initialize the FMC_NORSRAM device */ /* FMC_NORSRAM_BANK1 */ - if(Bank == FMC_NORSRAM_BANK1) + if (Bank == FMC_NORSRAM_BANK1) { Device->BTCR[Bank] = 0x000030DBU; } /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ else - { + { Device->BTCR[Bank] = 0x000030D2U; } - + Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; - ExDevice->BWTR[Bank] = 0x0FFFFFFFU; - + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; + return HAL_OK; } @@ -275,13 +391,16 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EX * parameters in the FMC_NORSRAM_TimingTypeDef * @param Device Pointer to NORSRAM device instance * @param Timing Pointer to NORSRAM Timing structure - * @param Bank NORSRAM bank number + * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; - +#if defined(FMC_BCR1_CCLKEN) + uint32_t tmpr; +#endif + /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); @@ -292,35 +411,27 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Bank + 1U]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ - tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ - FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ - FMC_BTR1_ACCMOD)); - - /* Set FMC_NORSRAM device timing parameters */ - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4U) |\ - ((Timing->DataSetupTime) << 8U) |\ - ((Timing->BusTurnAroundDuration) << 16U) |\ - (((Timing->CLKDivision) - 1U) << 20U) |\ - (((Timing->DataLatency) - 2U) << 24U) |\ - (Timing->AccessMode)); - - Device->BTCR[Bank + 1U] = tmpr; - + + /* Set FMC_NORSRAM device timing parameters */ + MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) | + ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) | + (Timing->AccessMode))); + +#if defined(FMC_BCR1_CCLKEN) /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ - if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) + if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U)); - tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << 20U); - Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpr; - } - - return HAL_OK; + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos); + MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr); + } + +#endif + return HAL_OK; } /** @@ -328,61 +439,57 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSR * parameters in the FMC_NORSRAM_TimingTypeDef * @param Device Pointer to NORSRAM device instance * @param Timing Pointer to NORSRAM Timing structure - * @param Bank NORSRAM bank number + * @param Bank NORSRAM bank number + * @param ExtendedMode FMC Extended Mode + * This parameter can be one of the following values: + * @arg FMC_EXTENDED_MODE_DISABLE + * @arg FMC_EXTENDED_MODE_ENABLE * @retval HAL status */ -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) -{ - uint32_t tmpr = 0U; - +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) +{ /* Check the parameters */ assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); - + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) + if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) { /* Check the parameters */ - assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); - assert_param(IS_FMC_NORSRAM_BANK(Bank)); - - /* Get the BWTR register value */ - tmpr = Device->BWTR[Bank]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ - tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ - FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); - - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4U) |\ - ((Timing->DataSetupTime) << 8U) |\ - ((Timing->BusTurnAroundDuration) << 16U) |\ - (Timing->AccessMode)); - - Device->BWTR[Bank] = tmpr; + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) | + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos))); } else { Device->BWTR[Bank] = 0x0FFFFFFFU; - } - - return HAL_OK; + } + + return HAL_OK; } /** * @} */ - + /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions - * -@verbatim + * @brief management functions + * +@verbatim ============================================================================== ##### FMC_NORSRAM Control functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to control dynamically the FMC NORSRAM interface. @@ -390,10 +497,11 @@ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef @endverbatim * @{ */ + /** * @brief Enables dynamically FMC_NORSRAM write operation. * @param Device Pointer to NORSRAM device instance - * @param Bank NORSRAM bank number + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) @@ -401,29 +509,29 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); - + /* Enable write operation */ - Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; + SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); - return HAL_OK; + return HAL_OK; } /** * @brief Disables dynamically FMC_NORSRAM write operation. * @param Device Pointer to NORSRAM device instance - * @param Bank NORSRAM bank number + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) -{ +{ /* Check the parameters */ assert_param(IS_FMC_NORSRAM_DEVICE(Device)); assert_param(IS_FMC_NORSRAM_BANK(Bank)); - + /* Disable write operation */ - Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; + CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); - return HAL_OK; + return HAL_OK; } /** @@ -433,317 +541,52 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device /** * @} */ +#endif /* FMC_Bank1 */ -/** @addtogroup FMC_LL_NAND - * @brief NAND Controller functions +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) + +/** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions + * @brief NAND Controller functions * - @verbatim + @verbatim ============================================================================== ##### How to use NAND device driver ##### ============================================================================== [..] This driver contains a set of APIs to interface with the FMC NAND banks in order to run the NAND external devices. - - (+) FMC NAND bank reset using the function FMC_NAND_DeInit() + + (+) FMC NAND bank reset using the function FMC_NAND_DeInit() (+) FMC NAND bank control configuration using the function FMC_NAND_Init() - (+) FMC NAND bank common space timing configuration using the function + (+) FMC NAND bank common space timing configuration using the function FMC_NAND_CommonSpace_Timing_Init() - (+) FMC NAND bank attribute space timing configuration using the function + (+) FMC NAND bank attribute space timing configuration using the function FMC_NAND_AttributeSpace_Timing_Init() (+) FMC NAND bank enable/disable ECC correction feature using the functions FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() - (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() + (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() @endverbatim * @{ */ - -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim + +/** @defgroup FMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim ============================================================================== ##### Initialization and de_initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: (+) Initialize and configure the FMC NAND interface - (+) De-initialize the FMC NAND interface + (+) De-initialize the FMC NAND interface (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the FMC_NAND device according to the specified - * control parameters in the FMC_NAND_HandleTypeDef - * @param Device Pointer to NAND device instance - * @param Init Pointer to NAND Initialization structure - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Init->NandBank)); - assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); - assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); - assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); - assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); - assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - - /* Get the NAND bank register value */ - tmpr = Device->PCR; - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \ - FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \ - FMC_PCR_TAR | FMC_PCR_ECCPS)); - - /* Set NAND device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FMC_PCR_MEMORY_TYPE_NAND |\ - Init->MemoryDataWidth |\ - Init->EccComputation |\ - Init->ECCPageSize |\ - ((Init->TCLRSetupTime) << 9U) |\ - ((Init->TARSetupTime) << 13U)); - - /* NAND bank registers configuration */ - Device->PCR = tmpr; - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_NAND Common space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device Pointer to NAND device instance - * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get the NAND bank 2 register value */ - tmpr = Device->PMEM; - - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \ - FMC_PMEM_MEMHIZ2)); - - /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U) - ); - - /* NAND bank registers configuration */ - Device->PMEM = tmpr; - - return HAL_OK; -} - -/** - * @brief Initializes the FMC_NAND Attribute space Timing according to the specified - * parameters in the FMC_NAND_PCC_TimingTypeDef - * @param Device Pointer to NAND device instance - * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) -{ - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); - assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); - assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); - assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get the NAND bank register value */ - tmpr = Device->PATT; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \ - FMC_PATT_ATTHIZ2)); - - /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - /* NAND bank registers configuration */ - Device->PATT = tmpr; - - return HAL_OK; -} - - -/** - * @brief DeInitializes the FMC_NAND device - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable the NAND Bank */ - __FMC_NAND_DISABLE(Device, Bank); - - /* De-initialize the NAND Bank */ - /* Set the FMC_NAND_BANK registers to their reset values */ - Device->PCR = 0x00000018U; - Device->SR = 0x00000040U; - Device->PMEM = 0xFCFCFCFCU; - Device->PATT = 0xFCFCFCFCU; - - return HAL_OK; -} - -/** - * @} - */ - - -/** @defgroup HAL_FMC_NAND_Group2 Control functions - * @brief management functions - * -@verbatim - ============================================================================== - ##### FMC_NAND Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control dynamically - the FMC NAND interface. @endverbatim * @{ - */ - - -/** - * @brief Enables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Enable ECC feature */ - Device->PCR |= FMC_PCR_ECCEN; - - return HAL_OK; -} - - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param Bank NAND bank number - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Disable ECC feature */ - Device->PCR &= ~FMC_PCR_ECCEN; - - return HAL_OK; -} - -/** - * @brief Disables dynamically FMC_NAND ECC feature. - * @param Device Pointer to NAND device instance - * @param ECCval Pointer to ECC value - * @param Bank NAND bank number - * @param Timeout Timeout wait value - * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) -{ - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); - assert_param(IS_FMC_NAND_BANK(Bank)); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait until FIFO is empty */ - while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) - { - /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) - { - return HAL_TIMEOUT; - } - } - } - - /* Get the ECCR register value */ - *ECCval = (uint32_t)Device->ECCR; - - return HAL_OK; -} - -/** - * @} */ -#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ -/** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and de_initialization functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the FMC NAND interface - (+) De-initialize the FMC NAND interface - (+) Configure the FMC clock and associated GPIOs - -@endverbatim - * @{ - */ /** * @brief Initializes the FMC_NAND device according to the specified * control parameters in the FMC_NAND_HandleTypeDef @@ -753,8 +596,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_NAND_BANK(Init->NandBank)); @@ -763,46 +604,44 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); + assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - if(Init->NandBank == FMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PCR2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PCR3; - } - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \ - FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ - FMC_PCR2_TAR | FMC_PCR2_ECCPS)); - +#if defined(FMC_Bank2_3) /* Set NAND device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FMC_PCR_MEMORY_TYPE_NAND |\ - Init->MemoryDataWidth |\ - Init->EccComputation |\ - Init->ECCPageSize |\ - ((Init->TCLRSetupTime) << 9U) |\ - ((Init->TARSetupTime) << 13U)); - - if(Init->NandBank == FMC_NAND_BANK2) + if (Init->NandBank == FMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PCR2 = tmpr; + MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PCR3 = tmpr; + MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos))); } - - return HAL_OK; +#else + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | + ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); +#endif + return HAL_OK; } /** @@ -810,13 +649,12 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * parameters in the FMC_NAND_PCC_TimingTypeDef * @param Device Pointer to NAND device instance * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number + * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); @@ -824,41 +662,37 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); assert_param(IS_FMC_NAND_BANK(Bank)); - - if(Bank == FMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PMEM2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PMEM3; - } - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \ - FMC_PMEM2_MEMHIZ2)); - + +#if defined(FMC_Bank2_3) /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U) - ); - - if(Bank == FMC_NAND_BANK2) + if (Bank == FMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PMEM2 = tmpr; + MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PMEM3 = tmpr; - } - - return HAL_OK; + MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos))); + } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ2_Pos))); +#endif + + return HAL_OK; } /** @@ -866,90 +700,97 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC * parameters in the FMC_NAND_PCC_TimingTypeDef * @param Device Pointer to NAND device instance * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number + * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); assert_param(IS_FMC_NAND_BANK(Bank)); - - if(Bank == FMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PATT2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PATT3; - } - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \ - FMC_PATT2_ATTHIZ2)); - + +#if defined(FMC_Bank2_3) /* Set FMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - if(Bank == FMC_NAND_BANK2) + if (Bank == FMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PATT2 = tmpr; + MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PATT3 = tmpr; - } - + MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos))); + } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* NAND bank 3 registers configuration */ + MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ2_Pos))); +#endif + return HAL_OK; } /** - * @brief DeInitializes the FMC_NAND device + * @brief DeInitializes the FMC_NAND device * @param Device Pointer to NAND device instance * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) { - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_NAND_BANK(Bank)); - + /* Disable the NAND Bank */ __FMC_NAND_DISABLE(Device, Bank); - + /* De-initialize the NAND Bank */ - if(Bank == FMC_NAND_BANK2) +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) { /* Set the FMC_NAND_BANK2 registers to their reset values */ - Device->PCR2 = 0x00000018U; - Device->SR2 = 0x00000040U; - Device->PMEM2 = 0xFCFCFCFCU; - Device->PATT2 = 0xFCFCFCFCU; + WRITE_REG(Device->PCR2, 0x00000018U); + WRITE_REG(Device->SR2, 0x00000040U); + WRITE_REG(Device->PMEM2, 0xFCFCFCFCU); + WRITE_REG(Device->PATT2, 0xFCFCFCFCU); } - /* FMC_Bank3_NAND */ + /* FMC_Bank3_NAND */ else { /* Set the FMC_NAND_BANK3 registers to their reset values */ - Device->PCR3 = 0x00000018U; - Device->SR3 = 0x00000040U; - Device->PMEM3 = 0xFCFCFCFCU; - Device->PATT3 = 0xFCFCFCFCU; + WRITE_REG(Device->PCR3, 0x00000018U); + WRITE_REG(Device->SR3, 0x00000040U); + WRITE_REG(Device->PMEM3, 0xFCFCFCFCU); + WRITE_REG(Device->PATT3, 0xFCFCFCFCU); } - +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + /* Set the FMC_NAND_BANK3 registers to their reset values */ + WRITE_REG(Device->PCR, 0x00000018U); + WRITE_REG(Device->SR, 0x00000040U); + WRITE_REG(Device->PMEM, 0xFCFCFCFCU); + WRITE_REG(Device->PATT, 0xFCFCFCFCU); +#endif + return HAL_OK; } @@ -957,68 +798,85 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) * @} */ -/** @addtogroup FMC_LL_NAND_Private_Functions_Group2 - * @brief management functions +/** @defgroup HAL_FMC_NAND_Group2 Peripheral Control functions + * @brief management functions * -@verbatim +@verbatim ============================================================================== ##### FMC_NAND Control functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to control dynamically the FMC NAND interface. @endverbatim * @{ - */ + */ + + /** * @brief Enables dynamically FMC_NAND ECC feature. * @param Device Pointer to NAND device instance * @param Bank NAND bank number * @retval HAL status - */ + */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) { - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_NAND_BANK(Bank)); - + /* Enable ECC feature */ - if(Bank == FMC_NAND_BANK2) +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) { - Device->PCR2 |= FMC_PCR2_ECCEN; + SET_BIT(Device->PCR2, FMC_PCR2_ECCEN); } else { - Device->PCR3 |= FMC_PCR3_ECCEN; - } - - return HAL_OK; + SET_BIT(Device->PCR3, FMC_PCR2_ECCEN); + } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); + + SET_BIT(Device->PCR, FMC_PCR_ECCEN); +#endif + + return HAL_OK; } + /** * @brief Disables dynamically FMC_NAND ECC feature. * @param Device Pointer to NAND device instance * @param Bank NAND bank number * @retval HAL status - */ -HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) -{ - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); + */ +HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_NAND_BANK(Bank)); - + /* Disable ECC feature */ - if(Bank == FMC_NAND_BANK2) +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) { - Device->PCR2 &= ~FMC_PCR2_ECCEN; + CLEAR_BIT(Device->PCR2, FMC_PCR2_ECCEN); } else { - Device->PCR3 &= ~FMC_PCR3_ECCEN; - } + CLEAR_BIT(Device->PCR3, FMC_PCR2_ECCEN); + } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); - return HAL_OK; + CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); +#endif + + return HAL_OK; } /** @@ -1026,129 +884,133 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Device Pointer to NAND device instance * @param ECCval Pointer to ECC value * @param Bank NAND bank number - * @param Timeout Timeout wait value + * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) { - uint32_t tickstart = 0U; + uint32_t tickstart; - /* Check the parameters */ - assert_param(IS_FMC_NAND_DEVICE(Device)); + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); assert_param(IS_FMC_NAND_BANK(Bank)); - /* Get tick */ + /* Get tick */ tickstart = HAL_GetTick(); /* Wait until FIFO is empty */ - while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) + while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_TIMEOUT; } - } + } } - - if(Bank == FMC_NAND_BANK2) - { + +#if defined(FMC_Bank2_3) + if (Bank == FMC_NAND_BANK2) + { /* Get the ECCR2 register value */ *ECCval = (uint32_t)Device->ECCR2; } else - { + { /* Get the ECCR3 register value */ *ECCval = (uint32_t)Device->ECCR3; } +#else + /* Prevent unused argument(s) compilation warning if no assert_param check */ + UNUSED(Bank); - return HAL_OK; + /* Get the ECCR register value */ + *ECCval = (uint32_t)Device->ECCR; +#endif + + return HAL_OK; } /** * @} */ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ -/** - * @} - */ +#if defined(FMC_Bank4) -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** @addtogroup FMC_LL_PCCARD - * @brief PCCARD Controller functions + * @brief PCCARD Controller functions * - @verbatim - ============================================================================== + @verbatim + ============================================================================== ##### How to use PCCARD device driver ##### ============================================================================== [..] This driver contains a set of APIs to interface with the FMC PCCARD bank in order to run the PCCARD/compact flash external devices. - - (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit() + + (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit() (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init() - (+) FMC PCCARD bank common space timing configuration using the function + (+) FMC PCCARD bank common space timing configuration using the function FMC_PCCARD_CommonSpace_Timing_Init() - (+) FMC PCCARD bank attribute space timing configuration using the function + (+) FMC PCCARD bank attribute space timing configuration using the function FMC_PCCARD_AttributeSpace_Timing_Init() - (+) FMC PCCARD bank IO space timing configuration using the function + (+) FMC PCCARD bank IO space timing configuration using the function FMC_PCCARD_IOSpace_Timing_Init() @endverbatim * @{ */ - + /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1 - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de_initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: (+) Initialize and configure the FMC PCCARD interface - (+) De-initialize the FMC PCCARD interface + (+) De-initialize the FMC PCCARD interface (+) Configure the FMC clock and associated GPIOs - + @endverbatim * @{ */ - + /** * @brief Initializes the FMC_PCCARD device according to the specified * control parameters in the FMC_PCCARD_HandleTypeDef * @param Device Pointer to PCCARD device instance - * @param Init Pointer to PCCARD Initialization structure + * @param Init Pointer to PCCARD Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) { - uint32_t tmpr = 0U; - - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); - - /* Get PCCARD control register value */ - tmpr = Device->PCR4; - - /* Clear TAR, TCLR, PWAITEN and PWID bits */ - tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \ - FMC_PCR4_PWID | FMC_PCR4_PTYP)); - + assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + /* Set FMC_PCCARD device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ - (Init->TCLRSetupTime << 9U) |\ - (Init->TARSetupTime << 13U)); - - Device->PCR4 = tmpr; - + MODIFY_REG(Device->PCR4, + (FMC_PCR4_PTYP | + FMC_PCR4_PWAITEN | + FMC_PCR4_PWID | + FMC_PCR4_TCLR | + FMC_PCR4_TAR), + (FMC_PCR_MEMORY_TYPE_PCCARD | + Init->Waitfeature | + FMC_NAND_PCC_MEM_BUS_WIDTH_16 | + (Init->TCLRSetupTime << FMC_PCR4_TCLR_Pos) | + (Init->TARSetupTime << FMC_PCR4_TAR_Pos))); + return HAL_OK; } @@ -1156,68 +1018,56 @@ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTyp * @brief Initializes the FMC_PCCARD Common space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef * @param Device Pointer to PCCARD device instance - * @param Timing Pointer to PCCARD timing structure + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ - /* Get PCCARD common space timing register value */ - tmpr = Device->PMEM4; - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \ - FMC_PMEM4_MEMHIZ4)); /* Set PCCARD timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - Device->PMEM4 = tmpr; - - return HAL_OK; + MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM4_MEMHIZ4_Pos))); + + return HAL_OK; } /** * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef * @param Device Pointer to PCCARD device instance - * @param Timing Pointer to PCCARD timing structure + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0U; - - /* Check the parameters */ - assert_param(IS_FMC_PCCARD_DEVICE(Device)); + /* Check the parameters */ + assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ - /* Get PCCARD timing parameters */ - tmpr = Device->PATT4; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \ - FMC_PATT4_ATTHIZ4)); - /* Set PCCARD timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - Device->PATT4 = tmpr; + MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT4_ATTHIZ4_Pos))); return HAL_OK; } @@ -1226,102 +1076,96 @@ HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Devi * @brief Initializes the FMC_PCCARD IO space Timing according to the specified * parameters in the FMC_NAND_PCC_TimingTypeDef * @param Device Pointer to PCCARD device instance - * @param Timing Pointer to PCCARD timing structure + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0; - - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ - /* Get FMC_PCCARD device timing parameters */ - tmpr = Device->PIO4; - - /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ - tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \ - FMC_PIO4_IOHIZ4)); - /* Set FMC_PCCARD device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - Device->PIO4 = tmpr; - + MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, + (Timing->SetupTime | + (Timing->WaitSetupTime << FMC_PIO4_IOWAIT4_Pos) | + (Timing->HoldSetupTime << FMC_PIO4_IOHOLD4_Pos) | + (Timing->HiZSetupTime << FMC_PIO4_IOHIZ4_Pos))); + return HAL_OK; } - + /** - * @brief DeInitializes the FMC_PCCARD device + * @brief DeInitializes the FMC_PCCARD device * @param Device Pointer to PCCARD device instance * @retval HAL status */ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) { - /* Check the parameters */ + /* Check the parameters */ assert_param(IS_FMC_PCCARD_DEVICE(Device)); - + /* Disable the FMC_PCCARD device */ __FMC_PCCARD_DISABLE(Device); - + /* De-initialize the FMC_PCCARD device */ - Device->PCR4 = 0x00000018U; - Device->SR4 = 0x00000000U; + Device->PCR4 = 0x00000018U; + Device->SR4 = 0x00000040U; Device->PMEM4 = 0xFCFCFCFCU; Device->PATT4 = 0xFCFCFCFCU; Device->PIO4 = 0xFCFCFCFCU; - + return HAL_OK; } /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) -/** @addtogroup FMC_LL_SDRAM - * @brief SDRAM Controller functions +/** @defgroup FMC_LL_SDRAM + * @brief SDRAM Controller functions * - @verbatim + @verbatim ============================================================================== ##### How to use SDRAM device driver ##### ============================================================================== - [..] + [..] This driver contains a set of APIs to interface with the FMC SDRAM banks in order to run the SDRAM external devices. - - (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() + + (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() (+) FMC SDRAM bank enable/disable write operation using the functions - FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() - (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() - + FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() + (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() + @endverbatim * @{ */ - + /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de_initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: (+) Initialize and configure the FMC SDRAM interface - (+) De-initialize the FMC SDRAM interface + (+) De-initialize the FMC SDRAM interface (+) Configure the FMC clock and associated GPIOs - + @endverbatim * @{ */ @@ -1330,14 +1174,11 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) * @brief Initializes the FMC_SDRAM device according to the specified * control parameters in the FMC_SDRAM_InitTypeDef * @param Device Pointer to SDRAM device instance - * @param Init Pointer to SDRAM Initialization structure + * @param Init Pointer to SDRAM Initialization structure * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) { - uint32_t tmpr1 = 0U; - uint32_t tmpr2 = 0U; - /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); @@ -1349,76 +1190,58 @@ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDe assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); - assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); + assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); /* Set SDRAM bank configuration parameters */ - if (Init->SDBank != FMC_SDRAM_BANK2) - { - tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - - tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ - Init->RowBitsNumber |\ - Init->MemoryDataWidth |\ - Init->InternalBankNumber |\ - Init->CASLatency |\ - Init->WriteProtection |\ - Init->SDClockPeriod |\ - Init->ReadBurst |\ - Init->ReadPipeDelay - ); - Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; + if (Init->SDBank == FMC_SDRAM_BANK1) + { + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + SDCR_CLEAR_MASK, + (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection | + Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); } - else /* FMC_Bank2_SDRAM */ + else /* FMC_Bank2_SDRAM */ { - tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr1 &= ((uint32_t)~(FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ - Init->ReadBurst |\ - Init->ReadPipeDelay); - - tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; - - /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ - tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ - FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ - FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); - - tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ - Init->RowBitsNumber |\ - Init->MemoryDataWidth |\ - Init->InternalBankNumber |\ - Init->CASLatency |\ - Init->WriteProtection); - - Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; - Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; - } - + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], + FMC_SDCR1_SDCLK | + FMC_SDCR1_RBURST | + FMC_SDCR1_RPIPE, + (Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay)); + + MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], + SDCR_CLEAR_MASK, + (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection)); + } + return HAL_OK; } + /** * @brief Initializes the FMC_SDRAM device timing according to the specified * parameters in the FMC_SDRAM_TimingTypeDef * @param Device Pointer to SDRAM device instance * @param Timing Pointer to SDRAM Timing structure - * @param Bank SDRAM bank number + * @param Bank SDRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr1 = 0U; - uint32_t tmpr2 = 0U; - /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); @@ -1429,57 +1252,42 @@ HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_Tim assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); assert_param(IS_FMC_SDRAM_BANK(Bank)); - - /* Set SDRAM device timing parameters */ - if (Bank != FMC_SDRAM_BANK2) - { - tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1U) |\ - (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\ - (((Timing->SelfRefreshTime)-1U) << 8U) |\ - (((Timing->RowCycleDelay)-1U) << 12U) |\ - (((Timing->WriteRecoveryTime)-1U) <<16U) |\ - (((Timing->RPDelay)-1U) << 20U) |\ - (((Timing->RCDDelay)-1U) << 24U)); - Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; + + /* Set SDRAM device timing parameters */ + if (Bank == FMC_SDRAM_BANK1) + { + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + SDTR_CLEAR_MASK, + (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | + (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); } - else /* FMC_Bank2_SDRAM */ + else /* FMC_Bank2_SDRAM */ { - tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; - - /* Clear TRC and TRP bits */ - tmpr1 &= ((uint32_t)~(FMC_SDTR1_TRC | FMC_SDTR1_TRP)); - - tmpr1 |= (uint32_t)((((Timing->RowCycleDelay)-1U) << 12U) |\ - (((Timing->RPDelay)-1U) << 20U)); - - tmpr2 = Device->SDTR[FMC_SDRAM_BANK2]; - - /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ - tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ - FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ - FMC_SDTR1_TRCD)); - - tmpr2 |= (uint32_t)((((Timing->LoadToActiveDelay)-1U) |\ - (((Timing->ExitSelfRefreshDelay)-1U) << 4U) |\ - (((Timing->SelfRefreshTime)-1U) << 8U) |\ - (((Timing->WriteRecoveryTime)-1U) <<16U) |\ - (((Timing->RCDDelay)-1U) << 24U))); - - Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; - Device->SDTR[FMC_SDRAM_BANK2] = tmpr2; + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], + FMC_SDTR1_TRC | + FMC_SDTR1_TRP, + (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos)); + + MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], + SDTR_CLEAR_MASK, + (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); } + return HAL_OK; } /** - * @brief DeInitializes the FMC_SDRAM peripheral + * @brief DeInitializes the FMC_SDRAM peripheral * @param Device Pointer to SDRAM device instance * @retval HAL status */ @@ -1488,10 +1296,10 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_SDRAM_BANK(Bank)); - + /* De-initialize the SDRAM device */ Device->SDCR[Bank] = 0x000002D0U; - Device->SDTR[Bank] = 0x0FFFFFFFU; + Device->SDTR[Bank] = 0x0FFFFFFFU; Device->SDCMR = 0x00000000U; Device->SDRTR = 0x00000000U; Device->SDSR = 0x00000000U; @@ -1502,14 +1310,14 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) /** * @} */ - + /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 - * @brief management functions + * @brief management functions * -@verbatim +@verbatim ============================================================================== ##### FMC_SDRAM Control functions ##### - ============================================================================== + ============================================================================== [..] This subsection provides a set of functions allowing to control dynamically the FMC SDRAM interface. @@ -1517,22 +1325,23 @@ HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) @endverbatim * @{ */ + /** * @brief Enables dynamically FMC_SDRAM write protection. * @param Device Pointer to SDRAM device instance - * @param Bank SDRAM bank number + * @param Bank SDRAM bank number * @retval HAL status */ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) -{ +{ /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_SDRAM_BANK(Bank)); - + /* Enable write protection */ - Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; - - return HAL_OK; + SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); + + return HAL_OK; } /** @@ -1545,64 +1354,58 @@ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, u /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_SDRAM_BANK(Bank)); - + /* Disable write protection */ - Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; - + CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); + return HAL_OK; } - + /** * @brief Send Command to the FMC SDRAM bank * @param Device Pointer to SDRAM device instance - * @param Command Pointer to SDRAM command structure + * @param Command Pointer to SDRAM command structure * @param Timing Pointer to SDRAM Timing structure * @param Timeout Timeout wait value * @retval HAL state - */ -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) + */ +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) { - __IO uint32_t tmpr = 0U; uint32_t tickstart = 0U; - /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); - assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); + assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); /* Set command register */ - tmpr = (uint32_t)((Command->CommandMode) |\ - (Command->CommandTarget) |\ - (((Command->AutoRefreshNumber)-1U) << 5U) |\ - ((Command->ModeRegisterDefinition) << 9U) - ); - - Device->SDCMR = tmpr; - - /* Get tick */ + MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD), + ((Command->CommandMode) | (Command->CommandTarget) | + (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | + ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos))); + /* Get tick */ tickstart = HAL_GetTick(); - /* Wait until command is send */ - while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) + /* wait until command is send */ + while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout)) { return HAL_TIMEOUT; } } } - return HAL_OK; } /** * @brief Program the SDRAM Memory Refresh rate. - * @param Device Pointer to SDRAM device instance + * @param Device Pointer to SDRAM device instance * @param RefreshRate The SDRAM refresh rate value. * @retval HAL state */ @@ -1611,58 +1414,59 @@ HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32 /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); - + /* Set the refresh rate in command register */ - Device->SDRTR |= (RefreshRate<<1U); - - return HAL_OK; + MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); + + return HAL_OK; } /** * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. - * @param Device Pointer to SDRAM device instance - * @param AutoRefreshNumber Specifies the auto Refresh number. + * @param Device Pointer to SDRAM device instance + * @param AutoRefreshNumber Specifies the auto Refresh number. * @retval None */ -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber) { /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); - + /* Set the Auto-refresh number in command register */ - Device->SDCMR |= (AutoRefreshNumber << 5U); + MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); - return HAL_OK; + return HAL_OK; } /** * @brief Returns the indicated FMC SDRAM bank mode status. - * @param Device Pointer to SDRAM device instance - * @param Bank Defines the FMC SDRAM bank. This parameter can be - * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. + * @param Device Pointer to SDRAM device instance + * @param Bank Defines the FMC SDRAM bank. This parameter can be + * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. * @retval The FMC SDRAM bank mode status, could be on of the following values: - * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or - * FMC_SDRAM_POWER_DOWN_MODE. + * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or + * FMC_SDRAM_POWER_DOWN_MODE. */ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) { - uint32_t tmpreg = 0U; - + uint32_t tmpreg; + /* Check the parameters */ assert_param(IS_FMC_SDRAM_DEVICE(Device)); assert_param(IS_FMC_SDRAM_BANK(Bank)); /* Get the corresponding bank mode */ - if(Bank == FMC_SDRAM_BANK1) + if (Bank == FMC_SDRAM_BANK1) { - tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); + tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); } else { tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); } - + /* Return the mode status */ return tmpreg; } @@ -1675,18 +1479,20 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) * @} */ +#endif /* FMC_Bank5_6 */ + /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ -#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ /** * @} */ +#endif /* HAL_NOR_MODULE_ENABLED */ +/** + * @} + */ /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.h index 71e7c7425e9..fe28f876cc7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmc.h @@ -6,23 +6,22 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_FMC_H -#define __STM32F4xx_LL_FMC_H +#ifndef STM32F4xx_LL_FMC_H +#define STM32F4xx_LL_FMC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -31,148 +30,336 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ - + /** @addtogroup FMC_LL * @{ - */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ - defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/* Private types -------------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Types FMC Private Types + */ + +/** @addtogroup FMC_LL_Private_Macros + * @{ + */ +#if defined(FMC_Bank1) + +#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ + ((__BANK__) == FMC_NORSRAM_BANK2) || \ + ((__BANK__) == FMC_NORSRAM_BANK3) || \ + ((__BANK__) == FMC_NORSRAM_BANK4)) +#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) +#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) +#if defined(FMC_BCR1_WFDIS) +#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \ + ((__FIFO__) == FMC_WRITE_FIFO_ENABLE)) +#endif /* FMC_BCR1_WFDIS */ +#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) +#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \ + ((__MODE__) == FMC_WRAP_MODE_ENABLE)) +#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) +#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) +#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) +#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) +#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) +#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) +#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) +#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) +#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) +#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) +#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) +#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) + +#endif /* FMC_Bank1 */ +#if (defined(FMC_Bank3) || defined(FMC_Bank2_3)) + +#if defined(FMC_Bank2_3) +#define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \ + ((__BANK__) == FMC_NAND_BANK3)) +#else +#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3) +#endif /* FMC_Bank2_3 */ +#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) +#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) +#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FMC_NAND_ECC_ENABLE)) + +#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) + +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ +#if defined(FMC_Bank4) +#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE) + +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) + +#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32)) +#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ + ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) +#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) +#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ + ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) +#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) +#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) +#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) +#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) +#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) +#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) +#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) +#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) +#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) +#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ + ((__BANK__) == FMC_SDRAM_BANK2)) +#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) +#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) +#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ + ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) +#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) + +#endif /* FMC_Bank5_6 */ + +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types * @{ */ -/** +#if defined(FMC_Bank1) +#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef +#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank2_3) +#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef +#else +#define FMC_NAND_TypeDef FMC_Bank3_TypeDef +#endif /* FMC_Bank2_3 */ +#if defined(FMC_Bank4) +#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) +#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef +#endif /* FMC_Bank5_6 */ + +#if defined(FMC_Bank1) +#define FMC_NORSRAM_DEVICE FMC_Bank1 +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank2_3) +#define FMC_NAND_DEVICE FMC_Bank2_3 +#else +#define FMC_NAND_DEVICE FMC_Bank3 +#endif /* FMC_Bank2_3 */ +#if defined(FMC_Bank4) +#define FMC_PCCARD_DEVICE FMC_Bank4 +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) +#define FMC_SDRAM_DEVICE FMC_Bank5_6 +#endif /* FMC_Bank5_6 */ + +#if defined(FMC_Bank1) +/** * @brief FMC NORSRAM Configuration Structure definition - */ + */ typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + multiplexed on the data bus or not. + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. This parameter can be a value of @ref FMC_Wrap_Mode - This mode is not available for the STM32F446/467/479xx devices */ + This mode is not available for the STM32F446/467/479xx devices */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. This parameter can be a value of @ref FMC_Write_FIFO - This mode is available only for the STM32F446/469/479xx devices */ + This mode is available only for the STM32F446/469/479xx devices */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ -}FMC_NORSRAM_InitTypeDef; + This parameter can be a value of @ref FMC_Page_Size */ +} FMC_NORSRAM_InitTypeDef; -/** - * @brief FMC NORSRAM Timing parameters structure definition +/** + * @brief FMC NORSRAM Timing parameters structure definition */ typedef struct { uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. + the duration of the address setup time. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. - This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + This parameter can be a value between Min_Data = 1 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between Min_Data = 1 and Max_Data = 255. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ + @note This parameter is only used for multiplexed NOR Flash memories. */ - uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM + accesses. */ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories - with synchronous burst mode enable */ + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ - uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ -}FMC_NORSRAM_TimingTypeDef; + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FMC_Access_Mode */ +} FMC_NORSRAM_TimingTypeDef; +#endif /* FMC_Bank1 */ -/** - * @brief FMC NAND Configuration Structure definition - */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) +/** + * @brief FMC NAND Configuration Structure definition + */ typedef struct { uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FMC_NAND_Bank */ + This parameter can be a value of @ref FMC_NAND_Bank */ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FMC_Wait_feature */ + This parameter can be any value of @ref FMC_Wait_feature */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FMC_NAND_Data_Width */ + This parameter can be any value of @ref FMC_NAND_Data_Width */ uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FMC_ECC */ + This parameter can be any value of @ref FMC_ECC */ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FMC_ECC_Page_Size */ + This parameter can be any value of @ref FMC_ECC_Page_Size */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -181,10 +368,12 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FMC_NAND_InitTypeDef; +} FMC_NAND_InitTypeDef; +#endif -/** - * @brief FMC NAND/PCCARD Timing parameters structure definition +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) +/** + * @brief FMC NAND Timing parameters structure definition */ typedef struct { @@ -192,35 +381,37 @@ typedef struct the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ -}FMC_NAND_PCC_TimingTypeDef; + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ +} FMC_NAND_PCC_TimingTypeDef; +#endif /* FMC_Bank3 || FMC_Bank2_3 */ -/** - * @brief FMC NAND Configuration Structure definition - */ +#if defined(FMC_Bank4) +/** + * @brief FMC PCCARD Configuration Structure definition + */ typedef struct { uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. - This parameter can be any value of @ref FMC_Wait_feature */ + This parameter can be any value of @ref FMC_Wait_feature */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -230,10 +421,12 @@ typedef struct delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ }FMC_PCCARD_InitTypeDef; +#endif /* FMC_Bank4 */ -/** - * @brief FMC SDRAM Configuration Structure definition - */ +#if defined(FMC_Bank5_6) +/** + * @brief FMC SDRAM Configuration Structure definition + */ typedef struct { uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. @@ -257,53 +450,53 @@ typedef struct uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ - uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow + uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow to disable the clock before changing frequency. This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ - uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read + uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands during the CAS latency and stores data in the Read FIFO. This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ -}FMC_SDRAM_InitTypeDef; +} FMC_SDRAM_InitTypeDef; -/** +/** * @brief FMC SDRAM Timing parameters structure definition */ typedef struct { - uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and + uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and an active or Refresh command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to + uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to issuing the Activate command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock + uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command - and the delay between two consecutive Refresh commands in number of + and the delay between two consecutive Refresh commands in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command + uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command in number of memory clock cycles. This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ - uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write + uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command in number of memory clock cycles. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ -}FMC_SDRAM_TimingTypeDef; + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ +} FMC_SDRAM_TimingTypeDef; -/** +/** * @brief SDRAM command parameters structure definition */ typedef struct @@ -316,47 +509,51 @@ typedef struct uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued in auto refresh mode. - This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ + uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ -}FMC_SDRAM_CommandTypeDef; +} FMC_SDRAM_CommandTypeDef; +#endif /* FMC_Bank5_6 */ /** * @} */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Constants FMC Private Constants +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants * @{ */ +#if defined(FMC_Bank1) -/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller +/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller * @{ - */ + */ + /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank * @{ */ -#define FMC_NORSRAM_BANK1 0x00000000U -#define FMC_NORSRAM_BANK2 0x00000002U -#define FMC_NORSRAM_BANK3 0x00000004U -#define FMC_NORSRAM_BANK4 0x00000006U +#define FMC_NORSRAM_BANK1 (0x00000000U) +#define FMC_NORSRAM_BANK2 (0x00000002U) +#define FMC_NORSRAM_BANK3 (0x00000004U) +#define FMC_NORSRAM_BANK4 (0x00000006U) /** * @} */ -/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing +/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing * @{ */ -#define FMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U -#define FMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U +#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) /** * @} */ -/** @defgroup FMC_Memory_Type FMC Memory Type +/** @defgroup FMC_Memory_Type FMC Memory Type * @{ */ -#define FMC_MEMORY_TYPE_SRAM 0x00000000U -#define FMC_MEMORY_TYPE_PSRAM 0x00000004U -#define FMC_MEMORY_TYPE_NOR 0x00000008U +#define FMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FMC_MEMORY_TYPE_NOR (0x00000008U) /** * @} */ @@ -364,9 +561,9 @@ typedef struct /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width * @{ */ -#define FMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U -#define FMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U -#define FMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -374,64 +571,63 @@ typedef struct /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access * @{ */ -#define FMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U -#define FMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) /** * @} */ -/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode +/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode * @{ */ -#define FMC_BURST_ACCESS_MODE_DISABLE 0x00000000U -#define FMC_BURST_ACCESS_MODE_ENABLE 0x00000100U +#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) /** * @} */ -/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity +/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity * @{ */ -#define FMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U -#define FMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U +#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) /** * @} */ -/** @defgroup FMC_Wrap_Mode FMC Wrap Mode +/** @defgroup FMC_Wrap_Mode FMC Wrap Mode + * @note This mode is not available for the STM32F446/469/479xx devices * @{ */ -/** @note This mode is not available for the STM32F446/469/479xx devices - */ -#define FMC_WRAP_MODE_DISABLE 0x00000000U -#define FMC_WRAP_MODE_ENABLE 0x00000400U +#define FMC_WRAP_MODE_DISABLE (0x00000000U) +#define FMC_WRAP_MODE_ENABLE (0x00000400U) /** * @} */ -/** @defgroup FMC_Wait_Timing FMC Wait Timing +/** @defgroup FMC_Wait_Timing FMC Wait Timing * @{ */ -#define FMC_WAIT_TIMING_BEFORE_WS 0x00000000U -#define FMC_WAIT_TIMING_DURING_WS 0x00000800U +#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS (0x00000800U) /** * @} */ -/** @defgroup FMC_Write_Operation FMC Write Operation +/** @defgroup FMC_Write_Operation FMC Write Operation * @{ */ -#define FMC_WRITE_OPERATION_DISABLE 0x00000000U -#define FMC_WRITE_OPERATION_ENABLE 0x00001000U +#define FMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE (0x00001000U) /** * @} */ -/** @defgroup FMC_Wait_Signal FMC Wait Signal +/** @defgroup FMC_Wait_Signal FMC Wait Signal * @{ */ -#define FMC_WAIT_SIGNAL_DISABLE 0x00000000U -#define FMC_WAIT_SIGNAL_ENABLE 0x00002000U +#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) /** * @} */ @@ -439,84 +635,92 @@ typedef struct /** @defgroup FMC_Extended_Mode FMC Extended Mode * @{ */ -#define FMC_EXTENDED_MODE_DISABLE 0x00000000U -#define FMC_EXTENDED_MODE_ENABLE 0x00004000U +#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) /** * @} */ -/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait +/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait * @{ */ -#define FMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U -#define FMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U +#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) /** * @} - */ + */ /** @defgroup FMC_Page_Size FMC Page Size * @{ */ -#define FMC_PAGE_SIZE_NONE 0x00000000U -#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0) -#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1) -#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1)) -#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2) +#define FMC_PAGE_SIZE_NONE (0x00000000U) +#define FMC_PAGE_SIZE_128 FMC_BCR1_CPSIZE_0 +#define FMC_PAGE_SIZE_256 FMC_BCR1_CPSIZE_1 +#define FMC_PAGE_SIZE_512 (FMC_BCR1_CPSIZE_0\ + | FMC_BCR1_CPSIZE_1) +#define FMC_PAGE_SIZE_1024 FMC_BCR1_CPSIZE_2 /** * @} */ -/** @defgroup FMC_Write_FIFO FMC Write FIFO - * @note These values are available only for the STM32F446/469/479xx devices. +/** @defgroup FMC_Write_Burst FMC Write Burst * @{ */ -#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS) -#define FMC_WRITE_FIFO_ENABLE 0x00000000U +#define FMC_WRITE_BURST_DISABLE (0x00000000U) +#define FMC_WRITE_BURST_ENABLE (0x00080000U) /** * @} */ -/** @defgroup FMC_Write_Burst FMC Write Burst +/** @defgroup FMC_Continous_Clock FMC Continuous Clock * @{ */ -#define FMC_WRITE_BURST_DISABLE 0x00000000U -#define FMC_WRITE_BURST_ENABLE 0x00080000U +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) /** * @} */ - -/** @defgroup FMC_Continous_Clock FMC Continuous Clock + +#if defined(FMC_BCR1_WFDIS) +/** @defgroup FMC_Write_FIFO FMC Write FIFO + * @note These values are available only for the STM32F446/469/479xx devices. * @{ */ -#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U -#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U +#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS +#define FMC_WRITE_FIFO_ENABLE (0x00000000U) +#endif /* FMC_BCR1_WFDIS */ /** * @} */ - -/** @defgroup FMC_Access_Mode FMC Access Mode + +/** @defgroup FMC_Access_Mode FMC Access Mode * @{ */ -#define FMC_ACCESS_MODE_A 0x00000000U -#define FMC_ACCESS_MODE_B 0x10000000U -#define FMC_ACCESS_MODE_C 0x20000000U -#define FMC_ACCESS_MODE_D 0x30000000U +#define FMC_ACCESS_MODE_A (0x00000000U) +#define FMC_ACCESS_MODE_B (0x10000000U) +#define FMC_ACCESS_MODE_C (0x20000000U) +#define FMC_ACCESS_MODE_D (0x30000000U) /** * @} */ - + /** * @} - */ + */ +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) -/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller +/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller * @{ */ -/** @defgroup FMC_NAND_Bank FMC NAND Bank +/** @defgroup FMC_NAND_Bank FMC NAND Bank * @{ */ -#define FMC_NAND_BANK2 0x00000010U -#define FMC_NAND_BANK3 0x00000100U +#if defined(FMC_Bank2_3) +#define FMC_NAND_BANK2 (0x00000010U) +#endif +#define FMC_NAND_BANK3 (0x00000100U) /** * @} */ @@ -524,75 +728,79 @@ typedef struct /** @defgroup FMC_Wait_feature FMC Wait feature * @{ */ -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U +#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) +#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) /** * @} */ -/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type +/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type * @{ */ -#define FMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U -#define FMC_PCR_MEMORY_TYPE_NAND 0x00000008U +#if defined(FMC_Bank4) +#define FMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) +#endif /* FMC_Bank4 */ +#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) /** * @} */ -/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width +/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width * @{ */ -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U +#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) /** * @} */ -/** @defgroup FMC_ECC FMC ECC +/** @defgroup FMC_ECC FMC ECC * @{ */ -#define FMC_NAND_ECC_DISABLE 0x00000000U -#define FMC_NAND_ECC_ENABLE 0x00000040U +#define FMC_NAND_ECC_DISABLE (0x00000000U) +#define FMC_NAND_ECC_ENABLE (0x00000040U) /** * @} */ -/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size +/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size * @{ */ -#define FMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U -#define FMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U -#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U -#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U -#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U -#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) /** * @} */ - + /** * @} - */ + */ +#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */ -/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller +#if defined(FMC_Bank5_6) +/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller * @{ */ /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank * @{ */ -#define FMC_SDRAM_BANK1 0x00000000U -#define FMC_SDRAM_BANK2 0x00000001U +#define FMC_SDRAM_BANK1 (0x00000000U) +#define FMC_SDRAM_BANK2 (0x00000001U) /** * @} */ -/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number +/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number * @{ */ -#define FMC_SDRAM_COLUMN_BITS_NUM_8 0x00000000U -#define FMC_SDRAM_COLUMN_BITS_NUM_9 0x00000001U -#define FMC_SDRAM_COLUMN_BITS_NUM_10 0x00000002U -#define FMC_SDRAM_COLUMN_BITS_NUM_11 0x00000003U +#define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) /** * @} */ @@ -600,9 +808,9 @@ typedef struct /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number * @{ */ -#define FMC_SDRAM_ROW_BITS_NUM_11 0x00000000U -#define FMC_SDRAM_ROW_BITS_NUM_12 0x00000004U -#define FMC_SDRAM_ROW_BITS_NUM_13 0x00000008U +#define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) +#define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) +#define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) /** * @} */ @@ -610,9 +818,9 @@ typedef struct /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width * @{ */ -#define FMC_SDRAM_MEM_BUS_WIDTH_8 0x00000000U -#define FMC_SDRAM_MEM_BUS_WIDTH_16 0x00000010U -#define FMC_SDRAM_MEM_BUS_WIDTH_32 0x00000020U +#define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -620,8 +828,8 @@ typedef struct /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number * @{ */ -#define FMC_SDRAM_INTERN_BANKS_NUM_2 0x00000000U -#define FMC_SDRAM_INTERN_BANKS_NUM_4 0x00000040U +#define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) /** * @} */ @@ -629,9 +837,9 @@ typedef struct /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency * @{ */ -#define FMC_SDRAM_CAS_LATENCY_1 0x00000080U -#define FMC_SDRAM_CAS_LATENCY_2 0x00000100U -#define FMC_SDRAM_CAS_LATENCY_3 0x00000180U +#define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) +#define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) +#define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) /** * @} */ @@ -639,9 +847,8 @@ typedef struct /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection * @{ */ -#define FMC_SDRAM_WRITE_PROTECTION_DISABLE 0x00000000U -#define FMC_SDRAM_WRITE_PROTECTION_ENABLE 0x00000200U - +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) /** * @} */ @@ -649,9 +856,9 @@ typedef struct /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period * @{ */ -#define FMC_SDRAM_CLOCK_DISABLE 0x00000000U -#define FMC_SDRAM_CLOCK_PERIOD_2 0x00000800U -#define FMC_SDRAM_CLOCK_PERIOD_3 0x00000C00U +#define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) +#define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) +#define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) /** * @} */ @@ -659,18 +866,18 @@ typedef struct /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst * @{ */ -#define FMC_SDRAM_RBURST_DISABLE 0x00000000U -#define FMC_SDRAM_RBURST_ENABLE 0x00001000U +#define FMC_SDRAM_RBURST_DISABLE (0x00000000U) +#define FMC_SDRAM_RBURST_ENABLE (0x00001000U) /** * @} */ - + /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay * @{ */ -#define FMC_SDRAM_RPIPE_DELAY_0 0x00000000U -#define FMC_SDRAM_RPIPE_DELAY_1 0x00002000U -#define FMC_SDRAM_RPIPE_DELAY_2 0x00004000U +#define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) +#define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) +#define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) /** * @} */ @@ -678,13 +885,13 @@ typedef struct /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode * @{ */ -#define FMC_SDRAM_CMD_NORMAL_MODE 0x00000000U -#define FMC_SDRAM_CMD_CLK_ENABLE 0x00000001U -#define FMC_SDRAM_CMD_PALL 0x00000002U -#define FMC_SDRAM_CMD_AUTOREFRESH_MODE 0x00000003U -#define FMC_SDRAM_CMD_LOAD_MODE 0x00000004U -#define FMC_SDRAM_CMD_SELFREFRESH_MODE 0x00000005U -#define FMC_SDRAM_CMD_POWERDOWN_MODE 0x00000006U +#define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) +#define FMC_SDRAM_CMD_PALL (0x00000002U) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) +#define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) +#define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) /** * @} */ @@ -692,75 +899,62 @@ typedef struct /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target * @{ */ -#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 -#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 -#define FMC_SDRAM_CMD_TARGET_BANK1_2 0x00000018U +#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 +#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 +#define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) /** * @} - */ + */ -/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status +/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status * @{ */ -#define FMC_SDRAM_NORMAL_MODE 0x00000000U -#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 -#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 +#define FMC_SDRAM_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 +#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 /** * @} - */ - + */ + /** * @} - */ + */ + +#endif /* FMC_Bank5_6 */ -/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition +/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition * @{ - */ -#define FMC_IT_RISING_EDGE 0x00000008U -#define FMC_IT_LEVEL 0x00000010U -#define FMC_IT_FALLING_EDGE 0x00000020U -#define FMC_IT_REFRESH_ERROR 0x00004000U + */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) +#define FMC_IT_RISING_EDGE (0x00000008U) +#define FMC_IT_LEVEL (0x00000010U) +#define FMC_IT_FALLING_EDGE (0x00000020U) +#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */ +#if defined(FMC_Bank5_6) +#define FMC_IT_REFRESH_ERROR (0x00004000U) +#endif /* FMC_Bank5_6 */ /** * @} */ - -/** @defgroup FMC_LL_Flag_definition FMC Flag definition + +/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition * @{ - */ -#define FMC_FLAG_RISING_EDGE 0x00000001U -#define FMC_FLAG_LEVEL 0x00000002U -#define FMC_FLAG_FALLING_EDGE 0x00000004U -#define FMC_FLAG_FEMPT 0x00000040U + */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4) +#define FMC_FLAG_RISING_EDGE (0x00000001U) +#define FMC_FLAG_LEVEL (0x00000002U) +#define FMC_FLAG_FALLING_EDGE (0x00000004U) +#define FMC_FLAG_FEMPT (0x00000040U) +#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */ +#if defined(FMC_Bank5_6) #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE +#endif /* FMC_Bank5_6 */ /** * @} */ -/** @defgroup FMC_LL_Alias_definition FMC Alias definition - * @{ - */ -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #define FMC_NAND_TypeDef FMC_Bank3_TypeDef -#else - #define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef - #define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ - #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef - #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef - #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef - - -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) - #define FMC_NAND_DEVICE FMC_Bank3 -#else - #define FMC_NAND_DEVICE FMC_Bank2_3 - #define FMC_PCCARD_DEVICE FMC_Bank4 -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ - #define FMC_NORSRAM_DEVICE FMC_Bank1 - #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E - #define FMC_SDRAM_DEVICE FMC_Bank5_6 /** * @} */ @@ -770,291 +964,282 @@ typedef struct */ /* Private macro -------------------------------------------------------------*/ -/** @defgroup FMC_LL_Private_Macros FMC Private Macros +/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros * @{ */ - +#if defined(FMC_Bank1) /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros - * @brief macros to handle NOR device enable/disable and read/write operations - * @{ - */ + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ + /** * @brief Enable the NORSRAM device access. * @param __INSTANCE__ FMC_NORSRAM Instance - * @param __BANK__ FMC_NORSRAM Bank + * @param __BANK__ FMC_NORSRAM Bank * @retval None - */ -#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN) + */ +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FMC_BCR1_MBKEN) /** * @brief Disable the NORSRAM device access. * @param __INSTANCE__ FMC_NORSRAM Instance - * @param __BANK__ FMC_NORSRAM Bank + * @param __BANK__ FMC_NORSRAM Bank * @retval None - */ -#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN) + */ +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FMC_BCR1_MBKEN) + /** * @} - */ + */ +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Enable the NAND device access. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @retval None - */ -#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) - -/** - * @brief Disable the NAND device access. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @retval None + * @brief macros to handle NAND device enable/disable + * @{ */ -#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN) -#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ + /** * @brief Enable the NAND device access. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank + * @param __BANK__ FMC_NAND Bank * @retval None - */ + */ +#if defined(FMC_Bank2_3) +#if defined (FMC_PCR_PBKEN) +#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) +#else #define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN)) + ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN)) +#endif /* FMC_PCR_PBKEN */ +#else +#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN) +#endif /* FMC_Bank2_3 */ /** * @brief Disable the NAND device access. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank + * @param __BANK__ FMC_NAND Bank * @retval None */ -#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN)) +#if defined(FMC_Bank2_3) +#if defined (FMC_PCR_PBKEN) +#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) +#else +#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCR2_PBKEN): \ + CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCR3_PBKEN)) +#endif /* FMC_PCR_PBKEN */ +#else +#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN) +#endif /* FMC_Bank2_3 */ -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ /** * @} - */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + */ +#endif /* FMC_Bank3 || FMC_Bank2_3 */ + +#if defined(FMC_Bank4) /** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros - * @brief macros to handle SRAM read/write operations - * @{ - */ + * @brief macros to handle PCCARD read/write operations + * @{ + */ /** * @brief Enable the PCCARD device access. - * @param __INSTANCE__ FMC_PCCARD Instance + * @param __INSTANCE__ FMC_PCCARD Instance * @retval None - */ + */ #define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN) /** * @brief Disable the PCCARD device access. - * @param __INSTANCE__ FMC_PCCARD Instance + * @param __INSTANCE__ FMC_PCCARD Instance * @retval None - */ + */ #define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN) /** * @} */ -#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ - -/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros - * @brief macros to handle FMC flags and interrupts - * @{ - */ -#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -/** - * @brief Enable the NAND device interrupt. - * @param __INSTANCE__ FMC_NAND instance - * @param __BANK__ FMC_NAND Bank - * @param __INTERRUPT__ FMC_NAND interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None - */ -#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) -/** - * @brief Disable the NAND device interrupt. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @param __INTERRUPT__ FMC_NAND interrupt - * This parameter can be any combination of the following values: - * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. - * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. - * @retval None +#endif +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) +/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt + * @brief macros to handle NAND interrupts + * @{ */ -#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) -/** - * @brief Get flag status of the NAND device. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @param __FLAG__ FMC_NAND flag - * This parameter can be any combination of the following values: - * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) -/** - * @brief Clear flag status of the NAND device. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @param __FLAG__ FMC_NAND flag - * This parameter can be any combination of the following values: - * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. - * @retval None - */ -#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) -#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ /** * @brief Enable the NAND device interrupt. * @param __INSTANCE__ FMC_NAND instance - * @param __BANK__ FMC_NAND Bank - * @param __INTERRUPT__ FMC_NAND interrupt + * @param __BANK__ FMC_NAND Bank + * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None - */ + */ +#if defined(FMC_Bank2_3) #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) + ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) +#else +#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__)) +#endif /* FMC_Bank2_3 */ /** * @brief Disable the NAND device interrupt. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank + * @param __BANK__ FMC_NAND Bank * @param __INTERRUPT__ FMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ +#if defined(FMC_Bank2_3) #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) + ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) +#else +#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__)) +#endif /* FMC_Bank2_3 */ /** * @brief Get flag status of the NAND device. * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @param __FLAG__ FMC_NAND flag + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ +#if defined(FMC_Bank2_3) #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ - (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) + (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) +#else +#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__)) +#endif /* FMC_Bank2_3 */ + /** * @brief Clear flag status of the NAND device. - * @param __INSTANCE__ FMC_NAND Instance - * @param __BANK__ FMC_NAND Bank - * @param __FLAG__ FMC_NAND flag + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ +#if defined(FMC_Bank2_3) #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ - ((__INSTANCE__)->SR3 &= ~(__FLAG__))) -#endif /* defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) */ + ((__INSTANCE__)->SR3 &= ~(__FLAG__))) +#else +#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__)) +#endif /* FMC_Bank2_3 */ + +/** + * @} + */ +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + +#if defined(FMC_Bank4) +/** @defgroup FMC_LL_PCCARD_Interrupt FMC PCCARD Interrupt + * @brief macros to handle PCCARD interrupts + * @{ + */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) /** * @brief Enable the PCCARD device interrupt. - * @param __INSTANCE__ FMC_PCCARD instance - * @param __INTERRUPT__ FMC_PCCARD interrupt + * @param __INSTANCE__ FMC_PCCARD instance + * @param __INTERRUPT__ FMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None - */ + */ #define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) /** * @brief Disable the PCCARD device interrupt. - * @param __INSTANCE__ FMC_PCCARD instance - * @param __INTERRUPT__ FMC_PCCARD interrupt + * @param __INSTANCE__ FMC_PCCARD instance + * @param __INTERRUPT__ FMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FMC_IT_LEVEL: Interrupt level. - * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. + * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None - */ -#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) + */ +#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) /** * @brief Get flag status of the PCCARD device. - * @param __INSTANCE__ FMC_PCCARD instance + * @param __INSTANCE__ FMC_PCCARD instance * @param __FLAG__ FMC_PCCARD flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ #define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) /** * @brief Clear flag status of the PCCARD device. - * @param __INSTANCE__ FMC_PCCARD instance + * @param __INSTANCE__ FMC_PCCARD instance * @param __FLAG__ FMC_PCCARD flag * This parameter can be any combination of the following values: * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FMC_FLAG_LEVEL: Interrupt level edge flag. * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @arg FMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ #define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) -#endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ + +/** + * @} + */ +#endif + +#if defined(FMC_Bank5_6) +/** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt + * @brief macros to handle SDRAM interrupts + * @{ + */ /** * @brief Enable the SDRAM device interrupt. - * @param __INSTANCE__ FMC_SDRAM instance - * @param __INTERRUPT__ FMC_SDRAM interrupt + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt * This parameter can be any combination of the following values: - * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error * @retval None */ #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) /** * @brief Disable the SDRAM device interrupt. - * @param __INSTANCE__ FMC_SDRAM instance - * @param __INTERRUPT__ FMC_SDRAM interrupt + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt * This parameter can be any combination of the following values: - * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error * @retval None */ #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) /** * @brief Get flag status of the SDRAM device. - * @param __INSTANCE__ FMC_SDRAM instance - * @param __FLAG__ FMC_SDRAM flag + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag * This parameter can be any combination of the following values: * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. @@ -1065,236 +1250,52 @@ typedef struct /** * @brief Clear flag status of the SDRAM device. - * @param __INSTANCE__ FMC_SDRAM instance - * @param __FLAG__ FMC_SDRAM flag + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag * This parameter can be any combination of the following values: * @arg FMC_SDRAM_FLAG_REFRESH_ERROR * @retval None */ #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) + /** * @} */ - -/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros - * @{ - */ -#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \ - ((BANK) == FMC_NORSRAM_BANK2) || \ - ((BANK) == FMC_NORSRAM_BANK3) || \ - ((BANK) == FMC_NORSRAM_BANK4)) - -#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) - -#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) - -#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32)) - -#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ - ((__MODE__) == FMC_ACCESS_MODE_B) || \ - ((__MODE__) == FMC_ACCESS_MODE_C) || \ - ((__MODE__) == FMC_ACCESS_MODE_D)) - -#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) || \ - ((BANK) == FMC_NAND_BANK3)) - -#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE)) - -#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ - ((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16)) - -#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \ - ((STATE) == FMC_NAND_ECC_ENABLE)) - -#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) - -#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U) - -#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) - -#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) - -#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) - -#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE) - -#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) - -#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FMC_WRAP_MODE_ENABLE)) -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - -#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) - -#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) - -#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) - -#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) - -#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) - -#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FMC_WRITE_BURST_ENABLE)) - -#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) - -#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) - -#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) - -#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) - -#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) - -#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) - -#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U)) - -#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \ - ((BANK) == FMC_SDRAM_BANK2)) - -#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ - ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ - ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ - ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11)) - -#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \ - ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \ - ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13)) - -#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ - ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \ - ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32)) - -#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ - ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4)) - - -#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \ - ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \ - ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3)) - -#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) || \ - ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) || \ - ((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3)) - -#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) || \ - ((RBURST) == FMC_SDRAM_RBURST_ENABLE)) - - -#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) || \ - ((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) || \ - ((DELAY) == FMC_SDRAM_RPIPE_DELAY_2)) - -#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U)) - -#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U)) - -#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U)) - -#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U)) - -#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U)) - -#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U)) - -#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U)) - -#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) || \ - ((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) || \ - ((COMMAND) == FMC_SDRAM_CMD_PALL) || \ - ((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ - ((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) || \ - ((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ - ((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE)) - -#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) || \ - ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) || \ - ((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2)) - -#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U)) - -#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U) - -#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U) - -#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE) - -#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ - ((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) - -#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) || \ - ((SIZE) == FMC_PAGE_SIZE_128) || \ - ((SIZE) == FMC_PAGE_SIZE_256) || \ - ((SIZE) == FMC_PAGE_SIZE_512) || \ - ((SIZE) == FMC_PAGE_SIZE_1024)) - -#if defined (STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) -#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) || \ - ((FIFO) == FMC_WRITE_FIFO_ENABLE)) -#endif /* STM32F446xx || STM32F469xx || STM32F479xx */ - +#endif /* FMC_Bank5_6 */ /** * @} */ /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions * @{ */ +#if defined(FMC_Bank1) /** @defgroup FMC_LL_NORSRAM NOR SRAM * @{ */ -/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); +HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} - */ + */ -/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions +/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions * @{ */ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); @@ -1305,45 +1306,54 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** * @} */ +#endif /* FMC_Bank1 */ +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) /** @defgroup FMC_LL_NAND NAND * @{ */ -/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions +/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} */ -/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions +/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions * @{ */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); - +HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); /** * @} */ /** * @} */ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + +#if defined(FMC_Bank4) /** @defgroup FMC_LL_PCCARD PCCARD * @{ */ -/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions +/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions * @{ */ HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init); -HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, + FMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); /** * @} @@ -1351,29 +1361,33 @@ HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device); /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#endif /* FMC_Bank4 */ +#if defined(FMC_Bank5_6) /** @defgroup FMC_LL_SDRAM SDRAM * @{ */ -/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions +/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions * @{ */ HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); -HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} */ -/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions +/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions * @{ */ HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); +HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout); HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); -HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber); +HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber); uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank); /** * @} @@ -1381,12 +1395,12 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t B /** * @} */ +#endif /* FMC_Bank5_6 */ /** * @} */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -1394,10 +1408,9 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t B /** * @} */ + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_LL_FMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_LL_FMC_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmpi2c.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmpi2c.c index 7d7aeaaf828..04966ea0187 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmpi2c.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmpi2c.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -26,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ @@ -216,5 +215,3 @@ void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct) #endif /* FMPI2C_CR1_PE */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmpi2c.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmpi2c.h index 1f2e707b1a0..dcc001605ee 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmpi2c.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fmpi2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -70,38 +69,46 @@ typedef struct uint32_t PeripheralMode; /*!< Specifies the peripheral mode. This parameter can be a value of @ref FMPI2C_LL_EC_PERIPHERAL_MODE. - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetMode(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_SetMode(). */ uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. This parameter must be set by referring to the STM32CubeMX Tool and the helper macro @ref __LL_FMPI2C_CONVERT_TIMINGS(). - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetTiming(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_SetTiming(). */ uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. This parameter can be a value of @ref FMPI2C_LL_EC_ANALOGFILTER_SELECTION. - This feature can be modified afterwards using unitary functions @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */ + This feature can be modified afterwards using unitary functions + @ref LL_FMPI2C_EnableAnalogFilter() or LL_FMPI2C_DisableAnalogFilter(). */ uint32_t DigitalFilter; /*!< Configures the digital noise filter. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetDigitalFilter(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_SetDigitalFilter(). */ uint32_t OwnAddress1; /*!< Specifies the device own address 1. This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_SetOwnAddress1(). */ - uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive + match code or next received byte. This parameter can be a value of @ref FMPI2C_LL_EC_I2C_ACKNOWLEDGE. - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_AcknowledgeNextData(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_AcknowledgeNextData(). */ uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). This parameter can be a value of @ref FMPI2C_LL_EC_OWNADDRESS1. - This feature can be modified afterwards using unitary function @ref LL_FMPI2C_SetOwnAddress1(). */ + This feature can be modified afterwards using unitary function + @ref LL_FMPI2C_SetOwnAddress1(). */ } LL_FMPI2C_InitTypeDef; /** * @} @@ -171,10 +178,11 @@ typedef struct /** @defgroup FMPI2C_LL_EC_PERIPHERAL_MODE Peripheral Mode * @{ */ -#define LL_FMPI2C_MODE_I2C 0x00000000U /*!< FMPI2C Master or Slave mode */ -#define LL_FMPI2C_MODE_SMBUS_HOST FMPI2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ -#define LL_FMPI2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ -#define LL_FMPI2C_MODE_SMBUS_DEVICE_ARP FMPI2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ +#define LL_FMPI2C_MODE_I2C 0x00000000U /*!< FMPI2C Master or Slave mode */ +#define LL_FMPI2C_MODE_SMBUS_HOST FMPI2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ +#define LL_FMPI2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode + (Default address not acknowledge) */ +#define LL_FMPI2C_MODE_SMBUS_DEVICE_ARP FMPI2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ /** * @} */ @@ -209,14 +217,15 @@ typedef struct /** @defgroup FMPI2C_LL_EC_OWNADDRESS2 Own Address 2 Masks * @{ */ -#define LL_FMPI2C_OWNADDRESS2_NOMASK FMPI2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ -#define LL_FMPI2C_OWNADDRESS2_MASK01 FMPI2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK02 FMPI2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK03 FMPI2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK04 FMPI2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK05 FMPI2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK06 FMPI2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ -#define LL_FMPI2C_OWNADDRESS2_MASK07 FMPI2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/ +#define LL_FMPI2C_OWNADDRESS2_NOMASK FMPI2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ +#define LL_FMPI2C_OWNADDRESS2_MASK01 FMPI2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK02 FMPI2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK03 FMPI2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK04 FMPI2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK05 FMPI2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK06 FMPI2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ +#define LL_FMPI2C_OWNADDRESS2_MASK07 FMPI2C_OAR2_OA2MASK07 /*!< No comparison is done. + All Address2 are acknowledged. */ /** * @} */ @@ -251,14 +260,21 @@ typedef struct /** @defgroup FMPI2C_LL_EC_MODE Transfer End Mode * @{ */ -#define LL_FMPI2C_MODE_RELOAD FMPI2C_CR2_RELOAD /*!< Enable FMPI2C Reload mode. */ -#define LL_FMPI2C_MODE_AUTOEND FMPI2C_CR2_AUTOEND /*!< Enable FMPI2C Automatic end mode with no HW PEC comparison. */ -#define LL_FMPI2C_MODE_SOFTEND 0x00000000U /*!< Enable FMPI2C Software end mode with no HW PEC comparison. */ -#define LL_FMPI2C_MODE_SMBUS_RELOAD LL_FMPI2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC LL_FMPI2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC LL_FMPI2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ -#define LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_AUTOEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_SOFTEND | FMPI2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */ +#define LL_FMPI2C_MODE_RELOAD FMPI2C_CR2_RELOAD /*!< Enable FMPI2C Reload mode. */ +#define LL_FMPI2C_MODE_AUTOEND FMPI2C_CR2_AUTOEND /*!< Enable FMPI2C Automatic end mode + with no HW PEC comparison. */ +#define LL_FMPI2C_MODE_SOFTEND 0x00000000U /*!< Enable FMPI2C Software end mode + with no HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_RELOAD LL_FMPI2C_MODE_RELOAD /*!< Enable FMPSMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_AUTOEND_NO_PEC LL_FMPI2C_MODE_AUTOEND /*!< Enable FMPSMBUS Automatic end mode + with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_SOFTEND_NO_PEC LL_FMPI2C_MODE_SOFTEND /*!< Enable FMPSMBUS Software end mode + with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_AUTOEND | FMPI2C_CR2_PECBYTE) +/*!< Enable FMPSMBUS Automatic end mode with HW PEC comparison. */ +#define LL_FMPI2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_FMPI2C_MODE_SOFTEND | FMPI2C_CR2_PECBYTE) +/*!< Enable FMPSMBUS Software end mode with HW PEC comparison. */ /** * @} */ @@ -266,14 +282,23 @@ typedef struct /** @defgroup FMPI2C_LL_EC_GENERATE Start And Stop Generation * @{ */ -#define LL_FMPI2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ -#define LL_FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ -#define LL_FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Start for read request. */ -#define LL_FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Start for write request. */ -#define LL_FMPI2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ +#define LL_FMPI2C_GENERATE_NOSTARTSTOP 0x00000000U +/*!< Don't Generate Stop and Start condition. */ +#define LL_FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) +/*!< Generate Stop condition (Size should be set to 0). */ +#define LL_FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) +/*!< Generate Start for read request. */ +#define LL_FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) +/*!< Generate Start for write request. */ +#define LL_FMPI2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) +/*!< Generate Restart for read request, slave 7Bit address. */ +#define LL_FMPI2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) +/*!< Generate Restart for write request, slave 7Bit address. */ +#define LL_FMPI2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | \ + FMPI2C_CR2_RD_WRN | FMPI2C_CR2_HEAD10R) +/*!< Generate Restart for read request, slave 10Bit address. */ +#define LL_FMPI2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) +/*!< Generate Restart for write request, slave 10Bit address.*/ /** * @} */ @@ -281,8 +306,10 @@ typedef struct /** @defgroup FMPI2C_LL_EC_DIRECTION Read Write Direction * @{ */ -#define LL_FMPI2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ -#define LL_FMPI2C_DIRECTION_READ FMPI2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ +#define LL_FMPI2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, + slave enters receiver mode. */ +#define LL_FMPI2C_DIRECTION_READ FMPI2C_ISR_DIR /*!< Read transfer request by master, + slave enters transmitter mode.*/ /** * @} */ @@ -290,8 +317,10 @@ typedef struct /** @defgroup FMPI2C_LL_EC_DMA_REG_DATA DMA Register Data * @{ */ -#define LL_FMPI2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_FMPI2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +#define LL_FMPI2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for + transmission */ +#define LL_FMPI2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for + reception */ /** * @} */ @@ -299,8 +328,10 @@ typedef struct /** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout * @{ */ -#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ -#define LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH FMPI2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ +#define LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect + SCL low level timeout. */ +#define LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH FMPI2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect + both SCL and SDA high level timeout.*/ /** * @} */ @@ -308,9 +339,12 @@ typedef struct /** @defgroup FMPI2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection * @{ */ -#define LL_FMPI2C_SMBUS_TIMEOUTA FMPI2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ -#define LL_FMPI2C_SMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ -#define LL_FMPI2C_SMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ +#define LL_FMPI2C_FMPSMBUS_TIMEOUTA FMPI2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ +#define LL_FMPI2C_FMPSMBUS_TIMEOUTB FMPI2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) + enable bit */ +#define LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT (uint32_t)(FMPI2C_TIMEOUTR_TIMOUTEN | \ + FMPI2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB +(extended clock) enable bits */ /** * @} */ @@ -354,18 +388,22 @@ typedef struct /** * @brief Configure the SDA setup, hold time and the SCL high, low period. * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc) - * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc) - * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc) - * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc) + * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tscldel = (SCLDEL+1)xtpresc) + * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. + (tsdadel = SDADELxtpresc) + * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tsclh = (SCLH+1)xtpresc) + * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. + (tscll = (SCLL+1)xtpresc) * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF */ -#define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \ - (((uint32_t)(__DATA_SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__DATA_HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__CLOCK_HIGH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \ - (((uint32_t)(__CLOCK_LOW_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL)) +#define __LL_FMPI2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ + ((((uint32_t)(__PRESCALER__) << FMPI2C_TIMINGR_PRESC_Pos) & FMPI2C_TIMINGR_PRESC) | \ + (((uint32_t)(__SETUP_TIME__) << FMPI2C_TIMINGR_SCLDEL_Pos) & FMPI2C_TIMINGR_SCLDEL) | \ + (((uint32_t)(__HOLD_TIME__) << FMPI2C_TIMINGR_SDADEL_Pos) & FMPI2C_TIMINGR_SDADEL) | \ + (((uint32_t)(__SCLH_PERIOD__) << FMPI2C_TIMINGR_SCLH_Pos) & FMPI2C_TIMINGR_SCLH) | \ + (((uint32_t)(__SCLL_PERIOD__) << FMPI2C_TIMINGR_SCLL_Pos) & FMPI2C_TIMINGR_SCLL)) /** * @} */ @@ -429,7 +467,8 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabled(FMPI2C_TypeDef *FMPI2Cx) * @param AnalogFilter This parameter can be one of the following values: * @arg @ref LL_FMPI2C_ANALOGFILTER_ENABLE * @arg @ref LL_FMPI2C_ANALOGFILTER_DISABLE - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk). + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk. * @retval None @@ -445,7 +484,8 @@ __STATIC_INLINE void LL_FMPI2C_ConfigFilters(FMPI2C_TypeDef *FMPI2Cx, uint32_t A * This filter can only be programmed when the FMPI2C is disabled (PE = 0). * @rmtoll CR1 DNF LL_FMPI2C_SetDigitalFilter * @param FMPI2Cx FMPI2C Instance. - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk). + * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) + and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*tfmpi2cclk). * This parameter is used to configure the digital noise filter on SDA and SCL input. * The digital filter will filter spikes with a length of up to DNF[3:0]*tfmpi2cclk. * @retval None @@ -663,7 +703,6 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSlaveByteControl(FMPI2C_TypeDef *FMP return ((READ_BIT(FMPI2Cx->CR1, FMPI2C_CR1_SBC) == (FMPI2C_CR1_SBC)) ? 1UL : 0UL); } - /** * @brief Enable General Call. * @note When enabled the Address 0x00 is ACKed. @@ -903,7 +942,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetDataSetupTime(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Configure peripheral mode. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 SMBHEN LL_FMPI2C_SetMode\n * CR1 SMBDEN LL_FMPI2C_SetMode @@ -922,7 +961,7 @@ __STATIC_INLINE void LL_FMPI2C_SetMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t Periphe /** * @brief Get peripheral mode. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 SMBHEN LL_FMPI2C_GetMode\n * CR1 SMBDEN LL_FMPI2C_GetMode @@ -940,7 +979,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetMode(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable SMBus alert (Host or Device mode) - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is drived low and @@ -958,7 +997,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Disable SMBus alert (Host or Device mode) - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note SMBus Device mode: * - SMBus Alert pin is not drived (can be used as a standard GPIO) and @@ -976,7 +1015,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 ALERTEN LL_FMPI2C_IsEnabledSMBusAlert * @param FMPI2Cx FMPI2C Instance. @@ -989,7 +1028,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusAlert(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable SMBus Packet Error Calculation (PEC). - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 PECEN LL_FMPI2C_EnableSMBusPEC * @param FMPI2Cx FMPI2C Instance. @@ -1002,7 +1041,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Disable SMBus Packet Error Calculation (PEC). - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 PECEN LL_FMPI2C_DisableSMBusPEC * @param FMPI2Cx FMPI2C Instance. @@ -1015,7 +1054,7 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR1 PECEN LL_FMPI2C_IsEnabledSMBusPEC * @param FMPI2Cx FMPI2C Instance. @@ -1028,7 +1067,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Configure the SMBus Clock Timeout. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_ConfigSMBusTimeout\n @@ -1037,8 +1076,8 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPEC(FMPI2C_TypeDef *FMPI2Cx) * @param FMPI2Cx FMPI2C Instance. * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. * @param TimeoutAMode This parameter can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH * @param TimeoutB * @retval None */ @@ -1051,7 +1090,7 @@ __STATIC_INLINE void LL_FMPI2C_ConfigSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint3 /** * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note These bits can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_SetSMBusTimeoutA @@ -1066,7 +1105,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx, uint32_ /** * @brief Get the SMBus Clock TimeoutA setting. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTA LL_FMPI2C_GetSMBusTimeoutA * @param FMPI2Cx FMPI2C Instance. @@ -1079,14 +1118,14 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutA(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Set the SMBus Clock TimeoutA mode. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note This bit can only be programmed when TimeoutA is disabled. * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_SetSMBusTimeoutAMode * @param FMPI2Cx FMPI2C Instance. * @param TimeoutAMode This parameter can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH * @retval None */ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uint32_t TimeoutAMode) @@ -1096,13 +1135,13 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx, uin /** * @brief Get the SMBus Clock TimeoutA mode. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIDLE LL_FMPI2C_GetSMBusTimeoutAMode * @param FMPI2Cx FMPI2C Instance. * @retval Returned value can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SCL_LOW + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH */ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx) { @@ -1111,7 +1150,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutAMode(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note These bits can only be programmed when TimeoutB is disabled. * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_SetSMBusTimeoutB @@ -1126,7 +1165,7 @@ __STATIC_INLINE void LL_FMPI2C_SetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx, uint32_ /** * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMEOUTB LL_FMPI2C_GetSMBusTimeoutB * @param FMPI2Cx FMPI2C Instance. @@ -1139,15 +1178,15 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetSMBusTimeoutB(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable the SMBus Clock Timeout. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_EnableSMBusTimeout\n * TIMEOUTR TEXTEN LL_FMPI2C_EnableSMBusTimeout * @param FMPI2Cx FMPI2C Instance. * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB - * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTB + * @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT * @retval None */ __STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) @@ -1157,15 +1196,15 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint3 /** * @brief Disable the SMBus Clock Timeout. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_DisableSMBusTimeout\n * TIMEOUTR TEXTEN LL_FMPI2C_DisableSMBusTimeout * @param FMPI2Cx FMPI2C Instance. * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB - * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTB + * @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT * @retval None */ __STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) @@ -1175,20 +1214,21 @@ __STATIC_INLINE void LL_FMPI2C_DisableSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint /** * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll TIMEOUTR TIMOUTEN LL_FMPI2C_IsEnabledSMBusTimeout\n * TIMEOUTR TEXTEN LL_FMPI2C_IsEnabledSMBusTimeout * @param FMPI2Cx FMPI2C Instance. * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTA - * @arg @ref LL_FMPI2C_SMBUS_TIMEOUTB - * @arg @ref LL_FMPI2C_SMBUS_ALL_TIMEOUT + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTA + * @arg @ref LL_FMPI2C_FMPSMBUS_TIMEOUTB + * @arg @ref LL_FMPI2C_FMPSMBUS_ALL_TIMEOUT * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusTimeout(FMPI2C_TypeDef *FMPI2Cx, uint32_t ClockTimeout) { - return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL); + return ((READ_BIT(FMPI2Cx->TIMEOUTR, (FMPI2C_TIMEOUTR_TIMOUTEN | FMPI2C_TIMEOUTR_TEXTEN)) == \ + (ClockTimeout)) ? 1UL : 0UL); } /** @@ -1405,7 +1445,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledIT_TC(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable Error interrupts. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1425,7 +1465,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableIT_ERR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Disable Error interrupts. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note Any of these errors will generate interrupt : * Arbitration Loss (ARLO) @@ -1607,7 +1647,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note RESET: Clear default value. * SET: When the received PEC does not match with the PEC register content. @@ -1622,7 +1662,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI /** * @brief Indicate the status of SMBus Timeout detection flag. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note RESET: Clear default value. * SET: When a timeout or extended clock timeout occurs. @@ -1637,7 +1677,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsActiveSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMP /** * @brief Indicate the status of SMBus alert flag. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @note RESET: Clear default value. * SET: When SMBus host configuration, SMBus alert enabled and @@ -1744,7 +1784,7 @@ __STATIC_INLINE void LL_FMPI2C_ClearFlag_OVR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Clear SMBus PEC error flag. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll ICR PECCF LL_FMPI2C_ClearSMBusFlag_PECERR * @param FMPI2Cx FMPI2C Instance. @@ -1757,7 +1797,7 @@ __STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_PECERR(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Clear SMBus Timeout detection flag. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll ICR TIMOUTCF LL_FMPI2C_ClearSMBusFlag_TIMEOUT * @param FMPI2Cx FMPI2C Instance. @@ -1770,7 +1810,7 @@ __STATIC_INLINE void LL_FMPI2C_ClearSMBusFlag_TIMEOUT(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Clear SMBus Alert flag. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll ICR ALERTCF LL_FMPI2C_ClearSMBusFlag_ALERT * @param FMPI2Cx FMPI2C Instance. @@ -1885,7 +1925,8 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetTransferSize(FMPI2C_TypeDef *FMPI2Cx) } /** - * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code + or next received byte. * @note Usage in Slave mode only. * @rmtoll CR2 NACK LL_FMPI2C_AcknowledgeNextData * @param FMPI2Cx FMPI2C Instance. @@ -1926,7 +1967,8 @@ __STATIC_INLINE void LL_FMPI2C_GenerateStopCondition(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). * @note The master sends the complete 10bit slave address read sequence : - * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction. + * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address + in Read direction. * @rmtoll CR2 HEAD10R LL_FMPI2C_EnableAuto10BitRead * @param FMPI2Cx FMPI2C Instance. * @retval None @@ -2087,9 +2129,10 @@ __STATIC_INLINE uint32_t LL_FMPI2C_GetAddressMatchCode(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. - * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. + * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition + or an Address Matched is received. * This bit has no effect when RELOAD bit is set. * This bit has no effect in device mode when SBC bit is not set. * @rmtoll CR2 PECBYTE LL_FMPI2C_EnableSMBusPECCompare @@ -2103,7 +2146,7 @@ __STATIC_INLINE void LL_FMPI2C_EnableSMBusPECCompare(FMPI2C_TypeDef *FMPI2Cx) /** * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll CR2 PECBYTE LL_FMPI2C_IsEnabledSMBusPECCompare * @param FMPI2Cx FMPI2C Instance. @@ -2116,7 +2159,7 @@ __STATIC_INLINE uint32_t LL_FMPI2C_IsEnabledSMBusPECCompare(FMPI2C_TypeDef *FMPI /** * @brief Get the SMBus Packet Error byte calculated. - * @note Macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not + * @note The macro IS_FMPSMBUS_ALL_INSTANCE(FMPI2Cx) can be used to check whether or not * SMBus feature is supported by the FMPI2Cx Instance. * @rmtoll PECR PEC LL_FMPI2C_GetSMBusPEC * @param FMPI2Cx FMPI2C Instance. @@ -2189,5 +2232,3 @@ void LL_FMPI2C_StructInit(LL_FMPI2C_InitTypeDef *FMPI2C_InitStruct); #endif #endif /* STM32F4xx_LL_FMPI2C_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.c index 98681374448..8172871fa61 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.c @@ -3,55 +3,55 @@ * @file stm32f4xx_ll_fsmc.c * @author MCD Application Team * @brief FSMC Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: + * + * This file provides firmware functions to manage the following + * functionalities of the Flexible Memory Controller (FSMC) peripheral memories: * + Initialization/de-initialization functions - * + Peripheral Control functions + * + Peripheral Control functions * + Peripheral State functions - * - @verbatim - ============================================================================== - ##### FSMC peripheral features ##### - ============================================================================== - [..] The Flexible static memory controller (FSMC) includes two memory controllers: - (+) The NOR/PSRAM memory controller - (+) The NAND/PC Card memory controller - - [..] The FSMC functional block makes the interface with synchronous and asynchronous static - memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: - (+) to translate AHB transactions into the appropriate external device protocol. - (+) to meet the access time requirements of the external memory devices. - - [..] All external memories share the addresses, data and control signals with the controller. - Each external device is accessed by means of a unique Chip Select. The FSMC performs - only one access at a time to an external device. - The main features of the FSMC controller are the following: - (+) Interface with static-memory mapped devices including: - (++) Static random access memory (SRAM). - (++) Read-only memory (ROM). - (++) NOR Flash memory/OneNAND Flash memory. - (++) PSRAM (4 memory banks). - (++) 16-bit PC Card compatible devices. - (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of - data. - (+) Independent Chip Select control for each memory bank. - (+) Independent configuration for each memory bank. - - @endverbatim + * ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + @verbatim + ============================================================================== + ##### FSMC peripheral features ##### + ============================================================================== + [..] The Flexible memory controller (FSMC) includes following memory controllers: + (+) The NOR/PSRAM memory controller + (+) The NAND/PC Card memory controller + + [..] The FSMC functional block makes the interface with synchronous and asynchronous static + memories and 16-bit PC memory cards. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FSMC performs + only one access at a time to an external device. + The main features of the FSMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) 16-bit PC Card compatible devices + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + data + (+) Independent Chip Select control for each memory bank + (+) Independent configuration for each memory bank + + @endverbatim + ****************************************************************************** + */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal.h" @@ -59,41 +59,131 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ +#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) /** @defgroup FSMC_LL FSMC Low Layer * @brief FSMC driver modules * @{ */ -#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + +/** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants + * @{ + */ + +/* ----------------------- FSMC registers bit mask --------------------------- */ + +#if defined(FSMC_Bank1) +/* --- BCR Register ---*/ +/* BCR register clear mask */ + +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD |\ + FSMC_BTR1_DATAST | FSMC_BTR1_BUSTURN |\ + FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT |\ + FSMC_BTR1_ACCMOD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD |\ + FSMC_BWTR1_DATAST | FSMC_BWTR1_BUSTURN |\ + FSMC_BWTR1_ACCMOD)) +#endif /* FSMC_Bank1 */ +#if defined(FSMC_Bank2_3) + +#if defined (FSMC_PCR_PWAITEN) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCR_PWAITEN | FSMC_PCR_PBKEN | \ + FSMC_PCR_PTYP | FSMC_PCR_PWID | \ + FSMC_PCR_ECCEN | FSMC_PCR_TCLR | \ + FSMC_PCR_TAR | FSMC_PCR_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEM_MEMSET2 | FSMC_PMEM_MEMWAIT2 |\ + FSMC_PMEM_MEMHOLD2 | FSMC_PMEM_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATT_ATTSET2 | FSMC_PATT_ATTWAIT2 |\ + FSMC_PATT_ATTHOLD2 | FSMC_PATT_ATTHIZ2)) +#else +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | \ + FSMC_PCR2_PTYP | FSMC_PCR2_PWID | \ + FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \ + FSMC_PCR2_TAR | FSMC_PCR2_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 |\ + FSMC_PMEM2_MEMHOLD2 | FSMC_PMEM2_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 |\ + FSMC_PATT2_ATTHOLD2 | FSMC_PATT2_ATTHIZ2)) + +#endif /* FSMC_PCR_PWAITEN */ +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR4_CLEAR_MASK ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN | \ + FSMC_PCR4_PTYP | FSMC_PCR4_PWID | \ + FSMC_PCR4_ECCEN | FSMC_PCR4_TCLR | \ + FSMC_PCR4_TAR | FSMC_PCR4_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM4_CLEAR_MASK ((uint32_t)(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 |\ + FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT4_CLEAR_MASK ((uint32_t)(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 |\ + FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4)) + +/* --- PIO4 Register ---*/ +/* PIO4 register clear mask */ +#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \ + FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4)) + +#endif /* FSMC_Bank4 */ + +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup FSMC_LL_Private_Functions +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions * @{ */ -/** @addtogroup FSMC_LL_NORSRAM - * @brief NORSRAM Controller functions +#if defined(FSMC_Bank1) + +/** @defgroup FSMC_LL_Exported_Functions_NORSRAM FSMC Low Layer NOR SRAM Exported Functions + * @brief NORSRAM Controller functions * - @verbatim + @verbatim ============================================================================== ##### How to use NORSRAM device driver ##### ============================================================================== - - [..] + + [..] This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order to run the NORSRAM external devices. - - (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() + + (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() - (+) FSMC NORSRAM bank extended timing configuration using the function + (+) FSMC NORSRAM bank extended timing configuration using the function FSMC_NORSRAM_Extended_Timing_Init() (+) FSMC NORSRAM bank enable/disable write operation using the functions FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() @@ -101,35 +191,38 @@ @endverbatim * @{ */ - -/** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1 - * @brief Initialization and Configuration functions + +/** @defgroup FSMC_LL_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * - @verbatim + @verbatim ============================================================================== ##### Initialization and de_initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: (+) Initialize and configure the FSMC NORSRAM interface - (+) De-initialize the FSMC NORSRAM interface - (+) Configure the FSMC clock and associated GPIOs - + (+) De-initialize the FSMC NORSRAM interface + (+) Configure the FSMC clock and associated GPIOs + @endverbatim * @{ */ - + /** * @brief Initialize the FSMC_NORSRAM device according to the specified * control parameters in the FSMC_NORSRAM_InitTypeDef * @param Device Pointer to NORSRAM device instance - * @param Init Pointer to NORSRAM Initialization structure + * @param Init Pointer to NORSRAM Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init) -{ - uint32_t tmpr = 0U; - +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_InitTypeDef *Init) +{ + uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; + /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); @@ -138,104 +231,115 @@ HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_ assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#if defined(FSMC_BCR1_WRAPMOD) assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#endif /* FSMC_BCR1_WRAPMOD */ assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); - assert_param(IS_FSMC_PAGESIZE(Init->PageSize)); -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) - assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo)); +#if defined(FSMC_BCR1_CCLKEN) assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock)); -#endif /* STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */ - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Init->NSBank]; - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT, CPSIZE and CBURSTRW bits */ - tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ - FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ - FSMC_BCR1_WAITPOL | FSMC_BCR1_WRAPMOD | FSMC_BCR1_WAITCFG | \ - FSMC_BCR1_WREN | FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | \ - FSMC_BCR1_ASYNCWAIT | FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW)); - /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WrapMode |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->PageSize |\ - Init->WriteBurst - ); -#else /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ - /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WAITCFG, WREN, - WAITEN, EXTMOD, ASYNCWAIT,CPSIZE, CBURSTRW, CCLKEN and WFDIS bits */ - tmpr &= ((uint32_t)~(FSMC_BCR1_MBKEN | FSMC_BCR1_MUXEN | FSMC_BCR1_MTYP | \ - FSMC_BCR1_MWID | FSMC_BCR1_FACCEN | FSMC_BCR1_BURSTEN | \ - FSMC_BCR1_WAITPOL | FSMC_BCR1_WAITCFG | FSMC_BCR1_WREN | \ - FSMC_BCR1_WAITEN | FSMC_BCR1_EXTMOD | FSMC_BCR1_ASYNCWAIT | \ - FSMC_BCR1_CPSIZE | FSMC_BCR1_CBURSTRW | FSMC_BCR1_CCLKEN | \ - FSMC_BCR1_WFDIS)); +#endif +#if defined(FSMC_BCR1_WFDIS) + assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo)); +#endif /* FSMC_BCR1_WFDIS */ + assert_param(IS_FSMC_PAGESIZE(Init->PageSize)); + + /* Disable NORSRAM Device */ + __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); + /* Set NORSRAM device control parameters */ - tmpr |= (uint32_t)(Init->DataAddressMux |\ - Init->MemoryType |\ - Init->MemoryDataWidth |\ - Init->BurstAccessMode |\ - Init->WaitSignalPolarity |\ - Init->WaitSignalActive |\ - Init->WriteOperation |\ - Init->WaitSignal |\ - Init->ExtendedMode |\ - Init->AsynchronousWait |\ - Init->WriteBurst |\ - Init->ContinuousClock |\ - Init->PageSize |\ - Init->WriteFifo); -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - - if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) + if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR) { - tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE; + flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE; } + else + { + flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE; + } + + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + +#if defined(FSMC_BCR1_WRAPMOD) + btcr_reg |= Init->WrapMode; +#endif /* FSMC_BCR1_WRAPMOD */ +#if defined(FSMC_BCR1_CCLKEN) + btcr_reg |= Init->ContinuousClock; +#endif /* FSMC_BCR1_CCLKEN */ +#if defined(FSMC_BCR1_WFDIS) + btcr_reg |= Init->WriteFifo; +#endif /* FSMC_BCR1_WFDIS */ + btcr_reg |= Init->PageSize; + + mask = (FSMC_BCR1_MBKEN | + FSMC_BCR1_MUXEN | + FSMC_BCR1_MTYP | + FSMC_BCR1_MWID | + FSMC_BCR1_FACCEN | + FSMC_BCR1_BURSTEN | + FSMC_BCR1_WAITPOL | + FSMC_BCR1_WAITCFG | + FSMC_BCR1_WREN | + FSMC_BCR1_WAITEN | + FSMC_BCR1_EXTMOD | + FSMC_BCR1_ASYNCWAIT | + FSMC_BCR1_CBURSTRW); - Device->BTCR[Init->NSBank] = tmpr; +#if defined(FSMC_BCR1_WRAPMOD) + mask |= FSMC_BCR1_WRAPMOD; +#endif /* FSMC_BCR1_WRAPMOD */ +#if defined(FSMC_BCR1_CCLKEN) + mask |= FSMC_BCR1_CCLKEN; +#endif +#if defined(FSMC_BCR1_WFDIS) + mask |= FSMC_BCR1_WFDIS; +#endif /* FSMC_BCR1_WFDIS */ + mask |= FSMC_BCR1_CPSIZE; -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) + MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); + +#if defined(FSMC_BCR1_CCLKEN) /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ - if((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1)) + if ((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1)) { - Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->ContinuousClock); + MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN, Init->ContinuousClock); } +#endif +#if defined(FSMC_BCR1_WFDIS) - if(Init->NSBank != FSMC_NORSRAM_BANK1) + if (Init->NSBank != FSMC_NORSRAM_BANK1) { - Device->BTCR[FSMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); + /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */ + SET_BIT(Device->BTCR[FSMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); } -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#endif /* FSMC_BCR1_WFDIS */ return HAL_OK; } /** - * @brief DeInitialize the FSMC_NORSRAM peripheral + * @brief DeInitialize the FSMC_NORSRAM peripheral * @param Device Pointer to NORSRAM device instance - * @param ExDevice Pointer to NORSRAM extended mode device instance - * @param Bank NORSRAM bank number + * @param ExDevice Pointer to NORSRAM extended mode device instance + * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); @@ -244,38 +348,40 @@ HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM /* Disable the FSMC_NORSRAM device */ __FSMC_NORSRAM_DISABLE(Device, Bank); - + /* De-initialize the FSMC_NORSRAM device */ /* FSMC_NORSRAM_BANK1 */ - if(Bank == FSMC_NORSRAM_BANK1) + if (Bank == FSMC_NORSRAM_BANK1) { - Device->BTCR[Bank] = 0x000030DBU; + Device->BTCR[Bank] = 0x000030DBU; } /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ else - { - Device->BTCR[Bank] = 0x000030D2U; + { + Device->BTCR[Bank] = 0x000030D2U; } - + Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; - ExDevice->BWTR[Bank] = 0x0FFFFFFFU; - + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; + return HAL_OK; } - /** * @brief Initialize the FSMC_NORSRAM Timing according to the specified * parameters in the FSMC_NORSRAM_TimingTypeDef * @param Device Pointer to NORSRAM device instance * @param Timing Pointer to NORSRAM Timing structure - * @param Bank NORSRAM bank number + * @param Bank NORSRAM bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; - +#if defined(FSMC_BCR1_CCLKEN) + uint32_t tmpr; +#endif + /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); @@ -286,36 +392,26 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - - /* Get the BTCR register value */ - tmpr = Device->BTCR[Bank + 1U]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ - tmpr &= ((uint32_t)~(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD | FSMC_BTR1_DATAST | \ - FSMC_BTR1_BUSTURN | FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT | \ - FSMC_BTR1_ACCMOD)); - - /* Set FSMC_NORSRAM device timing parameters */ - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4U) |\ - ((Timing->DataSetupTime) << 8U) |\ - ((Timing->BusTurnAroundDuration) << 16U) |\ - (((Timing->CLKDivision)-1U) << 20U) |\ - (((Timing->DataLatency)-2U) << 24U) |\ - (Timing->AccessMode)); - - Device->BTCR[Bank + 1] = tmpr; - -#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) + + /* Set FSMC_NORSRAM device timing parameters */ + MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FSMC_BTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FSMC_BTR1_DATAST_Pos) | + ((Timing->BusTurnAroundDuration) << FSMC_BTR1_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FSMC_BTR1_DATLAT_Pos) | + (Timing->AccessMode))); + +#if defined(FSMC_BCR1_CCLKEN) /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ - if(HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN)) + if (HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~(0x0FU << 20U)); - tmpr |= (uint32_t)(((Timing->CLKDivision)-1U) << 20U); - Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] = tmpr; + tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FSMC_BTR1_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos); + MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U], FSMC_BTR1_CLKDIV, tmpr); } -#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */ +#endif return HAL_OK; } @@ -324,18 +420,22 @@ HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NO * parameters in the FSMC_NORSRAM_TimingTypeDef * @param Device Pointer to NORSRAM device instance * @param Timing Pointer to NORSRAM Timing structure - * @param Bank NORSRAM bank number + * @param Bank NORSRAM bank number + * @param ExtendedMode FSMC Extended Mode + * This parameter can be one of the following values: + * @arg FSMC_EXTENDED_MODE_DISABLE + * @arg FSMC_EXTENDED_MODE_ENABLE * @retval HAL status */ -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) { - uint32_t tmpr = 0U; - /* Check the parameters */ assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); /* Set NORSRAM device timing register for write configuration, if extended mode is used */ - if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) + if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) { /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); @@ -345,37 +445,29 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - - /* Get the BWTR register value */ - tmpr = Device->BWTR[Bank]; - - /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ - tmpr &= ((uint32_t)~(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD | FSMC_BWTR1_DATAST | \ - FSMC_BWTR1_BUSTURN | FSMC_BWTR1_ACCMOD)); - - tmpr |= (uint32_t)(Timing->AddressSetupTime |\ - ((Timing->AddressHoldTime) << 4U) |\ - ((Timing->DataSetupTime) << 8U) |\ - ((Timing->BusTurnAroundDuration) << 16U) |\ - (Timing->AccessMode)); - - Device->BWTR[Bank] = tmpr; + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FSMC_BWTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FSMC_BWTR1_DATAST_Pos) | + Timing->AccessMode | + ((Timing->BusTurnAroundDuration) << FSMC_BWTR1_BUSTURN_Pos))); } - else + else { Device->BWTR[Bank] = 0x0FFFFFFFU; - } - - return HAL_OK; + } + + return HAL_OK; } /** * @} */ - + /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group2 - * @brief management functions + * @brief management functions * -@verbatim +@verbatim ============================================================================== ##### FSMC_NORSRAM Control functions ##### ============================================================================== @@ -386,11 +478,11 @@ HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeD @endverbatim * @{ */ - + /** * @brief Enables dynamically FSMC_NORSRAM write operation. * @param Device Pointer to NORSRAM device instance - * @param Bank NORSRAM bank number + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) @@ -400,15 +492,15 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Devic assert_param(IS_FSMC_NORSRAM_BANK(Bank)); /* Enable write operation */ - Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; + SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); - return HAL_OK; + return HAL_OK; } /** * @brief Disables dynamically FSMC_NORSRAM write operation. * @param Device Pointer to NORSRAM device instance - * @param Bank NORSRAM bank number + * @param Bank NORSRAM bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) @@ -416,12 +508,13 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi /* Check the parameters */ assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); assert_param(IS_FSMC_NORSRAM_BANK(Bank)); - + /* Disable write operation */ - Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; + CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); - return HAL_OK; + return HAL_OK; } + /** * @} */ @@ -429,50 +522,52 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi /** * @} */ +#endif /* FSMC_Bank1 */ + +#if defined(FSMC_Bank2_3) -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** @addtogroup FSMC_LL_NAND - * @brief NAND Controller functions +/** @defgroup FSMC_LL_Exported_Functions_NAND FSMC Low Layer NAND Exported Functions + * @brief NAND Controller functions * - @verbatim - ============================================================================== + @verbatim + ============================================================================== ##### How to use NAND device driver ##### ============================================================================== [..] This driver contains a set of APIs to interface with the FSMC NAND banks in order to run the NAND external devices. - - (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() + + (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init() - (+) FSMC NAND bank common space timing configuration using the function + (+) FSMC NAND bank common space timing configuration using the function FSMC_NAND_CommonSpace_Timing_Init() - (+) FSMC NAND bank attribute space timing configuration using the function + (+) FSMC NAND bank attribute space timing configuration using the function FSMC_NAND_AttributeSpace_Timing_Init() (+) FSMC NAND bank enable/disable ECC correction feature using the functions FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable() - (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC() + (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC() @endverbatim * @{ */ - -/** @addtogroup FSMC_LL_NAND_Private_Functions_Group1 - * @brief Initialization and Configuration functions + +/** @defgroup FSMC_LL_NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de_initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: (+) Initialize and configure the FSMC NAND interface - (+) De-initialize the FSMC NAND interface + (+) De-initialize the FSMC NAND interface (+) Configure the FSMC clock and associated GPIOs - + @endverbatim * @{ */ - + /** * @brief Initializes the FSMC_NAND device according to the specified * control parameters in the FSMC_NAND_HandleTypeDef @@ -482,53 +577,40 @@ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Devi */ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) { - uint32_t tmpr = 0U; - /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); + assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); - if(Init->NandBank == FSMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PCR2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PCR3; - } - - /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ - tmpr &= ((uint32_t)~(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | FSMC_PCR2_PTYP | \ - FSMC_PCR2_PWID | FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \ - FSMC_PCR2_TAR | FSMC_PCR2_ECCPS)); - /* Set NAND device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FSMC_PCR_MEMORY_TYPE_NAND |\ - Init->MemoryDataWidth |\ - Init->EccComputation |\ - Init->ECCPageSize |\ - ((Init->TCLRSetupTime) << 9U) |\ - ((Init->TARSetupTime) << 13U)); - - if(Init->NandBank == FSMC_NAND_BANK2) + if (Init->NandBank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PCR2 = tmpr; + MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | + FSMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) | + ((Init->TARSetupTime) << FSMC_PCR2_TAR_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PCR3 = tmpr; + MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | + FSMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) | + ((Init->TARSetupTime) << FSMC_PCR2_TAR_Pos))); } - + return HAL_OK; } @@ -537,53 +619,39 @@ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDe * parameters in the FSMC_NAND_PCC_TimingTypeDef * @param Device Pointer to NAND device instance * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number + * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; - /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - if(Bank == FSMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PMEM2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PMEM3; - } - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 | FSMC_PMEM2_MEMHOLD2 | \ - FSMC_PMEM2_MEMHIZ2)); - + assert_param(IS_FSMC_NAND_BANK(Bank)); + /* Set FSMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U) - ); - - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PMEM2 = tmpr; + MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PMEM3 = tmpr; - } - - return HAL_OK; + MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos))); + } + + return HAL_OK; } /** @@ -591,95 +659,86 @@ HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, F * parameters in the FSMC_NAND_PCC_TimingTypeDef * @param Device Pointer to NAND device instance * @param Timing Pointer to NAND timing structure - * @param Bank NAND bank number + * @param Bank NAND bank number * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) +HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { - uint32_t tmpr = 0U; - - /* Check the parameters */ + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); - - if(Bank == FSMC_NAND_BANK2) - { - /* Get the NAND bank 2 register value */ - tmpr = Device->PATT2; - } - else - { - /* Get the NAND bank 3 register value */ - tmpr = Device->PATT3; - } - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 | FSMC_PATT2_ATTHOLD2 | \ - FSMC_PATT2_ATTHIZ2)); - + assert_param(IS_FSMC_NAND_BANK(Bank)); + /* Set FSMC_NAND device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U) - ); - - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { /* NAND bank 2 registers configuration */ - Device->PATT2 = tmpr; + MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos))); } else { /* NAND bank 3 registers configuration */ - Device->PATT3 = tmpr; - } - + MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos))); + } + return HAL_OK; } /** - * @brief DeInitializes the FSMC_NAND device + * @brief DeInitializes the FSMC_NAND device * @param Device Pointer to NAND device instance * @param Bank NAND bank number * @retval HAL status */ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) { + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + /* Disable the NAND Bank */ __FSMC_NAND_DISABLE(Device, Bank); - + /* De-initialize the NAND Bank */ - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { /* Set the FSMC_NAND_BANK2 registers to their reset values */ - Device->PCR2 = 0x00000018U; - Device->SR2 = 0x00000040U; - Device->PMEM2 = 0xFCFCFCFCU; - Device->PATT2 = 0xFCFCFCFCU; + WRITE_REG(Device->PCR2, 0x00000018U); + WRITE_REG(Device->SR2, 0x00000040U); + WRITE_REG(Device->PMEM2, 0xFCFCFCFCU); + WRITE_REG(Device->PATT2, 0xFCFCFCFCU); } - /* FSMC_Bank3_NAND */ + /* FSMC_Bank3_NAND */ else { /* Set the FSMC_NAND_BANK3 registers to their reset values */ - Device->PCR3 = 0x00000018U; - Device->SR3 = 0x00000040U; - Device->PMEM3 = 0xFCFCFCFCU; - Device->PATT3 = 0xFCFCFCFCU; + WRITE_REG(Device->PCR3, 0x00000018U); + WRITE_REG(Device->SR3, 0x00000040U); + WRITE_REG(Device->PMEM3, 0xFCFCFCFCU); + WRITE_REG(Device->PATT3, 0xFCFCFCFCU); } - + return HAL_OK; } + /** * @} */ - -/** @addtogroup FSMC_LL_NAND_Private_Functions_Group2 - * @brief management functions + +/** @defgroup HAL_FSMC_NAND_Group2 Peripheral Control functions + * @brief management functions * -@verbatim +@verbatim ============================================================================== ##### FSMC_NAND Control functions ##### ============================================================================== @@ -689,48 +748,58 @@ HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) @endverbatim * @{ - */ - + */ + + /** * @brief Enables dynamically FSMC_NAND ECC feature. * @param Device Pointer to NAND device instance * @param Bank NAND bank number * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) + */ +HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) { + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + /* Enable ECC feature */ - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { - Device->PCR2 |= FSMC_PCR2_ECCEN; + SET_BIT(Device->PCR2, FSMC_PCR2_ECCEN); } else { - Device->PCR3 |= FSMC_PCR3_ECCEN; - } - - return HAL_OK; + SET_BIT(Device->PCR3, FSMC_PCR2_ECCEN); + } + + return HAL_OK; } + /** * @brief Disables dynamically FSMC_NAND ECC feature. * @param Device Pointer to NAND device instance * @param Bank NAND bank number * @retval HAL status - */ -HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) -{ + */ +HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); + assert_param(IS_FSMC_NAND_BANK(Bank)); + /* Disable ECC feature */ - if(Bank == FSMC_NAND_BANK2) + if (Bank == FSMC_NAND_BANK2) { - Device->PCR2 &= ~FSMC_PCR2_ECCEN; + CLEAR_BIT(Device->PCR2, FSMC_PCR2_ECCEN); } else { - Device->PCR3 &= ~FSMC_PCR3_ECCEN; - } + CLEAR_BIT(Device->PCR3, FSMC_PCR2_ECCEN); + } - return HAL_OK; + return HAL_OK; } /** @@ -738,127 +807,125 @@ HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank * @param Device Pointer to NAND device instance * @param ECCval Pointer to ECC value * @param Bank NAND bank number - * @param Timeout Timeout wait value + * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) +HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout) { - uint32_t tickstart = 0U; - - /* Check the parameters */ - assert_param(IS_FSMC_NAND_DEVICE(Device)); + uint32_t tickstart; + + /* Check the parameters */ + assert_param(IS_FSMC_NAND_DEVICE(Device)); assert_param(IS_FSMC_NAND_BANK(Bank)); - /* Get tick */ + /* Get tick */ tickstart = HAL_GetTick(); /* Wait until FIFO is empty */ - while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) + while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) { /* Check for the Timeout */ - if(Timeout != HAL_MAX_DELAY) + if (Timeout != HAL_MAX_DELAY) { - if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) { return HAL_TIMEOUT; } - } + } } - - if(Bank == FSMC_NAND_BANK2) - { + + if (Bank == FSMC_NAND_BANK2) + { /* Get the ECCR2 register value */ *ECCval = (uint32_t)Device->ECCR2; } else - { + { /* Get the ECCR3 register value */ *ECCval = (uint32_t)Device->ECCR3; } - return HAL_OK; + return HAL_OK; } /** * @} */ - -/** - * @} - */ - +#endif /* FSMC_Bank2_3 */ + +#if defined(FSMC_Bank4) + /** @addtogroup FSMC_LL_PCCARD - * @brief PCCARD Controller functions + * @brief PCCARD Controller functions * - @verbatim + @verbatim ============================================================================== ##### How to use PCCARD device driver ##### ============================================================================== [..] This driver contains a set of APIs to interface with the FSMC PCCARD bank in order to run the PCCARD/compact flash external devices. - - (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() + + (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init() - (+) FSMC PCCARD bank common space timing configuration using the function + (+) FSMC PCCARD bank common space timing configuration using the function FSMC_PCCARD_CommonSpace_Timing_Init() - (+) FSMC PCCARD bank attribute space timing configuration using the function + (+) FSMC PCCARD bank attribute space timing configuration using the function FSMC_PCCARD_AttributeSpace_Timing_Init() - (+) FSMC PCCARD bank IO space timing configuration using the function + (+) FSMC PCCARD bank IO space timing configuration using the function FSMC_PCCARD_IOSpace_Timing_Init() - @endverbatim * @{ */ - + /** @addtogroup FSMC_LL_PCCARD_Private_Functions_Group1 - * @brief Initialization and Configuration functions + * @brief Initialization and Configuration functions * -@verbatim +@verbatim ============================================================================== ##### Initialization and de_initialization functions ##### ============================================================================== - [..] + [..] This section provides functions allowing to: (+) Initialize and configure the FSMC PCCARD interface - (+) De-initialize the FSMC PCCARD interface + (+) De-initialize the FSMC PCCARD interface (+) Configure the FSMC clock and associated GPIOs - + @endverbatim * @{ */ - + /** * @brief Initializes the FSMC_PCCARD device according to the specified * control parameters in the FSMC_PCCARD_HandleTypeDef * @param Device Pointer to PCCARD device instance - * @param Init Pointer to PCCARD Initialization structure + * @param Init Pointer to PCCARD Initialization structure * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) { - uint32_t tmpr = 0U; - - /* Check the parameters */ + /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_Bank2_3) assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); - assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); - - /* Get PCCARD control register value */ - tmpr = Device->PCR4; - - /* Clear TAR, TCLR, PWAITEN and PWID bits */ - tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \ - FSMC_PCR4_PWID | FSMC_PCR4_PTYP)); - + assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); +#endif /* FSMC_Bank2_3 */ + /* Set FSMC_PCCARD device control parameters */ - tmpr |= (uint32_t)(Init->Waitfeature |\ - FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ - (Init->TCLRSetupTime << 9U) |\ - (Init->TARSetupTime << 13U)); - - Device->PCR4 = tmpr; - + MODIFY_REG(Device->PCR4, + (FSMC_PCR4_PTYP | + FSMC_PCR4_PWAITEN | + FSMC_PCR4_PWID | + FSMC_PCR4_TCLR | + FSMC_PCR4_TAR), + (FSMC_PCR_MEMORY_TYPE_PCCARD | + Init->Waitfeature | + FSMC_NAND_PCC_MEM_BUS_WIDTH_16 | + (Init->TCLRSetupTime << FSMC_PCR4_TCLR_Pos) | + (Init->TARSetupTime << FSMC_PCR4_TAR_Pos))); + return HAL_OK; } @@ -866,67 +933,57 @@ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_Init * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified * parameters in the FSMC_NAND_PCC_TimingTypeDef * @param Device Pointer to PCCARD device instance - * @param Timing Pointer to PCCARD timing structure + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0U; - /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_Bank2_3) assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FSMC_Bank2_3 */ - /* Get PCCARD common space timing register value */ - tmpr = Device->PMEM4; - - /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 | FSMC_PMEM4_MEMHOLD4 | \ - FSMC_PMEM4_MEMHIZ4)); /* Set PCCARD timing parameters */ - tmpr |= (uint32_t)((Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - (Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - Device->PMEM4 = tmpr; - - return HAL_OK; + MODIFY_REG(Device->PMEM4, PMEM4_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PMEM4_MEMWAIT4_Pos) | + ((Timing->HoldSetupTime) << FSMC_PMEM4_MEMHOLD4_Pos) | + ((Timing->HiZSetupTime) << FSMC_PMEM4_MEMHIZ4_Pos))); + + return HAL_OK; } /** * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified * parameters in the FSMC_NAND_PCC_TimingTypeDef * @param Device Pointer to PCCARD device instance - * @param Timing Pointer to PCCARD timing structure + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0U; - - /* Check the parameters */ + /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_Bank2_3) assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FSMC_Bank2_3 */ - /* Get PCCARD timing parameters */ - tmpr = Device->PATT4; - - /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ - tmpr &= ((uint32_t)~(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 | FSMC_PATT4_ATTHOLD4 | \ - FSMC_PATT4_ATTHIZ4)); - /* Set PCCARD timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - Device->PATT4 = tmpr; - + MODIFY_REG(Device->PATT4, PATT4_CLEAR_MASK, + (Timing->SetupTime | + ((Timing->WaitSetupTime) << FSMC_PATT4_ATTWAIT4_Pos) | + ((Timing->HoldSetupTime) << FSMC_PATT4_ATTHOLD4_Pos) | + ((Timing->HiZSetupTime) << FSMC_PATT4_ATTHIZ4_Pos))); + return HAL_OK; } @@ -934,76 +991,72 @@ HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *De * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified * parameters in the FSMC_NAND_PCC_TimingTypeDef * @param Device Pointer to PCCARD device instance - * @param Timing Pointer to PCCARD timing structure + * @param Timing Pointer to PCCARD timing structure * @retval HAL status */ -HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) +HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing) { - uint32_t tmpr = 0U; - - /* Check the parameters */ + /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); +#if defined(FSMC_Bank2_3) assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); +#endif /* FSMC_Bank2_3 */ - /* Get FSMC_PCCARD device timing parameters */ - tmpr = Device->PIO4; - - /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ - tmpr &= ((uint32_t)~(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | FSMC_PIO4_IOHOLD4 | \ - FSMC_PIO4_IOHIZ4)); - /* Set FSMC_PCCARD device timing parameters */ - tmpr |= (uint32_t)(Timing->SetupTime |\ - ((Timing->WaitSetupTime) << 8U) |\ - ((Timing->HoldSetupTime) << 16U) |\ - ((Timing->HiZSetupTime) << 24U)); - - Device->PIO4 = tmpr; - + MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, + (Timing->SetupTime | + (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) | + (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) | + (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos))); + return HAL_OK; } - + /** - * @brief DeInitializes the FSMC_PCCARD device + * @brief DeInitializes the FSMC_PCCARD device * @param Device Pointer to PCCARD device instance * @retval HAL status */ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) { + /* Check the parameters */ + assert_param(IS_FSMC_PCCARD_DEVICE(Device)); + /* Disable the FSMC_PCCARD device */ __FSMC_PCCARD_DISABLE(Device); - + /* De-initialize the FSMC_PCCARD device */ - Device->PCR4 = 0x00000018U; - Device->SR4 = 0x00000000U; + Device->PCR4 = 0x00000018U; + Device->SR4 = 0x00000040U; Device->PMEM4 = 0xFCFCFCFCU; Device->PATT4 = 0xFCFCFCFCU; Device->PIO4 = 0xFCFCFCFCU; - + return HAL_OK; } + /** * @} */ +#endif /* FSMC_Bank4 */ + /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */ -#endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */ +#endif /* HAL_NOR_MODULE_ENABLED */ /** * @} */ - /** * @} */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.h index 12f3a14dfe5..8b0ceb75f96 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_fsmc.h @@ -6,23 +6,22 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** - */ + */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_FSMC_H -#define __STM32F4xx_LL_FSMC_H +#ifndef STM32F4xx_LL_FSMC_H +#define STM32F4xx_LL_FSMC_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -31,152 +30,271 @@ /** @addtogroup STM32F4xx_HAL_Driver * @{ */ - + /** @addtogroup FSMC_LL * @{ */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\ - defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx) -/* Private types -------------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Types FSMC Private Types +/** @addtogroup FSMC_LL_Private_Macros + * @{ + */ +#if defined(FSMC_Bank1) + +#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ + ((__BANK__) == FSMC_NORSRAM_BANK2) || \ + ((__BANK__) == FSMC_NORSRAM_BANK3) || \ + ((__BANK__) == FSMC_NORSRAM_BANK4)) +#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) +#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ + ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) +#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FSMC_PAGE_SIZE_1024)) +#if defined(FSMC_BCR1_WFDIS) +#define IS_FSMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FSMC_WRITE_FIFO_DISABLE) || \ + ((__FIFO__) == FSMC_WRITE_FIFO_ENABLE)) +#endif /* FSMC_BCR1_WFDIS */ +#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ + ((__MODE__) == FSMC_ACCESS_MODE_B) || \ + ((__MODE__) == FSMC_ACCESS_MODE_C) || \ + ((__MODE__) == FSMC_ACCESS_MODE_D)) +#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ + ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) +#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) +#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) +#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) +#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) +#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) +#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) +#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) +#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) +#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) +#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) +#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) +#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) + +#endif /* FSMC_Bank1 */ +#if defined(FSMC_Bank2_3) + +#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \ + ((__BANK__) == FSMC_NAND_BANK3)) +#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) +#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) +#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FSMC_NAND_ECC_ENABLE)) + +#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) +#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) + +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) +#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) + +#endif /* FSMC_Bank4 */ + +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types * @{ */ -/** - * @brief FSMC NORSRAM Configuration Structure definition - */ +#if defined(FSMC_Bank1) +#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef +#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef +#endif /* FSMC_Bank1 */ +#if defined(FSMC_Bank2_3) +#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) +#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef +#endif /* FSMC_Bank4 */ + +#if defined(FSMC_Bank1) +#define FSMC_NORSRAM_DEVICE FSMC_Bank1 +#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E +#endif /* FSMC_Bank1 */ +#if defined(FSMC_Bank2_3) +#define FSMC_NAND_DEVICE FSMC_Bank2_3 +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) +#define FSMC_PCCARD_DEVICE FSMC_Bank4 +#endif /* FSMC_Bank4 */ + +#if defined(FSMC_Bank1) +/** + * @brief FSMC NORSRAM Configuration Structure definition + */ typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are - multiplexed on the data bus or not. - This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + multiplexed on the data bus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FSMC_Memory_Type */ + This parameter can be a value of @ref FSMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash memory, valid only when accessing Flash memories in burst mode. - This parameter can be a value of @ref FSMC_Wrap_Mode - This mode is available only for the STM32F405/407/4015/417xx devices */ + This parameter can be a value of @ref FSMC_Wrap_Mode + This mode is available only for the STM32F405/407/4015/417xx devices */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, - valid only when accessing memories in burst mode. - This parameter can be a value of @ref FSMC_Wait_Timing */ + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. - This parameter can be a value of @ref FSMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait - signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FSMC_Wait_Signal */ + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FSMC_Extended_Mode */ + This parameter can be a value of @ref FSMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FSMC_AsynchronousWait */ + This parameter can be a value of @ref FSMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FSMC_Write_Burst */ + This parameter can be a value of @ref FSMC_Write_Burst */ - uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock - This mode is available only for the STM32F412Vx/Zx/Rx devices */ + uint32_t ContinuousClock; /*!< Enables or disables the FSMC clock output to external memory devices. + This parameter is only enabled through the FSMC_BCR1 register, + and don't care through FSMC_BCR2..4 registers. + This parameter can be a value of @ref FSMC_Continous_Clock + This mode is available only for the STM32F412Vx/Zx/Rx devices */ - uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. - This parameter is only enabled through the FMC_BCR1 register, and don't care - through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO - This mode is available only for the STM32F412Vx/Vx devices */ + uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FSMC controller. + This parameter is only enabled through the FSMC_BCR1 register, + and don't care through FSMC_BCR2..4 registers. + This parameter can be a value of @ref FSMC_Write_FIFO + This mode is available only for the STM32F412Vx/Vx devices */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ -}FSMC_NORSRAM_InitTypeDef; + This parameter can be a value of @ref FSMC_Page_Size */ +} FSMC_NORSRAM_InitTypeDef; -/** - * @brief FSMC NORSRAM Timing parameters structure definition +/** + * @brief FSMC NORSRAM Timing parameters structure definition */ typedef struct { uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure - the duration of the address setup time. + the duration of the address setup time. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure the duration of the address hold time. - This parameter can be a value between Min_Data = 1 and Max_Data = 15. - @note This parameter is not used with synchronous NOR Flash memories. */ + This parameter can be a value between Min_Data = 1 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure the duration of the data setup time. This parameter can be a value between Min_Data = 1 and Max_Data = 255. - @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed - NOR Flash memories. */ + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure the duration of the bus turnaround. This parameter can be a value between Min_Data = 0 and Max_Data = 15. - @note This parameter is only used for multiplexed NOR Flash memories. */ + @note This parameter is only used for multiplexed NOR Flash memories. */ - uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of - HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. - @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM - accesses. */ + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM + accesses. */ uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue to the memory before getting the first data. The parameter value depends on the memory type as shown below: - It must be set to 0 in case of a CRAM - It is don't care in asynchronous NOR, SRAM or ROM accesses - - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories - with synchronous burst mode enable */ + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ - uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FSMC_Access_Mode */ + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +} FSMC_NORSRAM_TimingTypeDef; +#endif /* FSMC_Bank1 */ -}FSMC_NORSRAM_TimingTypeDef; - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** - * @brief FSMC NAND Configuration Structure definition - */ +#if defined(FSMC_Bank2_3) +/** + * @brief FSMC NAND Configuration Structure definition + */ typedef struct { uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. - This parameter can be a value of @ref FSMC_NAND_Bank */ + This parameter can be a value of @ref FSMC_NAND_Bank */ uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. - This parameter can be any value of @ref FSMC_Wait_feature */ + This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be any value of @ref FSMC_NAND_Data_Width */ + This parameter can be any value of @ref FSMC_NAND_Data_Width */ uint32_t EccComputation; /*!< Enables or disables the ECC computation. - This parameter can be any value of @ref FSMC_ECC */ + This parameter can be any value of @ref FSMC_ECC */ uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. - This parameter can be any value of @ref FSMC_ECC_Page_Size */ + This parameter can be any value of @ref FSMC_ECC_Page_Size */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -185,11 +303,12 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ +} FSMC_NAND_InitTypeDef; +#endif -}FSMC_NAND_InitTypeDef; - -/** - * @brief FSMC NAND/PCCARD Timing parameters structure definition +#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) +/** + * @brief FSMC NAND Timing parameters structure definition */ typedef struct { @@ -197,36 +316,37 @@ typedef struct the command assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the command for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the - memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address (and data for write access) after the command de-assertion for NAND-Flash read or write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the data bus is kept in HiZ after the start of a NAND-Flash write access to common/Attribute or I/O memory space (depending on the memory space timing to be configured). - This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - -}FSMC_NAND_PCC_TimingTypeDef; + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ +} FSMC_NAND_PCC_TimingTypeDef; +#endif /* FSMC_Bank2_3 */ -/** - * @brief FSMC NAND Configuration Structure definition +#if defined(FSMC_Bank4) +/** + * @brief FSMC PCCARD Configuration Structure definition */ typedef struct { uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. - This parameter can be any value of @ref FSMC_Wait_feature */ + This parameter can be any value of @ref FSMC_Wait_feature */ uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between CLE low and RE low. @@ -235,28 +355,30 @@ typedef struct uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the delay between ALE low and RE low. This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ - }FSMC_PCCARD_InitTypeDef; +#endif /* FSMC_Bank4 */ + /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Constants FSMC Private Constants +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants * @{ */ +#if defined(FSMC_Bank1) -/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller +/** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller * @{ - */ + */ + /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank * @{ */ -#define FSMC_NORSRAM_BANK1 0x00000000U -#define FSMC_NORSRAM_BANK2 0x00000002U -#define FSMC_NORSRAM_BANK3 0x00000004U -#define FSMC_NORSRAM_BANK4 0x00000006U +#define FSMC_NORSRAM_BANK1 (0x00000000U) +#define FSMC_NORSRAM_BANK2 (0x00000002U) +#define FSMC_NORSRAM_BANK3 (0x00000004U) +#define FSMC_NORSRAM_BANK4 (0x00000006U) /** * @} */ @@ -264,8 +386,8 @@ typedef struct /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing * @{ */ -#define FSMC_DATA_ADDRESS_MUX_DISABLE 0x00000000U -#define FSMC_DATA_ADDRESS_MUX_ENABLE 0x00000002U +#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) /** * @} */ @@ -273,19 +395,19 @@ typedef struct /** @defgroup FSMC_Memory_Type FSMC Memory Type * @{ */ -#define FSMC_MEMORY_TYPE_SRAM 0x00000000U -#define FSMC_MEMORY_TYPE_PSRAM 0x00000004U -#define FSMC_MEMORY_TYPE_NOR 0x00000008U +#define FSMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FSMC_MEMORY_TYPE_NOR (0x00000008U) /** * @} */ -/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width +/** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width * @{ */ -#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 0x00000000U -#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 0x00000010U -#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 0x00000020U +#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) /** * @} */ @@ -293,8 +415,8 @@ typedef struct /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access * @{ */ -#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE 0x00000040U -#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE 0x00000000U +#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) /** * @} */ @@ -302,8 +424,8 @@ typedef struct /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode * @{ */ -#define FSMC_BURST_ACCESS_MODE_DISABLE 0x00000000U -#define FSMC_BURST_ACCESS_MODE_ENABLE 0x00000100U +#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) /** * @} */ @@ -311,8 +433,8 @@ typedef struct /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity * @{ */ -#define FSMC_WAIT_SIGNAL_POLARITY_LOW 0x00000000U -#define FSMC_WAIT_SIGNAL_POLARITY_HIGH 0x00000200U +#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) /** * @} */ @@ -321,8 +443,8 @@ typedef struct * @note These values are available only for the STM32F405/415/407/417xx devices. * @{ */ -#define FSMC_WRAP_MODE_DISABLE 0x00000000U -#define FSMC_WRAP_MODE_ENABLE 0x00000400U +#define FSMC_WRAP_MODE_DISABLE (0x00000000U) +#define FSMC_WRAP_MODE_ENABLE (0x00000400U) /** * @} */ @@ -330,8 +452,8 @@ typedef struct /** @defgroup FSMC_Wait_Timing FSMC Wait Timing * @{ */ -#define FSMC_WAIT_TIMING_BEFORE_WS 0x00000000U -#define FSMC_WAIT_TIMING_DURING_WS 0x00000800U +#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) /** * @} */ @@ -339,8 +461,8 @@ typedef struct /** @defgroup FSMC_Write_Operation FSMC Write Operation * @{ */ -#define FSMC_WRITE_OPERATION_DISABLE 0x00000000U -#define FSMC_WRITE_OPERATION_ENABLE 0x00001000U +#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) /** * @} */ @@ -348,8 +470,8 @@ typedef struct /** @defgroup FSMC_Wait_Signal FSMC Wait Signal * @{ */ -#define FSMC_WAIT_SIGNAL_DISABLE 0x00000000U -#define FSMC_WAIT_SIGNAL_ENABLE 0x00002000U +#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) /** * @} */ @@ -357,8 +479,8 @@ typedef struct /** @defgroup FSMC_Extended_Mode FSMC Extended Mode * @{ */ -#define FSMC_EXTENDED_MODE_DISABLE 0x00000000U -#define FSMC_EXTENDED_MODE_ENABLE 0x00004000U +#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) /** * @} */ @@ -366,8 +488,8 @@ typedef struct /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait * @{ */ -#define FSMC_ASYNCHRONOUS_WAIT_DISABLE 0x00000000U -#define FSMC_ASYNCHRONOUS_WAIT_ENABLE 0x00008000U +#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) /** * @} */ @@ -375,40 +497,43 @@ typedef struct /** @defgroup FSMC_Page_Size FSMC Page Size * @{ */ -#define FSMC_PAGE_SIZE_NONE 0x00000000U -#define FSMC_PAGE_SIZE_128 ((uint32_t)FSMC_BCR1_CPSIZE_0) -#define FSMC_PAGE_SIZE_256 ((uint32_t)FSMC_BCR1_CPSIZE_1) -#define FSMC_PAGE_SIZE_512 ((uint32_t)(FSMC_BCR1_CPSIZE_0 | FSMC_BCR1_CPSIZE_1)) -#define FSMC_PAGE_SIZE_1024 ((uint32_t)FSMC_BCR1_CPSIZE_2) +#define FSMC_PAGE_SIZE_NONE (0x00000000U) +#define FSMC_PAGE_SIZE_128 FSMC_BCR1_CPSIZE_0 +#define FSMC_PAGE_SIZE_256 FSMC_BCR1_CPSIZE_1 +#define FSMC_PAGE_SIZE_512 (FSMC_BCR1_CPSIZE_0\ + | FSMC_BCR1_CPSIZE_1) +#define FSMC_PAGE_SIZE_1024 FSMC_BCR1_CPSIZE_2 /** * @} */ -/** @defgroup FSMC_Write_FIFO FSMC Write FIFO - * @note These values are available only for the STM32F412Vx/Zx/Rx devices. +/** @defgroup FSMC_Write_Burst FSMC Write Burst * @{ */ -#define FSMC_WRITE_FIFO_DISABLE ((uint32_t)FSMC_BCR1_WFDIS) -#define FSMC_WRITE_FIFO_ENABLE 0x00000000U +#define FSMC_WRITE_BURST_DISABLE (0x00000000U) +#define FSMC_WRITE_BURST_ENABLE (0x00080000U) /** * @} */ -/** @defgroup FSMC_Write_Burst FSMC Write Burst +/** @defgroup FSMC_Continous_Clock FSMC Continuous Clock + * @note These values are available only for the STM32F412Vx/Zx/Rx devices. * @{ */ -#define FSMC_WRITE_BURST_DISABLE 0x00000000U -#define FSMC_WRITE_BURST_ENABLE 0x00080000U +#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) /** * @} */ - -/** @defgroup FSMC_Continous_Clock FSMC Continous Clock + +#if defined(FSMC_BCR1_WFDIS) +/** @defgroup FSMC_Write_FIFO FSMC Write FIFO * @note These values are available only for the STM32F412Vx/Zx/Rx devices. * @{ */ -#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY 0x00000000U -#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC 0x00100000U +#define FSMC_WRITE_FIFO_DISABLE FSMC_BCR1_WFDIS +#define FSMC_WRITE_FIFO_ENABLE (0x00000000U) +#endif /* FSMC_BCR1_WFDIS */ /** * @} */ @@ -416,26 +541,31 @@ typedef struct /** @defgroup FSMC_Access_Mode FSMC Access Mode * @{ */ -#define FSMC_ACCESS_MODE_A 0x00000000U -#define FSMC_ACCESS_MODE_B 0x10000000U -#define FSMC_ACCESS_MODE_C 0x20000000U -#define FSMC_ACCESS_MODE_D 0x30000000U +#define FSMC_ACCESS_MODE_A (0x00000000U) +#define FSMC_ACCESS_MODE_B (0x10000000U) +#define FSMC_ACCESS_MODE_C (0x20000000U) +#define FSMC_ACCESS_MODE_D (0x30000000U) /** * @} */ + /** * @} */ +#endif /* FSMC_Bank1 */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -/** @defgroup FSMC_LL_NAND_Controller FSMC NAND and PCCARD Controller +#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) + +/** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller * @{ */ /** @defgroup FSMC_NAND_Bank FSMC NAND Bank * @{ */ -#define FSMC_NAND_BANK2 0x00000010U -#define FSMC_NAND_BANK3 0x00000100U +#if defined(FSMC_Bank2_3) +#define FSMC_NAND_BANK2 (0x00000010U) +#endif +#define FSMC_NAND_BANK3 (0x00000100U) /** * @} */ @@ -443,8 +573,8 @@ typedef struct /** @defgroup FSMC_Wait_feature FSMC Wait feature * @{ */ -#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE 0x00000000U -#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE 0x00000002U +#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) +#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) /** * @} */ @@ -452,8 +582,10 @@ typedef struct /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type * @{ */ -#define FSMC_PCR_MEMORY_TYPE_PCCARD 0x00000000U -#define FSMC_PCR_MEMORY_TYPE_NAND 0x00000008U +#if defined(FSMC_Bank4) +#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) +#endif /* FSMC_Bank4 */ +#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U) /** * @} */ @@ -461,8 +593,8 @@ typedef struct /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width * @{ */ -#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 0x00000000U -#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 0x00000010U +#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) +#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) /** * @} */ @@ -470,8 +602,8 @@ typedef struct /** @defgroup FSMC_ECC FSMC ECC * @{ */ -#define FSMC_NAND_ECC_DISABLE 0x00000000U -#define FSMC_NAND_ECC_ENABLE 0x00000040U +#define FSMC_NAND_ECC_DISABLE (0x00000000U) +#define FSMC_NAND_ECC_ENABLE (0x00000040U) /** * @} */ @@ -479,38 +611,43 @@ typedef struct /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size * @{ */ -#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE 0x00000000U -#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE 0x00020000U -#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE 0x00040000U -#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE 0x00060000U -#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE 0x00080000U -#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE 0x000A0000U +#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) /** * @} */ + /** * @} - */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ + */ +#endif /* FSMC_Bank2_3 || FSMC_Bank4 */ + -/** @defgroup FSMC_LL_Interrupt_definition FSMC Interrupt definition +/** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition * @{ - */ -#define FSMC_IT_RISING_EDGE 0x00000008U -#define FSMC_IT_LEVEL 0x00000010U -#define FSMC_IT_FALLING_EDGE 0x00000020U -#define FSMC_IT_REFRESH_ERROR 0x00004000U + */ +#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) +#define FSMC_IT_RISING_EDGE (0x00000008U) +#define FSMC_IT_LEVEL (0x00000010U) +#define FSMC_IT_FALLING_EDGE (0x00000020U) +#endif /* FSMC_Bank2_3 || FSMC_Bank4 */ /** * @} */ - -/** @defgroup FSMC_LL_Flag_definition FSMC Flag definition + +/** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition * @{ - */ -#define FSMC_FLAG_RISING_EDGE 0x00000001U -#define FSMC_FLAG_LEVEL 0x00000002U -#define FSMC_FLAG_FALLING_EDGE 0x00000004U -#define FSMC_FLAG_FEMPT 0x00000040U + */ +#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4) +#define FSMC_FLAG_RISING_EDGE (0x00000001U) +#define FSMC_FLAG_LEVEL (0x00000002U) +#define FSMC_FLAG_FALLING_EDGE (0x00000004U) +#define FSMC_FLAG_FEMPT (0x00000040U) +#endif /* FSMC_Bank2_3 || FSMC_Bank4 */ /** * @} */ @@ -518,19 +655,8 @@ typedef struct /** @defgroup FSMC_LL_Alias_definition FSMC Alias definition * @{ */ -#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef -#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef -#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#define FSMC_NORSRAM_DEVICE FSMC_Bank1 -#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) -#define FSMC_NAND_DEVICE FSMC_Bank2_3 -#define FSMC_PCCARD_DEVICE FSMC_Bank4 -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#define FMC_WRITE_OPERATION_DISABLE FSMC_WRITE_OPERATION_DISABLE +#define FMC_WRITE_OPERATION_ENABLE FSMC_WRITE_OPERATION_ENABLE #define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16 @@ -549,7 +675,7 @@ typedef struct #define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable #define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE -#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE +#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef @@ -591,16 +717,16 @@ typedef struct #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ #define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE -#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE +#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) #define FMC_NAND_DEVICE FSMC_NAND_DEVICE -#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE +#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE #define FMC_NAND_BANK2 FSMC_NAND_BANK2 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ -#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 -#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 +#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1 +#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2 #define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3 #define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE @@ -620,388 +746,317 @@ typedef struct * @} */ +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ -/** @defgroup FSMC_LL_Private_Macros FSMC Private Macros +/** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros + * @{ + */ +#if defined(FSMC_Bank1) +/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros + * @brief macros to handle NOR device enable/disable and read/write operations * @{ */ -/** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Exported Macros - * @brief macros to handle NOR device enable/disable and read/write operations - * @{ - */ /** * @brief Enable the NORSRAM device access. * @param __INSTANCE__ FSMC_NORSRAM Instance - * @param __BANK__ FSMC_NORSRAM Bank - * @retval none - */ -#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN) + * @param __BANK__ FSMC_NORSRAM Bank + * @retval None + */ +#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FSMC_BCR1_MBKEN) /** * @brief Disable the NORSRAM device access. * @param __INSTANCE__ FSMC_NORSRAM Instance - * @param __BANK__ FSMC_NORSRAM Bank - * @retval none - */ -#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN) + * @param __BANK__ FSMC_NORSRAM Bank + * @retval None + */ +#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FSMC_BCR1_MBKEN) + /** * @} - */ - + */ +#endif /* FSMC_Bank1 */ + +#if defined(FSMC_Bank2_3) /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros - * @brief macros to handle NAND device enable/disable - * @{ - */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) + * @brief macros to handle NAND device enable/disable + * @{ + */ + /** * @brief Enable the NAND device access. * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @retval none - */ + * @param __BANK__ FSMC_NAND Bank + * @retval None + */ #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) + ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN)) /** * @brief Disable the NAND device access. * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @retval none - */ -#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \ - ((__INSTANCE__)->PCR3 &= ~FSMC_PCR3_PBKEN)) + * @param __BANK__ FSMC_NAND Bank + * @retval None + */ +#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN): \ + CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN)) + /** * @} - */ - -/** @defgroup FSMC_LL_PCCARD_Macros FSMC PCCARD Macros - * @brief macros to handle SRAM read/write operations + */ +#endif /* FSMC_Bank2_3 */ + +#if defined(FSMC_Bank4) +/** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros + * @brief macros to handle PCCARD read/write operations * @{ */ /** * @brief Enable the PCCARD device access. - * @param __INSTANCE__ FSMC_PCCARD Instance - * @retval none - */ + * @param __INSTANCE__ FSMC_PCCARD Instance + * @retval None + */ #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) /** * @brief Disable the PCCARD device access. - * @param __INSTANCE__ FSMC_PCCARD Instance - * @retval none - */ + * @param __INSTANCE__ FSMC_PCCARD Instance + * @retval None + */ #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) /** * @} */ - -/** @defgroup FSMC_LL_Flag_Interrupt_Macros FSMC Flag&Interrupt Macros - * @brief macros to handle FSMC flags and interrupts - * @{ - */ + +#endif +#if defined(FSMC_Bank2_3) +/** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt + * @brief macros to handle NAND interrupts + * @{ + */ + /** * @brief Enable the NAND device interrupt. - * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @param __INTERRUPT__ FSMC_NAND interrupt + * @param __INSTANCE__ FSMC_NAND instance + * @param __BANK__ FSMC_NAND Bank + * @param __INTERRUPT__ FSMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. - * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None - */ + */ #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) + ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) /** * @brief Disable the NAND device interrupt. - * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank * @param __INTERRUPT__ FSMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. - * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None */ #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ - ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) + ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) /** * @brief Get flag status of the NAND device. * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank + * @param __BANK__ FSMC_NAND Bank * @param __FLAG__ FSMC_NAND flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT: FIFO empty flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ - (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) + (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) /** * @brief Clear flag status of the NAND device. * @param __INSTANCE__ FSMC_NAND Instance - * @param __BANK__ FSMC_NAND Bank - * @param __FLAG__ FSMC_NAND flag + * @param __BANK__ FSMC_NAND Bank + * @param __FLAG__ FSMC_NAND flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT: FIFO empty flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ - ((__INSTANCE__)->SR3 &= ~(__FLAG__))) + ((__INSTANCE__)->SR3 &= ~(__FLAG__))) + +/** + * @} + */ +#endif /* FSMC_Bank2_3 */ + +#if defined(FSMC_Bank4) +/** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt + * @brief macros to handle PCCARD interrupts + * @{ + */ /** * @brief Enable the PCCARD device interrupt. - * @param __INSTANCE__ FSMC_PCCARD Instance - * @param __INTERRUPT__ FSMC_PCCARD interrupt + * @param __INSTANCE__ FSMC_PCCARD instance + * @param __INTERRUPT__ FSMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. - * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None - */ + */ #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) /** * @brief Disable the PCCARD device interrupt. - * @param __INSTANCE__ FSMC_PCCARD Instance - * @param __INTERRUPT__ FSMC_PCCARD interrupt + * @param __INSTANCE__ FSMC_PCCARD instance + * @param __INTERRUPT__ FSMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. - * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. + * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. * @retval None - */ -#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) + */ +#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) /** * @brief Get flag status of the PCCARD device. - * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INSTANCE__ FSMC_PCCARD instance * @param __FLAG__ FSMC_PCCARD flag * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT: FIFO empty flag. + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval The state of FLAG (SET or RESET). */ #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) /** * @brief Clear flag status of the PCCARD device. - * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INSTANCE__ FSMC_PCCARD instance * @param __FLAG__ FSMC_PCCARD flag * This parameter can be any combination of the following values: - * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. - * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. - * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. - * @arg FSMC_FLAG_FEMPT: FIFO empty flag. + * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. + * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. + * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. + * @arg FSMC_FLAG_FEMPT: FIFO empty flag. * @retval None */ #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) + /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros - * @{ - */ -#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ - ((__BANK__) == FSMC_NORSRAM_BANK2) || \ - ((__BANK__) == FSMC_NORSRAM_BANK3) || \ - ((__BANK__) == FSMC_NORSRAM_BANK4)) - -#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ - ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) - -#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ - ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) - -#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ - ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) - -#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ - ((__MODE__) == FSMC_ACCESS_MODE_B) || \ - ((__MODE__) == FSMC_ACCESS_MODE_C) || \ - ((__MODE__) == FSMC_ACCESS_MODE_D)) - -#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_NAND_BANK2) || \ - ((BANK) == FSMC_NAND_BANK3)) - -#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ - ((FEATURE) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) - -#define IS_FSMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ - ((WIDTH) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) - -#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_NAND_ECC_DISABLE) || \ - ((STATE) == FSMC_NAND_ECC_ENABLE)) - -#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ - ((SIZE) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) - -#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 255U) - -#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) - -#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) - -#define IS_FSMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FSMC_NAND_DEVICE) - -#define IS_FSMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FSMC_PCCARD_DEVICE) - -#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ - ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) - -#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ - ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) - -#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ - ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) - -#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ - ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) - -#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ - ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) - -#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ - ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) - -#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ - ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) - -#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ - ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) - -#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) - -#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ - ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) - -#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) - -#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) - -#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) - -#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) - -#define IS_FSMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ - ((CCLOCK) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) - -#define IS_FSMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U)) - -#define IS_FSMC_PAGESIZE(SIZE) (((SIZE) == FSMC_PAGE_SIZE_NONE) || \ - ((SIZE) == FSMC_PAGE_SIZE_128) || \ - ((SIZE) == FSMC_PAGE_SIZE_256) || \ - ((SIZE) == FSMC_PAGE_SIZE_512) || \ - ((SIZE) == FSMC_PAGE_SIZE_1024)) - -#define IS_FSMC_WRITE_FIFO(FIFO) (((FIFO) == FSMC_WRITE_FIFO_DISABLE) || \ - ((FIFO) == FSMC_WRITE_FIFO_ENABLE)) +#endif /** * @} */ + /** * @} - */ + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions * @{ */ +#if defined(FSMC_Bank1) /** @defgroup FSMC_LL_NORSRAM NOR SRAM * @{ */ - -/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions +/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); -HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_InitTypeDef *Init); +HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, + FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); +HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, + FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); /** * @} - */ + */ -/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions +/** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions * @{ */ HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); /** * @} - */ + */ /** * @} */ +#endif /* FSMC_Bank1 */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) +#if defined(FSMC_Bank2_3) /** @defgroup FSMC_LL_NAND NAND * @{ */ -/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions +/** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); +HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} */ -/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions +/** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions * @{ */ HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); +HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, + uint32_t Timeout); /** * @} - */ + */ /** * @} - */ + */ +#endif /* FSMC_Bank2_3 */ +#if defined(FSMC_Bank4) /** @defgroup FSMC_LL_PCCARD PCCARD * @{ */ -/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions +/** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions * @{ */ HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); -HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); -HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); +HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, + FSMC_NAND_PCC_TimingTypeDef *Timing); HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); /** * @} @@ -1009,25 +1064,23 @@ HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +#endif /* FSMC_Bank4 */ + /** * @} */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ /** * @} - */ + */ /** * @} */ - + #ifdef __cplusplus } #endif -#endif /* __STM32F4xx_LL_FSMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_LL_FSMC_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.c index bfdcb1e6eef..4d100b522b5 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -302,4 +301,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.h index 76e9170a0d9..6bee7fd15e9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_gpio.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -980,4 +979,3 @@ void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); #endif /* __STM32F4xx_LL_GPIO_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.c index 125fb2ca13f..d25e5901301 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -250,4 +249,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.h index 5a46babfdc8..babba6bf9d6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_i2c.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1889,4 +1888,3 @@ void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); #endif /* __STM32F4xx_LL_I2C_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_iwdg.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_iwdg.h index 2f1b844a9ce..4158363d1c0 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_iwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_iwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -301,5 +300,3 @@ __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) #endif #endif /* STM32F4xx_LL_IWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.c index cd446924005..4ec08400f1c 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -28,7 +27,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ @@ -138,7 +137,7 @@ void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct) * - SUCCESS: LPTIMx instance has been initialized * - ERROR: LPTIMx instance hasn't been initialized */ -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct) +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct) { ErrorStatus result = SUCCESS; /* Check the parameters */ @@ -189,12 +188,15 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) uint32_t tmpCFGR; uint32_t tmpCMP; uint32_t tmpARR; + uint32_t primask_bit; uint32_t tmpOR; /* Check the parameters */ assert_param(IS_LPTIM_INSTANCE(LPTIMx)); - __disable_irq(); + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1) ; /********** Save LPTIM Config *********/ /* Save LPTIM source clock */ @@ -274,7 +276,8 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) LPTIMx->CFGR = tmpCFGR; LPTIMx->OR = tmpOR; - __enable_irq(); + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); } /** @@ -296,5 +299,3 @@ void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.h index 0d8e8eaee8e..f84ed6b1de9 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_lptim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -67,22 +66,26 @@ typedef struct uint32_t ClockSource; /*!< Specifies the source of the clock used by the LPTIM instance. This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_SetClockSource().*/ uint32_t Prescaler; /*!< Specifies the prescaler division ratio. This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER. - This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/ + This feature can be modified afterwards using using unitary + function @ref LL_LPTIM_SetPrescaler().*/ uint32_t Waveform; /*!< Specifies the waveform shape. This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_ConfigOutput().*/ uint32_t Polarity; /*!< Specifies waveform polarity. This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/ + This feature can be modified afterwards using unitary + function @ref LL_LPTIM_ConfigOutput().*/ } LL_LPTIM_InitTypeDef; /** @@ -100,9 +103,9 @@ typedef struct * @{ */ #define LL_LPTIM_ISR_CMPM LPTIM_ISR_CMPM /*!< Compare match */ +#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARRM LPTIM_ISR_ARRM /*!< Autoreload match */ #define LL_LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG /*!< External trigger edge event */ -#define LL_LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK /*!< Compare register update OK */ #define LL_LPTIM_ISR_ARROK LPTIM_ISR_ARROK /*!< Autoreload register update OK */ #define LL_LPTIM_ISR_UP LPTIM_ISR_UP /*!< Counter direction change down to up */ #define LL_LPTIM_ISR_DOWN LPTIM_ISR_DOWN /*!< Counter direction change up to down */ @@ -114,13 +117,13 @@ typedef struct * @brief IT defines which can be used with LL_LPTIM_ReadReg and LL_LPTIM_WriteReg functions * @{ */ -#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match Interrupt Enable */ -#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match Interrupt Enable */ -#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger valid edge Interrupt Enable */ -#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK Interrupt Enable */ -#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK Interrupt Enable */ -#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Direction change to UP Interrupt Enable */ -#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Direction change to down Interrupt Enable */ +#define LL_LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE /*!< Compare match */ +#define LL_LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE /*!< Compare register update OK */ +#define LL_LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE /*!< Autoreload match */ +#define LL_LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE /*!< External trigger edge event */ +#define LL_LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE /*!< Autoreload register update OK */ +#define LL_LPTIM_IER_UPIE LPTIM_IER_UPIE /*!< Counter direction change down to up */ +#define LL_LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE /*!< Counter direction change up to down */ /** * @} */ @@ -319,7 +322,7 @@ typedef struct ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); -ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct); +ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); /** * @} @@ -349,7 +352,7 @@ __STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL)); } @@ -395,7 +398,7 @@ __STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t Upda * @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE * @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD */ -__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD)); } @@ -410,7 +413,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx) * @note autoreload value be strictly greater than the compare value. * @rmtoll ARR ARR LL_LPTIM_SetAutoReload * @param LPTIMx Low-Power Timer instance - * @param AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @param AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF * @retval None */ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload) @@ -422,9 +425,9 @@ __STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t Auto * @brief Get actual auto reload value * @rmtoll ARR ARR LL_LPTIM_GetAutoReload * @param LPTIMx Low-Power Timer instance - * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval AutoReload Value between Min_Data=0x0001 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR)); } @@ -451,7 +454,7 @@ __STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t Compare * @param LPTIMx Low-Power Timer instance * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP)); } @@ -466,7 +469,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval Counter value */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT)); } @@ -494,7 +497,7 @@ __STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t Cou * @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL * @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE)); } @@ -543,7 +546,7 @@ __STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Wavefo * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM * @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE)); } @@ -570,7 +573,7 @@ __STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polari * @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR * @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL)); } @@ -614,7 +617,7 @@ __STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Presc * @arg @ref LL_LPTIM_PRESCALER_DIV64 * @arg @ref LL_LPTIM_PRESCALER_DIV128 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC)); } @@ -680,7 +683,7 @@ __STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL)); } @@ -741,7 +744,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Sour * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM1_TRGO * @arg @ref LL_LPTIM_TRIG_SOURCE_TIM5_TRGO */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL)); } @@ -756,7 +759,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_FILTER_4 * @arg @ref LL_LPTIM_TRIG_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT)); } @@ -770,7 +773,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING * @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN)); } @@ -806,13 +809,14 @@ __STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t Clo * @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL * @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL)); } /** - * @brief Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source. + * @brief Configure the active edge or edges used by the counter when + the LPTIM is clocked by an external clock source. * @note This function must be called when the LPTIM instance is disabled. * @note When both external clock signal edges are considered active ones, * the LPTIM must also be clocked by an internal clock source with a @@ -847,7 +851,7 @@ __STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockF * @arg @ref LL_LPTIM_CLK_POLARITY_FALLING * @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -862,7 +866,7 @@ __STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx) * @arg @ref LL_LPTIM_CLK_FILTER_4 * @arg @ref LL_LPTIM_CLK_FILTER_8 */ -__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT)); } @@ -900,7 +904,7 @@ __STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t Enc * @arg @ref LL_LPTIM_ENCODER_MODE_FALLING * @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL)); } @@ -939,7 +943,7 @@ __STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL)); } @@ -969,7 +973,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL)); } @@ -991,7 +995,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL)); } @@ -1013,7 +1017,7 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL)); } @@ -1030,12 +1034,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully + completed. If so, a new one can be initiated. * @rmtoll ISR CMPOK LL_LPTIM_IsActiveFlag_CMPOK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL)); } @@ -1052,12 +1057,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. + * @brief Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully + completed. If so, a new one can be initiated. * @rmtoll ISR ARROK LL_LPTIM_IsActiveFlag_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL)); } @@ -1074,12 +1080,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode). + * @brief Informs the application whether the counter direction has changed from down to up (when the LPTIM instance + operates in encoder mode). * @rmtoll ISR UP LL_LPTIM_IsActiveFlag_UP * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL)); } @@ -1096,12 +1103,13 @@ __STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx) } /** - * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode). + * @brief Informs the application whether the counter direction has changed from up to down (when the LPTIM instance + operates in encoder mode). * @rmtoll ISR DOWN LL_LPTIM_IsActiveFlag_DOWN * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL)); } @@ -1142,7 +1150,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL)); } @@ -1175,7 +1183,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL)); } @@ -1208,7 +1216,7 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL)); } @@ -1241,14 +1249,14 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx) * @param LPTIMx Low-Power Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL)); } /** * @brief Enable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_EnableIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1259,7 +1267,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Disable autoreload register write completed interrupt (ARROKIE). - * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_DisableIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1270,18 +1278,18 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled. - * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK + * @rmtoll IER ARROKIE LL_LPTIM_IsEnabledIT_ARROK * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL)); } /** * @brief Enable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP + * @rmtoll IER UPIE LL_LPTIM_EnableIT_UP * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1292,7 +1300,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Disable direction change to up interrupt (UPIE). - * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP + * @rmtoll IER UPIE LL_LPTIM_DisableIT_UP * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1303,18 +1311,18 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the direction change to up interrupt (UPIE) is enabled. - * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP + * @rmtoll IER UPIE LL_LPTIM_IsEnabledIT_UP * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(const LPTIM_TypeDef *LPTIMx) { return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL)); } /** * @brief Enable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_EnableIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1325,7 +1333,7 @@ __STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx) /** * @brief Disable direction change to down interrupt (DOWNIE). - * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_DisableIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval None */ @@ -1336,11 +1344,11 @@ __STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx) /** * @brief Indicates whether the direction change to down interrupt (DOWNIE) is enabled. - * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN + * @rmtoll IER DOWNIE LL_LPTIM_IsEnabledIT_DOWN * @param LPTIMx Low-Power Timer instance * @retval State of bit(1 or 0). */ -__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) +__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(const LPTIM_TypeDef *LPTIMx) { return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL); } @@ -1368,5 +1376,3 @@ __STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx) #endif #endif /* STM32F4xx_LL_LPTIM_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.c index fe04bc44c93..0c6f61e3dbf 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.c @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) @@ -81,5 +79,3 @@ ErrorStatus LL_PWR_DeInit(void) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.h index 03b8706e989..ea23dc528a7 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_pwr.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -985,5 +983,3 @@ ErrorStatus LL_PWR_DeInit(void); #endif #endif /* __STM32F4xx_LL_PWR_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.c index ea18adc325e..efa3e5711b3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.c @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) @@ -1660,4 +1658,3 @@ uint32_t RCC_PLLI2S_GetFreqDomain_48M(void) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.h index d4c249fc31d..1df1b586474 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rcc.h @@ -6,14 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * + * This software is licensed under terms that can be found in the LICENSE file in + * the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. ****************************************************************************** */ @@ -7096,4 +7094,3 @@ uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); #endif /* __STM32F4xx_LL_RCC_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.c index d31a5ed28fa..333d63ca45f 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -26,7 +25,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ @@ -62,22 +61,32 @@ */ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) { + ErrorStatus status = SUCCESS; + /* Check the parameters */ assert_param(IS_RNG_ALL_INSTANCE(RNGx)); -#if !defined (RCC_AHB2_SUPPORT) - /* Enable RNG reset state */ - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG); - - /* Release RNG from reset state */ - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG); + if (RNGx == RNG) + { +#if !defined(RCC_AHB2_SUPPORT) + /* Enable RNG reset state */ + LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_RNG); + + /* Release RNG from reset state */ + LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_RNG); #else - /* Enable RNG reset state */ - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); + /* Enable RNG reset state */ + LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_RNG); /* Release RNG from reset state */ - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); -#endif - return (SUCCESS); + LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_RNG); +#endif /* !RCC_AHB2_SUPPORT */ + } + else + { + status = ERROR; + } + + return status; } /** @@ -100,5 +109,3 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.h index c142717b0cf..151cb4a7281 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rng.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -334,4 +333,3 @@ ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); #endif /* __STM32F4xx_LL_RNG_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.c index c6fa695a18c..f3ee3ce0166 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -85,22 +84,11 @@ || ((__VALUE__) == LL_RTC_WEEKDAY_SATURDAY) \ || ((__VALUE__) == LL_RTC_WEEKDAY_SUNDAY)) -#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) +#define IS_LL_RTC_DAY(__DAY__) (((__DAY__) >= 1U) && ((__DAY__) <= 31U)) -#define IS_LL_RTC_MONTH(__VALUE__) (((__VALUE__) == LL_RTC_MONTH_JANUARY) \ - || ((__VALUE__) == LL_RTC_MONTH_FEBRUARY) \ - || ((__VALUE__) == LL_RTC_MONTH_MARCH) \ - || ((__VALUE__) == LL_RTC_MONTH_APRIL) \ - || ((__VALUE__) == LL_RTC_MONTH_MAY) \ - || ((__VALUE__) == LL_RTC_MONTH_JUNE) \ - || ((__VALUE__) == LL_RTC_MONTH_JULY) \ - || ((__VALUE__) == LL_RTC_MONTH_AUGUST) \ - || ((__VALUE__) == LL_RTC_MONTH_SEPTEMBER) \ - || ((__VALUE__) == LL_RTC_MONTH_OCTOBER) \ - || ((__VALUE__) == LL_RTC_MONTH_NOVEMBER) \ - || ((__VALUE__) == LL_RTC_MONTH_DECEMBER)) +#define IS_LL_RTC_MONTH(__MONTH__) (((__MONTH__) >= 1U) && ((__MONTH__) <= 12U)) -#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) +#define IS_LL_RTC_YEAR(__YEAR__) ((__YEAR__) <= 99U) #define IS_LL_RTC_ALMA_MASK(__VALUE__) (((__VALUE__) == LL_RTC_ALMA_MASK_NONE) \ || ((__VALUE__) == LL_RTC_ALMA_MASK_DATEWEEKDAY) \ @@ -116,14 +104,12 @@ || ((__VALUE__) == LL_RTC_ALMB_MASK_SECONDS) \ || ((__VALUE__) == LL_RTC_ALMB_MASK_ALL)) - #define IS_LL_RTC_ALMA_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_DATE) || \ ((__SEL__) == LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY)) #define IS_LL_RTC_ALMB_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_DATE) || \ ((__SEL__) == LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY)) - /** * @} */ @@ -139,7 +125,7 @@ /** * @brief De-Initializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * @note This function does not reset the RTC Clock source and RTC Backup Data * registers. * @param RTCx RTC Instance * @retval An ErrorStatus enumeration value: @@ -161,21 +147,17 @@ ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) { /* Reset TR, DR and CR registers */ LL_RTC_WriteReg(RTCx, TR, 0x00000000U); -#if defined(RTC_WAKEUP_SUPPORT) LL_RTC_WriteReg(RTCx, WUTR, RTC_WUTR_WUT); -#endif /* RTC_WAKEUP_SUPPORT */ - LL_RTC_WriteReg(RTCx, DR , (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + LL_RTC_WriteReg(RTCx, DR, (RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); + /* Reset All CR bits except CR[2:0] */ -#if defined(RTC_WAKEUP_SUPPORT) LL_RTC_WriteReg(RTCx, CR, (LL_RTC_ReadReg(RTCx, CR) & RTC_CR_WUCKSEL)); -#else - LL_RTC_WriteReg(RTCx, CR, 0x00000000U); -#endif /* RTC_WAKEUP_SUPPORT */ - LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); + + LL_RTC_WriteReg(RTCx, PRER, (RTC_PRER_PREDIV_A | RTC_SYNCH_PRESC_DEFAULT)); LL_RTC_WriteReg(RTCx, ALRMAR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMBR, 0x00000000U); - LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U); LL_RTC_WriteReg(RTCx, CALR, 0x00000000U); + LL_RTC_WriteReg(RTCx, SHIFTR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMASSR, 0x00000000U); LL_RTC_WriteReg(RTCx, ALRMBSSR, 0x00000000U); @@ -325,7 +307,7 @@ ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Time } /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTC); + LL_RTC_DisableInitMode(RTCx); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) @@ -379,7 +361,7 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date if ((RTC_Format == LL_RTC_FORMAT_BIN) && ((RTC_DateStruct->Month & 0x10U) == 0x10U)) { - RTC_DateStruct->Month = (RTC_DateStruct->Month & (uint32_t)~(0x10U)) + 0x0AU; + RTC_DateStruct->Month = (uint8_t)(RTC_DateStruct->Month & (uint8_t)~(0x10U)) + 0x0AU; } if (RTC_Format == LL_RTC_FORMAT_BIN) { @@ -413,7 +395,7 @@ ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_Date } /* Exit Initialization mode */ - LL_RTC_DisableInitMode(RTC); + LL_RTC_DisableInitMode(RTCx); /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if (LL_RTC_IsShadowRegBypassEnabled(RTCx) == 0U) @@ -794,7 +776,7 @@ ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) * synchronized with RTC APB clock. * @note The RTC Resynchronization mode is write protected, use the * @ref LL_RTC_DisableWriteProtection before calling this function. - * @note To read the calendar through the shadow registers after Calendar + * @note To read the calendar through the shadow registers after calendar * initialization, calendar update or after wakeup from low power modes * the software must first clear the RSF flag. * The software must then wait until it is set again before reading @@ -819,7 +801,7 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) /* Wait the registers to be synchronised */ tmp = LL_RTC_IsActiveFlag_RS(RTCx); - while ((timeout != 0U) && (tmp != 0U)) + while ((timeout != 0U) && (tmp != 1U)) { if (LL_SYSTICK_IsActiveCounterFlag() == 1U) { @@ -832,24 +814,6 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) } } - if (status != ERROR) - { - timeout = RTC_SYNCHRO_TIMEOUT; - tmp = LL_RTC_IsActiveFlag_RS(RTCx); - while ((timeout != 0U) && (tmp != 1U)) - { - if (LL_SYSTICK_IsActiveCounterFlag() == 1U) - { - timeout--; - } - tmp = LL_RTC_IsActiveFlag_RS(RTCx); - if (timeout == 0U) - { - status = ERROR; - } - } - } - return (status); } @@ -872,5 +836,3 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) */ #endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.h index 1f57ce44454..bceea23ec64 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_rtc.h @@ -6,20 +6,19 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32F4xx_LL_RTC_H -#define __STM32F4xx_LL_RTC_H +#ifndef STM32F4xx_LL_RTC_H +#define STM32F4xx_LL_RTC_H #ifdef __cplusplus extern "C" { @@ -46,7 +45,7 @@ extern "C" { */ /* Masks Definition */ #define RTC_INIT_MASK 0xFFFFFFFFU -#define RTC_RSF_MASK 0xFFFFFF5FU +#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) /* Write protection defines */ #define RTC_WRITE_PROTECTION_DISABLE ((uint8_t)0xFFU) @@ -87,19 +86,19 @@ typedef struct { uint32_t HourFormat; /*!< Specifies the RTC Hours Format. This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT - + This feature can be modified afterwards using unitary function @ref LL_RTC_SetHourFormat(). */ uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F - + This feature can be modified afterwards using unitary function @ref LL_RTC_SetAsynchPrescaler(). */ uint32_t SynchPrescaler; /*!< Specifies the RTC Synchronous Predivider value. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF - + This feature can be modified afterwards using unitary function @ref LL_RTC_SetSynchPrescaler(). */ } LL_RTC_InitTypeDef; @@ -167,8 +166,8 @@ typedef struct uint32_t AlarmMask; /*!< Specifies the RTC Alarm Masks. This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B. - This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A - or @ref LL_RTC_ALMB_SetMask() for ALARM B + This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A + or @ref LL_RTC_ALMB_SetMask() for ALARM B. */ uint32_t AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on day or WeekDay. @@ -205,8 +204,8 @@ typedef struct /** @defgroup RTC_LL_EC_FORMAT FORMAT * @{ */ -#define LL_RTC_FORMAT_BIN 0x000000000U /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD 0x000000001U /*!< BCD data format */ +#define LL_RTC_FORMAT_BIN 0x00000000U /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD 0x00000001U /*!< BCD data format */ /** * @} */ @@ -236,8 +235,9 @@ typedef struct * @{ */ #define LL_RTC_ISR_RECALPF RTC_ISR_RECALPF -#define LL_RTC_ISR_TAMP3F RTC_ISR_TAMP3F +#if defined(RTC_TAMPER2_SUPPORT) #define LL_RTC_ISR_TAMP2F RTC_ISR_TAMP2F +#endif /* RTC_TAMPER2_SUPPORT */ #define LL_RTC_ISR_TAMP1F RTC_ISR_TAMP1F #define LL_RTC_ISR_TSOVF RTC_ISR_TSOVF #define LL_RTC_ISR_TSF RTC_ISR_TSF @@ -330,16 +330,6 @@ typedef struct * @} */ -/** @defgroup RTC_LL_EC_PIN PIN - * @{ - */ -#define LL_RTC_PIN_PC13 RTC_TAFCR_PC13MODE /*!< PC13 is forced to push-pull output if all RTC alternate functions are disabled */ -#define LL_RTC_PIN_PC14 RTC_TAFCR_PC14MODE /*!< PC14 is forced to push-pull output if LSE is disabled */ -#define LL_RTC_PIN_PC15 RTC_TAFCR_PC15MODE /*!< PC15 is forced to push-pull output if LSE is disabled */ -/** - * @} - */ - /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN * @{ */ @@ -392,11 +382,11 @@ typedef struct /** @defgroup RTC_LL_EC_ALMB_MASK ALARMB MASK * @{ */ -#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B*/ +#define LL_RTC_ALMB_MASK_NONE 0x00000000U /*!< No masks applied on Alarm B */ #define LL_RTC_ALMB_MASK_DATEWEEKDAY RTC_ALRMBR_MSK4 /*!< Date/day do not care in Alarm B comparison */ -#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ -#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ -#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_HOURS RTC_ALRMBR_MSK3 /*!< Hours do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_MINUTES RTC_ALRMBR_MSK2 /*!< Minutes do not care in Alarm B comparison */ +#define LL_RTC_ALMB_MASK_SECONDS RTC_ALRMBR_MSK1 /*!< Seconds do not care in Alarm B comparison */ #define LL_RTC_ALMB_MASK_ALL (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */ /** * @} @@ -440,29 +430,6 @@ typedef struct * @} */ -/** @defgroup RTC_LL_EC_TAMPER_MASK TAMPER MASK - * @{ - */ -#define LL_RTC_TAMPER_MASK_TAMPER1 RTC_TAFCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */ -#if defined(RTC_TAMPER2_SUPPORT) -#define LL_RTC_TAMPER_MASK_TAMPER2 RTC_TAFCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */ -#endif /* RTC_TAMPER2_SUPPORT */ -/** - * @} - */ - -/** @defgroup RTC_LL_EC_TAMPER_NOERASE TAMPER NO ERASE - * @{ - */ -#define LL_RTC_TAMPER_NOERASE_TAMPER1 RTC_TAFCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */ -#if defined(RTC_TAMPER2_SUPPORT) -#define LL_RTC_TAMPER_NOERASE_TAMPER2 RTC_TAFCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */ -#endif /* RTC_TAMPER2_SUPPORT */ -/** - * @} - */ - -#if defined(RTC_TAFCR_TAMPPRCH) /** @defgroup RTC_LL_EC_TAMPER_DURATION TAMPER DURATION * @{ */ @@ -473,9 +440,7 @@ typedef struct /** * @} */ -#endif /* RTC_TAFCR_TAMPPRCH */ -#if defined(RTC_TAFCR_TAMPFLT) /** @defgroup RTC_LL_EC_TAMPER_FILTER TAMPER FILTER * @{ */ @@ -486,9 +451,7 @@ typedef struct /** * @} */ -#endif /* RTC_TAFCR_TAMPFLT */ -#if defined(RTC_TAFCR_TAMPFREQ) /** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV TAMPER SAMPLING FREQUENCY DIVIDER * @{ */ @@ -503,14 +466,13 @@ typedef struct /** * @} */ -#endif /* RTC_TAFCR_TAMPFREQ */ /** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL TAMPER ACTIVE LEVEL * @{ */ -#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 RTC_TAFCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ #if defined(RTC_TAMPER2_SUPPORT) -#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/ +#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 RTC_TAFCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */ #endif /* RTC_TAMPER2_SUPPORT */ /** * @} @@ -537,7 +499,6 @@ typedef struct #define LL_RTC_BKP_DR2 0x00000002U #define LL_RTC_BKP_DR3 0x00000003U #define LL_RTC_BKP_DR4 0x00000004U -#if RTC_BKP_NUMBER > 5 #define LL_RTC_BKP_DR5 0x00000005U #define LL_RTC_BKP_DR6 0x00000006U #define LL_RTC_BKP_DR7 0x00000007U @@ -549,14 +510,10 @@ typedef struct #define LL_RTC_BKP_DR13 0x0000000DU #define LL_RTC_BKP_DR14 0x0000000EU #define LL_RTC_BKP_DR15 0x0000000FU -#endif /* RTC_BKP_NUMBER > 5 */ - -#if RTC_BKP_NUMBER > 16 #define LL_RTC_BKP_DR16 0x00000010U #define LL_RTC_BKP_DR17 0x00000011U #define LL_RTC_BKP_DR18 0x00000012U #define LL_RTC_BKP_DR19 0x00000013U -#endif /* RTC_BKP_NUMBER > 16 */ /** * @} */ @@ -580,7 +537,7 @@ typedef struct * @} */ -/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion +/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE Calibration pulse insertion * @{ */ #define LL_RTC_CALIB_INSERTPULSE_NONE 0x00000000U /*!< No RTCCLK pulses are added */ @@ -605,7 +562,7 @@ typedef struct #define LL_RTC_TimeStampPin_Default 0x00000000U /*!< Use RTC_AF1 as TIMESTAMP */ #if defined(RTC_AF2_SUPPORT) #define LL_RTC_TimeStampPin_Pos1 RTC_TAFCR_TSINSEL /*!< Use RTC_AF2 as TIMESTAMP */ -#endif +#endif /* RTC_AF2_SUPPORT */ /** * @} */ @@ -616,7 +573,7 @@ typedef struct #define LL_RTC_TamperPin_Default 0x00000000U /*!< Use RTC_AF1 as TAMPER1 */ #if defined(RTC_AF2_SUPPORT) #define LL_RTC_TamperPin_Pos1 RTC_TAFCR_TAMP1INSEL /*!< Use RTC_AF2 as TAMPER1 */ -#endif +#endif /* RTC_AF2_SUPPORT */ /** * @} */ @@ -837,8 +794,6 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) /** * @brief Set RTC_ALARM output type (ALARM in push-pull or open-drain output) * @note Used only when RTC_ALARM is mapped on PC13 - * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the - * PC13 output data * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_SetAlarmOutputType * @param RTCx RTC Instance * @param Output This parameter can be one of the following values: @@ -854,8 +809,6 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Outpu /** * @brief Get RTC_ALARM output type (ALARM in push-pull or open-drain output) * @note used only when RTC_ALARM is mapped on PC13 - * @note If all RTC alternate functions are disabled and PC13MODE = 1, PC13VALUE configures the - * PC13 output data * @rmtoll TAFCR ALARMOUTTYPE LL_RTC_GetAlarmOutputType * @param RTCx RTC Instance * @retval Returned value can be one of the following values: @@ -867,76 +820,6 @@ __STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_ALARMOUTTYPE)); } -/** - * @brief Enable push-pull output on PC13, PC14 and/or PC15 - * @note PC13 forced to push-pull output if all RTC alternate functions are disabled - * @note PC14 and PC15 forced to push-pull output if LSE is disabled - * @rmtoll TAFCR PC13MODE LL_RTC_EnablePushPullMode\n - * @rmtoll TAFCR PC14MODE LL_RTC_EnablePushPullMode\n - * @rmtoll TAFCR PC15MODE LL_RTC_EnablePushPullMode - * @param RTCx RTC Instance - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_PIN_PC13 - * @arg @ref LL_RTC_PIN_PC14 - * @arg @ref LL_RTC_PIN_PC15 - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnablePushPullMode(RTC_TypeDef *RTCx, uint32_t PinMask) -{ - SET_BIT(RTCx->TAFCR, PinMask); -} - -/** - * @brief Disable push-pull output on PC13, PC14 and/or PC15 - * @note PC13, PC14 and/or PC15 are controlled by the GPIO configuration registers. - * Consequently PC13, PC14 and/or PC15 are floating in Standby mode. - * @rmtoll TAFCR PC13MODE LL_RTC_DisablePushPullMode\n - * TAFCR PC14MODE LL_RTC_DisablePushPullMode\n - * TAFCR PC15MODE LL_RTC_DisablePushPullMode - * @param RTCx RTC Instance - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_PIN_PC13 - * @arg @ref LL_RTC_PIN_PC14 - * @arg @ref LL_RTC_PIN_PC15 - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisablePushPullMode(RTC_TypeDef* RTCx, uint32_t PinMask) -{ - CLEAR_BIT(RTCx->TAFCR, PinMask); -} - -/** - * @brief Set PC14 and/or PC15 to high level. - * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode) - * @rmtoll TAFCR PC14VALUE LL_RTC_SetOutputPin\n - * TAFCR PC15VALUE LL_RTC_SetOutputPin - * @param RTCx RTC Instance - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_PIN_PC14 - * @arg @ref LL_RTC_PIN_PC15 - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask) -{ - SET_BIT(RTCx->TAFCR, (PinMask >> 1)); -} - -/** - * @brief Set PC14 and/or PC15 to low level. - * @note Output data configuration is possible if the LSE is disabled and PushPull output is enabled (through @ref LL_RTC_EnablePushPullMode) - * @rmtoll TAFCR PC14VALUE LL_RTC_ResetOutputPin\n - * TAFCR PC15VALUE LL_RTC_ResetOutputPin - * @param RTCx RTC Instance - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_RTC_PIN_PC14 - * @arg @ref LL_RTC_PIN_PC15 - * @retval None - */ -__STATIC_INLINE void LL_RTC_ResetOutputPin(RTC_TypeDef* RTCx, uint32_t PinMask) -{ - CLEAR_BIT(RTCx->TAFCR, (PinMask >> 1)); -} - /** * @brief Enable initialization mode * @note Initialization mode is used to program time and date register (RTC_TR and RTC_DR) @@ -1023,7 +906,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)); + return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL); } /** @@ -1147,7 +1030,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma /** * @brief Get time format (AM or PM notation) - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1181,7 +1064,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) /** * @brief Get Hours in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1216,7 +1099,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) /** * @brief Get Minutes in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1229,7 +1112,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU))>> RTC_TR_MNU_Pos); + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); } /** @@ -1251,7 +1134,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) /** * @brief Get Seconds in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1290,18 +1173,18 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp; - temp = Format12_24 | \ - (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \ - (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); + (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)); MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp); } /** * @brief Get time (hour, minute and second) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar * shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)). @@ -1318,12 +1201,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, */ __STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU)); - return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR) | \ - (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \ - ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos))); + return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU))); } /** @@ -1358,7 +1236,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)); + return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL); } /** @@ -1386,17 +1264,18 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) } /** - * @brief Get Sub second value in the synchronous prescaler counter. + * @brief Get subseconds value in the synchronous prescaler counter. * @note You can use both SubSeconds value and SecondFraction (PREDIV_S through * LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar * SubSeconds value in second fraction ratio with time unit following * generic formula: - * ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit + * ==> Seconds fraction ratio * time_unit = + * [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit * This conversion can be performed only if no shift operation is pending * (ie. SHFP=0) when PREDIV_S >= SS. * @rmtoll SSR SS LL_RTC_TIME_GetSubSecond * @param RTCx RTC Instance - * @retval Sub second value (number between 0 and 65535) + * @retval Subseconds value (number between 0 and 65535) */ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) { @@ -1447,7 +1326,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) /** * @brief Get Year in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format * @rmtoll DR YT LL_RTC_DATE_GetYear\n @@ -1481,7 +1360,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) /** * @brief Get Week day - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @rmtoll DR WDU LL_RTC_DATE_GetWeekDay * @param RTCx RTC Instance @@ -1528,7 +1407,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) /** * @brief Get Month in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format * @rmtoll DR MT LL_RTC_DATE_GetMonth\n @@ -1550,7 +1429,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) */ __STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) { - return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU)))>> RTC_DR_MU_Pos); + return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); } /** @@ -1570,7 +1449,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) /** * @brief Get Day in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format * @rmtoll DR DT LL_RTC_DATE_GetDay\n @@ -1620,19 +1499,19 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) { - register uint32_t temp = 0U; + uint32_t temp; - temp = (WeekDay << RTC_DR_WDU_Pos) | \ - (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ + temp = ( WeekDay << RTC_DR_WDU_Pos) | \ + (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)) | \ (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \ - (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); + (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)); MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp); } /** * @brief Get date (WeekDay, Day, Month and Year) in BCD format - * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set + * @note if RTC shadow registers are not bypassed (BYPSHAD=0), need to check if RSF flag is set * before reading this bit * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH, * and __LL_RTC_GET_DAY are available to get independently each parameter. @@ -1648,13 +1527,14 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin */ __STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - + uint32_t temp; + temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU)); - return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ - (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY) | \ - (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \ - ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos))); + + return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \ + (((temp & (RTC_DR_DT | RTC_DR_DU)) >> RTC_DR_DU_Pos) << RTC_OFFSET_DAY) | \ + (((temp & (RTC_DR_MT | RTC_DR_MU)) >> RTC_DR_MU_Pos) << RTC_OFFSET_MONTH) | \ + ((temp & (RTC_DR_YT | RTC_DR_YU)) >> RTC_DR_YU_Pos)); } /** @@ -1869,7 +1749,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) */ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) { - return (uint32_t)(( READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); + return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } /** @@ -1948,11 +1828,12 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp; - temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ - (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); + (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); } @@ -1976,7 +1857,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) } /** - * @brief Set Alarm A Mask the most-significant bits starting at this bit + * @brief Mask the most-significant bits of the subseconds field starting from + * the bit specified in parameter Mask * @note This register can be written only when ALRAE is reset in RTC_CR register, * or in initialization mode. * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_SetSubSecondMask @@ -1990,7 +1872,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma } /** - * @brief Get Alarm A Mask the most-significant bits starting at this bit + * @brief Get Alarm A subseconds mask * @rmtoll ALRMASSR MASKSS LL_RTC_ALMA_GetSubSecondMask * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF @@ -2001,7 +1883,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) } /** - * @brief Set Alarm A Sub seconds value + * @brief Set Alarm A subseconds value * @rmtoll ALRMASSR SS LL_RTC_ALMA_SetSubSecond * @param RTCx RTC Instance * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF @@ -2013,7 +1895,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec } /** - * @brief Get Alarm A Sub seconds value + * @brief Get Alarm A subseconds value * @rmtoll ALRMASSR SS LL_RTC_ALMA_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF @@ -2129,7 +2011,7 @@ __STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) { - MODIFY_REG(RTC->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), + MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU), (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos))); } @@ -2143,7 +2025,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) { - return (uint32_t)(( READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } /** @@ -2291,10 +2173,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) */ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) { - register uint32_t temp = 0U; - - temp = READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU)); - return (uint32_t)((((temp & RTC_ALRMBR_ST) >> RTC_ALRMBR_ST_Pos) << 4U) | ((temp & RTC_ALRMBR_SU) >> RTC_ALRMBR_SU_Pos)); + return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } /** @@ -2317,13 +2196,14 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) { - register uint32_t temp = 0U; + uint32_t temp; - temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ + temp = Format12_24 | \ + (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)) | \ (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ - (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); + (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); - MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM| RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); } /** @@ -2345,7 +2225,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx) } /** - * @brief Set Alarm B Mask the most-significant bits starting at this bit + * @brief Mask the most-significant bits of the subseconds field starting from + * the bit specified in parameter Mask * @note This register can be written only when ALRBE is reset in RTC_CR register, * or in initialization mode. * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_SetSubSecondMask @@ -2359,7 +2240,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma } /** - * @brief Get Alarm B Mask the most-significant bits starting at this bit + * @brief Get Alarm B subseconds mask * @rmtoll ALRMBSSR MASKSS LL_RTC_ALMB_GetSubSecondMask * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF @@ -2370,7 +2251,7 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) } /** - * @brief Set Alarm B Sub seconds value + * @brief Set Alarm B subseconds value * @rmtoll ALRMBSSR SS LL_RTC_ALMB_SetSubSecond * @param RTCx RTC Instance * @param Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF @@ -2382,7 +2263,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec } /** - * @brief Get Alarm B Sub seconds value + * @brief Get Alarm B subseconds value * @rmtoll ALRMBSSR SS LL_RTC_ALMB_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF @@ -2599,7 +2480,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) } /** - * @brief Get time-stamp sub second value + * @brief Get time-stamp subseconds value * @rmtoll TSSSR SS LL_RTC_TS_GetSubSecond * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF @@ -2637,17 +2518,17 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) * @brief Set timestamp Pin * @rmtoll TAFCR TSINSEL LL_RTC_TS_SetPin * @param RTCx RTC Instance - * @param TSPin specifies the RTC TimeStamp Pin. + * @param TSPin specifies the RTC Timestamp Pin. * This parameter can be one of the following values: - * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC TimeStamp. - * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is selected as RTC TimeStamp. (*) - * - * (*) value not defined in all devices. + * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC Timestamp Pin. + * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is used as RTC Timestamp Pin. (*) + * + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TS_SetPin(RTC_TypeDef *RTCx, uint32_t TSPin) { - MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TSINSEL , TSPin); + MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TSINSEL, TSPin); } /** @@ -2655,16 +2536,15 @@ __STATIC_INLINE void LL_RTC_TS_SetPin(RTC_TypeDef *RTCx, uint32_t TSPin) * @rmtoll TAFCR TSINSEL LL_RTC_TS_GetPin * @param RTCx RTC Instance * @retval Returned value can be one of the following values: - * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC TimeStamp Pin. - * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is selected as RTC TimeStamp Pin. (*) - * - * (*) value not defined in all devices. + * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC Timestamp Pin. + * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is used as RTC Timestamp Pin. (*) + * + * (*) value not applicable to all devices. * @retval None */ - __STATIC_INLINE uint32_t LL_RTC_TS_GetPin(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TSINSEL)); + return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TSINSEL)); } /** @@ -2681,10 +2561,10 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetPin(RTC_TypeDef *RTCx) * TAFCR TAMP2E LL_RTC_TAMPER_Enable\n * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_1 * @arg @ref LL_RTC_TAMPER_2 (*) - * - * (*) value not defined in all devices. + * + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2698,10 +2578,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) * TAFCR TAMP2E LL_RTC_TAMPER_Disable\n * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_1 + * @arg @ref LL_RTC_TAMPER_1 * @arg @ref LL_RTC_TAMPER_2 (*) - * - * (*) value not defined in all devices. + * + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2709,7 +2589,6 @@ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) CLEAR_BIT(RTCx->TAFCR, Tamper); } -#if defined(RTC_TAFCR_TAMPPUDIS) /** * @brief Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins) * @rmtoll TAFCR TAMPPUDIS LL_RTC_TAMPER_DisablePullUp @@ -2731,9 +2610,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) { CLEAR_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPUDIS); } -#endif /* RTC_TAFCR_TAMPPUDIS */ -#if defined(RTC_TAFCR_TAMPPRCH) /** * @brief Set RTC_TAMPx precharge duration * @rmtoll TAFCR TAMPPRCH LL_RTC_TAMPER_SetPrecharge @@ -2764,9 +2641,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPPRCH)); } -#endif /* RTC_TAFCR_TAMPPRCH */ -#if defined(RTC_TAFCR_TAMPFLT) /** * @brief Set RTC_TAMPx filter count * @rmtoll TAFCR TAMPFLT LL_RTC_TAMPER_SetFilterCount @@ -2797,9 +2672,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFLT)); } -#endif /* RTC_TAFCR_TAMPFLT */ -#if defined(RTC_TAFCR_TAMPFREQ) /** * @brief Set Tamper sampling frequency * @rmtoll TAFCR TAMPFREQ LL_RTC_TAMPER_SetSamplingFreq @@ -2838,7 +2711,6 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMPFREQ)); } -#endif /* RTC_TAFCR_TAMPFREQ */ /** * @brief Enable Active level for Tamper input @@ -2846,10 +2718,10 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) * TAFCR TAMP2TRG LL_RTC_TAMPER_EnableActiveLevel\n * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*) - * - * (*) value not defined in all devices. + * + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2863,10 +2735,10 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t * TAFCR TAMP2TRG LL_RTC_TAMPER_DisableActiveLevel\n * @param RTCx RTC Instance * @param Tamper This parameter can be a combination of the following values: - * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 + * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1 * @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2 (*) - * - * (*) value not defined in all devices. + * + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) @@ -2880,15 +2752,15 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_ * @param RTCx RTC Instance * @param TamperPin specifies the RTC Tamper Pin. * This parameter can be one of the following values: - * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper. - * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper. (*) - * - * (*) value not defined in all devices. + * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper Pin. + * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is used as RTC Tamper Pin. (*) + * + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE void LL_RTC_TAMPER_SetPin(RTC_TypeDef *RTCx, uint32_t TamperPin) { - MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL , TamperPin); + MODIFY_REG(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL, TamperPin); } /** @@ -2898,14 +2770,14 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetPin(RTC_TypeDef *RTCx, uint32_t TamperPin) * @retval Returned value can be one of the following values: * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper Pin. * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper Pin. (*) - * - * (*) value not defined in all devices. + * + * (*) value not applicable to all devices. * @retval None */ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPin(RTC_TypeDef *RTCx) { - return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL)); + return (uint32_t)(READ_BIT(RTCx->TAFCR, RTC_TAFCR_TAMP1INSEL)); } /** @@ -2948,13 +2820,13 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)); + return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL); } /** * @brief Select Wakeup clock * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 + * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1 * @rmtoll CR WUCKSEL LL_RTC_WAKEUP_SetClock * @param RTCx RTC Instance * @param WakeupClock This parameter can be one of the following values: @@ -2990,7 +2862,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) /** * @brief Set Wakeup auto-reload value - * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR + * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR * @rmtoll WUTR WUT LL_RTC_WAKEUP_SetAutoReload * @param RTCx RTC Instance * @param Value Value between Min_Data=0x00 and Max_Data=0xFFFF @@ -3050,13 +2922,13 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) */ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) { - register uint32_t tmp = 0U; + uint32_t temp; - tmp = (uint32_t)(&(RTCx->BKP0R)); - tmp += (BackupRegister * 4U); + temp = (uint32_t)(&(RTCx->BKP0R)); + temp += (BackupRegister * 4U); /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; + *(__IO uint32_t *)temp = (uint32_t)Data; } /** @@ -3088,13 +2960,13 @@ __STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe */ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) { - register uint32_t tmp = 0U; + uint32_t temp; - tmp = (uint32_t)(&(RTCx->BKP0R)); - tmp += (BackupRegister * 4U); + temp = (uint32_t)(&(RTCx->BKP0R)); + temp += (BackupRegister * 4U); /* Read the specified register */ - return (*(__IO uint32_t *)tmp); + return (*(__IO uint32_t *)temp); } /** @@ -3115,6 +2987,7 @@ __STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t Back * @arg @ref LL_RTC_CALIB_OUTPUT_NONE * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * * @retval None */ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency) @@ -3131,6 +3004,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque * @arg @ref LL_RTC_CALIB_OUTPUT_NONE * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ + * */ __STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) { @@ -3178,7 +3052,7 @@ __STATIC_INLINE void LL_RTC_CAL_DisableCoarseDigital(RTC_TypeDef *RTCx) * @note This Calibration value should be between 0 and 126 when using positive sign with a 4-ppm step. * @retval None */ -__STATIC_INLINE void LL_RTC_CAL_ConfigCoarseDigital(RTC_TypeDef* RTCx, uint32_t Sign, uint32_t Value) +__STATIC_INLINE void LL_RTC_CAL_ConfigCoarseDigital(RTC_TypeDef *RTCx, uint32_t Sign, uint32_t Value) { MODIFY_REG(RTCx->CALIBR, RTC_CALIBR_DCS | RTC_CALIBR_DC, Sign | Value); } @@ -3202,7 +3076,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalValue(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_CALIB_SIGN_POSITIVE * @arg @ref LL_RTC_CALIB_SIGN_NEGATIVE */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalSign(RTC_TypeDef* RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalSign(RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALIBR, RTC_CALIBR_DCS)); } @@ -3210,7 +3084,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigitalSign(RTC_TypeDef* RTCx) /** * @brief Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm) * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR + * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR * @rmtoll CALR CALP LL_RTC_CAL_SetPulse * @param RTCx RTC Instance * @param Pulse This parameter can be one of the following values: @@ -3231,11 +3105,11 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) */ __STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)); + return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL); } /** - * @brief Set the calibration cycle period + * @brief Set smooth calibration cycle period * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR * @rmtoll CALR CALW8 LL_RTC_CAL_SetPeriod\n @@ -3253,7 +3127,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) } /** - * @brief Get the calibration cycle period + * @brief Get smooth calibration cycle period * @rmtoll CALR CALW8 LL_RTC_CAL_GetPeriod\n * CALR CALW16 LL_RTC_CAL_GetPeriod * @param RTCx RTC Instance @@ -3268,7 +3142,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) } /** - * @brief Set Calibration minus + * @brief Set smooth Calibration minus * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. * @note Bit can be written only when RECALPF is set to 0 in RTC_ISR * @rmtoll CALR CALM LL_RTC_CAL_SetMinus @@ -3282,7 +3156,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) } /** - * @brief Get Calibration minus + * @brief Get smooth Calibration minus * @rmtoll CALR CALM LL_RTC_CAL_GetMinus * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF @@ -3308,10 +3182,9 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL); } - #if defined(RTC_TAMPER2_SUPPORT) /** * @brief Get RTC_TAMP2 detection flag @@ -3321,7 +3194,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL); } #endif /* RTC_TAMPER2_SUPPORT */ @@ -3333,7 +3206,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL); } /** @@ -3344,7 +3217,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL); } /** @@ -3355,7 +3228,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL); } /** @@ -3366,7 +3239,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL); } /** @@ -3377,7 +3250,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL); } /** @@ -3388,10 +3261,9 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL); } - #if defined(RTC_TAMPER2_SUPPORT) /** * @brief Clear RTC_TAMP2 detection flag @@ -3479,7 +3351,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL); } /** @@ -3490,7 +3362,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL); } /** @@ -3512,7 +3384,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL); } /** @@ -3523,7 +3395,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL); } /** @@ -3534,7 +3406,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL); } /** @@ -3545,7 +3417,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL); } /** @@ -3556,7 +3428,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)); + return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL); } /** @@ -3693,7 +3565,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)); + return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL); } /** @@ -3704,7 +3576,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)); + return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL); } /** @@ -3715,7 +3587,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)); + return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL); } /** @@ -3726,7 +3598,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)); + return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL); } /** @@ -3737,8 +3609,8 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) */ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx) { - return (READ_BIT(RTCx->TAFCR, - RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE)); + return ((READ_BIT(RTCx->TAFCR, + RTC_TAFCR_TAMPIE) == (RTC_TAFCR_TAMPIE)) ? 1UL : 0UL); } /** @@ -3788,6 +3660,4 @@ ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); } #endif -#endif /* __STM32F4xx_LL_RTC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +#endif /* STM32F4xx_LL_RTC_H */ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.c index ff89435bf7e..ab4830393a4 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.c @@ -11,6 +11,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### SDMMC peripheral features ##### @@ -142,17 +153,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ @@ -177,11 +177,6 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx); -static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout); -static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx); -static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx); -static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx); -static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA); /* Exported functions --------------------------------------------------------*/ @@ -311,10 +306,6 @@ HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx) /* Set power state to ON */ SDIOx->POWER = SDIO_POWER_PWRCTRL; - /* 1ms: required power up waiting time before starting the SD initialization - sequence */ - HAL_Delay(2); - return HAL_OK; } @@ -1026,6 +1017,31 @@ uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA) return errorstate; } +/** + * @brief Send the Set Relative Address command to MMC card (not SD card). + * @param SDIOx Pointer to SDIO register base + * @param RCA Card RCA + * @retval HAL status + */ +uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD3 SD_CMD_SET_REL_ADDR */ + sdmmc_cmdinit.Argument = ((uint32_t)RCA << 16U); + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SET_REL_ADDR; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_SET_REL_ADDR, SDIO_CMDTIMEOUT); + + return errorstate; +} + /** * @brief Send the Status command and check the response. * @param SDIOx: Pointer to SDIO register base @@ -1125,47 +1141,54 @@ uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument) } /** - * @} + * @brief Send the Send EXT_CSD command and check the response. + * @param SDIOx Pointer to SDMMC register base + * @param Argument Command Argument + * @retval HAL status */ +uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) +{ + SDIO_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + /* Send CMD9 SEND_CSD */ + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; + sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; + sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; + (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SEND_EXT_CSD,SDIO_CMDTIMEOUT); + + return errorstate; +} -/* Private function ----------------------------------------------------------*/ -/** @addtogroup SD_Private_Functions - * @{ - */ - /** - * @brief Checks for error conditions for CMD0. - * @param hsd: SD handle - * @retval SD Card error state + * @} */ -static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) -{ - /* 8 is the number of required instructions cycles for the below loop statement. - The SDIO_CMDTIMEOUT is expressed in ms */ - uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); - - do - { - if (count-- == 0U) - { - return SDMMC_ERROR_TIMEOUT; - } - - }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); - - /* Clear all the static flags */ - __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); - - return SDMMC_ERROR_NONE; -} +/** @defgroup HAL_SDMMC_LL_Group5 Responses management functions + * @brief Responses functions + * +@verbatim + =============================================================================== + ##### Responses management functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the needed responses. + +@endverbatim + * @{ + */ /** * @brief Checks for error conditions for R1 response. - * @param hsd: SD handle + * @param SDIOx Pointer to SDMMC register base * @param SD_CMD: The sent command index * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) +uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout) { uint32_t response_r1; uint32_t sta_reg; @@ -1297,10 +1320,10 @@ static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t /** * @brief Checks for error conditions for R2 (CID or CSD) response. - * @param hsd: SD handle + * @param SDIOx Pointer to SDMMC register base * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) +uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) { uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. @@ -1341,10 +1364,10 @@ static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx) /** * @brief Checks for error conditions for R3 (OCR) response. - * @param hsd: SD handle + * @param SDIOx Pointer to SDMMC register base * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) +uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) { uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. @@ -1378,13 +1401,13 @@ static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx) /** * @brief Checks for error conditions for R6 (RCA) response. - * @param hsd: SD handle + * @param SDIOx Pointer to SDMMC register base * @param SD_CMD: The sent command index * @param pRCA: Pointer to the variable that will contain the SD card relative * address RCA * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) +uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA) { uint32_t response_r1; uint32_t sta_reg; @@ -1454,10 +1477,10 @@ static uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t /** * @brief Checks for error conditions for R7 response. - * @param hsd: SD handle + * @param SDIOx Pointer to SDMMC register base * @retval SD Card error state */ -static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) +uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) { uint32_t sta_reg; /* 8 is the number of required instructions cycles for the below loop statement. @@ -1504,28 +1527,38 @@ static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx) } /** - * @brief Send the Send EXT_CSD command and check the response. - * @param SDIOx: Pointer to SDMMC register base - * @param Argument: Command Argument - * @retval HAL status + * @} */ -uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) -{ - SDIO_CmdInitTypeDef sdmmc_cmdinit; - uint32_t errorstate; - /* Send CMD9 SEND_CSD */ - sdmmc_cmdinit.Argument = Argument; - sdmmc_cmdinit.CmdIndex = SDMMC_CMD_HS_SEND_EXT_CSD; - sdmmc_cmdinit.Response = SDIO_RESPONSE_SHORT; - sdmmc_cmdinit.WaitForInterrupt = SDIO_WAIT_NO; - sdmmc_cmdinit.CPSM = SDIO_CPSM_ENABLE; - (void)SDIO_SendCommand(SDIOx, &sdmmc_cmdinit); - - /* Check for error conditions */ - errorstate = SDMMC_GetCmdResp1(SDIOx, SDMMC_CMD_HS_SEND_EXT_CSD,SDIO_CMDTIMEOUT); - - return errorstate; +/* Private function ----------------------------------------------------------*/ +/** @addtogroup SD_Private_Functions + * @{ + */ + +/** + * @brief Checks for error conditions for CMD0. + * @param SDIOx Pointer to SDMMC register base + * @retval SD Card error state + */ +static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx) +{ + /* 8 is the number of required instructions cycles for the below loop statement. + The SDIO_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDIO_CMDTIMEOUT * (SystemCoreClock / 8U /1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + + }while(!__SDIO_GET_FLAG(SDIOx, SDIO_FLAG_CMDSENT)); + + /* Clear all the static flags */ + __SDIO_CLEAR_FLAG(SDIOx, SDIO_STATIC_CMD_FLAGS); + + return SDMMC_ERROR_NONE; } @@ -1543,5 +1576,3 @@ uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument) */ #endif /* SDIO */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.h index 540a0e180d2..a4092d042e6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_sdmmc.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1069,8 +1068,14 @@ uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx); /* SDMMC Cards mode management functions */ HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode); +/** + * @} + */ /* SDMMC Commands management functions */ +/** @addtogroup HAL_SDMMC_LL_Group4 + * @{ + */ uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); @@ -1091,13 +1096,26 @@ uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); -uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); +uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA); uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); +uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); +/** + * @} + */ +/* SDMMC Responses management functions *****************************************/ +/** @addtogroup HAL_SDMMC_LL_Group5 + * @{ + */ +uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout); +uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx); +uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA); +uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx); /** * @} */ @@ -1121,5 +1139,3 @@ uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); #endif #endif /* STM32F4xx_LL_SDMMC_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.c index dfbdabe3c7f..02a074068ec 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -27,7 +26,7 @@ #include "stm32_assert.h" #else #define assert_param(expr) ((void)0U) -#endif +#endif /* USE_FULL_ASSERT */ /** @addtogroup STM32F4xx_LL_Driver * @{ @@ -623,4 +622,3 @@ ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.h index ec61b36e7f8..4f3b0306f1d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_spi.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -1075,7 +1074,7 @@ __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) */ __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) { - return (uint8_t)(READ_REG(SPIx->DR)); + return (*((__IO uint8_t *)&SPIx->DR)); } /** @@ -2026,4 +2025,3 @@ ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_ #endif /* STM32F4xx_LL_SPI_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_system.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_system.h index cc7635e9f88..84ea5c4d1a3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_system.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_system.h @@ -3,6 +3,18 @@ * @file stm32f4xx_ll_system.h * @author MCD Application Team * @brief Header file of SYSTEM LL module. + * + ****************************************************************************** + * @attention + * + *Copyright (c) 2017 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -16,17 +28,6 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** */ /* Define to prevent recursive inclusion -------------------------------------*/ @@ -767,7 +768,7 @@ __STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void) /** * @brief Enables the DFSDM1 or DFSDM2 Delay clock * @rmtoll SYSCFG_MCHDLYCR MCHDLYEN LL_SYSCFG_DFSDM_EnableDelayClock - * @param MCHDLY This paramater can be one of the following values + * @param MCHDLY This parameter can be one of the following values * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN * @retval None @@ -780,7 +781,7 @@ __STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY) /** * @brief Disables the DFSDM1 or the DFSDM2 Delay clock * @rmtoll SYSCFG_MCHDLYCR MCHDLY1EN LL_SYSCFG_DFSDM1_DisableDelayClock - * @param MCHDLY This paramater can be one of the following values + * @param MCHDLY This parameter can be one of the following values * @arg @ref LL_SYSCFG_DFSDM1_MCHDLYEN * @arg @ref LL_SYSCFG_DFSDM2_MCHDLYEN * @retval None @@ -1707,4 +1708,4 @@ __STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void) #endif /* __STM32F4xx_LL_SYSTEM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.c index fb1cfe78a8a..a0890c3383d 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -138,14 +137,14 @@ /** @defgroup TIM_LL_Private_Functions TIM Private Functions * @{ */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); /** * @} */ @@ -184,91 +183,91 @@ ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); } -#endif +#endif /* TIM2 */ #if defined(TIM3) else if (TIMx == TIM3) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); } -#endif +#endif /* TIM3 */ #if defined(TIM4) else if (TIMx == TIM4) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); } -#endif +#endif /* TIM4 */ #if defined(TIM5) else if (TIMx == TIM5) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); } -#endif +#endif /* TIM5 */ #if defined(TIM6) else if (TIMx == TIM6) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); } -#endif +#endif /* TIM6 */ #if defined (TIM7) else if (TIMx == TIM7) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); } -#endif +#endif /* TIM7 */ #if defined(TIM8) else if (TIMx == TIM8) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); } -#endif +#endif /* TIM8 */ #if defined(TIM9) else if (TIMx == TIM9) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); } -#endif +#endif /* TIM9 */ #if defined(TIM10) else if (TIMx == TIM10) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10); } -#endif +#endif /* TIM10 */ #if defined(TIM11) else if (TIMx == TIM11) { LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11); LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11); } -#endif +#endif /* TIM11 */ #if defined(TIM12) else if (TIMx == TIM12) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); } -#endif +#endif /* TIM12 */ #if defined(TIM13) else if (TIMx == TIM13) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); } -#endif +#endif /* TIM13 */ #if defined(TIM14) else if (TIMx == TIM14) { LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); } -#endif +#endif /* TIM14 */ else { result = ERROR; @@ -296,12 +295,13 @@ void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) /** * @brief Configure the TIMx time base unit. * @param TIMx Timer Instance - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure + * (TIMx time base unit configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) { uint32_t tmpcr1; @@ -349,7 +349,8 @@ ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) /** * @brief Set the fields of the TIMx output channel configuration data * structure to their default values. - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure + * (the output channel configuration data structure) * @retval None */ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) @@ -373,12 +374,13 @@ void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration + * data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) { ErrorStatus result = ERROR; @@ -406,7 +408,8 @@ ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTy /** * @brief Set the fields of the TIMx input channel configuration data * structure to their default values. - * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration + * data structure) * @retval None */ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) @@ -426,12 +429,13 @@ void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) * @arg @ref LL_TIM_CHANNEL_CH2 * @arg @ref LL_TIM_CHANNEL_CH3 * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data + * structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx output channel is initialized * - ERROR: TIMx output channel is not initialized */ -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) { ErrorStatus result = ERROR; @@ -458,7 +462,8 @@ ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTy /** * @brief Fills each TIM_EncoderInitStruct field with its default value - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface + * configuration data structure) * @retval None */ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) @@ -478,12 +483,13 @@ void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct /** * @brief Configure the encoder interface of the timer instance. * @param TIMx Timer Instance - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface + * configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -542,7 +548,8 @@ ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *T /** * @brief Set the fields of the TIMx Hall sensor interface configuration data * structure to their default values. - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface + * configuration data structure) * @retval None */ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) @@ -569,12 +576,13 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor + * interface configuration data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) { uint32_t tmpcr2; uint32_t tmpccmr1; @@ -649,7 +657,8 @@ ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitType /** * @brief Set the fields of the Break and Dead Time configuration data structure * to their default values. - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) * @retval None */ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) @@ -672,12 +681,13 @@ void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * a timer instance provides a break input. * @param TIMx Timer Instance - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration + * data structure) * @retval An ErrorStatus enumeration value: * - SUCCESS: Break and Dead Time is initialized * - ERROR: not applicable */ -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) { uint32_t tmpbdtr = 0; @@ -728,7 +738,7 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -807,7 +817,7 @@ static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr1; uint32_t tmpccer; @@ -886,7 +896,7 @@ static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -965,7 +975,7 @@ static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) { uint32_t tmpccmr2; uint32_t tmpccer; @@ -1036,7 +1046,7 @@ static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); @@ -1069,7 +1079,7 @@ static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(TIMx)); @@ -1102,7 +1112,7 @@ static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(TIMx)); @@ -1135,7 +1145,7 @@ static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni * - SUCCESS: TIMx registers are de-initialized * - ERROR: not applicable */ -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(TIMx)); @@ -1177,4 +1187,3 @@ static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICIni #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.h index e9b0b742688..a5cbe24301e 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_tim.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -185,24 +184,29 @@ typedef struct uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetPrescaler().*/ uint32_t CounterMode; /*!< Specifies the counter mode. This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetCounterMode().*/ uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active Auto-Reload Register at the next update event. This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must + be a number between 0x0000 and 0xFFFFFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetAutoReload().*/ uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetClockDivision().*/ uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter reaches zero, an update event is generated and counting restarts @@ -210,10 +214,13 @@ typedef struct This means in PWM mode that (N+1) corresponds to: - the number of PWM periods in edge-aligned mode - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + GP timers: this parameter must be a number between Min_Data = 0x00 and + Max_Data = 0xFF. + Advanced timers: this parameter must be a number between Min_Data = 0x0000 and + Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetRepetitionCounter().*/ } LL_TIM_InitTypeDef; /** @@ -224,43 +231,51 @@ typedef struct uint32_t OCMode; /*!< Specifies the output mode. This parameter can be a value of @ref TIM_LL_EC_OCMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetMode().*/ uint32_t OCState; /*!< Specifies the TIM Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + This feature can be modified afterwards using unitary functions + @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ + This feature can be modified afterwards using unitary function + LL_TIM_OC_SetCompareCHx (x=1..6).*/ uint32_t OCPolarity; /*!< Specifies the output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetPolarity().*/ uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetIdleState().*/ } LL_TIM_OC_InitTypeDef; /** @@ -273,22 +288,26 @@ typedef struct uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t ICActiveInput; /*!< Specifies the input. This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_IC_InitTypeDef; @@ -300,47 +319,56 @@ typedef struct uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. - This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetEncoderMode().*/ uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetActiveInput().*/ uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC2Filter; /*!< Specifies the TI2 input filter. This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ } LL_TIM_ENCODER_InitTypeDef; @@ -353,26 +381,31 @@ typedef struct uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPolarity().*/ uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. Prescaler must be set to get a maximum counter period longer than the time interval between 2 consecutive changes on the Hall inputs. This parameter can be a value of @ref TIM_LL_EC_ICPSC. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetPrescaler().*/ uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + This parameter can be a value of + @ref TIM_LL_EC_IC_FILTER. - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_IC_SetFilter().*/ uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. A positive pulse (TRGO event) is generated with a programmable delay every time a change occurs on the Hall inputs. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetCompareCH2().*/ } LL_TIM_HALLSENSOR_InitTypeDef; /** @@ -383,51 +416,63 @@ typedef struct uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. This parameter can be a value of @ref TIM_LL_EC_OSSR - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. This parameter can be a value of @ref TIM_LL_EC_OSSI - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + This feature can be modified afterwards using unitary function + @ref LL_TIM_SetOffStates() - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + @note This bit-field cannot be modified as long as LOCK level 2 has been + programmed. */ uint32_t LockLevel; /*!< Specifies the LOCK level parameters. This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL - @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register - has been written, their content is frozen until the next reset.*/ + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR + register has been written, their content is frozen until the next reset.*/ uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the switching-on of the outputs. This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + This feature can be modified afterwards using unitary function + @ref LL_TIM_OC_SetDeadTime() - @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been + programmed. */ uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + This feature can be modified afterwards using unitary function + @ref LL_TIM_ConfigBRK() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + This feature can be modified afterwards using unitary functions + @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + @note This bit-field can not be modified as long as LOCK level 1 has been + programmed. */ } LL_TIM_BDTR_InitTypeDef; /** @@ -978,10 +1023,17 @@ typedef struct * @retval DTG[0:7] */ #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ + (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ + (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 0U) /** @@ -992,7 +1044,7 @@ typedef struct * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) */ #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) /** * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. @@ -1006,7 +1058,8 @@ typedef struct ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) /** - * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare + * active/inactive delay. * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -1018,7 +1071,8 @@ typedef struct / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) /** - * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration + * (when the timer operates in one pulse mode). * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); * @param __TIMCLK__ timer input clock frequency (in Hz) * @param __PSC__ prescaler @@ -1089,7 +1143,7 @@ __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); } @@ -1122,7 +1176,7 @@ __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval Inverted state of bit (0 or 1). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); } @@ -1156,7 +1210,7 @@ __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSo * @arg @ref LL_TIM_UPDATESOURCE_REGULAR * @arg @ref LL_TIM_UPDATESOURCE_COUNTER */ -__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); } @@ -1183,7 +1237,7 @@ __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulse * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE */ -__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); } @@ -1227,7 +1281,7 @@ __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMo * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) { uint32_t counter_mode; @@ -1269,13 +1323,14 @@ __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); } /** - * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators + * (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. @@ -1293,7 +1348,8 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi } /** - * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time + * generators (when supported) and the digital filters. * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check * whether or not the clock division feature is supported by the timer * instance. @@ -1304,7 +1360,7 @@ __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDi * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 */ -__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); } @@ -1331,7 +1387,7 @@ __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) * @param TIMx Timer instance * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) */ -__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CNT)); } @@ -1344,7 +1400,7 @@ __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) * @arg @ref LL_TIM_COUNTERDIRECTION_UP * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN */ -__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); } @@ -1371,7 +1427,7 @@ __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) * @param TIMx Timer instance * @retval Prescaler value between Min_Data=0 and Max_Data=65535 */ -__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->PSC)); } @@ -1400,7 +1456,7 @@ __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload * @param TIMx Timer instance * @retval Auto-reload value */ -__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->ARR)); } @@ -1427,7 +1483,7 @@ __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t Rep * @param TIMx Timer instance * @retval Repetition counter value */ -__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->RCR)); } @@ -1506,7 +1562,7 @@ __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAR * @arg @ref LL_TIM_CCDMAREQUEST_CC * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE */ -__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); } @@ -1676,7 +1732,7 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); } /** @@ -1701,11 +1757,11 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_PWM1 * @arg @ref LL_TIM_OCMODE_PWM2 */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); } /** @@ -1759,7 +1815,7 @@ __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCPOLARITY_HIGH * @arg @ref LL_TIM_OCPOLARITY_LOW */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); @@ -1820,7 +1876,7 @@ __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCIDLESTATE_LOW * @arg @ref LL_TIM_OCIDLESTATE_HIGH */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); @@ -2031,7 +2087,8 @@ __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Ch } /** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of + * the Ocx and OCxN signals). * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not * dead-time insertion feature is supported by a timer instance. * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter @@ -2124,7 +2181,7 @@ __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t Compare * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -2140,7 +2197,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -2156,7 +2213,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -2172,7 +2229,7 @@ __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CompareValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -2224,7 +2281,8 @@ __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint3 uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), - ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ + << SHIFT_TAB_ICxx[iChannel]); MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); } @@ -2271,7 +2329,7 @@ __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI * @arg @ref LL_TIM_ACTIVEINPUT_TRC */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2322,7 +2380,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_ICPSC_DIV4 * @arg @ref LL_TIM_ICPSC_DIV8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2397,7 +2455,7 @@ __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, ui * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2454,7 +2512,7 @@ __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_IC_POLARITY_FALLING * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> @@ -2511,7 +2569,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR1)); } @@ -2527,7 +2585,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR2)); } @@ -2543,7 +2601,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR3)); } @@ -2559,7 +2617,7 @@ __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) { return (uint32_t)(READ_REG(TIMx->CCR4)); } @@ -2606,7 +2664,7 @@ __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); } @@ -2755,7 +2813,7 @@ __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); } @@ -2916,7 +2974,7 @@ __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); } @@ -2959,7 +3017,7 @@ __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); } @@ -3132,7 +3190,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); } @@ -3154,7 +3212,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); } @@ -3176,7 +3234,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); } @@ -3198,7 +3256,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); } @@ -3220,7 +3278,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); } @@ -3242,7 +3300,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); } @@ -3264,7 +3322,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); } @@ -3286,7 +3344,7 @@ __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); } @@ -3303,12 +3361,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set + * (Capture/Compare 1 interrupt is pending). * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); } @@ -3325,12 +3384,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set + * (Capture/Compare 2 over-capture interrupt is pending). * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); } @@ -3347,12 +3407,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set + * (Capture/Compare 3 over-capture interrupt is pending). * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); } @@ -3369,12 +3430,13 @@ __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) } /** - * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set + * (Capture/Compare 4 over-capture interrupt is pending). * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); } @@ -3414,7 +3476,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); } @@ -3447,7 +3509,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); } @@ -3480,7 +3542,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); } @@ -3513,7 +3575,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); } @@ -3546,7 +3608,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); } @@ -3579,7 +3641,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); } @@ -3612,7 +3674,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); } @@ -3645,7 +3707,7 @@ __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); } @@ -3654,7 +3716,7 @@ __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) * @} */ -/** @defgroup TIM_LL_EF_DMA_Management DMA-Management +/** @defgroup TIM_LL_EF_DMA_Management DMA Management * @{ */ /** @@ -3685,7 +3747,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); } @@ -3718,7 +3780,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); } @@ -3751,7 +3813,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); } @@ -3784,7 +3846,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); } @@ -3817,7 +3879,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); } @@ -3850,7 +3912,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); } @@ -3883,7 +3945,7 @@ __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); } @@ -3994,17 +4056,17 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); /** * @} */ @@ -4029,4 +4091,3 @@ ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDT #endif #endif /* __STM32F4xx_LL_TIM_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.c index d47e99cf859..5b1ffa838e3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -64,41 +63,41 @@ #define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) #define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_USART_DIRECTION_RX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) #define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ - || ((__VALUE__) == LL_USART_PARITY_EVEN) \ - || ((__VALUE__) == LL_USART_PARITY_ODD)) + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) #define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) #define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ - || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) #define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ - || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) #define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ - || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) #define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ - || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) #define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ - || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) #define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_0_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) + || ((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_1_5) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) #define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) /** * @} @@ -122,7 +121,7 @@ * - SUCCESS: USART registers are de-initialized * - ERROR: USART registers are not de-initialized */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx) { ErrorStatus status = SUCCESS; @@ -246,7 +245,7 @@ ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) * - SUCCESS: USART registers are initialized according to USART_InitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct) { ErrorStatus status = ERROR; uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; @@ -410,7 +409,7 @@ void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content * - ERROR: Problem occurred during USART Registers initialization */ -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct) { ErrorStatus status = SUCCESS; @@ -498,5 +497,4 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) #endif /* USE_FULL_LL_DRIVER */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.h index 1ddddb48ddf..14b9cb64d95 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usart.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -359,11 +358,12 @@ typedef struct */ #define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__))))) #define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100) -#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8) + 50) / 100) +#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8)\ + + 50) / 100) /* UART BRR = mantissa + overflow + fraction = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ #define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ - ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ + ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07)) /** @@ -375,11 +375,12 @@ typedef struct */ #define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__))))) #define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) -#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16) + 50) / 100) +#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16)\ + + 50) / 100) /* USART BRR = mantissa + overflow + fraction = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ #define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ - (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F)) /** @@ -431,7 +432,7 @@ __STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); } @@ -444,7 +445,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); } /** @@ -455,7 +456,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); } /** @@ -466,7 +467,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); } /** @@ -477,7 +478,7 @@ __STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); } /** @@ -495,7 +496,7 @@ __STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) { - MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); } /** @@ -509,7 +510,7 @@ __STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32 * @arg @ref LL_USART_DIRECTION_TX * @arg @ref LL_USART_DIRECTION_TX_RX */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); } @@ -543,7 +544,7 @@ __STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) * @arg @ref LL_USART_PARITY_EVEN * @arg @ref LL_USART_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); } @@ -570,7 +571,7 @@ __STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Me * @arg @ref LL_USART_WAKEUP_IDLELINE * @arg @ref LL_USART_WAKEUP_ADDRESSMARK */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); } @@ -597,7 +598,7 @@ __STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataW * @arg @ref LL_USART_DATAWIDTH_8B * @arg @ref LL_USART_DATAWIDTH_9B */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); } @@ -624,7 +625,7 @@ __STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t Ov * @arg @ref LL_USART_OVERSAMPLING_16 * @arg @ref LL_USART_OVERSAMPLING_8 */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); } @@ -656,7 +657,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); } @@ -687,7 +688,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc * @arg @ref LL_USART_PHASE_1EDGE * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); } @@ -718,7 +719,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C * @arg @ref LL_USART_POLARITY_LOW * @arg @ref LL_USART_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); } @@ -785,7 +786,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); } @@ -816,7 +817,7 @@ __STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t * @arg @ref LL_USART_STOPBITS_1_5 * @arg @ref LL_USART_STOPBITS_2 */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); } @@ -874,7 +875,7 @@ __STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t Nod * @param USARTx USART Instance * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD)); } @@ -963,7 +964,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard * @arg @ref LL_USART_HWCONTROL_CTS * @arg @ref LL_USART_HWCONTROL_RTS_CTS */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); } @@ -996,7 +997,7 @@ __STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)); } @@ -1041,7 +1042,7 @@ __STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t Periph * @arg @ref LL_USART_OVERSAMPLING_8 * @retval Baud Rate */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) { uint32_t usartdiv = 0x0U; uint32_t brrresult = 0x0U; @@ -1108,7 +1109,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)); } @@ -1139,7 +1140,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P * @arg @ref LL_USART_IRDA_POWER_NORMAL * @arg @ref LL_USART_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); } @@ -1168,7 +1169,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P * @param USARTx USART Instance * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -1215,7 +1216,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)); } @@ -1254,7 +1255,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)); } @@ -1283,7 +1284,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 * @param USARTx USART Instance * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); } @@ -1312,7 +1313,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 * @param USARTx USART Instance * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT); } @@ -1359,7 +1360,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); } @@ -1398,7 +1399,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 * @arg @ref LL_USART_LINBREAK_DETECT_10B * @arg @ref LL_USART_LINBREAK_DETECT_11B */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); } @@ -1437,7 +1438,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)); } @@ -1733,7 +1734,7 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE)); } @@ -1744,7 +1745,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE)); } @@ -1755,7 +1756,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE)); } @@ -1766,7 +1767,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE)); } @@ -1777,7 +1778,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE)); } @@ -1788,7 +1789,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE)); } @@ -1799,7 +1800,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC)); } @@ -1810,7 +1811,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE)); } @@ -1823,7 +1824,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD)); } @@ -1836,7 +1837,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS)); } @@ -1847,7 +1848,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK)); } @@ -1858,7 +1859,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU)); } @@ -2022,7 +2023,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } /** @@ -2033,7 +2034,7 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); } /** @@ -2044,7 +2045,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TCIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } /** @@ -2055,7 +2056,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_TXEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE); } /** @@ -2066,7 +2067,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR1, USART_CR1_PEIE); + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); } /** @@ -2094,7 +2095,7 @@ __STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_EIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); } /** @@ -2107,7 +2108,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_CTSIE); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); } /** @@ -2118,7 +2119,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } /** @@ -2129,7 +2130,7 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); } /** @@ -2140,7 +2141,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } /** @@ -2151,7 +2152,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); } /** @@ -2162,7 +2163,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); } /** @@ -2190,7 +2191,7 @@ __STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); } /** @@ -2203,7 +2204,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); } /** @@ -2212,7 +2213,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); } @@ -2223,7 +2224,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); } @@ -2234,7 +2235,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); } @@ -2245,7 +2246,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); } @@ -2256,7 +2257,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); } @@ -2269,7 +2270,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)); } @@ -2280,7 +2281,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); } @@ -2293,7 +2294,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); } @@ -2314,7 +2315,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_DMAR); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); } /** @@ -2325,7 +2326,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); } /** @@ -2334,7 +2335,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); } @@ -2347,7 +2348,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) { - SET_BIT(USARTx->CR3, USART_CR3_DMAT); + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); } /** @@ -2358,7 +2359,7 @@ __STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) */ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) { - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); } /** @@ -2367,7 +2368,7 @@ __STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) { return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); } @@ -2379,10 +2380,10 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx) { /* return address of DR register */ - return ((uint32_t) & (USARTx->DR)); + return ((uint32_t) &(USARTx->DR)); } /** @@ -2399,7 +2400,7 @@ __STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) { return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR)); } @@ -2410,7 +2411,7 @@ __STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) * @param USARTx USART Instance * @retval Value between Min_Data=0x00 and Max_Data=0x1FF */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) { return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR)); } @@ -2488,10 +2489,10 @@ __STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx) /** @defgroup USART_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); /** * @} @@ -2518,4 +2519,3 @@ void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitS #endif /* __STM32F4xx_LL_USART_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.c index 78df37addf6..59c83e104a2 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.c @@ -11,6 +11,17 @@ * + Peripheral Control functions * + Peripheral State functions * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** @verbatim ============================================================================== ##### How to use this driver ##### @@ -23,17 +34,7 @@ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * + ****************************************************************************** */ @@ -82,7 +83,6 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { HAL_StatusTypeDef ret; - if (cfg.phy_itface == USB_OTG_ULPI_PHY) { USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); @@ -96,7 +96,8 @@ HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c { USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; } - /* Reset after a PHY select */ + + /* Reset after a PHY select */ ret = USB_CoreReset(USBx); } else /* FS interface (embedded Phy) */ @@ -247,21 +248,39 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) { + uint32_t ms = 0U; + USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); if (mode == USB_HOST_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + + do + { + HAL_Delay(1U); + ms++; + } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < 50U)); } else if (mode == USB_DEVICE_MODE) { USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + + do + { + HAL_Delay(1U); + ms++; + } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < 50U)); } else { return HAL_ERROR; } - HAL_Delay(50U); + + if (ms == 50U) + { + return HAL_ERROR; + } return HAL_OK; } @@ -327,9 +346,6 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf /* Restart the Phy Clock */ USBx_PCGCCTL = 0U; - /* Device mode configuration */ - USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; - if (cfg.phy_itface == USB_OTG_ULPI_PHY) { if (cfg.speed == USBD_HS_SPEED) @@ -443,7 +459,7 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf } /** - * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO + * @brief USB_FlushTxFifo Flush a Tx FIFO * @param USBx Selected device * @param num FIFO number * This parameter can be a value from 1 to 15 @@ -452,13 +468,28 @@ HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cf */ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) { - uint32_t count = 0U; + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + /* Flush TX Fifo */ + count = 0U; USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -468,19 +499,34 @@ HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) } /** - * @brief USB_FlushRxFifo : Flush Rx FIFO + * @brief USB_FlushRxFifo Flush Rx FIFO * @param USBx Selected device * @retval HAL status */ HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0; + __IO uint32_t count = 0U; + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > 200000U) + { + return HAL_TIMEOUT; + } + } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Flush RX Fifo */ + count = 0U; USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -736,7 +782,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef */ USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & + (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); if (ep->type == EP_TYPE_ISOC) @@ -813,8 +861,10 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef else { pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt); + USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; } if (dma == 1U) @@ -922,8 +972,11 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe ep->xfer_len = ep->maxpacket; } + /* Store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket)); + USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); if (dma == 1U) { @@ -940,6 +993,64 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDe return HAL_OK; } + +/** + * @brief USB_EPStoptXfer Stop transfer on an EP + * @param USBx usb device instance + * @param ep pointer to endpoint structure + * @retval HAL status + */ +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) +{ + __IO uint32_t count = 0U; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t USBx_BASE = (uint32_t)USBx; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* EP enable, IN data in FIFO */ + if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) + { + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); + USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); + } + } + else /* OUT endpoint */ + { + if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) + { + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); + USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); + + do + { + count++; + + if (count > 10000U) + { + ret = HAL_ERROR; + break; + } + } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); + } + } + + return ret; +} + + /** * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated * with the EP/channel @@ -957,8 +1068,9 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t *pSrc = (uint32_t *)src; - uint32_t count32b, i; + uint8_t *pSrc = src; + uint32_t count32b; + uint32_t i; if (dma == 0U) { @@ -967,6 +1079,9 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, { USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); pSrc++; + pSrc++; + pSrc++; + pSrc++; } } @@ -983,14 +1098,34 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t *pDest = (uint32_t *)dest; + uint8_t *pDest = dest; + uint32_t pData; uint32_t i; - uint32_t count32b = ((uint32_t)len + 3U) / 4U; + uint32_t count32b = (uint32_t)len >> 2U; + uint16_t remaining_bytes = len % 4U; for (i = 0U; i < count32b; i++) { __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); pDest++; + pDest++; + pDest++; + pDest++; + } + + /* When Number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + i = 0U; + __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); + + do + { + *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); + i++; + pDest++; + remaining_bytes--; + } while (remaining_bytes != 0U); } return ((void *)pDest); @@ -1222,7 +1357,9 @@ uint32_t USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) { uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg, msk, emp; + uint32_t tmpreg; + uint32_t msk; + uint32_t emp; msk = USBx_DEVICE->DIEPMSK; emp = USBx_DEVICE->DIEPEMPMSK; @@ -1240,7 +1377,7 @@ uint32_t USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) */ void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) { - USBx->GINTSTS |= interrupt; + USBx->GINTSTS &= interrupt; } /** @@ -1318,12 +1455,14 @@ HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uin */ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) { - uint32_t count = 0U; + __IO uint32_t count = 0U; /* Wait for AHB master IDLE state. */ do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -1335,7 +1474,9 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) do { - if (++count > 200000U) + count++; + + if (count > 200000U) { return HAL_TIMEOUT; } @@ -1354,6 +1495,7 @@ static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) */ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) { + HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; uint32_t i; @@ -1397,8 +1539,15 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c } /* Make sure the FIFOs are flushed. */ - (void)USB_FlushTxFifo(USBx, 0x10U); /* all Tx FIFOs */ - (void)USB_FlushRxFifo(USBx); + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } /* Clear all pending HC Interrupts */ for (i = 0U; i < cfg.Host_channels; i++) @@ -1407,11 +1556,6 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USBx_HC(i)->HCINTMSK = 0U; } - /* Enable VBUS driving */ - (void)USB_DriveVbus(USBx, 1U); - - HAL_Delay(200U); - /* Disable all interrupts. */ USBx->GINTMSK = 0U; @@ -1444,7 +1588,7 @@ HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef c USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - return HAL_OK; + return ret; } /** @@ -1595,7 +1739,8 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, { HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t HCcharEpDir, HCcharLowSpeed; + uint32_t HCcharEpDir; + uint32_t HCcharLowSpeed; uint32_t HostCoreSpeed; /* Clear old interrupt conditions for this host channel. */ @@ -1660,6 +1805,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, break; } + /* Enable host channel Halt interrupt */ + USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; + /* Enable the top level host channel interrupt. */ USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); @@ -1693,9 +1841,9 @@ HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | HCcharEpDir | HCcharLowSpeed; - if (ep_type == EP_TYPE_INTR) + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) { - USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ; + USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; } return ret; @@ -1868,7 +2016,7 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { uint32_t USBx_BASE = (uint32_t)USBx; uint32_t hcnum = (uint32_t)hc_num; - uint32_t count = 0U; + __IO uint32_t count = 0U; uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; @@ -1889,10 +2037,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -1912,10 +2061,11 @@ HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) { USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR; do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -1963,16 +2113,24 @@ HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) */ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) { + HAL_StatusTypeDef ret = HAL_OK; uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t count = 0U; + __IO uint32_t count = 0U; uint32_t value; uint32_t i; (void)USB_DisableGlobalInt(USBx); - /* Flush FIFO */ - (void)USB_FlushTxFifo(USBx, 0x10U); - (void)USB_FlushRxFifo(USBx); + /* Flush USB FIFO */ + if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ + { + ret = HAL_ERROR; + } + + if (USB_FlushRxFifo(USBx) != HAL_OK) + { + ret = HAL_ERROR; + } /* Flush out any leftover queued requests. */ for (i = 0U; i <= 15U; i++) @@ -1995,7 +2153,9 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) do { - if (++count > 1000U) + count++; + + if (count > 1000U) { break; } @@ -2008,7 +2168,7 @@ HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) (void)USB_EnableGlobalInt(USBx); - return HAL_OK; + return ret; } /** @@ -2059,5 +2219,3 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx) /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.h index 28be5186563..a7114cd02a3 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_usb.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -23,7 +22,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /* __cplusplus */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_hal_def.h" @@ -80,6 +79,7 @@ typedef enum HC_DATATGLERR } USB_OTG_HCStateTypeDef; + /** * @brief USB Instance Initialization Structure definition */ @@ -94,14 +94,15 @@ typedef struct This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ uint32_t speed; /*!< USB Core speed. - This parameter can be any value of @ref USB_Core_Speed */ + This parameter can be any value of @ref PCD_Speed/HCD_Speed + (HCD_SPEED_xxx, HCD_SPEED_xxx) */ uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ uint32_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref USB_Core_PHY */ + This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ uint32_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ @@ -130,8 +131,11 @@ typedef struct uint8_t is_stall; /*!< Endpoint stall condition This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_EP_Type_ */ + This parameter can be any value of @ref USB_LL_EP_Type */ uint8_t data_pid_start; /*!< Initial data PID This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ @@ -151,6 +155,8 @@ typedef struct uint32_t xfer_len; /*!< Current transfer length */ + uint32_t xfer_size; /*!< requested transfer size */ + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ } USB_OTG_EPTypeDef; @@ -168,15 +174,16 @@ typedef struct uint8_t ep_is_in; /*!< Endpoint direction This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - uint8_t speed; /*!< USB Host speed. - This parameter can be any value of @ref USB_Core_Speed_ */ + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref HCD_Device_Speed: + (HCD_DEVICE_SPEED_xxx) */ uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ uint8_t process_ping; /*!< Execute the PING protocol for HS mode. */ uint8_t ep_type; /*!< Endpoint Type. - This parameter can be any value of @ref USB_EP_Type_ */ + This parameter can be any value of @ref USB_LL_EP_Type */ uint16_t max_packet; /*!< Endpoint Max packet size. This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ @@ -186,7 +193,7 @@ typedef struct uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - uint32_t XferSize; /*!< OTG Channel transfer size. */ + uint32_t XferSize; /*!< OTG Channel transfer size. */ uint32_t xfer_len; /*!< Current transfer length. */ @@ -316,10 +323,10 @@ typedef struct /** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS * @{ */ -#define EP_MPS_64 0U -#define EP_MPS_32 1U -#define EP_MPS_16 2U -#define EP_MPS_8 3U +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U /** * @} */ @@ -393,19 +400,36 @@ typedef struct #define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U #define GRXSTS_PKTSTS_CH_HALTED 7U +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + #define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) #define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) #define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) +#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + +#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ + + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) + #define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) #define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) +#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ + + USB_OTG_HOST_CHANNEL_BASE\ + + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) + #endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ #define EP_ADDR_MSK 0xFU + +#ifndef USE_USB_DOUBLE_BUFFER +#define USE_USB_DOUBLE_BUFFER 1U +#endif /* USE_USB_DOUBLE_BUFFER */ /** * @} */ @@ -451,6 +475,7 @@ HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); +HAL_StatusTypeDef USB_EPStopXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address); HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx); HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx); @@ -505,9 +530,7 @@ HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx); #ifdef __cplusplus } -#endif +#endif /* __cplusplus */ #endif /* STM32F4xx_LL_USB_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.c index 96f65272be1..34df6eaec31 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.c @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -748,5 +747,3 @@ static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_ /** * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.h index 3bac30cf08d..2b254a17282 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_utils.h @@ -18,13 +18,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -306,5 +305,3 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa #endif #endif /* __STM32F4xx_LL_UTILS_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_wwdg.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_wwdg.h index f20b82dd805..5cbca0d8ffe 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_wwdg.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/STM32F4xx_HAL_Driver/stm32f4xx_ll_wwdg.h @@ -6,13 +6,12 @@ ****************************************************************************** * @attention * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -315,5 +314,3 @@ __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) #endif #endif /* STM32F4xx_LL_WWDG_H */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/stm32f4xx_hal_conf.h b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/stm32f4xx_hal_conf.h index af2a9cc2e83..023678e3802 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/stm32f4xx_hal_conf.h +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/stm32f4xx_hal_conf.h @@ -1,18 +1,19 @@ /** ****************************************************************************** - * @file stm32f4xx_hal_conf.h + * @file stm32f4xx_hal_conf_template.h * @author MCD Application Team - * @brief HAL configuration file. + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32f4xx_hal_conf.h. ****************************************************************************** * @attention * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

+ * Copyright (c) 2017 STMicroelectronics. + * All rights reserved. * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. * ****************************************************************************** */ @@ -34,7 +35,7 @@ */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -/* #define HAL_CAN_MODULE_ENABLED */ +// #define HAL_CAN_MODULE_ENABLED #define HAL_CAN_LEGACY_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED #define HAL_CEC_MODULE_ENABLED @@ -43,7 +44,8 @@ #define HAL_DCMI_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED #define HAL_DMA2D_MODULE_ENABLED -#define HAL_ETH_MODULE_ENABLED +// #define HAL_ETH_MODULE_ENABLED +#define HAL_ETH_LEGACY_MODULE_ENABLED #define HAL_FLASH_MODULE_ENABLED #define HAL_NAND_MODULE_ENABLED #define HAL_NOR_MODULE_ENABLED @@ -313,10 +315,17 @@ /* ################## Ethernet peripheral configuration ##################### */ -/* Definition of the Ethernet driver buffers size and count */ -#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ -#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +/* Section 1 : Ethernet peripheral configuration */ +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ #ifdef MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* default value in connectivity/drivers/emac/TARGET_STM/mbed_lib.json */ #define ETH_RXBUFNB MBED_CONF_STM32_EMAC_ETH_RXBUFNB /* Rx buffers of size ETH_RX_BUF_SIZE */ @@ -329,25 +338,39 @@ /* Section 2: PHY configuration section */ -/* PHY delay */ +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #ifdef MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY #define PHY_RESET_DELAY MBED_CONF_STM32_EMAC_ETH_PHY_RESET_DELAY #else #define PHY_RESET_DELAY 0 #endif +/* PHY Configuration delay */ #define PHY_CONFIG_DELAY 0x00000FFFU + #define PHY_READ_TO 0x0000FFFFU #define PHY_WRITE_TO 0x0000FFFFU /* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ +#define PHY_BCR ((uint16_t)0x0000) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x0001) /*!< Transceiver Basic Status Register */ -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_RESET ((uint16_t)0x8000) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< Jabber condition detected */ /* Section 4: Extended PHY Registers */ #ifdef MBED_CONF_STM32_EMAC_ETH_PHY_STATUS_REGISTER @@ -355,10 +378,20 @@ #define PHY_SPEED_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_SPEED_STATUS /*!< PHY Speed mask */ #define PHY_DUPLEX_STATUS MBED_CONF_STM32_EMAC_ETH_PHY_DUPLEX_STATUS /*!< PHY Duplex mask */ #else -#define PHY_SR 0 -#define PHY_SPEED_STATUS 0 -#define PHY_DUPLEX_STATUS 0 +#define PHY_SR ((uint16_t)0x0010) /*!< PHY status register Offset */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< PHY Duplex mask */ #endif + +#define PHY_MICR ((uint16_t)0x0011) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x0012) /*!< MII Interrupt Status and Misc. Control Register */ +#define PHY_LINK_STATUS ((uint16_t)0x0001) /*!< PHY Link mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000) /*!< PHY link status interrupt mask */ /* ################## SPI peripheral configuration ########################## */ @@ -430,6 +463,10 @@ #include "stm32f4xx_hal_eth.h" #endif /* HAL_ETH_MODULE_ENABLED */ +#ifdef HAL_ETH_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_eth_legacy.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32f4xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ @@ -577,7 +614,6 @@ #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ - #ifdef __cplusplus } #endif @@ -585,4 +621,4 @@ #endif /* __STM32F4xx_HAL_CONF_H */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/system_stm32f4xx.c b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/system_stm32f4xx.c index 2e257035168..4a19d323fdf 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/system_stm32f4xx.c +++ b/targets/TARGET_STM/TARGET_STM32F4/STM32Cube_FW/system_stm32f4xx.c @@ -47,6 +47,7 @@ #include "stm32f4xx.h" +#include "nvic_addr.h" #if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ @@ -92,7 +93,8 @@ /*!< Uncomment the following line if you need to relocate the vector table anywhere in Flash or Sram, else the vector table is kept at the automatic remap of boot address selected */ -/* #define USER_VECT_TAB_ADDRESS */ +#define USER_VECT_TAB_ADDRESS +#define FLASH_BASE NVIC_FLASH_VECTOR_ADDRESS #if defined(USER_VECT_TAB_ADDRESS) /*!< Uncomment the following line if you need to relocate your vector Table @@ -104,7 +106,8 @@ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ #else - +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ @@ -164,11 +167,8 @@ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; * @param None * @retval None */ -__weak void SystemInit(void) +void SystemInit(void) { -#include "nvic_addr.h" // MBED - SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; // MBED - /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */