diff --git a/1. Verilog Language/2. Vectors/08_ReplicationOperator.v b/1. Verilog Language/2. Vectors/08_ReplicationOperator.v
index c146a1f..b6ee379 100644
--- a/1. Verilog Language/2. Vectors/08_ReplicationOperator.v	
+++ b/1. Verilog Language/2. Vectors/08_ReplicationOperator.v	
@@ -3,6 +3,6 @@ module top_module (
     output [31:0] out 
     );
   
-  assign out = { { 24{in[7] } } , in[7:0] };
+    assign out = { { { 24{in[7] } } , in};
 
 endmodule