Merge branch 'isa_fix_jenkins_ver' into 'devel'

fix verification PTC, NETWORK MOD, PCIE MOD

See merge request ndk/ndk-fpga!292

Author: jakubcabal

comp/pcie/ptc/uvm/tbench/tests/sequence.sv

@@ -25,13 +25,13 @@ class virt_seq #(MRRS, MIN_READ_REQ_SIZE, MPS, MIN_WRITE_REQ_SIZE) extends uvm_s
         m_packet.init_sequence();
         m_packet.cfg = new();
         m_packet.cfg.array_size_set(MIN_WRITE_REQ_SIZE, MPS);
-        m_packet.min_random_count = 60;
-        m_packet.max_random_count = 80;
+        m_packet.min_random_count = 40;
+        m_packet.max_random_count = 60;
 
         m_info_lib   = uvm_ptc_info::sequence_lib_info #(MRRS, MIN_READ_REQ_SIZE)::type_id::create("m_info_lib");
         m_info_lib.init_sequence();
-        m_info_lib.min_random_count = 60;
-        m_info_lib.max_random_count = 80;
+        m_info_lib.min_random_count = 40;
+        m_info_lib.max_random_count = 60;
         m_info = m_info_lib;
     endfunction
 

core/comp/eth/network_mod/uvm/tbench/cmac/env/sequence.sv

@@ -437,7 +437,7 @@ class virt_sequence_simple #(
         end
 
         // Stop the sequences
-        wait (transactions >= ETH_PORTS*30_000);
+        wait (transactions >= ETH_PORTS*20_000);
         seq_sync_port_end.send_stop();
         for (int unsigned it = 0; it < ETH_PORTS; it++) begin
             wait(port_end[it] == 1);

core/comp/eth/network_mod/uvm/tbench/e-tile/env/sequence.sv

@@ -393,7 +393,7 @@ class virt_sequence_simple #(ETH_PORTS, ETH_TX_HDR_WIDTH, ETH_RX_HDR_WIDTH, ITEM
         end
 
         //SEND STOP
-        wait (transactions >= ETH_PORTS*30_000);
+        wait (transactions >= ETH_PORTS*20_000);
         seq_sync_port_end.send_stop();
         for (int unsigned it = 0; it < ETH_PORTS; it++) begin
             wait(port_end[it] == 1);

core/comp/eth/network_mod/uvm/tbench/f-tile/env/sequence.sv

@@ -428,7 +428,7 @@ class virt_sequence_simple #(
         end
 
         //SEND STOP
-        wait (transactions >= ETH_PORTS*30_000);
+        wait (transactions >= ETH_PORTS*20_000);
         seq_sync_port_end.send_stop();
         for (int unsigned it = 0; it < ETH_PORTS; it++) begin
             wait(port_end[it] == 1);

core/comp/pcie/pcie_mod/uvm/tbench/env/model_ptc.sv

@@ -254,6 +254,9 @@ class model_ptc#(RQ_REGIONS, DMA_PORTS, ITEM_WIDTH) extends uvm_component;
             dma_tr.completed = completed;
             dma_tr.tag       = dma_info.tag;
             dma_tr.unit_id   = dma_info.unit_id;
+            if (DMA_PORTS > 1) begin
+                dma_tr.unit_id[$clog2(DMA_PORTS)-1:0] = 0;
+            end
             dma_tr.data      = pcie_tr.data;
             `uvm_info(this.get_full_name(), $sformatf("\nDMA RC PORT %0d %s", dma_info.port, dma_tr.convert2string()), UVM_FULL);
 
@@ -268,6 +271,7 @@ class model_ptc#(RQ_REGIONS, DMA_PORTS, ITEM_WIDTH) extends uvm_component;
         int unsigned rq_tr_tmp;
 
         forever begin
+            logic [uvm_ptc_info::sequence_item::DMA_REQUEST_UNITID_W-1:0] unitid;
             dma_rq[dma].get(rq_tr);
 
             rsp_tr       = uvm_pcie::request_header::type_id::create("rsp_tr", this);
@@ -279,7 +283,6 @@ class model_ptc#(RQ_REGIONS, DMA_PORTS, ITEM_WIDTH) extends uvm_component;
             rsp_tr.fmt        = {1'b0, rq_tr.hdr.type_ide, rq_tr.hdr.global_id[64-1:0] != 32'b0 ? 1'b1 : 1'b0};
             rsp_tr.pcie_type  = 5'b0;
 
-            //rq_tr.hdr.unitid // NOT USED
 
             `uvm_info(this.get_full_name(), $sformatf("\nGET DMA RX [%0d] TRANSACTION %0d %s", dma, rq_tr_tmp, rq_tr.convert2string()), UVM_FULL);
 
@@ -294,7 +297,12 @@ class model_ptc#(RQ_REGIONS, DMA_PORTS, ITEM_WIDTH) extends uvm_component;
             rsp_tr.length            = rq_tr.hdr.length;
             rsp_tr.data              = rq_tr.hdr.type_ide == 1'b1 ? rq_tr.data : {};
             rsp_tr.requester_id      = {8'b0,  rq_tr.hdr.vfid};
-            tags.get_dma2pcie(rq_tr.hdr.type_ide, dma, rq_tr.hdr.tag, rq_tr.hdr.unitid, rsp_tr.tag);
+            unitid = rq_tr.hdr.unitid;
+            if (DMA_PORTS > 1) begin
+                 unitid[$clog2(DMA_PORTS)-1:0] = dma;
+            end
+
+            tags.get_dma2pcie(rq_tr.hdr.type_ide, dma, rq_tr.hdr.tag, unitid, rsp_tr.tag);
             case(rq_tr.hdr.lastib)
                 0 : rsp_tr.lbe = 4'b1111;
                 1 : rsp_tr.lbe = 4'b0111;

core/comp/pcie/pcie_mod/uvm/tbench/env/sequence.sv

@@ -124,10 +124,8 @@ class sequence_base #(
     endfunction
 
     virtual task run_rq(int unsigned pcie, int unsigned dma);
-        const int unsigned dma_unitid_const = (DMA_PORTS*pcie + dma);
-
         while (stop == 0) begin
-            assert (dma_rq[pcie][dma].randomize() with {dma_rq[pcie][dma].unit_id ==  dma_unitid_const;});
+            assert (dma_rq[pcie][dma].randomize());
             dma_rq[pcie][dma].start(p_sequencer.m_dma_rq[pcie][dma]);
         end
         rx_stop[pcie][dma] = 1;

core/comp/pcie/pcie_mod/uvm/tbench/env/sequence_dma_rq.sv

@@ -11,13 +11,16 @@ class sequence_dma_rq#(DMA_PORTS) extends uvm_sequence#(uvm_dma::sequence_item_r
     localparam MAX_REQUEST_SIZE = 128;
     localparam MAX_PAYLOAD_SIZE = 64;
 
-    rand int unsigned unit_id;
+    rand logic [uvm_ptc_info::sequence_item::DMA_REQUEST_UNITID_W-1:0] unit_id;
     rand int unsigned transactions;
     //protected logic [sv_dma_bus_pack::DMA_REQUEST_TAG_W-1:0] tags[logic [sv_dma_bus_pack::DMA_REQUEST_TAG_W-1:0]];
     uvm_dma::seq_info info;
 
     constraint trans_const {
         transactions inside {[20:60]};
+        if (DMA_PORTS > 1) {
+		unit_id[($clog2(DMA_PORTS) > 1 ? $clog2(DMA_PORTS) : 1) -1:0] == 0;
+	}
     };
 
     function new(string name = "mi_cc_sequence");
@@ -40,9 +43,6 @@ class sequence_dma_rq#(DMA_PORTS) extends uvm_sequence#(uvm_dma::sequence_item_r
 
             assert(req.randomize() with {
                 req.hdr.unitid == unit_id;
-                if (DMA_PORTS > 1) {
-                    req.hdr.tag[sv_dma_bus_pack::DMA_REQUEST_TAG_W-1 -: $clog2(DMA_PORTS) > 1 ? $clog2(DMA_PORTS) : 1] == unit_id[($clog2(DMA_PORTS) > 1 ? $clog2(DMA_PORTS) : 1) -1:0];
-                }
                 (req.hdr.type_ide == 0) -> !(req.hdr.tag inside {info.tags[unit_id]});
                 req.hdr.firstib inside {0};
                 req.hdr.lastib  inside {0};