style(uvm): satisfy linter

Author: radek-isa

comp/uvm/logic_vector_array_lbus/monitor.sv

@@ -41,7 +41,9 @@ class monitor_logic_vector_array extends uvm_logic_vector_array::monitor #(8);
     endfunction
 
     protected virtual function void send_packet();
-        uvm_logic_vector_array::sequence_item #(8) item = uvm_logic_vector_array::sequence_item #(8)::type_id::create("item");
+        uvm_logic_vector_array::sequence_item #(8) item;
+
+        item = uvm_logic_vector_array::sequence_item #(8)::type_id::create("item");
         item.data = bytes;
         bytes.delete();
         analysis_port.write(item);
@@ -82,7 +84,10 @@ class monitor_logic_vector_array extends uvm_logic_vector_array::monitor #(8);
                 else begin
                     assert(t.eop[i] !== 1'b1)
                     else begin
-                       `uvm_error(this.get_full_name(), "\n\tThe EOP was set before a new packet transfer started. A SOP wasn't set before this EOP")
+                        string msg;
+                        // verilog_lint: waive line-length
+                        msg = "\n\tThe EOP was set before a new packet transfer started. A SOP wasn't set before this EOP";
+                       `uvm_error(this.get_full_name(), msg);
                     end
                 end
             end
@@ -98,7 +103,10 @@ class monitor_logic_vector_array extends uvm_logic_vector_array::monitor #(8);
 
                 assert(t.sop[i] !== 1'b1)
                 else begin
-                    `uvm_error(this.get_full_name(), "\n\tThe SOP was before the last packet transfer correctly ended. A EOP wasn't set at the end of the packet transfer")
+                    string msg;
+                    // verilog_lint: waive line-length
+                    msg = "\n\tThe SOP was before the last packet transfer correctly ended. A EOP wasn't set at the end of the packet transfer";
+                    `uvm_error(this.get_full_name(), msg);
                 end
             end
         end
@@ -150,7 +158,9 @@ class monitor_logic_vector extends uvm_logic_vector::monitor #(1);
 
         for (int unsigned i = 0; i < 4; i++) begin
             if (t.ena[i] === 1'b1 && t.eop[i] === 1'b1) begin
-                uvm_logic_vector::sequence_item #(1) item = uvm_logic_vector::sequence_item #(1)::type_id::create("item");
+                uvm_logic_vector::sequence_item #(1) item;
+
+                item = uvm_logic_vector::sequence_item #(1)::type_id::create("item");
                 item.data = t.err[i];
                 analysis_port.write(item);
             end

core/comp/eth/network_mod/uvm/tbench/cmac/dut.sv

@@ -4,6 +4,7 @@
 
 // SPDX-License-Identifier: BSD-3-Clause
 
+// verilog_lint: waive module-filename
 module DUT #(
     string       ETH_CORE_ARCH,
     int unsigned ETH_PORTS,
@@ -124,21 +125,25 @@ module DUT #(
     );
 
     generate;
-        for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin
-            localparam int unsigned ETH_PORT_CHAN_LOCAL = ETH_PORT_CHAN[eth_it];
-            initial assert(ETH_PORT_CHAN_LOCAL == 1);
+        for (genvar eth_it = 0; eth_it < ETH_PORTS; eth_it++) begin : eth_inf
+            initial begin
+                assert(ETH_PORT_CHAN[eth_it] == 1);
+            end
 
             logic CLK_ETH_GEN = 1'b0;
 
+            // verilog_lint: waive explicit-begin
             always #(CLK_ETH_PERIOD[eth_it]/2) CLK_ETH_GEN = ~CLK_ETH_GEN;
 
             // ------- //
             // TX side //
             // ------- //
 
-            for (genvar slice = 0; slice < 4; slice++) begin
+            for (genvar slice = 0; slice < 4; slice++) begin : slice_tx
                 initial begin
+                    // verilog_lint: waive line-length
                     force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_data[slice] = eth_tx[eth_it].DATA[128*(slice+1)-1 -: 128]; // Byte reordering
+                    // verilog_lint: waive line-length
                     force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_rx_lbus_mty [slice] = eth_tx[eth_it].MTY[4*(slice+1)-1 -: 4];
                 end
             end
@@ -156,8 +161,10 @@ module DUT #(
             // RX side //
             // ------- //
 
-            for (genvar segment = 0; segment < 4; segment++) begin
+            for (genvar segment = 0; segment < 4; segment++) begin : slice_rx
+                // verilog_lint: waive line-length
                 assign eth_rx[eth_it].DATA[128*(segment+1)-1 -: 128] = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_data[segment]; // Byte reordering
+                // verilog_lint: waive line-length
                 assign eth_rx[eth_it].MTY[4*(segment+1)-1 -: 4]      = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_mty[segment];
             end
 
@@ -166,14 +173,20 @@ module DUT #(
             assign eth_rx[eth_it].EOP = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_eop;
             assign eth_rx[eth_it].ERR = DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_err;
 
-            initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_rdy = eth_rx[eth_it].RDY;
+            // verilog_lint: waive line-length
+            initial begin
+                force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_tx_lbus_rdy = eth_rx[eth_it].RDY;
+            end
 
             // ----- //
             // Other //
             // ----- //
 
             // CLK connection
-            initial force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_gt_tx_clk_322m = CLK_ETH_GEN;
+            // verilog_lint: waive line-length
+            initial begin
+                force DUT_BASE_U.VHDL_DUT_U.eth_core_g[eth_it].network_mod_core_i.cmac_gt_tx_clk_322m = CLK_ETH_GEN;
+            end
         end
     endgenerate