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jakubcabaljakubcabal
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Merge branch 'valek-opt-calypte_latency' into 'devel'
OPT: DMA Calypte throughput See merge request ndk/ndk-fpga!316
2 parents 8da728e + 2cb720b commit 2fbe077

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72 files changed

+5622
-1848
lines changed

‎comp/base/pkg/pcie_hdr_fields_pkg.vhd‎

Lines changed: 322 additions & 0 deletions
Large diffs are not rendered by default.

‎comp/dma/dma_calypte/DevTree.tcl‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@ proc dts_dma_calypte_ctrl {DTS dir id base pcie} {
88

99
dts_create_node dts "dma_ctrl_calypte_$dir$id" {
1010
dts_appendprop_comp_node dts $base 0x80 "cesnet,dma_ctrl_calypte_$dir"
11-
dts_appendprop_int dts "version" 0x10000
11+
dts_appendprop_int dts "version" 0x20000
1212
dts_appendprop_int dts "pcie" $pcie
1313
if { $dir == "tx" } {
1414
append dts "data_buff = <&dma_calypte_tx_data_buff$id\_pcie$pcie>;"

‎comp/dma/dma_calypte/Modules.tcl‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,15 +6,18 @@
66

77
lappend PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd"
88
lappend PACKAGEG "$OFM_PATH/comp/base/pkg/type_pack.vhd"
9+
lappend PACKAGEG "$OFM_PATH/comp/base/pkg/pcie_meta_pack.vhd"
910

1011
set RX_CALYPTE_BASE "$ENTITY_BASE/comp/rx"
1112
set TX_CALYPTE_BASE "$ENTITY_BASE/comp/tx"
12-
set MFB_FIFOX_BASE "$OFM_PATH/comp/mfb_tools/storage/fifox"
13+
set PTR_UPDATER_BASE "$ENTITY_BASE/comp/ptr_updater"
14+
set MFB_MERGER_BASE "$OFM_PATH/comp/mfb_tools/flow/merger_simple"
1315
set MI_SPLITTER_PLUS_GEN_BASE "$OFM_PATH/comp/mi_tools/splitter_plus_gen"
1416

1517
lappend COMPONENTS [ list "RX_DMA_CALYPTE" $RX_CALYPTE_BASE "FULL"]
1618
lappend COMPONENTS [ list "TX_DMA_CALYPTE" $TX_CALYPTE_BASE "FULL"]
17-
lappend COMPONENTS [ list "MFB_FIFOX" $MFB_FIFOX_BASE "FULL"]
19+
lappend COMPONENTS [ list "DMA_PTR_UPDATER" $PTR_UPDATER_BASE "FULL"]
20+
lappend COMPONENTS [ list "MFB_MERGER_SIMPLE" $MFB_MERGER_BASE "FULL"]
1821
lappend COMPONENTS [ list "MI_SPLITTER_PLUS_GEN" $MI_SPLITTER_PLUS_GEN_BASE "FULL"]
1922

2023
lappend MOD "$ENTITY_BASE/dma_calypte.vhd"

‎comp/dma/dma_calypte/comp/ptr_updater/Modules.tcl‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
# Modules.tcl: Components include script
2+
# Copyright (C) 2025 MAGMIO, a.s.
3+
# Author(s): Vladislav Valek <[email protected]>
4+
5+
lappend PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd"
6+
lappend PACKAGEG "$OFM_PATH/comp/base/pkg/type_pack.vhd"
7+
lappend PACKAGES "$OFM_PATH/comp/base/pkg/pcie_meta_pack.vhd"
8+
9+
set RQ_HDR_GEN_BASE "$OFM_PATH/comp/pcie/others/hdr_gen/rq_hdr_gen"
10+
set FIFOX_MULTI_BASE "$OFM_PATH/comp/base/fifo/fifox_multi"
11+
12+
lappend COMPONENTS [ list "PCIE_RQ_HDR_GEN" $RQ_HDR_GEN_BASE "FULL"]
13+
lappend COMPONENTS [ list "FIFOX_MULTI" $FIFOX_MULTI_BASE "FULL"]
14+
15+
lappend MOD "$ENTITY_BASE/dma_ptr_updater.vhd"

‎comp/dma/dma_calypte/comp/ptr_updater/dma_ptr_updater.vhd‎

Lines changed: 398 additions & 0 deletions
Large diffs are not rendered by default.

‎comp/dma/dma_calypte/comp/rx/comp/hdr_insertor/Modules.tcl‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,3 +11,4 @@ lappend COMPONENTS [list "BARREL_SHIFTER_GEN" "$OFM_PATH/comp/base/logic/barrel_
1111

1212
lappend PACKAGES "$OFM_PATH/comp/base/pkg/math_pack.vhd"
1313
lappend PACKAGES "$OFM_PATH/comp/base/pkg/type_pack.vhd"
14+
lappend PACKAGES "$OFM_PATH/comp/base/pkg/pcie_hdr_fields_pkg.vhd"

‎comp/dma/dma_calypte/comp/rx/comp/hdr_insertor/rx_dma_calypte_hdr_insertor.vhd‎

Lines changed: 941 additions & 307 deletions
Large diffs are not rendered by default.

‎comp/dma/dma_calypte/comp/rx/comp/hdr_manager/addr_manager/rx_dma_calypte_addr_manager.vhd‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,8 @@ entity RX_DMA_CALYPTE_ADDR_MANAGER is
5656
ADDR_MASK : in std_logic_vector(POINTER_WIDTH-1 downto 0);
5757
-- SW pointer to ring buffer
5858
ADDR_SW_POINTER : in std_logic_vector(POINTER_WIDTH-1 downto 0);
59-
59+
-- Assert if Peer-to-peer transfer is enabled on the channel
60+
ADDR_P2P_EN : in std_logic;
6061

6162
-- =====================================================================
6263
-- HW UPDATE ADDRESS INTERFACE (To SW manager)
@@ -85,6 +86,7 @@ entity RX_DMA_CALYPTE_ADDR_MANAGER is
8586
-- Address to RAM
8687
ADDR : out std_logic_vector(ADDR_WIDTH-1 downto 0);
8788
OFFSET : out std_logic_vector(POINTER_WIDTH-1 downto 0);
89+
P2P_EN : out std_logic;
8890
ADDR_VLD : out std_logic
8991
);
9092

@@ -215,6 +217,7 @@ begin
215217
if (rising_edge(CLK)) then
216218
ADDR <= std_logic_vector(unsigned(ADDR_BASE) + hw_offset);
217219
OFFSET <= hw_pointer_rd_data;
220+
P2P_EN <= ADDR_P2P_EN;
218221
ADDR_VLD <= packet_vld;
219222
if (RESET = '1') then
220223
ADDR_VLD <= '0';
@@ -224,6 +227,7 @@ begin
224227
else generate
225228
ADDR <= std_logic_vector(unsigned(ADDR_BASE) + hw_offset);
226229
OFFSET <= hw_pointer_rd_data;
230+
P2P_EN <= ADDR_P2P_EN;
227231
ADDR_VLD <= packet_vld;
228232
end generate;
229233

‎comp/dma/dma_calypte/comp/rx/comp/hdr_manager/pkg/dma_hdr_pkg.vhd‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,8 @@ package dma_hdr_pkg is
1616
constant DMA_FRAME_LENGTH_W : natural := 16;
1717
constant DMA_FRAME_PTR_W : natural := 16;
1818
constant DMA_VLD_BIT_W : natural := 1;
19-
constant DMA_RSVD_BITS_W : natural := 7;
19+
constant DMA_P2P_EN_W : natural := 1;
20+
constant DMA_RSVD_BITS_W : natural := 6;
2021
constant DMA_USR_METADATA_W : natural := 24;
2122
--=============================================================================================================
2223

@@ -47,7 +48,8 @@ package dma_hdr_pkg is
4748
constant DMA_FRAME_LENGTH_O : natural := 0;
4849
constant DMA_FRAME_PTR_O : natural := DMA_FRAME_LENGTH_O + DMA_FRAME_LENGTH_W;
4950
constant DMA_VLD_BIT_O : natural := DMA_FRAME_PTR_O + DMA_FRAME_PTR_W;
50-
constant DMA_RSVD_BITS_O : natural := DMA_VLD_BIT_O + DMA_VLD_BIT_W;
51+
constant DMA_P2P_EN_O : natural := DMA_VLD_BIT_O + DMA_VLD_BIT_W;
52+
constant DMA_RSVD_BITS_O : natural := DMA_P2P_EN_O + DMA_P2P_EN_W;
5153
constant DMA_USR_METADATA_O : natural := DMA_RSVD_BITS_O + DMA_RSVD_BITS_W;
5254
--=============================================================================================================
5355

@@ -78,6 +80,7 @@ package dma_hdr_pkg is
7880
subtype DMA_FRAME_LENGTH is natural range DMA_FRAME_LENGTH_O + DMA_FRAME_LENGTH_W - 1 downto DMA_FRAME_LENGTH_O;
7981
subtype DMA_FRAME_PTR is natural range DMA_FRAME_PTR_O + DMA_FRAME_PTR_W - 1 downto DMA_FRAME_PTR_O;
8082
subtype DMA_VLD_BIT is natural range DMA_VLD_BIT_O + DMA_VLD_BIT_W - 1 downto DMA_VLD_BIT_O;
83+
subtype DMA_P2P_EN is natural range DMA_P2P_EN_O + DMA_P2P_EN_W - 1 downto DMA_P2P_EN_O;
8184
subtype DMA_RSVD_BITS is natural range DMA_RSVD_BITS_O + DMA_RSVD_BITS_W - 1 downto DMA_RSVD_BITS_O;
8285
subtype DMA_USR_METADATA is natural range DMA_USR_METADATA_O + DMA_USR_METADATA_W - 1 downto DMA_USR_METADATA_O;
8386
--=============================================================================================================

‎comp/dma/dma_calypte/comp/rx/comp/hdr_manager/rx_dma_calypte_hdr_manager.vhd‎

Lines changed: 40 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,7 @@ entity RX_DMA_CALYPTE_HDR_MANAGER is
7171
ADDR_HEADER_BASE : in std_logic_vector(ADDR_WIDTH-1 downto 0);
7272
ADDR_HEADER_MASK : in std_logic_vector(POINTER_WIDTH-1 downto 0);
7373
ADDR_HEADER_SW_POINTER : in std_logic_vector(POINTER_WIDTH-1 downto 0);
74+
ADDR_HEADER_P2P_EN : in std_logic;
7475

7576
-- =====================================================================
7677
-- HW POINTER UPDATE INTERFACE
@@ -195,7 +196,7 @@ architecture FULL of RX_DMA_CALYPTE_HDR_MANAGER is
195196
-- PCIe header FIFOs
196197
-- =============================================================================================
197198
-- Width of data in the FIFO for PCIe headers of transactions carrying DMA header
198-
constant PCIE_HDR_DMA_TRAN_FIFO_W : natural := 128;
199+
constant PCIE_HDR_DMA_TRAN_FIFO_W : natural := 128 + 1 + 1;
199200
constant PCIE_HDR_DMA_TRAN_FIFO_SIZE : natural := 8;
200201
-- Width of data in the FIFO for PCIe headers of transactions carrying user data
201202
constant PCIE_HDR_DATA_TRAN_FIFO_W : natural := 128;
@@ -237,11 +238,14 @@ architecture FULL of RX_DMA_CALYPTE_HDR_MANAGER is
237238
-- Address for a DMA header PCIe transaction
238239
signal dma_hdr_pcie_addr : std_logic_vector(ADDR_WIDTH -1 downto 0);
239240
signal dma_hdr_pcie_addr_reg : std_logic_vector(ADDR_WIDTH -1 downto 0);
241+
signal dma_hdr_ptr : std_logic_vector(POINTER_WIDTH -1 downto 0);
240242
signal dma_hdr_pcie_addr_vld : std_logic;
241243
-- determines if the PCIe header is the size of 3 or 4 DWs
242244
signal pcie_addr_len_dma_hdr_tran : std_logic;
243245
-- Content of a PCIe header for a transaction with DMA header
244246
signal pcie_hdr_dma_hdr_tran : std_logic_vector(128-1 downto 0);
247+
signal dma_hdr_p2p_en : std_logic;
248+
signal dma_hdr_p2p_en_reg : std_logic;
245249

246250
-- =============================================================================================
247251
-- FSM that tracks the current state of the packet reception
@@ -266,6 +270,10 @@ architecture FULL of RX_DMA_CALYPTE_HDR_MANAGER is
266270
signal dma_hdr_addr_next : std_logic;
267271
signal dma_hdr_addr_next_n : std_logic;
268272
signal dma_hdr_addr_next_wr : std_logic;
273+
signal vld_bits_per_ch : std_logic_vector(CHANNELS -1 downto 0);
274+
signal vld_bit_sel : std_logic;
275+
signal vld_bit_out : std_logic;
276+
signal p2p_en_out : std_logic;
269277

270278
signal pkt_chan_reg : std_logic_vector(log2(CHANNELS) -1 downto 0);
271279
signal pkt_chan_new : std_logic_vector(log2(CHANNELS) -1 downto 0);
@@ -761,6 +769,7 @@ begin
761769
ADDR_BASE => ADDR_DATA_BASE,
762770
ADDR_MASK => ADDR_DATA_MASK,
763771
ADDR_SW_POINTER => ADDR_DATA_SW_POINTER,
772+
ADDR_P2P_EN => '0',
764773

765774
POINTER_UPDATE_CHAN => HDP_UPDATE_CHAN,
766775
POINTER_UPDATE_DATA => HDP_UPDATE_DATA,
@@ -774,6 +783,7 @@ begin
774783

775784
ADDR => data_pcie_addr,
776785
OFFSET => data_ptr,
786+
P2P_EN => open,
777787
ADDR_VLD => data_pcie_addr_vld
778788
);
779789

@@ -813,6 +823,7 @@ begin
813823
ADDR_BASE => ADDR_HEADER_BASE,
814824
ADDR_MASK => ADDR_HEADER_MASK,
815825
ADDR_SW_POINTER => ADDR_HEADER_SW_POINTER,
826+
ADDR_P2P_EN => ADDR_HEADER_P2P_EN,
816827

817828
POINTER_UPDATE_CHAN => HHP_UPDATE_CHAN,
818829
POINTER_UPDATE_DATA => HHP_UPDATE_DATA,
@@ -825,7 +836,8 @@ begin
825836
START_REQ_CHANNEL => START_REQ_CHANNEL,
826837

827838
ADDR => dma_hdr_pcie_addr,
828-
OFFSET => open,
839+
OFFSET => dma_hdr_ptr,
840+
P2P_EN => dma_hdr_p2p_en,
829841
ADDR_VLD => dma_hdr_pcie_addr_vld
830842
);
831843

@@ -856,10 +868,29 @@ begin
856868
dma_hdr_pcie_addr_reg <= dma_hdr_pcie_addr;
857869
pcie_hdr_dma_hdr_tran_fifo_wr <= dma_hdr_pcie_addr_vld;
858870
pcie_addr_len_dma_hdr_tran <= '1' when (DEVICE = "ULTRASCALE" or dma_hdr_pcie_addr(64-1 downto 32) /= (32-1 downto 0 => '0')) else '0';
871+
dma_hdr_p2p_en_reg <= dma_hdr_p2p_en;
872+
vld_bit_sel <= vld_bits_per_ch(to_integer(unsigned(dma_hdr_addr_chan)));
859873
end if;
860874
end process;
861875

862-
pcie_hdr_dma_hdr_tran_fifo_in <= pcie_hdr_dma_hdr_tran;
876+
vld_bit_flip_p : process (CLK) is
877+
begin
878+
if (rising_edge(CLK)) then
879+
if (RESET = '1') then
880+
vld_bits_per_ch <= (others => '1');
881+
else
882+
if (dma_hdr_pcie_addr_vld = '1' and dma_hdr_ptr = ADDR_HEADER_MASK) then
883+
vld_bits_per_ch(to_integer(unsigned(dma_hdr_addr_chan))) <= not vld_bits_per_ch(to_integer(unsigned(dma_hdr_addr_chan)));
884+
end if;
885+
886+
if (START_REQ_VLD = '1') then
887+
vld_bits_per_ch(to_integer(unsigned(START_REQ_CHANNEL))) <= '1';
888+
end if;
889+
end if;
890+
end if;
891+
end process;
892+
893+
pcie_hdr_dma_hdr_tran_fifo_in <= pcie_hdr_dma_hdr_tran & vld_bit_sel & dma_hdr_p2p_en_reg;
863894

864895
pcie_hdr_dma_hdr_tran_fifo_i : entity work.FIFOX
865896
generic map (
@@ -887,9 +918,9 @@ begin
887918
AEMPTY => open
888919
);
889920

890-
DMA_PCIE_HDR <= pcie_hdr_dma_hdr_tran_fifo_do;
891-
DMA_PCIE_HDR_SRC_RDY <= not pcie_hdr_dma_hdr_tran_fifo_empty;
892-
pcie_hdr_dma_hdr_tran_fifo_rd <= DMA_PCIE_HDR_DST_RDY;
921+
(DMA_PCIE_HDR, vld_bit_out, p2p_en_out) <= pcie_hdr_dma_hdr_tran_fifo_do;
922+
DMA_PCIE_HDR_SRC_RDY <= not pcie_hdr_dma_hdr_tran_fifo_empty;
923+
pcie_hdr_dma_hdr_tran_fifo_rd <= DMA_PCIE_HDR_DST_RDY;
893924

894925
pcie_hdr_data_tran_reg_p : process (CLK) is
895926
begin
@@ -1059,8 +1090,9 @@ begin
10591090
DMA_DISCARD <= discard_fifo_do(0);
10601091
DMA_HDR <= (24-1 downto METADATA_SIZE => '0')
10611092
& hdr_meta_fifo_do
1062-
& (7-1 downto 0 => '0')
1063-
& '1'
1093+
& (6-1 downto 0 => '0')
1094+
& p2p_en_out
1095+
& vld_bit_out
10641096
& std_logic_vector(resize(unsigned(ptr_fifo_do), 16))
10651097
& (16-1 downto log2(PKT_MTU+1) => '0')
10661098
& pkt_size_fifo_do;

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