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chore(build): update default AGILEX device in build system
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build/targets/comp_quartus.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ if {![info exists SYNTH_FLAGS(FPGA)]} {
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}
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set SYNTH_FLAGS(FPGA) [string map {
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"STRATIX10" "1SD280PT2F55E1VG"
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"AGILEX" "AGIB027R29A1E2VR0"
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"AGILEX" "AGIB023R18A1E1V"
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} $SYNTH_FLAGS(DEVICE)]
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}
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