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jakubcabaljakubcabal
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Merge branch 'cabal_ptc_quick' into 'devel'
A few improvements around PTC and timing See merge request ndk/ndk-fpga!328
2 parents 58c5f2e + 8858e23 commit 899dd36

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4 files changed

+60
-40
lines changed

4 files changed

+60
-40
lines changed

‎comp/base/misc/pipe/pipe_reg.vhd‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,10 @@ architecture BEHAVIORAL of PIPE_REG is
5252
signal reg1_we : std_logic;
5353
signal reg2_we : std_logic;
5454

55+
attribute maxfan : integer;
56+
attribute maxfan of reg1_we : signal is 128;
57+
attribute maxfan of reg2_we : signal is 128;
58+
5559
begin
5660

5761
fake_reg_true : if(FAKE_PIPE = true) generate

‎comp/pcie/ptc/Modules.tcl‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -17,6 +17,7 @@ lappend PACKAGES "$PKG_BASE/type_pack.vhd"
1717
lappend PACKAGES "$PKG_BASE/dma_bus_pack.vhd"
1818

1919
# list of sub-components
20+
lappend COMPONENTS [ list "ASYNC_RESET" "$OFM_PATH/comp/base/async/reset" "FULL" ]
2021
lappend COMPONENTS [ list "MVB_SFIFOX" "$MVB_TOOLS_BASE/storage/fifox" "FULL" ]
2122
lappend COMPONENTS [ list "MVB_ASFIFOX" "$MVB_TOOLS_BASE/storage/asfifox" "FULL" ]
2223
lappend COMPONENTS [ list "MVB_SHAKEDOWN" "$MVB_TOOLS_BASE/flow/shakedown" "FULL" ]

‎comp/pcie/ptc/comp/storage_fifo/ptc_storage_fifo.vhd‎

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,6 @@ architecture FULL of PTC_STORAGE_FIFO is
153153
signal mvb_fifo_rd : std_logic_vector(MVB_ITEMS-1 downto 0);
154154
signal mvb_fifo_empty : std_logic_vector(MVB_ITEMS-1 downto 0);
155155
signal safe_mvb_items_reg : unsigned(log2(MAIN_FIFO_ITEMS*MFB_REGIONS+1)-1 downto 0);
156-
signal mvb_items_vld_cnt : unsigned(log2(MVB_ITEMS+1)-1 downto 0);
157156

158157
-- Main MFB FIFO input
159158
signal main_mfb_fifo_in_data : std_logic_vector(MFB_REGIONS*MFB_REG_SIZE*MFB_BLOCK_SIZE*MFB_ITEM_WIDTH-1 downto 0);
@@ -334,9 +333,11 @@ begin
334333

335334
-- substract 1 for every MVB item read from main MVB FIFO
336335
decrement := (others => '0');
337-
if (TX_MVB_SRC_RDY = '1' and TX_MVB_DST_RDY = '1') then
338-
decrement := mvb_items_vld_cnt;
339-
end if;
336+
for i in 0 to MVB_ITEMS-1 loop
337+
if (TX_MVB_SRC_RDY = '1' and TX_MVB_DST_RDY = '1' and TX_MVB_VLD(i) = '1') then
338+
decrement := decrement+1;
339+
end if;
340+
end loop;
340341

341342
-- set new register value
342343
safe_mvb_items_reg <= safe_mvb_items_reg + resize(increment,safe_mvb_items_reg'length) - resize(decrement,safe_mvb_items_reg'length);
@@ -417,21 +418,16 @@ begin
417418

418419
-- safe MVB items checking
419420
safe_mvb_items_check_pr : process (safe_mvb_items_reg,TX_MVB_DST_RDY,mvb_fifo_empty)
420-
variable items : unsigned(log2(MVB_ITEMS+1)-1 downto 0);
421421
begin
422422
-- read from FIFO, send TX MVB, count number of sent items
423423
mvb_fifo_rd <= (others => '0');
424424
TX_MVB_VLD <= (others => '0');
425-
items := (others => '0');
426425
for i in 0 to MVB_ITEMS-1 loop
427426
if (i < safe_mvb_items_reg) then
428427
mvb_fifo_rd(i) <= TX_MVB_DST_RDY;
429428
TX_MVB_VLD (i) <= not mvb_fifo_empty(i);
430-
items := items+1;
431429
end if;
432430
end loop;
433-
434-
mvb_items_vld_cnt <= items;
435431
end process;
436432

437433
TX_MVB_SRC_RDY <= (or TX_MVB_VLD);

‎comp/pcie/ptc/ptc_full.vhd‎

Lines changed: 50 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -65,13 +65,16 @@ architecture FULL of PCIE_TRANSACTION_CTRL is
6565
-- Name(s) (4-letter IDs) of Streaming Debug Probes.
6666
-- DRQ0 = DMA RQ 0
6767
constant DBG_PROBE_STR : string := "PUMFPUMVPURQPDMFPDMVPDRC";
68+
constant RST_WIDTH : natural := 5;
6869

6970
---------------------------------------------------------------------------
7071

7172
---------------------------------------------------------------------------
7273
-- Signals
7374
---------------------------------------------------------------------------
7475

76+
signal rst_local : std_logic_vector(RST_WIDTH-1 downto 0);
77+
7578
-- UP MVB ASFIFO output / UP MVB Transformer input
7679
signal up_mvb_asfifo_out_data : slv_array_t(DMA_PORTS-1 downto 0)(DMA_MVB_UP_ITEMS*DMA_UPHDR_WIDTH-1 downto 0);
7780
signal up_mvb_asfifo_out_vld : slv_array_t(DMA_PORTS-1 downto 0)(DMA_MVB_UP_ITEMS -1 downto 0);
@@ -302,6 +305,22 @@ begin
302305
report "PCIE_TRANSACTION_CTRL: unsupported ENDPOINT_TYPE (Intel FPGA only)!"
303306
severity failure;
304307

308+
-- =========================================================================
309+
-- RESET DISTRIBUTION
310+
-- =========================================================================
311+
312+
rst_i : entity work.ASYNC_RESET
313+
generic map (
314+
TWO_REG => false,
315+
OUT_REG => true,
316+
REPLICAS => RST_WIDTH
317+
)
318+
port map (
319+
CLK => CLK,
320+
ASYNC_RST => RESET,
321+
OUT_RST => rst_local
322+
);
323+
305324
-- ========================================================================
306325
-- UPSTREAM
307326
-- ========================================================================
@@ -331,7 +350,7 @@ begin
331350
RX_DST_RDY => UP_MVB_DST_RDY(i),
332351

333352
TX_CLK => CLK,
334-
TX_RESET => RESET,
353+
TX_RESET => rst_local(0),
335354

336355
TX_DATA => up_mvb_asfifo_out_data(i),
337356
TX_VLD => up_mvb_asfifo_out_vld(i),
@@ -355,7 +374,7 @@ begin
355374
)
356375
port map (
357376
CLK => CLK,
358-
RESET => RESET,
377+
RESET => rst_local(0),
359378

360379
RX_DATA => up_mvb_asfifo_out_data(i),
361380
RX_VLD => up_mvb_asfifo_out_vld(i),
@@ -408,7 +427,7 @@ begin
408427
RX_DST_RDY => UP_MFB_DST_RDY(i),
409428

410429
TX_CLK => CLK,
411-
TX_RESET => RESET,
430+
TX_RESET => rst_local(1),
412431

413432
TX_DATA => up_mfb_asfifo_out_data(i),
414433
TX_SOF_POS => up_mfb_asfifo_out_sof_pos(i),
@@ -435,7 +454,7 @@ begin
435454
)
436455
port map (
437456
CLK => CLK,
438-
RESET => RESET,
457+
RESET => rst_local(1),
439458

440459
RX_DATA => up_mfb_asfifo_out_data(i),
441460
RX_SOP => up_mfb_asfifo_out_sof(i),
@@ -519,7 +538,7 @@ begin
519538
)
520539
port map (
521540
CLK => CLK,
522-
RESET => RESET,
541+
RESET => rst_local(1),
523542

524543
RX_MVB_DATA => up_mvb_trans_out_data_fix,
525544
RX_MVB_PAYLOAD => up_mvb_trans_out_payload,
@@ -562,7 +581,7 @@ begin
562581
)
563582
port map (
564583
CLK => CLK,
565-
RESET => RESET,
584+
RESET => rst_local(0),
566585

567586
RX_DATA => up_mvb_merge_out_data,
568587
RX_VLD => up_mvb_merge_out_vld,
@@ -592,7 +611,7 @@ begin
592611
)
593612
port map (
594613
CLK => CLK,
595-
RESET => RESET,
614+
RESET => rst_local(0),
596615

597616
DIN => up_mfb_merge_out_eof,
598617
DIN_MASK => (others => '1'),
@@ -611,7 +630,7 @@ begin
611630
s_codapa_inc_sync_reg <= (others => '0');
612631
end if;
613632

614-
if (RESET = '1') then
633+
if (rst_local(0) = '1') then
615634
s_codapa_inc_sync_reg <= (others => '0');
616635
end if;
617636
end if;
@@ -633,7 +652,7 @@ begin
633652
)
634653
port map (
635654
CLK => CLK,
636-
RESET => RESET,
655+
RESET => rst_local(0),
637656

638657
RX_MVB_DATA => up_mvb_mrgfi_out_data,
639658
RX_MVB_VLD => up_mvb_mrgfi_out_vld,
@@ -678,7 +697,7 @@ begin
678697
)
679698
port map (
680699
CLK => CLK,
681-
RESET => RESET,
700+
RESET => rst_local(0),
682701

683702
RX_MVB_DATA => up_mvb_dma2pcie_out_data,
684703
RX_MVB_BE => up_mvb_dma2pcie_out_be,
@@ -725,7 +744,7 @@ begin
725744
)
726745
port map (
727746
CLK => CLK,
728-
RESET => RESET,
747+
RESET => rst_local(1),
729748

730749
RX_MVB_DATA => up_mvb_c_checker_out_data,
731750
RX_MVB_BE => up_mvb_c_checker_out_be,
@@ -799,7 +818,7 @@ begin
799818
)
800819
port map (
801820
CLK => CLK,
802-
RESET => RESET,
821+
RESET => rst_local(2),
803822

804823
MVB_UP_HDR_IN => tagm_mvb_in,
805824
MVB_UP_HDR_IN_VLD => tagm_mvb_in_vld,
@@ -837,7 +856,7 @@ begin
837856
DEVICE => DEVICE
838857
) port map (
839858
WR_CLK => CLK,
840-
WR_RST => RESET,
859+
WR_RST => rst_local(2),
841860

842861
WR_DATA => pcie_tag_status_async,
843862
WR_EN => '1',
@@ -896,7 +915,7 @@ begin
896915
)
897916
port map (
898917
CLK => CLK,
899-
RESET => RESET,
918+
RESET => rst_local(3),
900919

901920
RX_DATA => RC_MFB_DATA,
902921
RX_SOF => RC_MFB_SOF,
@@ -939,7 +958,7 @@ begin
939958
)
940959
port map (
941960
CLK => CLK,
942-
RESET => RESET,
961+
RESET => rst_local(3),
943962

944963
RX_DATA => down_mfb_cutter_in_data,
945964
RX_SOF_POS => down_mfb_cutter_in_sof_pos,
@@ -1001,7 +1020,7 @@ begin
10011020
)
10021021
port map (
10031022
CLK => CLK,
1004-
RESET => RESET,
1023+
RESET => rst_local(3),
10051024

10061025
RX_MVB_DATA => down_mvb_stfifo_in_data,
10071026
RX_MVB_VLD => down_mvb_stfifo_in_vld,
@@ -1046,7 +1065,7 @@ begin
10461065
)
10471066
port map (
10481067
CLK => CLK,
1049-
RESET => RESET,
1068+
RESET => rst_local(4),
10501069

10511070
RX_DATA => down_mvb_stfifo_in_data,
10521071
RX_VLD => down_mvb_stfifo_in_vld,
@@ -1073,7 +1092,7 @@ begin
10731092
)
10741093
port map (
10751094
CLK => CLK,
1076-
RESET => RESET,
1095+
RESET => rst_local(3),
10771096

10781097
RX_DATA => down_mfb_stfifo_in_data,
10791098
RX_SOF => down_mfb_stfifo_in_sof,
@@ -1119,7 +1138,7 @@ begin
11191138
)
11201139
port map (
11211140
CLK => CLK,
1122-
RESET => RESET,
1141+
RESET => rst_local(4),
11231142

11241143
RX_MVB_DATA => down_mvb_pcie2dma_in_data,
11251144
RX_MVB_VLD => down_mvb_pcie2dma_in_vld,
@@ -1151,7 +1170,7 @@ begin
11511170
)
11521171
port map (
11531172
CLK => CLK,
1154-
RESET => RESET,
1173+
RESET => rst_local(4),
11551174

11561175
RX_DATA => down_mvb_tfifo_in_data,
11571176
RX_VLD => down_mvb_tfifo_in_vld,
@@ -1223,7 +1242,7 @@ begin
12231242
)
12241243
port map (
12251244
CLK => CLK,
1226-
RST => RESET,
1245+
RST => rst_local(3),
12271246

12281247
RX_DATA => down_mfb_splfi_in_data,
12291248
RX_SOF => down_mfb_splfi_in_sof,
@@ -1263,7 +1282,7 @@ begin
12631282
)
12641283
port map (
12651284
CLK => CLK,
1266-
RESET => RESET,
1285+
RESET => rst_local(3),
12671286

12681287
RX_MVB_DATA => down_mvb_split_in_data,
12691288
RX_MVB_SWITCH => down_mvb_split_in_switch,
@@ -1328,7 +1347,7 @@ begin
13281347
)
13291348
port map (
13301349
CLK => CLK,
1331-
RESET => RESET,
1350+
RESET => rst_local(4),
13321351

13331352
RX_DATA => down_mvb_trans_in_data(i),
13341353
RX_VLD => down_mvb_trans_in_vld(i),
@@ -1376,7 +1395,7 @@ begin
13761395
)
13771396
port map (
13781397
RX_CLK => CLK,
1379-
RX_RESET => RESET,
1398+
RX_RESET => rst_local(4),
13801399

13811400
RX_DATA => down_mvb_asfifo_in_data(i),
13821401
RX_VLD => down_mvb_asfifo_in_vld(i),
@@ -1409,7 +1428,7 @@ begin
14091428
)
14101429
port map (
14111430
CLK => CLK,
1412-
RESET => RESET,
1431+
RESET => rst_local(3),
14131432

14141433
RX_DATA => down_mfb_trans_in_data(i),
14151434
RX_SOP => down_mfb_trans_in_sof(i),
@@ -1447,7 +1466,7 @@ begin
14471466
)
14481467
port map (
14491468
RX_CLK => CLK,
1450-
RX_RESET => RESET,
1469+
RX_RESET => rst_local(3),
14511470

14521471
RX_DATA => down_mfb_asfifo_in_data(i),
14531472
RX_SOF_POS => down_mfb_asfifo_in_sof_pos(i),
@@ -1495,7 +1514,7 @@ begin
14951514
)
14961515
port map (
14971516
CLK => CLK,
1498-
RESET => RESET,
1517+
RESET => rst_local(4),
14991518

15001519
MI_DWR => DBG_MI_DWR,
15011520
MI_ADDR => DBG_MI_ADDR,
@@ -1663,7 +1682,7 @@ begin
16631682
begin
16641683
dbg_rq_cnt_v := (others => '0');
16651684
if (rising_edge(CLK)) then
1666-
if (RESET = '1') then
1685+
if (rst_local(4) = '1') then
16671686
dbg_rq_cnt <= (others => '0');
16681687
elsif (RQ_MFB_SRC_RDY = '1' and RQ_MFB_DST_RDY = '1') then
16691688
for i in 0 to MFB_UP_REGIONS-1 loop
@@ -1679,7 +1698,7 @@ begin
16791698
begin
16801699
dbg_rc_cnt_v := (others => '0');
16811700
if (rising_edge(CLK)) then
1682-
if (RESET = '1') then
1701+
if (rst_local(4) = '1') then
16831702
dbg_rc_cnt <= (others => '0');
16841703
elsif (RC_MFB_SRC_RDY = '1' and RC_MFB_DST_RDY = '1') then
16851704
for i in 0 to MFB_DOWN_REGIONS-1 loop
@@ -1695,7 +1714,7 @@ begin
16951714
begin
16961715
dbg_di_cnt_v := (others => '0');
16971716
if (rising_edge(CLK)) then
1698-
if (RESET = '1') then
1717+
if (rst_local(4) = '1') then
16991718
dbg_di_mvb_cnt <= (others => '0');
17001719
elsif (down_mvb_split_in_src_rdy = '1' and down_mvb_split_in_dst_rdy = '1') then
17011720
for i in 0 to MFB_DOWN_REGIONS-1 loop
@@ -1711,7 +1730,7 @@ begin
17111730
begin
17121731
dbg_di_cnt_v := (others => '0');
17131732
if (rising_edge(CLK)) then
1714-
if (RESET = '1') then
1733+
if (rst_local(4) = '1') then
17151734
dbg_di_mfb_cnt <= (others => '0');
17161735
elsif (down_mfb_split_in_src_rdy = '1' and down_mfb_split_in_dst_rdy = '1') then
17171736
for i in 0 to MFB_DOWN_REGIONS-1 loop

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