JK Flip Flop valid output for error input

[ricknun]

Describe the bug
I am using Cedar v1.5 on a Windows 10 PC. The JK Flip Flop produces a valid toggle when J=K=Clock and all 3 receive a +edge simultaneously. This should be an error output because it is unknown whether the edge, or J=K=0=latch, or J=K=1=toggle would be sensed first. A setup time of zero should not produce a valid toggle. I am guessing this is an issue for other Cedar edge-triggered devices as well.

To Reproduce
A student of mine submitted the following circuit and I had to say "OK because Cedar allows it, but wrong in the real world."

[casanova-uja]

Hi ricknun,
your comment is correct, this circuit is wrong in the real world. In Cedar it is OK because J and K are set to high before than rising edge is detected. It's difficult to resolve this bug just in the mode Cedar works.