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robtaylorrobtaylor
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Move drivers from chipflow-lib to alongside the IP.
This makes use of the new `amaranth.lib.wiring.Signature` `chipflow_lib.platform.DriverSignature` to annotate the driver information for the IP
1 parent 01a379a commit 64fc1d4

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20 files changed

+497
-38
lines changed

20 files changed

+497
-38
lines changed

‎chipflow_digital_ip/base/_platform_timer.py‎

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,10 @@
11
from amaranth import *
22
from amaranth.lib import wiring
33
from amaranth.lib.wiring import In, Out, flipped, connect
4-
54
from amaranth_soc import csr
65

6+
from chipflow_lib.platforms import SoftwareDriverSignature
7+
78

89
__all__ = ["PlatformTimer"]
910

@@ -34,10 +35,19 @@ def __init__(self):
3435

3536
self._bridge = csr.Bridge(regs.as_memory_map())
3637

37-
super().__init__({
38-
"bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
39-
"irq": Out(unsigned(1)),
40-
})
38+
super().__init__(
39+
SoftwareDriverSignature(
40+
members={
41+
"bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
42+
"irq": Out(unsigned(1)),
43+
},
44+
component=self,
45+
regs_struct='plat_timer_regs_t',
46+
c_files=['drivers/plat_timer.c'],
47+
h_files=['drivers/plat_timer.h'],
48+
)
49+
)
50+
4151
self.bus.memory_map = self._bridge.bus.memory_map
4252

4353
def elaborate(self, platform):

‎chipflow_digital_ip/base/_soc_id.py‎

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66

77
from amaranth_soc import csr
88

9+
from chipflow_lib.platforms import SoftwareDriverSignature
910

1011
__all__ = ["SoCID"]
1112

@@ -31,10 +32,16 @@ def __init__(self, *, type_id=0xbadca77e):
3132
self._soc_version = regs.add("soc_version", self.Register(32), offset=0x4)
3233

3334
self._bridge = csr.Bridge(regs.as_memory_map())
35+
super().__init__(
36+
SoftwareDriverSignature(
37+
members={
38+
"bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
39+
},
40+
component=self,
41+
regs_struct='soc_id_regs_t',
42+
h_files=['drivers/soc_id.h'])
43+
)
3444

35-
super().__init__({
36-
"bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
37-
})
3845
self.bus.memory_map = self._bridge.bus.memory_map
3946

4047
def elaborate(self, platform):

‎chipflow_digital_ip/base/drivers/plat_timer.c‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,14 @@
1+
/* SPDX-License-Identifier: BSD-2-Clause */
2+
#include "plat_timer.h"
3+
4+
uint64_t plat_timer_read(volatile plat_timer_regs_t *timer) {
5+
uint32_t cnt_lo = timer->cnt_lo;
6+
__asm__ volatile ("" : : : "memory");
7+
return (((uint64_t)timer->cnt_hi) << 32ULL) | cnt_lo;
8+
}
9+
10+
void plat_timer_schedule(volatile plat_timer_regs_t *timer, uint64_t val) {
11+
timer->cmp_lo = val & 0xFFFFFFFFU;
12+
__asm__ volatile ("" : : : "memory");
13+
timer->cmp_hi = (val >> 32U) & 0xFFFFFFFFU;
14+
}

‎chipflow_digital_ip/base/drivers/plat_timer.h‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,17 @@
1+
/* SPDX-License-Identifier: BSD-2-Clause */
2+
#ifndef PLAT_TIMER_H
3+
#define PLAT_TIMER_H
4+
5+
#include <stdint.h>
6+
7+
typedef struct __attribute__((packed, aligned(4))) {
8+
uint32_t cnt_lo;
9+
uint32_t cnt_hi;
10+
uint32_t cmp_lo;
11+
uint32_t cmp_hi;
12+
} plat_timer_regs_t;
13+
14+
uint64_t plat_timer_read(volatile plat_timer_regs_t *timer);
15+
void plat_timer_schedule(volatile plat_timer_regs_t *timer, uint64_t val);
16+
17+
#endif

‎chipflow_digital_ip/base/drivers/soc_id.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,12 @@
1+
/* SPDX-License-Identifier: BSD-2-Clause */
2+
#ifndef SOC_ID_H
3+
#define SOC_ID_H
4+
5+
#include <stdint.h>
6+
7+
typedef struct __attribute__((packed, aligned(4))) {
8+
uint32_t type;
9+
uint32_t version;
10+
} soc_id_regs_t;
11+
12+
#endif

‎chipflow_digital_ip/io/_gpio.py‎

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,8 @@
55

66
from amaranth_soc import csr, gpio
77

8-
from chipflow_lib.platforms import GPIOSignature
8+
from chipflow_lib.platforms import GPIOSignature, SoftwareDriverSignature
9+
910

1011
__all__ = ["GPIOPeripheral"]
1112

@@ -49,18 +50,24 @@ def __init__(self, *, pin_count, addr_width=4, data_width=8, input_stages=2):
4950

5051
if pin_count > 32 or pin_count <= 0:
5152
# TODO: why?
52-
raise ValueError(f"Pin pin_count must be a postive integrer less than 32, not {pin_count}")
53+
raise ValueError(f"Pin pin_count must be a postive integer 32 or less, not {pin_count}")
5354

5455
self._gpio = gpio.Peripheral(pin_count=pin_count,
5556
addr_width=addr_width,
5657
data_width=data_width,
5758
input_stages=input_stages)
59+
super().__init__(
60+
SoftwareDriverSignature(
61+
members={
62+
"bus": In(csr.Signature(addr_width=addr_width, data_width=data_width)),
63+
"pins": Out(GPIOSignature(pin_count)),
64+
"alt_mode": Out(unsigned(pin_count)),
65+
},
66+
component=self,
67+
regs_struct='gpio_regs_t',
68+
h_files=['drivers/gpio.h'])
69+
)
5870

59-
super().__init__({
60-
"bus": In(csr.Signature(addr_width=addr_width, data_width=data_width)),
61-
"pins": Out(GPIOSignature(pin_count)),
62-
"alt_mode": Out(unsigned(pin_count)),
63-
})
6471
self.bus.memory_map = self._gpio.bus.memory_map
6572

6673
def elaborate(self, platform):

‎chipflow_digital_ip/io/_i2c.py‎

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
from amaranth.lib.wiring import In, Out, connect, flipped
44

55
from amaranth_soc import csr
6-
from chipflow_lib.platforms import I2CSignature
6+
from chipflow_lib.platforms import I2CSignature, SoftwareDriverSignature
77
from ._glasgow_i2c import I2CInitiator
88

99
__all__ = ["I2CPeripheral"]
@@ -55,10 +55,20 @@ def __init__(self):
5555

5656
self._bridge = csr.Bridge(regs.as_memory_map())
5757

58-
super().__init__({
59-
"i2c_pins": Out(I2CSignature()),
60-
"bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
61-
})
58+
super().__init__(
59+
SoftwareDriverSignature(
60+
members={
61+
"i2c_pins": Out(I2CSignature()),
62+
"bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
63+
},
64+
component=self,
65+
regs_struct='i2c_regs_t',
66+
c_files=['drivers/i2c.c'],
67+
h_files=['drivers/i2c.h'],
68+
)
69+
70+
)
71+
6272
self.bus.memory_map = self._bridge.bus.memory_map
6373

6474
def elaborate(self, platform):

‎chipflow_digital_ip/io/_spi.py‎

Lines changed: 15 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3,10 +3,12 @@
33
from amaranth.lib.wiring import In, Out, connect, flipped
44

55
from amaranth_soc import csr
6-
from chipflow_lib.platforms import SPISignature
6+
from chipflow_lib.platforms import SPISignature, SoftwareDriverSignature
7+
78

89
__all__ = ["SPIPeripheral"]
910

11+
1012
class SPIController(wiring.Component):
1113
def __init__(self):
1214
super().__init__({
@@ -149,10 +151,18 @@ def __init__(self):
149151

150152
self._bridge = csr.Bridge(regs.as_memory_map())
151153

152-
super().__init__({
153-
"spi_pins": Out(SPISignature()),
154-
"bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
155-
})
154+
super().__init__(
155+
SoftwareDriverSignature(
156+
members={
157+
"spi_pins": Out(SPISignature()),
158+
"bus": In(csr.Signature(addr_width=regs.addr_width, data_width=regs.data_width)),
159+
},
160+
component=self,
161+
regs_struct='spi_regs_t',
162+
c_files=['drivers/spi.c'],
163+
h_files=['drivers/spi.h'])
164+
)
165+
156166
self.bus.memory_map = self._bridge.bus.memory_map
157167

158168
def elaborate(self, platform):

‎chipflow_digital_ip/io/_uart.py‎

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
from amaranth_soc import csr
66
from amaranth_stdio.serial import AsyncSerialRX, AsyncSerialTX
77

8-
from chipflow_lib.platforms import UARTSignature
8+
from chipflow_lib.platforms import UARTSignature, SoftwareDriverSignature
99

1010
from . import _rfc_uart
1111

@@ -117,7 +117,6 @@ def elaborate(self, platform):
117117

118118
return m
119119

120-
121120
class UARTPeripheral(wiring.Component):
122121

123122
"""Wrapper for amaranth_soc RFC UART with PHY and chipflow_lib.IOSignature support
@@ -149,10 +148,18 @@ def __init__(self, *, addr_width=5, data_width=8, init_divisor=0):
149148
phy_config_init=phy_config_shape.const({"divisor": init_divisor}),
150149
)
151150

152-
super().__init__({
153-
"bus": In(csr.Signature(addr_width=addr_width, data_width=data_width)),
154-
"pins": Out(UARTSignature()),
155-
})
151+
super().__init__(
152+
SoftwareDriverSignature(
153+
members={
154+
"bus": In(csr.Signature(addr_width=addr_width, data_width=data_width)),
155+
"pins": Out(UARTSignature()),
156+
},
157+
component=self,
158+
regs_struct='uart_regs_t',
159+
c_files=['drivers/uart.c'],
160+
h_files=['drivers/uart.h'])
161+
)
162+
156163
self.bus.memory_map = self._uart.bus.memory_map
157164
self._phy = UARTPhy(ports=self.pins, init_divisor=init_divisor)
158165

‎chipflow_digital_ip/io/drivers/gpio.h‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
/* SPDX-License-Identifier: BSD-2-Clause */
2+
#ifndef GPIO_H
3+
#define GPIO_H
4+
5+
#include <stdint.h>
6+
7+
typedef struct __attribute__((packed, aligned(2))) {
8+
uint16_t mode;
9+
uint8_t input;
10+
uint8_t output;
11+
uint16_t setclr;
12+
} gpio_regs_t;
13+
14+
typedef enum {
15+
#define _GPIO_PIN(n) \
16+
GPIO_PIN ## n ## _INPUT_ONLY = (0 << 2 * (n)), \
17+
GPIO_PIN ## n ## _PUSH_PULL = (1 << 2 * (n)), \
18+
GPIO_PIN ## n ## _OPEN_DRAIN = (2 << 2 * (n)), \
19+
GPIO_PIN ## n ## _ALTERNATE = (3 << 2 * (n))
20+
21+
_GPIO_PIN(0),
22+
_GPIO_PIN(1),
23+
_GPIO_PIN(2),
24+
_GPIO_PIN(3),
25+
_GPIO_PIN(4),
26+
_GPIO_PIN(5),
27+
_GPIO_PIN(6),
28+
_GPIO_PIN(7),
29+
#undef _GPIO_PIN
30+
} gpio_mode_t;
31+
32+
typedef enum {
33+
#define _GPIO_PIN(n) \
34+
GPIO_PIN ## n ## _SET = (1 << 2 * (n)), \
35+
GPIO_PIN ## n ## _CLEAR = (2 << 2 * (n))
36+
37+
_GPIO_PIN(0),
38+
_GPIO_PIN(1),
39+
_GPIO_PIN(2),
40+
_GPIO_PIN(3),
41+
_GPIO_PIN(4),
42+
_GPIO_PIN(5),
43+
_GPIO_PIN(6),
44+
_GPIO_PIN(7),
45+
#undef _GPIO_PIN
46+
} gpio_setclr_t;
47+
48+
#endif

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