[aarch64] Add function multiversioning support

This adds initial support for function multiversioning on aarch64 using
the target_version and target_clones attributes.  This loosely follows
the Beta specification in the ACLE [1], although with some differences
that still need to be resolved (possibly as follow-up patches).

Existing function multiversioning implementations are broken in various
ways when used across translation units.  This includes placing
resolvers in the wrong translation units, and using symbol mangling that
callers to unintentionally bypass the resolver in some circumstances.
Fixing these issues for aarch64 will require modifications to our ACLE
specification.  It will also require further adjustments to existing
middle end code, to facilitate different mangling and resolver
placement while preserving existing target behaviours.

The list of function multiversioning features specified in the ACLE is
also inconsistent with the list of features supported in target option
extensions.  I intend to resolve some or all of these inconsistencies at
a later stage.

The target_version attribute is currently only supported in C++, since
this is the only frontend with existing support for multiversioning
using the target attribute.  On the other hand, this patch happens to
enable multiversioning with the target_clones attribute in Ada and D, as
well as the entire C family, using their existing frontend support.

This patch also does not support the following aspects of the Beta
specification:

- The target_clones attribute should allow an implicit unlisted
  "default" version.
- There should be an option to disable function multiversioning at
  compile time.
- Unrecognised target names in a target_clones attribute should be
  ignored (with an optional warning).  This current patch raises an
  error instead.

[1] https://github.com/ARM-software/acle/blob/main/main/acle.md#function-multi-versioning

gcc/ChangeLog:

	* config/aarch64/aarch64-feature-deps.h (fmv_deps_<FEAT_NAME>):
	Define aarch64_feature_flags mask foreach FMV feature.
	* config/aarch64/aarch64-option-extensions.def: Use new macros
	to define FMV feature extensions.
	* config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
	Check for target_version attribute after processing target
	attribute.
	(aarch64_fmv_feature_data): New.
	(aarch64_parse_fmv_features): New.
	(aarch64_process_target_version_attr): New.
	(aarch64_option_valid_version_attribute_p): New.
	(get_feature_mask_for_version): New.
	(compare_feature_masks): New.
	(aarch64_compare_version_priority): New.
	(build_ifunc_arg_type): New.
	(make_resolver_func): New.
	(add_condition_to_bb): New.
	(dispatch_function_versions): New.
	(aarch64_generate_version_dispatcher_body): New.
	(aarch64_get_function_versions_dispatcher): New.
	(aarch64_common_function_versions): New.
	(aarch64_mangle_decl_assembler_name): New.
	(TARGET_OPTION_VALID_VERSION_ATTRIBUTE_P): New implementation.
	(TARGET_OPTION_EXPANDED_CLONES_ATTRIBUTE): New implementation.
	(TARGET_OPTION_FUNCTION_VERSIONS): New implementation.
	(TARGET_COMPARE_VERSION_PRIORITY): New implementation.
	(TARGET_GENERATE_VERSION_DISPATCHER_BODY): New implementation.
	(TARGET_GET_FUNCTION_VERSIONS_DISPATCHER): New implementation.
	(TARGET_MANGLE_DECL_ASSEMBLER_NAME): New implementation.
	* config/aarch64/aarch64.h (TARGET_HAS_FMV_TARGET_ATTRIBUTE):
	Set target macro.
	* config/arm/aarch-common.h (enum aarch_parse_opt_result): Add
	new value to report duplicate FMV feature.
	* common/config/aarch64/cpuinfo.h: New file.

libgcc/ChangeLog:

	* config/aarch64/cpuinfo.c (enum CPUFeatures): Move to shared
	copy in gcc/common

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/options_set_17.c: Reorder expected flags.
	* gcc.target/aarch64/cpunative/native_cpu_0.c: Ditto.
	* gcc.target/aarch64/cpunative/native_cpu_13.c: Ditto.
	* gcc.target/aarch64/cpunative/native_cpu_16.c: Ditto.
	* gcc.target/aarch64/cpunative/native_cpu_17.c: Ditto.
	* gcc.target/aarch64/cpunative/native_cpu_18.c: Ditto.
	* gcc.target/aarch64/cpunative/native_cpu_19.c: Ditto.
	* gcc.target/aarch64/cpunative/native_cpu_20.c: Ditto.
	* gcc.target/aarch64/cpunative/native_cpu_21.c: Ditto.
	* gcc.target/aarch64/cpunative/native_cpu_22.c: Ditto.
	* gcc.target/aarch64/cpunative/native_cpu_6.c: Ditto.
	* gcc.target/aarch64/cpunative/native_cpu_7.c: Ditto.

Author: andrewcarlotti

gcc/common/config/aarch64/cpuinfo.h

@@ -0,0 +1,94 @@
+/* CPU feature detection for AArch64 architecture.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+   This file is part of GCC.
+
+   This file is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 3, or (at your option) any
+   later version.
+
+   This file is distributed in the hope that it will be useful, but
+   WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+   General Public License for more details.
+
+   Under Section 7 of GPL version 3, you are granted additional
+   permissions described in the GCC Runtime Library Exception, version
+   3.1, as published by the Free Software Foundation.
+
+   You should have received a copy of the GNU General Public License and
+   a copy of the GCC Runtime Library Exception along with this program;
+   see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
+   <http://www.gnu.org/licenses/>.  */
+
+/* This enum is used in libgcc feature detection, and in the function
+   multiversioning implementation in aarch64.cc.  The enum should use the same
+   values as the corresponding enum in LLVM's compiler-rt, to faciliate
+   compatibility between compilers.  */
+
+enum CPUFeatures {
+  FEAT_RNG,
+  FEAT_FLAGM,
+  FEAT_FLAGM2,
+  FEAT_FP16FML,
+  FEAT_DOTPROD,
+  FEAT_SM4,
+  FEAT_RDM,
+  FEAT_LSE,
+  FEAT_FP,
+  FEAT_SIMD,
+  FEAT_CRC,
+  FEAT_SHA1,
+  FEAT_SHA2,
+  FEAT_SHA3,
+  FEAT_AES,
+  FEAT_PMULL,
+  FEAT_FP16,
+  FEAT_DIT,
+  FEAT_DPB,
+  FEAT_DPB2,
+  FEAT_JSCVT,
+  FEAT_FCMA,
+  FEAT_RCPC,
+  FEAT_RCPC2,
+  FEAT_FRINTTS,
+  FEAT_DGH,
+  FEAT_I8MM,
+  FEAT_BF16,
+  FEAT_EBF16,
+  FEAT_RPRES,
+  FEAT_SVE,
+  FEAT_SVE_BF16,
+  FEAT_SVE_EBF16,
+  FEAT_SVE_I8MM,
+  FEAT_SVE_F32MM,
+  FEAT_SVE_F64MM,
+  FEAT_SVE2,
+  FEAT_SVE_AES,
+  FEAT_SVE_PMULL128,
+  FEAT_SVE_BITPERM,
+  FEAT_SVE_SHA3,
+  FEAT_SVE_SM4,
+  FEAT_SME,
+  FEAT_MEMTAG,
+  FEAT_MEMTAG2,
+  FEAT_MEMTAG3,
+  FEAT_SB,
+  FEAT_PREDRES,
+  FEAT_SSBS,
+  FEAT_SSBS2,
+  FEAT_BTI,
+  FEAT_LS64,
+  FEAT_LS64_V,
+  FEAT_LS64_ACCDATA,
+  FEAT_WFXT,
+  FEAT_SME_F64,
+  FEAT_SME_I64,
+  FEAT_SME2,
+  FEAT_RCPC3,
+  FEAT_MAX,
+  FEAT_EXT = 62, /* Reserved to indicate presence of additional features field
+		    in __aarch64_cpu_features.  */
+  FEAT_INIT      /* Used as flag of features initialization completion.  */
+};

gcc/config/aarch64/aarch64-feature-deps.h

@@ -115,6 +115,13 @@ get_flags_off (aarch64_feature_flags mask)
   constexpr auto cpu_##CORE_IDENT = ARCH_IDENT ().enable | get_enable FEATURES;
 #include "config/aarch64/aarch64-cores.def"
 
+/* Define fmv_deps_<NAME> variables for each FMV feature, giving the transitive
+   closure of all the features that the FMV feature enables.  */
+#define AARCH64_FMV_FEATURE(A, FEAT_NAME, OPT_FLAGS) \
+  constexpr auto fmv_deps_##FEAT_NAME = get_enable OPT_FLAGS;
+#include "config/aarch64/aarch64-option-extensions.def"
+
+
 }
 }
 

gcc/config/aarch64/aarch64-option-extensions.def

@@ -17,17 +17,22 @@
    along with GCC; see the file COPYING3.  If not see
    <http://www.gnu.org/licenses/>.  */
 
-/* This is a list of ISA extentsions in AArch64.
+/* This is a list of ISA extensions in AArch64.
 
-   Before using #include to read this file, define a macro:
+   Before using #include to read this file, define one of the following
+   macros:
 
       AARCH64_OPT_EXTENSION(NAME, IDENT, REQUIRES, EXPLICIT_ON,
 			    EXPLICIT_OFF, FEATURE_STRING)
 
+      AARCH64_FMV_FEATURE(NAME, FEAT_NAME, IDENT)
+
    - NAME is the name of the extension, represented as a string constant.
 
    - IDENT is the canonical internal name for this flag.
 
+   - FEAT_NAME is the unprefixed name used in the CPUFeatures enum.
+
    - REQUIRES is a list of features that must be enabled whenever this
      feature is enabled.  The relationship is implicitly transitive:
      if A appears in B's REQUIRES and B appears in C's REQUIRES then
@@ -58,112 +63,224 @@
      that are required.  Their order is not important.  An empty string means
      do not detect this feature during auto detection.
 
-   The list of features must follow topological order wrt REQUIRES
-   and EXPLICIT_ON.  For example, if A is in B's REQUIRES list, A must
-   come before B.  This is enforced by aarch64-feature-deps.h.
+   - OPT_FLAGS is a list of feature IDENTS that should be enabled (along with
+     their transitive dependencies) when the specified FMV feature is present.
+
+   Where a feature is present as both an extension and a function
+   multiversioning feature, and IDENT matches the FEAT_NAME suffix, then these
+   can be listed here simultaneously using the macro:
+
+      AARCH64_OPT_FMV_EXTENSION(NAME, IDENT, REQUIRES, EXPLICIT_ON,
+				EXPLICIT_OFF, FEATURE_STRING)
+
+   The list of features extensions must follow topological order wrt REQUIRES
+   and EXPLICIT_ON.  For example, if A is in B's REQUIRES list, A must come
+   before B.  This is enforced by aarch64-feature-deps.h.
+
+   The list of multiversioning features must be ordered by increasing priority,
+   as defined in https://github.com/ARM-software/acle/blob/main/main/acle.md
 
    NOTE: Any changes to the AARCH64_OPT_EXTENSION macro need to be mirrored in
    config.gcc.  */
 
+#ifndef AARCH64_OPT_EXTENSION
+#define AARCH64_OPT_EXTENSION(NAME, IDENT, REQUIRES, EXPLICIT_ON, \
+			      EXPLICIT_OFF, FEATURE_STRING)
+#endif
+
+#ifndef AARCH64_FMV_FEATURE
+#define AARCH64_FMV_FEATURE(NAME, FEAT_NAME, OPT_FLAGS)
+#endif
+
+#define AARCH64_OPT_FMV_EXTENSION(NAME, IDENT, REQUIRES, EXPLICIT_ON,   \
+				  EXPLICIT_OFF, FEATURE_STRING)		\
+AARCH64_OPT_EXTENSION(NAME, IDENT, REQUIRES, EXPLICIT_ON, EXPLICIT_OFF,	\
+		      FEATURE_STRING)					\
+AARCH64_FMV_FEATURE(NAME, IDENT, (IDENT))
+
+
 AARCH64_OPT_EXTENSION("fp", FP, (), (), (), "fp")
 
 AARCH64_OPT_EXTENSION("simd", SIMD, (FP), (), (), "asimd")
 
-AARCH64_OPT_EXTENSION("crc", CRC, (), (), (), "crc32")
+AARCH64_OPT_FMV_EXTENSION("rng", RNG, (), (), (), "rng")
 
-AARCH64_OPT_EXTENSION("lse", LSE, (), (), (), "atomics")
+AARCH64_OPT_FMV_EXTENSION("flagm", FLAGM, (), (), (), "flagm")
 
-/* +nofp16 disables an implicit F16FML, even though an implicit F16FML
-   does not imply F16.  See F16FML for more details.  */
-AARCH64_OPT_EXTENSION("fp16", F16, (FP), (), (F16FML), "fphp asimdhp")
+AARCH64_FMV_FEATURE("flagm2", FLAGM2, (FLAGM))
+
+AARCH64_FMV_FEATURE("fp16fml", FP16FML, (F16FML))
+
+AARCH64_OPT_FMV_EXTENSION("dotprod", DOTPROD, (SIMD), (), (), "asimddp")
 
-AARCH64_OPT_EXTENSION("rcpc", RCPC, (), (), (), "lrcpc")
+AARCH64_OPT_FMV_EXTENSION("sm4", SM4, (SIMD), (), (), "sm3 sm4")
 
 /* An explicit +rdma implies +simd, but +rdma+nosimd still enables scalar
    RDMA instructions.  */
 AARCH64_OPT_EXTENSION("rdma", RDMA, (), (SIMD), (), "asimdrdm")
 
-AARCH64_OPT_EXTENSION("dotprod", DOTPROD, (SIMD), (), (), "asimddp")
+AARCH64_FMV_FEATURE("rmd", RDM, (RDMA))
+
+AARCH64_OPT_FMV_EXTENSION("lse", LSE, (), (), (), "atomics")
+
+AARCH64_FMV_FEATURE("fp", FP, (FP))
+
+AARCH64_FMV_FEATURE("simd", SIMD, (SIMD))
+
+AARCH64_OPT_FMV_EXTENSION("crc", CRC, (), (), (), "crc32")
+
+AARCH64_FMV_FEATURE("sha1", SHA1, ())
 
-AARCH64_OPT_EXTENSION("aes", AES, (SIMD), (), (), "aes")
+AARCH64_OPT_FMV_EXTENSION("sha2", SHA2, (SIMD), (), (), "sha1 sha2")
 
-AARCH64_OPT_EXTENSION("sha2", SHA2, (SIMD), (), (), "sha1 sha2")
+AARCH64_FMV_FEATURE("sha3", SHA3, (SHA3))
+
+AARCH64_OPT_FMV_EXTENSION("aes", AES, (SIMD), (), (), "aes")
+
+AARCH64_FMV_FEATURE("pmull", PMULL, ())
 
 /* +nocrypto disables AES, SHA2 and SM4, and anything that depends on them
    (such as SHA3 and the SVE2 crypto extensions).  */
 AARCH64_OPT_EXTENSION("crypto", CRYPTO, (AES, SHA2), (), (AES, SHA2, SM4),
 		      "aes pmull sha1 sha2")
 
+/* Listing sha3 after crypto means we pass "+aes+sha3" to the assembler
+   instead of "+sha3+crypto".  */
 AARCH64_OPT_EXTENSION("sha3", SHA3, (SHA2), (), (), "sha3 sha512")
 
-AARCH64_OPT_EXTENSION("sm4", SM4, (SIMD), (), (), "sm3 sm4")
+/* +nofp16 disables an implicit F16FML, even though an implicit F16FML
+   does not imply F16.  See F16FML for more details.  */
+AARCH64_OPT_EXTENSION("fp16", F16, (FP), (), (F16FML), "fphp asimdhp")
+
+AARCH64_FMV_FEATURE("fp16", FP16, (F16))
 
 /* An explicit +fp16fml implies +fp16, but a dependence on it does not.
    Thus -march=armv8.4-a implies F16FML but not F16.  -march=armv8.4-a+fp16
    and -march=armv8.4-a+fp16fml are equivalent and enable both F16FML and F16.
    -march=armv8.4-a+nofp16+fp16 enables F16 but not F16FML.  */
 AARCH64_OPT_EXTENSION("fp16fml", F16FML, (), (F16), (), "asimdfhm")
 
-AARCH64_OPT_EXTENSION("sve", SVE, (SIMD, F16), (), (), "sve")
+AARCH64_FMV_FEATURE("dit", DIT, ())
 
-AARCH64_OPT_EXTENSION("profile", PROFILE, (), (), (), "")
+AARCH64_FMV_FEATURE("dpb", DPB, ())
 
-AARCH64_OPT_EXTENSION("rng", RNG, (), (), (), "rng")
+AARCH64_FMV_FEATURE("dpb2", DPB2, ())
 
-AARCH64_OPT_EXTENSION("memtag", MEMTAG, (), (), (), "")
+AARCH64_FMV_FEATURE("jscvt", JSCVT, ())
 
-AARCH64_OPT_EXTENSION("sb", SB, (), (), (), "sb")
+AARCH64_FMV_FEATURE("fcma", FCMA, (SIMD))
 
-AARCH64_OPT_EXTENSION("ssbs", SSBS, (), (), (), "ssbs")
+AARCH64_OPT_FMV_EXTENSION("rcpc", RCPC, (), (), (), "lrcpc")
 
-AARCH64_OPT_EXTENSION("predres", PREDRES, (), (), (), "")
+AARCH64_FMV_FEATURE("rcpc2", RCPC2, (RCPC))
 
-AARCH64_OPT_EXTENSION("sve2", SVE2, (SVE), (), (), "sve2")
+AARCH64_OPT_FMV_EXTENSION("rcpc3", RCPC3, (), (), (), "rcpc3")
 
-AARCH64_OPT_EXTENSION("sve2-sm4", SVE2_SM4, (SVE2, SM4), (), (), "svesm4")
+AARCH64_FMV_FEATURE("frintts", FRINTTS, ())
+
+AARCH64_FMV_FEATURE("dgh", DGH, ())
+
+AARCH64_OPT_FMV_EXTENSION("i8mm", I8MM, (SIMD), (), (), "i8mm")
+
+/* An explicit +bf16 implies +simd, but +bf16+nosimd still enables scalar BF16
+   instructions.  */
+AARCH64_OPT_FMV_EXTENSION("bf16", BF16, (FP), (SIMD), (), "bf16")
+
+AARCH64_FMV_FEATURE("ebf16", EBF16, (BF16))
+
+AARCH64_FMV_FEATURE("rpres", RPRES, ())
+
+AARCH64_OPT_FMV_EXTENSION("sve", SVE, (SIMD, F16), (), (), "sve")
+
+AARCH64_FMV_FEATURE("sve-bf16", SVE_BF16, (SVE, BF16))
+
+AARCH64_FMV_FEATURE("sve-ebf16", SVE_EBF16, (SVE, BF16))
+
+AARCH64_FMV_FEATURE("sve-i8mm", SVE_I8MM, (SVE, I8MM))
+
+AARCH64_OPT_EXTENSION("f32mm", F32MM, (SVE), (), (), "f32mm")
+
+AARCH64_FMV_FEATURE("f32mm", SVE_F32MM, (F32MM))
+
+AARCH64_OPT_EXTENSION("f64mm", F64MM, (SVE), (), (), "f64mm")
+
+AARCH64_FMV_FEATURE("f64mm", SVE_F64MM, (F64MM))
+
+AARCH64_OPT_FMV_EXTENSION("sve2", SVE2, (SVE), (), (), "sve2")
 
 AARCH64_OPT_EXTENSION("sve2-aes", SVE2_AES, (SVE2, AES), (), (), "sveaes")
 
-AARCH64_OPT_EXTENSION("sve2-sha3", SVE2_SHA3, (SVE2, SHA3), (), (), "svesha3")
+AARCH64_FMV_FEATURE("sve2-aes", SVE_AES, (SVE2_AES))
+
+AARCH64_FMV_FEATURE("sve2-pmull128", SVE_PMULL128, (SVE2))
 
 AARCH64_OPT_EXTENSION("sve2-bitperm", SVE2_BITPERM, (SVE2), (), (),
 		      "svebitperm")
 
-AARCH64_OPT_EXTENSION("tme", TME, (), (), (), "")
+AARCH64_FMV_FEATURE("sve2-bitperm", SVE_BITPERM, (SVE2_BITPERM))
 
-AARCH64_OPT_EXTENSION("i8mm", I8MM, (SIMD), (), (), "i8mm")
+AARCH64_OPT_EXTENSION("sve2-sha3", SVE2_SHA3, (SVE2, SHA3), (), (), "svesha3")
 
-AARCH64_OPT_EXTENSION("f32mm", F32MM, (SVE), (), (), "f32mm")
+AARCH64_FMV_FEATURE("sve2-sha3", SVE_SHA3, (SVE2_SHA3))
 
-AARCH64_OPT_EXTENSION("f64mm", F64MM, (SVE), (), (), "f64mm")
+AARCH64_OPT_EXTENSION("sve2-sm4", SVE2_SM4, (SVE2, SM4), (), (), "svesm4")
 
-/* An explicit +bf16 implies +simd, but +bf16+nosimd still enables scalar BF16
-   instructions.  */
-AARCH64_OPT_EXTENSION("bf16", BF16, (FP), (SIMD), (), "bf16")
+AARCH64_FMV_FEATURE("sve2-sm4", SVE_SM4, (SVE2_SM4))
+
+AARCH64_OPT_FMV_EXTENSION("sme", SME, (BF16, SVE2), (), (), "sme")
+
+AARCH64_OPT_FMV_EXTENSION("memtag", MEMTAG, (), (), (), "")
+
+AARCH64_FMV_FEATURE("memtag2", MEMTAG2, (MEMTAG))
+
+AARCH64_FMV_FEATURE("memtag3", MEMTAG3, (MEMTAG))
 
-AARCH64_OPT_EXTENSION("flagm", FLAGM, (), (), (), "flagm")
+AARCH64_OPT_FMV_EXTENSION("sb", SB, (), (), (), "sb")
+
+AARCH64_OPT_FMV_EXTENSION("predres", PREDRES, (), (), (), "")
+
+AARCH64_OPT_FMV_EXTENSION("ssbs", SSBS, (), (), (), "ssbs")
+
+AARCH64_FMV_FEATURE("ssbs2", SSBS2, (SSBS))
+
+AARCH64_FMV_FEATURE("bti", BTI, ())
+
+AARCH64_OPT_EXTENSION("profile", PROFILE, (), (), (), "")
+
+AARCH64_OPT_EXTENSION("tme", TME, (), (), (), "")
 
 AARCH64_OPT_EXTENSION("pauth", PAUTH, (), (), (), "paca pacg")
 
 AARCH64_OPT_EXTENSION("ls64", LS64, (), (), (), "")
 
-AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "")
+AARCH64_FMV_FEATURE("ls64", LS64, ())
 
-AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc")
+AARCH64_FMV_FEATURE("ls64_v", LS64_V, ())
 
-AARCH64_OPT_EXTENSION("sme", SME, (BF16, SVE2), (), (), "sme")
+AARCH64_FMV_FEATURE("ls64_accdata", LS64_ACCDATA, (LS64))
 
-AARCH64_OPT_EXTENSION("sme-i16i64", SME_I16I64, (SME), (), (), "")
+AARCH64_FMV_FEATURE("wfxt", WFXT, ())
 
 AARCH64_OPT_EXTENSION("sme-f64f64", SME_F64F64, (SME), (), (), "")
 
-AARCH64_OPT_EXTENSION("sme2", SME2, (SME), (), (), "sme2")
+AARCH64_FMV_FEATURE("sme-f64f64", SME_F64, (SME_F64F64))
+
+AARCH64_OPT_EXTENSION("sme-i16i64", SME_I16I64, (SME), (), (), "")
+
+AARCH64_FMV_FEATURE("sme-i16i64", SME_I64, (SME_I16I64))
+
+AARCH64_OPT_FMV_EXTENSION("sme2", SME2, (SME), (), (), "sme2")
+
+AARCH64_OPT_EXTENSION("mops", MOPS, (), (), (), "")
+
+AARCH64_OPT_EXTENSION("cssc", CSSC, (), (), (), "cssc")
 
 AARCH64_OPT_EXTENSION("d128", D128, (), (), (), "d128")
 
 AARCH64_OPT_EXTENSION("the", THE, (), (), (), "the")
 
 AARCH64_OPT_EXTENSION("gcs", GCS, (), (), (), "gcs")
 
-AARCH64_OPT_EXTENSION("rcpc3", RCPC3, (), (), (), "rcpc3")
+#undef AARCH64_OPT_FMV_EXTENSION
 #undef AARCH64_OPT_EXTENSION
+#undef AARCH64_FMV_FEATURE