Approximate CRTC registers for HDMI/DVI output #9
Description
Summary
Some software uses non-standard CRTC register settings to achieve visual effects. Currently, these effects only display correctly on a 12" monitor.
Background
Native video for the PET is generated by the FPGA, which implements the 6845 CRTC chip in gateware for video addressing and sync generation.
HDMI/DVI output is independently generated by the RP2040 by reading back video memory and bit-banging TMDS encoded video in real-time. Currently, the HDMI/DVI output always displays a 40x25 or 80x25 grid of characters starting at $8000 (the same as non-CRTC PET models.)
Proposal
While there are insufficient free cycles to accurately emulate the CRTC on the RP2040, you can get a decent approximation by reading back the CRTC registers and using the starting display address for R12/13 and adjusting row/col lengths and the character height in pixels (R1, R6, R9).
The nightly (unreleased) firmware does this, which is sufficient for the NPA demo. Possibly the effects of HSYNC/VSYNC timing could be incorporated as well to shift the display off-center, but scaling rasterlines to change the pixel shape is likely beyond what the RP2040 can do in real-time.
Known affected software
Related Note
When the EconoPET is configured for a 9" display, we lock the CRTC registers to values that produce a compatible 15 kHz / 60 Hz display. This is by design to prevent accidental damage, as software that that modifies CRTC registers is by definition targeting a 12" 20 kHz display.
We could probably relax this a bit and allow CRTC registers that are deemed "safe" to be updated (e.g., display address).