vivado-library/ip/Pmods/Pmod_Bridge_v1_1/utils/board/board.xit at f261272e924b53136e9e96c3da84637c2d4dd541 · Digilent/vivado-library · GitHub

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package require xilinx::board 1.0
namespace import ::xilinx::board::*

puts "RUNNING BOARD.XIT"

set instname [current_inst]
set f_xdc [add_ipfile -usedIn  [list synthesis implementation board ] -force ${instname}_board.xdc]
puts "    $f_xdc"
puts_ipfile $f_xdc "#--------------------Physical Constraints-----------------\n"
if { [get_project_property BOARD] == "" } {
    close_ipfile $f_xdc
    return
}

set board_if [get_property PARAM_VALUE.PMOD]
if { $board_if ne "Custom"} {
	board_add_tri_state_port_constraints $f_xdc $board_if \
		PIN1_O out0_O\
		PIN1_I out0_I\
		PIN1_T out0_T
	board_add_tri_state_port_constraints $f_xdc $board_if \
		PIN2_O out1_O\
		PIN2_I out1_I\
		PIN2_T out1_T
	board_add_tri_state_port_constraints $f_xdc $board_if \
		PIN3_O out2_O\
		PIN3_I out2_I\
		PIN3_T out2_T
	board_add_tri_state_port_constraints $f_xdc $board_if \
		PIN4_O out3_O\
		PIN4_I out3_I\
		PIN4_T out3_T
    board_add_tri_state_port_constraints $f_xdc $board_if \
		PIN7_O out4_O\
		PIN7_I out4_I\
		PIN7_T out4_T
	board_add_tri_state_port_constraints $f_xdc $board_if \
		PIN8_O out5_O\
		PIN8_I out5_I\
		PIN8_T out5_T
	board_add_tri_state_port_constraints $f_xdc $board_if \
		PIN9_O out6_O\
		PIN9_I out6_I\
		PIN9_T out6_T
	board_add_tri_state_port_constraints $f_xdc $board_if \
		PIN10_O out7_O\
		PIN10_I out7_I\
		PIN10_T out7_T
	if {[get_property PARAM_VALUE.USE_PULLUPS] == true && [get_property PARAM_VALUE.Top_Row_Interface] == "I2C"} {
		puts_ipfile $f_xdc {set_property -dict {PULLUP TRUE } [get_ports out2_T]}
		puts_ipfile $f_xdc {set_property -dict {PULLUP TRUE } [get_ports out3_T]}
	}
}
close_ipfile $f_xdc