Add Zydis x86/x86-64 disassembler support

Integrate Zydis as an optional dependency to enable x86/x86-64 guest
instruction disassembly during JIT compilation.

Build with -DENABLE_ZYDIS=TRUE.
Use FEX_X86DISASSEMBLE=1 at runtime to output guest x86 instructions
for each compiled block.

Author: pmatos

.gitmodules

@@ -49,3 +49,7 @@
 [submodule "External/range-v3"]
 	path = External/range-v3
 	url = https://github.com/ericniebler/range-v3.git
+[submodule "External/zydis"]
+	shallow = true
+	path = External/zydis
+	url = https://github.com/zyantific/zydis.git

CMakeLists.txt

@@ -28,6 +28,7 @@ option(ENABLE_LIBCXX "Enables LLVM libc++" FALSE)
 option(ENABLE_CCACHE "Enables ccache for compile caching" TRUE)
 option(ENABLE_VIXL_SIMULATOR "Enable use of VIXL simulator for emulation (only useful for CI testing)" FALSE)
 option(ENABLE_VIXL_DISASSEMBLER "Enables debug disassembler output with VIXL" FALSE)
+option(ENABLE_ZYDIS "Enables x86/x86-64 guest disassembler output with Zydis" FALSE)
 option(USE_LEGACY_BINFMTMISC "Uses legacy method of setting up binfmt_misc" FALSE)
 option(ENABLE_FEXCORE_PROFILER "Enables use of the FEXCore timeline profiling capabilities" FALSE)
 set (FEXCORE_PROFILER_BACKEND "gpuvis" CACHE STRING "Set which backend to use for the FEXCore profiler (gpuvis, tracy)")
@@ -315,6 +316,12 @@ if (BUILD_TESTING OR ENABLE_VIXL_DISASSEMBLER OR ENABLE_VIXL_SIMULATOR)
   include_directories(SYSTEM External/vixl/src/)
 endif()
 
+if (ENABLE_ZYDIS)
+  set(ZYDIS_BUILD_TOOLS OFF CACHE BOOL "" FORCE)
+  set(ZYDIS_BUILD_EXAMPLES OFF CACHE BOOL "" FORCE)
+  add_subdirectory(External/zydis/)
+endif()
+
 if (ENABLE_FEXCORE_PROFILER AND FEXCORE_PROFILER_BACKEND STREQUAL "TRACY")
   add_subdirectory(External/tracy)
 endif()

External/zydis

@@ -96,6 +96,10 @@ if (ENABLE_VIXL_DISASSEMBLER)
   list(APPEND DEFINES -DVIXL_DISASSEMBLER=1)
 endif()
 
+if (ENABLE_ZYDIS)
+  list(APPEND DEFINES -DZYDIS_DISASSEMBLER=1)
+endif()
+
 if (_M_ARM_64 AND HAS_CLANG_PRESERVE_ALL)
   list(APPEND DEFINES "-DFEXCORE_PRESERVE_ALL_ATTR=__attribute__((preserve_all));-DFEXCORE_HAS_PRESERVE_ALL_ATTR=1")
 else()
@@ -108,6 +112,10 @@ if (ENABLE_VIXL_DISASSEMBLER OR ENABLE_VIXL_SIMULATOR)
   list (APPEND LIBS vixl)
 endif()
 
+if (ENABLE_ZYDIS)
+  list (APPEND LIBS Zydis)
+endif()
+
 if (NOT MINGW_BUILD)
   list (APPEND LIBS dl)
 else()

FEXCore/Source/CMakeLists.txt

@@ -334,6 +334,14 @@
           "\tstats: Will print stats when disassembling the code"
         ]
       },
+      "X86Disassemble": {
+        "Type": "bool",
+        "Default": "false",
+        "Desc": [
+          "Enables x86/x86-64 guest disassembly output for compiled blocks.",
+          "Requires FEX to be built with -DENABLE_ZYDIS=TRUE"
+        ]
+      },
       "ForceSVEWidth": {
         "Type": "uint32",
         "Default": "0",

FEXCore/Source/Interface/Config/Config.json.in

@@ -9,6 +9,9 @@ desc: Glues Frontend, OpDispatcher and IR Opts & Compilation, LookupCache, Dispa
 */
 
 #include <cstdint>
+#ifdef ZYDIS_DISASSEMBLER
+#include <Zydis/Zydis.h>
+#endif
 #include "Interface/Core/ArchHelpers/Arm64Emitter.h"
 #include "Interface/Core/LookupCache.h"
 #include "Interface/Core/CPUBackend.h"
@@ -694,6 +697,32 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
     Thread->FrontendDecoder->DelayedDisownBuffer();
   }
 
+#ifdef ZYDIS_DISASSEMBLER
+  {
+    FEX_CONFIG_OPT(X86Disassemble, X86DISASSEMBLE);
+    if (X86Disassemble()) {
+      const uint64_t StartAddr = Thread->FrontendDecoder->DecodedMinAddress;
+      const uint64_t Length = Thread->FrontendDecoder->DecodedMaxAddress - StartAddr;
+      const auto MachineMode = Config.Is64BitMode ? ZYDIS_MACHINE_MODE_LONG_64 : ZYDIS_MACHINE_MODE_LEGACY_32;
+      const uint8_t* Data = reinterpret_cast<const uint8_t*>(StartAddr);
+      ZydisDisassembledInstruction Instruction;
+      ZyanUSize Offset = 0;
+
+      LogMan::Msg::IFmt("Guest x86 Begin");
+      while (Offset < Length) {
+        if (ZYAN_SUCCESS(ZydisDisassembleIntel(MachineMode, StartAddr + Offset, Data + Offset, Length - Offset, &Instruction))) {
+          LogMan::Msg::IFmt("0x{:x}: {}", StartAddr + Offset, Instruction.text);
+          Offset += Instruction.info.length;
+        } else {
+          LogMan::Msg::IFmt("0x{:x}: (invalid)", StartAddr + Offset);
+          Offset++;
+        }
+      }
+      LogMan::Msg::IFmt("Guest x86 End");
+    }
+  }
+#endif
+
   IR::IREmitter* IREmitter = Thread->OpDispatcher.get();
 
   auto ShouldDump = Thread->OpDispatcher->ShouldDumpIR();