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Shanthipriya20Shanthipriya20
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Merge pull request #435 from Senbagaseelan18/IC-Subcircuits
Subcircuit Files for different ICs
2 parents 4737ea0 + 1aeca27 commit 8b7780d

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‎library/SubcircuitLibrary/74HC126/74HC126-cache.lib‎

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EESchema-LIBRARY Version 2.3
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#encoding utf-8
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#
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# PORT
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#
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DEF PORT U 0 40 Y Y 26 F N
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F0 "U" 50 100 30 H V C CNN
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F1 "PORT" 0 0 30 H V C CNN
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F2 "" 0 0 60 H V C CNN
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F3 "" 0 0 60 H V C CNN
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DRAW
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A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
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A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
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S -100 50 100 -50 0 1 0 N
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X ~ 1 250 0 100 L 30 30 1 1 B
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X ~ 2 250 0 100 L 30 30 2 1 B
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X ~ 3 250 0 100 L 30 30 3 1 B
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X ~ 4 250 0 100 L 30 30 4 1 B
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X ~ 5 250 0 100 L 30 30 5 1 B
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X ~ 6 250 0 100 L 30 30 6 1 B
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X ~ 7 250 0 100 L 30 30 7 1 B
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X ~ 8 250 0 100 L 30 30 8 1 B
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X ~ 9 250 0 100 L 30 30 9 1 B
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X ~ 10 250 0 100 L 30 30 10 1 B
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X ~ 11 250 0 100 L 30 30 11 1 B
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X ~ 12 250 0 100 L 30 30 12 1 B
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X ~ 13 250 0 100 L 30 30 13 1 B
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X ~ 14 250 0 100 L 30 30 14 1 B
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X ~ 15 250 0 100 L 30 30 15 1 B
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X ~ 16 250 0 100 L 30 30 16 1 B
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X ~ 17 250 0 100 L 30 30 17 1 B
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X ~ 18 250 0 100 L 30 30 18 1 B
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X ~ 19 250 0 100 L 30 30 19 1 B
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X ~ 20 250 0 100 L 30 30 20 1 B
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X ~ 21 250 0 100 L 30 30 21 1 B
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X ~ 22 250 0 100 L 30 30 22 1 B
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X ~ 23 250 0 100 L 30 30 23 1 B
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X ~ 24 250 0 100 L 30 30 24 1 B
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X ~ 25 250 0 100 L 30 30 25 1 B
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X ~ 26 250 0 100 L 30 30 26 1 B
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ENDDRAW
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ENDDEF
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#
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# d_inverter
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#
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DEF d_inverter U 0 40 Y Y 1 F N
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F0 "U" 0 -100 60 H V C CNN
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F1 "d_inverter" 0 150 60 H V C CNN
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F2 "" 50 -50 60 H V C CNN
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F3 "" 50 -50 60 H V C CNN
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DRAW
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P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
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X ~ 1 -300 0 200 R 50 50 1 1 I
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X ~ 2 300 0 200 L 50 50 1 1 O I
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ENDDRAW
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ENDDEF
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#
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# d_tristate
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#
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DEF d_tristate U 0 40 Y Y 1 F N
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F0 "U" -250 250 60 H V C CNN
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F1 "d_tristate" -200 450 60 H V C CNN
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F2 "" -100 350 60 H V C CNN
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F3 "" -100 350 60 H V C CNN
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DRAW
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P 4 0 1 0 -400 550 -400 150 350 350 -400 550 N
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X IN 1 -600 350 200 R 50 50 1 1 I
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X EN 2 -50 50 193 U 50 50 1 1 I
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X OUT 3 550 350 200 L 50 50 1 1 O
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ENDDRAW
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ENDDEF
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#
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#End Library

‎library/SubcircuitLibrary/74HC126/74HC126.cir‎

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* C:\Users\senba\Desktop\FOSSEE\eSim\library\SubcircuitLibrary\74HC126\74HC126.cir
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* EESchema Netlist Version 1.1 (Spice format) creation date: 12/27/25 10:39:50
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* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
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* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
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* Sheet Name: /
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U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter
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U4 Net-_U2-Pad2_ Net-_U4-Pad2_ d_inverter
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U6 Net-_U4-Pad2_ Net-_U6-Pad2_ d_inverter
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U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter
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U5 Net-_U3-Pad2_ Net-_U5-Pad2_ d_inverter
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U7 Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter
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U8 Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad3_ d_tristate
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U9 Net-_U8-Pad3_ Net-_U1-Pad3_ d_inverter
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U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ PORT
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.end

‎library/SubcircuitLibrary/74HC126/74HC126.cir.out‎

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* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\74hc126\74hc126.cir
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* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
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* u4 net-_u2-pad2_ net-_u4-pad2_ d_inverter
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* u6 net-_u4-pad2_ net-_u6-pad2_ d_inverter
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* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter
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* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter
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* u7 net-_u5-pad2_ net-_u7-pad2_ d_inverter
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* u8 net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad3_ d_tristate
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* u9 net-_u8-pad3_ net-_u1-pad3_ d_inverter
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* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ port
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a1 net-_u1-pad1_ net-_u2-pad2_ u2
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a2 net-_u2-pad2_ net-_u4-pad2_ u4
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a3 net-_u4-pad2_ net-_u6-pad2_ u6
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a4 net-_u1-pad2_ net-_u3-pad2_ u3
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a5 net-_u3-pad2_ net-_u5-pad2_ u5
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a6 net-_u5-pad2_ net-_u7-pad2_ u7
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a7 net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad3_ u8
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a8 net-_u8-pad3_ net-_u1-pad3_ u9
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* Schematic Name: d_inverter, NgSpice Name: d_inverter
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.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
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* Schematic Name: d_inverter, NgSpice Name: d_inverter
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.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
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* Schematic Name: d_inverter, NgSpice Name: d_inverter
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.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
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* Schematic Name: d_inverter, NgSpice Name: d_inverter
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.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
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* Schematic Name: d_inverter, NgSpice Name: d_inverter
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.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
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* Schematic Name: d_inverter, NgSpice Name: d_inverter
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.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
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* Schematic Name: d_tristate, NgSpice Name: d_tristate
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.model u8 d_tristate(delay=1.0e-9 input_load=1.0e-12 enable_load=1.0e-12 )
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* Schematic Name: d_inverter, NgSpice Name: d_inverter
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.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
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.tran 0e-00 0e-00 0e-00
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* Control Statements
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.control
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run
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print allv > plot_data_v.txt
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print alli > plot_data_i.txt
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.endc
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.end

‎library/SubcircuitLibrary/74HC126/74HC126.pro‎

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update=22/05/2015 07:44:53
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version=1
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last_client=kicad
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[general]
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version=1
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RootSch=
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BoardNm=
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[pcbnew]
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version=1
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LastNetListRead=
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UseCmpFile=1
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PadDrill=0.600000000000
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PadDrillOvalY=0.600000000000
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PadSizeH=1.500000000000
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PadSizeV=1.500000000000
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PcbTextSizeV=1.500000000000
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PcbTextSizeH=1.500000000000
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PcbTextThickness=0.300000000000
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ModuleTextSizeV=1.000000000000
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ModuleTextSizeH=1.000000000000
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ModuleTextSizeThickness=0.150000000000
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SolderMaskClearance=0.000000000000
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SolderMaskMinWidth=0.000000000000
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DrawSegmentWidth=0.200000000000
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BoardOutlineThickness=0.100000000000
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ModuleOutlineThickness=0.150000000000
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[cvpcb]
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version=1
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NetIExt=net
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[eeschema]
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version=1
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LibDir=
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[eeschema/libraries]
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LibName1=adc-dac
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LibName2=memory
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LibName3=xilinx
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LibName4=microcontrollers
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LibName5=dsp
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LibName6=microchip
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LibName7=analog_switches
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LibName8=motorola
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LibName9=texas
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LibName10=intel
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LibName11=audio
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LibName12=interface
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LibName13=digital-audio
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LibName14=philips
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LibName15=display
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LibName16=cypress
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LibName17=siliconi
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LibName18=opto
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LibName19=atmel
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LibName20=contrib
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LibName21=power
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LibName22=eSim_Plot
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LibName23=transistors
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LibName24=conn
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LibName25=eSim_User
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LibName26=regul
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LibName27=74xx
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LibName28=cmos4000
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LibName29=eSim_Analog
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LibName30=eSim_Devices
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LibName31=eSim_Digital
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LibName32=eSim_Hybrid
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LibName33=eSim_Miscellaneous
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LibName34=eSim_Power
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LibName35=eSim_Sources
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LibName36=eSim_Subckt
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LibName37=eSim_Nghdl
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LibName38=eSim_Ngveri
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LibName39=eSim_SKY130
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LibName40=eSim_SKY130_Subckts

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