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Project_qsim.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.1.0 Build 162 10/23/2013 SJ Web Edition
# Date created = 12:46:28 November 20, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Project_qsim_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY testing_clk
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:19:25 NOVEMBER 29, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR "C:/Users/jadme/Downloads/project/Project/simulation/qsim/" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name VHDL_FILE receiver.vhd
set_global_assignment -name VHDL_FILE eightBitRightShiftRegister.vhd
set_global_assignment -name VHDL_FILE three_bit_register_reset_increment.vhdl
set_global_assignment -name VHDL_FILE three_bit_counter_logic.vhdl
set_global_assignment -name VHDL_FILE Receiver_FSM_controller.vhdl
set_global_assignment -name VHDL_FILE mux_4to1.vhd
set_global_assignment -name VHDL_FILE lab3VHDL.vhd
set_global_assignment -name VHDL_FILE timer.vhd
set_global_assignment -name VHDL_FILE Project.vhd
set_global_assignment -name VHDL_FILE oneBitComparator.vhd
set_global_assignment -name VHDL_FILE oneBitAdder.vhd
set_global_assignment -name VHDL_FILE mux2x1_4.vhd
set_global_assignment -name VHDL_FILE FSM_Controller.vhd
set_global_assignment -name VHDL_FILE fourBitComparator.vhd
set_global_assignment -name VHDL_FILE four_bit_register_reset_increment.vhd
set_global_assignment -name VHDL_FILE fiveBitAdderSub.vhd
set_global_assignment -name VHDL_FILE fiveBitAdder.vhd
set_global_assignment -name VHDL_FILE enARdFF_2.vhd
set_global_assignment -name VHDL_FILE dec_7seg.vhd
set_global_assignment -name VHDL_FILE debouncer_2.vhd
set_global_assignment -name VHDL_FILE counter.vhd
set_global_assignment -name BDF_FILE lab3.bdf
set_global_assignment -name BDF_FILE Tasinda.bdf
set_global_assignment -name VHDL_FILE endFF_2.vhd
set_global_assignment -name VHDL_FILE Tx_controller.vhd
set_global_assignment -name VHDL_FILE fourBitBCDDecoder.vhd
set_global_assignment -name VHDL_FILE enardFF_2.vhd
set_global_assignment -name VHDL_FILE 8bit_RIGHT_shift_register.vhdl
set_global_assignment -name VHDL_FILE 8bit_register_load.vhdl
set_global_assignment -name VHDL_FILE 4bit_counter_logic.vhdl
set_global_assignment -name BDF_FILE testing.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform.vwf
set_global_assignment -name VHDL_FILE two_to_one_mux.vhd
set_global_assignment -name BDF_FILE testing_counter.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform1.vwf
set_global_assignment -name BDF_FILE testing_bus.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform2.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform3.vwf
set_global_assignment -name BDF_FILE TxDesign.bdf
set_global_assignment -name VHDL_FILE UART_FSM.vhd
set_global_assignment -name BDF_FILE projectDraft.bdf
set_global_assignment -name VHDL_FILE mux_32to8.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform4.vwf
set_global_assignment -name VHDL_FILE mux_8bit_8to1.vhd
set_global_assignment -name VHDL_FILE mux2x1_8.vhd
set_global_assignment -name VHDL_FILE eightBitRegisterSingle.vhd
set_global_assignment -name VHDL_FILE BusHandlerUART.vhd
set_global_assignment -name VHDL_FILE clk_divider.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE full_system_test_1.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE baud_rate_test.vwf
set_global_assignment -name BDF_FILE baud_test.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE baud_test.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform5.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform6.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform7.vwf
set_global_assignment -name BDF_FILE testing_clk.bdf
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name VECTOR_WAVEFORM_FILE output_files/Waveform.vwf
set_location_assignment PIN_AC28 -to BaudSel[1]
set_location_assignment PIN_AC27 -to BaudSel[2]
set_location_assignment PIN_H15 -to BClk
set_location_assignment PIN_F19 -to doneOneTransimission
set_location_assignment PIN_E19 -to DoneTx
set_location_assignment PIN_Y2 -to GClock
set_location_assignment PIN_Y23 -to GReset
set_location_assignment PIN_AB26 -to MSC[0]
set_location_assignment PIN_AC25 -to MSC[1]
set_location_assignment PIN_AB25 -to MSC[2]
set_location_assignment PIN_AC24 -to MSC[3]
set_location_assignment PIN_E21 -to RDR[0]
set_location_assignment PIN_E22 -to RDR[1]
set_location_assignment PIN_E25 -to RDR[2]
set_location_assignment PIN_E24 -to RDR[3]
set_location_assignment PIN_H21 -to RDR[4]
set_location_assignment PIN_G20 -to RDR[5]
set_location_assignment PIN_G22 -to RDR[6]
set_location_assignment PIN_G21 -to RDR[7]
set_location_assignment PIN_AD27 -to SSC[0]
set_location_assignment PIN_AB27 -to SSC[1]
set_location_assignment PIN_AC26 -to SSC[2]
set_location_assignment PIN_AD26 -to SSC[3]
set_location_assignment PIN_J19 -to statess_out_rx[0]
set_location_assignment PIN_H19 -to statess_out_rx[1]
set_location_assignment PIN_J17 -to statess_out_rx[2]
set_location_assignment PIN_G17 -to statess_out_rx[3]
set_location_assignment PIN_J15 -to statess_out_rx[4]
set_location_assignment PIN_H16 -to statess_out_rx[5]
set_location_assignment PIN_J16 -to Tx_sattes[0]
set_location_assignment PIN_H17 -to Tx_sattes[1]
set_location_assignment PIN_G19 -to TxD
set_location_assignment PIN_Y24 -to Tx_trigger
set_location_assignment PIN_F15 -to U_states[0]
set_location_assignment PIN_G15 -to U_states[1]
set_location_assignment PIN_G16 -to U_states[2]
set_location_assignment PIN_AB28 -to BaudSel[0]
set_location_assignment PIN_AA23 -to SSCS
set_location_assignment PIN_AA22 -to RxD
set_global_assignment -name VECTOR_WAVEFORM_FILE output_files/Waveform1.vwf
set_global_assignment -name VECTOR_WAVEFORM_FILE output_files/Waveform2.vwf
set_global_assignment -name VHDL_FILE baud_gen.vhd
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VECTOR_WAVEFORM_FILE Waveform8.vwf
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name VECTOR_OUTPUT_FORMAT VWF
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "Z:/CEG 3155 Labs/Project/project/Waveform8.vwf"