16bitCPU/controlunit.vcd at master · Graystripe17/16bitCPU · GitHub

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$date
  Wed Apr  1 13:56:42 2020
$end
$version
  GHDL v0
$end
$timescale
  1 fs
$end
$scope module standard $end
$upscope $end
$scope module std_logic_1164 $end
$upscope $end
$scope module numeric_std $end
$upscope $end
$scope module t_controlunit $end
$var reg 4 ! opcode_t[15:12] $end
$var reg 1 " cregwrite_t $end
$var reg 1 # coffset_t $end
$var reg 4 $ caluop_t[3:0] $end
$var reg 1 % cmemwrite_t $end
$var reg 1 & cmemread_t $end
$var reg 1 ' cmemtoreg_t $end
$var reg 1 ( cldi_t $end
$var reg 1 ) cjalr_t $end
$var reg 1 * reset_t $end
$scope module control $end
$var reg 4 + opcode[15:12] $end
$var reg 1 , cregwrite $end
$var reg 1 - coffset $end
$var reg 4 . caluop[3:0] $end
$var reg 1 / cmemwrite $end
$var reg 1 0 cmemread $end
$var reg 1 1 cmemtoreg $end
$var reg 1 2 cldi $end
$var reg 1 3 cjalr $end
$var reg 1 4 reset $end
$upscope $end
$upscope $end
$enddefinitions $end
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