From b48f24e0dc2bcdb584cd2f2c5e324040df230334 Mon Sep 17 00:00:00 2001 From: HiddenTrojan <93521146+Labeeb2339@users.noreply.github.com> Date: Tue, 11 Aug 2026 16:26:52 +0800 Subject: [PATCH] docs: rename and simplify RTL project --- README.md | 19 +++++++++---------- assets/rtl-ci-transcript.svg | 2 +- assets/rtl-regression.svg | 2 +- assets/rtl-saturation-evidence.svg | 2 +- model/__init__.py | 2 +- tools/capture_ci_receipt.py | 4 ++-- tools/render_readme_assets.py | 12 ++++++++---- 7 files changed, 23 insertions(+), 20 deletions(-) diff --git a/README.md b/README.md index 0021fa4..b605440 100644 --- a/README.md +++ b/README.md @@ -1,21 +1,20 @@ -# Edge AI RTL Lab +# INT8 Dot-Product RTL -I built Edge AI RTL Lab as a small, reproducible hardware-design project that -connects quantized AI inference arithmetic with an RTL verification workflow. -The core computes a signed int8 vector dot product using one multiply-accumulate -lane, then clamps -the exact internal sum to a signed output width. +This project started while I was learning how signed INT8 inference arithmetic +maps to RTL. It contains one vector dot-product core, a bit-exact Python model, +a self-checking testbench, and Yosys checks. The core uses one +multiply-accumulate lane, then clamps the exact internal sum to a signed output +width. -I kept the scope deliberately small: parameterized SystemVerilog, ready/valid -control, a bit-exact Python reference model, deterministic regression, and CI. -This is **not** a trained AI model or a complete neural-network accelerator. +The small scope is intentional. This is one verified arithmetic block, not a +trained model, a complete neural-network accelerator, or a silicon result.

Successful public CI transcript: Icarus Verilog passed deterministic vectors at lengths 1, 8, and 17, and Yosys found no structural problems

This transcript comes from successful public -[GitHub Actions run 30224621114](https://github.com/Labeeb2339/edge-ai-rtl-lab/actions/runs/30224621114) +[GitHub Actions run 30224621114](https://github.com/Labeeb2339/int8-dot-product-rtl/actions/runs/30224621114) at commit `6fd552b`. The checked-in receipt can be regenerated from the run log with `python tools/capture_ci_receipt.py`; the SVG renderer consumes that receipt instead of inventing a result. diff --git a/assets/rtl-ci-transcript.svg b/assets/rtl-ci-transcript.svg index 822433b..8295a21 100644 --- a/assets/rtl-ci-transcript.svg +++ b/assets/rtl-ci-transcript.svg @@ -1,5 +1,5 @@ - Successful Edge AI RTL Lab simulator and synthesis transcript + Successful INT8 Dot-Product RTL simulator and synthesis transcript A terminal-style rendering of GitHub Actions run 30224621114: Icarus Verilog passed all deterministic vectors at vector lengths 1, 8, and 17, and Yosys reported no structural problems.