bus_ctrl: forward error to caches to hart

Author: devins2518

source_code/caches/l1/l1_cache.sv

@@ -139,6 +139,9 @@ module l1_cache #(
     //Snooping signals
     logic[N_TAG_BITS-1:0] bus_frame_tag; //Tag from bus to compare
 
+    // error handling
+    assign proc_gen_bus_if.error = bus_ctrl_if.derror[HART_ID];
+
     assign snoop_decoded_addr = decoded_cache_addr_t'(bus_ctrl_if.ccsnoopaddr[HART_ID]);
 
     // sram instance
@@ -543,7 +546,7 @@ module l1_cache #(
                     next_state = FLUSH_CACHE;
 	        end
 	        FETCH: begin
-                if (!bus_ctrl_if.dwait[HART_ID]) begin
+                if (bus_ctrl_if.derror[HART_ID] || !bus_ctrl_if.dwait[HART_ID]) begin
                     cache_miss = 1;
                     next_state = HIT;
                 end else if (snoop_hit && !sramWEN)
@@ -552,7 +555,7 @@ module l1_cache #(
                     next_state = CANCEL_REQ;
             end
             WB: begin
-                if (!bus_ctrl_if.dwait[HART_ID])
+                if (bus_ctrl_if.derror[HART_ID] || !bus_ctrl_if.dwait[HART_ID])
                     next_state = HIT;
                 else if (snoop_hit && !sramWEN)
                     next_state = SNOOP;

source_code/include/bus_ctrl_if.vh

@@ -66,7 +66,7 @@ typedef logic [DATA_WIDTH-1:0] transfer_width_t;
 // modified from coherence_ctrl_if.vh
 interface bus_ctrl_if ();
     // L1 generic control signals
-    logic               [CPUS-1:0] dREN, dWEN, dwait; 
+    logic               [CPUS-1:0] dREN, dWEN, dwait, derror;
     transfer_width_t    [CPUS-1:0] dload, dstore, snoop_dstore, driver_dstore;
     bus_word_t          [CPUS-1:0] daddr;
     logic         [CPUS-1:0] [3:0] dbyte_en;
@@ -83,7 +83,7 @@ interface bus_ctrl_if ();
     // L2 signals
     l2_state_t l2state; 
     bus_word_t l2load, l2store;
-    logic l2WEN, l2REN; 
+    logic l2WEN, l2REN, l2error;
     bus_word_t l2addr; 
     logic [3:0] l2_byte_en;
     // Core outputs
@@ -106,14 +106,14 @@ interface bus_ctrl_if ();
     modport cc(
         input   dREN, dWEN, daddr, dstore, dbyte_en,
                 ccwrite, ccsnoophit, ccdirty, ccsnoopdone,
-                l2load, l2state, ccabort,
-        output  dwait, dload, 
+                l2load, l2state, l2error, ccabort,
+        output  dwait, dload, derror,
                 ccwait, ccinv, ccsnoopaddr, ccexclusive, 
                 l2addr, l2store, l2REN, l2WEN, l2_byte_en
     ); 
 
     modport cache(
-        input dwait, dload, ccwait, ccinv, ccsnoopaddr, ccexclusive,
+        input dwait, dload, derror, ccwait, ccinv, ccsnoopaddr, ccexclusive,
         output dREN, dWEN, daddr, dstore, dbyte_en, ccwrite, ccsnoophit, ccdirty, ccsnoopdone
     );
 

source_code/standard_core/bus_ctrl.sv

@@ -111,7 +111,8 @@ module bus_ctrl #(
             // BUS_TO_CACHE:       nstate = IDLE;
             TRANSFER_R:         nstate = ccif.ccdirty[supplier_cpu] ? WRITEBACK_MS : BUS_TO_CACHE;
             TRANSFER_RX:        nstate = BUS_TO_CACHE;
-            READ_L2:            nstate = block_count_done ? BUS_TO_CACHE : state;
+            READ_L2:            nstate = ccif.l2error ? IDLE :
+                                         block_count_done ? BUS_TO_CACHE : state;
             WRITEBACK_MS:       nstate = block_count_done ? IDLE : state;
             WRITEBACK:          nstate = block_count_done ? IDLE : state;
             BUS_TO_CACHE:       nstate = IDLE;
@@ -134,6 +135,7 @@ module bus_ctrl #(
         ccif.l2WEN = '0;
         ccif.ccexclusive = '0;
         ccif.ccinv = '0;
+        ccif.derror = '0;
         ndload = ccif.dload[requester_cpu];
         nexclusiveUpdate = exclusiveUpdate;
         nrequester_cpu = requester_cpu;
@@ -143,6 +145,7 @@ module bus_ctrl #(
 
         casez(state)
             IDLE: begin // obtain the requester CPU id
+                nblock_count = 0;
                 if (|(ccif.dWEN & ~ccif.ccabort))
                     nrequester_cpu = priorityEncode(ccif.dWEN & ~ccif.ccabort);
                 else if (|(ccif.dREN & ccif.ccwrite & ~ccif.ccabort))
@@ -188,7 +191,9 @@ module bus_ctrl #(
                 nblock_count = block_count;
                 ccif.l2REN = !block_count_done;
 
-                if (ccif.l2state == L2_ACCESS) begin
+                if (ccif.l2error) begin
+                    ccif.derror[requester_cpu] = 1;
+                end if (ccif.l2state == L2_ACCESS) begin
                     ccif.l2REN = 0;
                     nblock_count = block_count + 1;
                     if (!pass_through && block_count < BLOCK_SIZE - 1) begin

source_code/standard_core/memory_controller.sv

@@ -51,5 +51,6 @@ module memory_controller #(
 
         bus_ctrl_if.l2load = out_gen_bus_if.rdata;
         bus_ctrl_if.l2state = out_gen_bus_if.busy ? L2_BUSY : L2_ACCESS;
+        bus_ctrl_if.l2error = out_gen_bus_if.error;
     end
 endmodule