tlb/page perm check: added support for Svade

Author: wrcunnin

source_code/caches/page_perm_check.sv

@@ -99,6 +99,18 @@ always_comb begin
           fault_insn_page  = access == ACCESS_INSN;
         end
       end
+      // Svade
+      // fault if accessed bit not set
+      else if (~pte_perms.accessed) begin
+        fault_load_page  = access == ACCESS_LOAD;
+        fault_store_page = access == ACCESS_STORE;
+        fault_insn_page  = access == ACCESS_INSN;
+      end
+      // Svade
+      // fault if a store and dirty bit not set
+      else if (access == ACCESS_STORE && ~pte_perms.dirty) begin
+        fault_store_page = 1;
+      end
     end
   end
 end

source_code/caches/tlb/tlb.sv

@@ -188,7 +188,7 @@ module tlb #(
         if (IS_ITLB) begin
             assign access = ACCESS_INSN;
         end else begin
-            assign access = prv_pipe_if.ex_mem_wen ? ACCESS_STORE : ACCESS_LOAD;
+            assign access = prv_pipe_if.ex_mem_wen ? ACCESS_STORE : prv_pipe_if.ex_mem_ren ? ACCESS_LOAD : ACCESS_NONE;
         end
     endgenerate
 

source_code/tb/tb_page_perm_check.sv

@@ -31,6 +31,7 @@
 *                 - Fault    -> U = 0, in U-Mode
 *                 - No Fault -> Level != 0, sv32 = 0, should NEVER EVER happen in RV32
 *                 - Fault    -> Level != 0, sv32 = 1, pte_sv32.ppn[9:0] != 0
+*                 - Fault    -> Access bit not set
 *                 - No Fault -> U = 1, in S-Mode, and mstatus.sum = 1
 *                 - No Fault -> U = 1, in U-Mode
 *                 - No Fault -> Level != 0, sv32 = 1, pte_sv32.ppn[9:0] == 0
@@ -56,6 +57,7 @@
 *                 - Fault    -> R = 1, W = 0, X = 1
 *                 - No Fault -> R = 1, W = 1, X = 0
 *                 - No Fault -> R = 1, W = 1, X = 1
+*                 - Fault    -> Dirty bit not set
 *                 Instructions:
 *                 - Fault    -> R = 0, W = 0, X = 0
 *                 - No Fault -> R = 0, W = 0, X = 1
@@ -326,6 +328,25 @@ initial begin : MAIN
   complete_test();
 
 
+  /**************************
+  * Fault -> Access bit not set
+  **************************/
+  begin_test("All", "Fault -> Access bit not set");
+
+  // non test related inputs
+  set_level('0);
+  set_satp(1, '1, '1);
+  set_priv_level(S_MODE);
+
+  // test related inputs
+  set_pte('1, RWXV_PERMS, 0, 1);
+
+  // check outputs
+  check_all_fault();
+
+  complete_test();
+
+
   /**************************
   * No Fault -> U = 1, in S-Mode, and mstatus.sum = 1
   **************************/
@@ -774,6 +795,25 @@ initial begin : MAIN
   complete_test();
 
 
+  /**************************
+  * Fault -> Dirty bit not set
+  **************************/
+  begin_test("Stores", "Fault -> Dirty bit not set");
+
+  // non test related inputs
+  set_priv_level(S_MODE);
+  set_level(0);
+  set_satp(1, '1, '1);
+
+  // test related inputs
+  set_pte('1, PAGE_PERM_VALID | PAGE_PERM_READ | PAGE_PERM_WRITE | PAGE_PERM_EXECUTE, 1, 0);
+
+  // check outputs
+  check_store_fault();
+
+  complete_test();
+
+
   /**************************
   * Instructions:
   * Fault -> R = 0, W = 0, X = 0
@@ -968,11 +1008,15 @@ task set_access;
   access = new_access;
 endtask
 
-task set_pte;
-  input logic [SV32_PPNLEN-1:0] new_ppn;
-  input logic [9:0]             new_perms;
+task set_pte (
+  input logic [SV32_PPNLEN-1:0] new_ppn,
+  input logic [9:0]             new_perms,
+  input logic set_accessed = 1,
+  input logic set_dirty = 1
+);
+  
   pte_sv32.ppn = new_ppn;
-  pte_sv32.perms = pte_perms_t'(new_perms);
+  pte_sv32.perms = pte_perms_t'(new_perms | (set_accessed ? PAGE_PERM_ACCESSED : 0) | (set_dirty ? PAGE_PERM_DIRTY : 0));
 endtask
 
 task set_priv_level;