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cole-nelsoncole-nelson
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rv32c_pkg: Fix names of localparams
1 parent ac12809 commit f0dc587

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Lines changed: 75 additions & 77 deletions

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‎source_code/rv32c/rv32c_pkg.sv‎

Lines changed: 75 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -27,33 +27,34 @@ package rv32c_pkg;
2727
RVC_CS_FUNC_FSW = 3'b111,
2828
RVC_CS_FUNC_SD = 3'b111;
2929

30-
localparam logic [2:0] RVC_CI_ADDI = 3'b000,
31-
RVC_CI_ADDIW = 3'b001,
32-
RVC_CI_ADDI16SP = 3'b011,
33-
RVC_CI_LI = 3'b010,
34-
RVC_CI_LUI = 3'b011,
35-
RVC_CI_SRLI = 3'b100,
36-
RVC_CI_SRAI = 3'b100,
37-
RVC_CI_SLLI = 3'b000,
30+
localparam logic [2:0] RVC_CI_FUNC_ADDI = 3'b000,
31+
RVC_CI_FUNC_NOP = 3'b000,
32+
RVC_CI_FUNC_ADDIW = 3'b001,
33+
RVC_CI_FUNC_ADDI16SP = 3'b011,
34+
RVC_CI_FUNC_LI = 3'b010,
35+
RVC_CI_FUNC_LUI = 3'b011,
36+
RVC_CI_FUNC_SRLI = 3'b100,
37+
RVC_CI_FUNC_SRAI = 3'b100,
38+
RVC_CI_FUNC_SLLI = 3'b000,
3839
// SP-relative load/store
39-
RVC_CI_FLDSP = 3'b001,
40-
RVC_CI_LWSP = 3'b010,
41-
RVC_CI_FLWSP = 3'b011,
42-
RVC_CI_LDSP = 3'b011;
40+
RVC_CI_FUNC_FLDSP = 3'b001,
41+
RVC_CI_FUNC_LWSP = 3'b010,
42+
RVC_CI_FUNC_FLWSP = 3'b011,
43+
RVC_CI_FUNC_LDSP = 3'b011;
4344

44-
localparam logic [7:0] RVC_CA_SUB = 8'b1000_1100,
45-
RVC_CA_XOR = 8'b1000_1101,
46-
RVC_CA_OR = 8'b1000_1110,
47-
RVC_CA_AND = 8'b1000_1111,
48-
RVC_CA_SUBW = 8'b1001_1100,
49-
RVC_CA_ADDW = 8'b1001_1101;
45+
localparam logic [7:0] RVC_CA_FUNC_SUB = 8'b1000_1100,
46+
RVC_CA_FUNC_XOR = 8'b1000_1101,
47+
RVC_CA_FUNC_OR = 8'b1000_1110,
48+
RVC_CA_FUNC_AND = 8'b1000_1111,
49+
RVC_CA_FUNC_SUBW = 8'b1001_1100,
50+
RVC_CA_FUNC_ADDW = 8'b1001_1101;
5051

51-
localparam logic [2:0] RVC_CB_BEQZ = 3'b110,
52-
RVC_CB_BNEZ = 3'b111,
53-
RVC_CB_ANDI = 3'b100;
52+
localparam logic [2:0] RVC_CB_FUNC_BEQZ = 3'b110,
53+
RVC_CB_FUNC_BNEZ = 3'b111,
54+
RVC_CB_FUNC_ANDI = 3'b100;
5455

55-
localparam logic [2:0] RVC_CJ_J = 3'b101,
56-
RVC_CJ_JAL = 3'b001;
56+
localparam logic [2:0] RVC_CJ_FUNC_J = 3'b101,
57+
RVC_CJ_FUNC_JAL = 3'b001;
5758

5859

5960
localparam logic [31:0] UNIMP = 32'h0;
@@ -79,8 +80,8 @@ package rv32c_pkg;
7980
// CR-format is always op == C2.
8081
// CR-format has 2 valid functs, overloaded to 5 insns
8182
rvc_cr_t ifmt = compressed;
82-
assert(ifmt.op == RVC_C2);
83-
assert(ifmt.funct4 == RVC_CR_FUNC_ADD || ifmt.funct4 == RVC_CR_FUNC_MV);
83+
//assert(ifmt.op == RVC_C2);
84+
//assert(ifmt.funct4 == RVC_CR_FUNC_ADD || ifmt.funct4 == RVC_CR_FUNC_MV);
8485

8586
// instruction determined on rs1/rs2
8687
// C.ADD/C.MV: rs2 != 0. rs1 != 0 -> HINT
@@ -118,7 +119,7 @@ package rv32c_pkg;
118119
ofmt.rs1 = (ifmt.funct4 == RVC_CR_FUNC_ADD) ? ifmt.rs1 : 5'd0;
119120
ofmt.funct3 = rv32i_types_pkg::ADDSUB;
120121
ofmt.rd = ifmt.rs1;
121-
ofmt.opcode = rv32i_types_pkt::REGREG;
122+
ofmt.opcode = rv32i_types_pkg::REGREG;
122123

123124
return ofmt;
124125
end
@@ -132,11 +133,11 @@ package rv32c_pkg;
132133
logic [1:0] op;
133134
} rvc_ciw_t;
134135

135-
function decompress_ciw(logic [15:0] compress);
136+
function automatic decompress_ciw(logic [15:0] compress);
136137
// only ADDI4SPN -> addi rd', x2, imm
137138
rvc_ciw_t ifmt = compress;
138139
// if imm = 0, it's the canonical illegal instruciton
139-
assert(ifmt.op == RVC_C0 && ifmt.funct3 == RVC_CIW_FUNC_ADDI4SPN && ifmt.nzuimm != 0);
140+
////assert(ifmt.op == RVC_C0 && ifmt.funct3 == RVC_CIW_FUNC_ADDI4SPN && ifmt.nzuimm != 0);
140141

141142
rv32i_types_pkg::itype_t ofmt;
142143
ofmt.imm11_00 = {2'b00, ifmt.nzuimm[10:7], ifmt.nzuimm[12:11], ifmt.nzuimm[5], ifmt.nzuimm[6], 2'b00};
@@ -166,10 +167,10 @@ package rv32c_pkg;
166167
// based on RV32/64/128. This assumes
167168
// RV32 *only* for now.
168169
rvc_cl_cs_t ifmt = compressed;
169-
assert(ifmt.op == RVC_C0
170-
&& ifmt.funct3 != 3'b000
171-
&& ifmt.funct3 != 3'b100
172-
&& ifmt.funct3[15] == 1'b0);
170+
//assert(ifmt.op == RVC_C0
171+
// && ifmt.funct3 != 3'b000
172+
// && ifmt.funct3 != 3'b100
173+
// && ifmt.funct3[15] == 1'b0);
173174

174175
rv32i_types_pkg::itype_t ofmt;
175176
ofmt.imm11_00 = (ifmt.funct3 == RVC_CL_FUNC_FLD)
@@ -196,10 +197,10 @@ package rv32c_pkg;
196197
// based on RV32/64/128. This assumes
197198
// RV32 *only* for now.
198199
rvc_cl_cs_t ifmt = compressed;
199-
assert(ifmt.op == RVC_C0
200-
&& ifmt.funct3 != 3'b000
201-
&& ifmt.funct3 != 3'b100
202-
&& ifmt.funct3[15] == 1'b1);
200+
//assert(ifmt.op == RVC_C0
201+
// && ifmt.funct3 != 3'b000
202+
// && ifmt.funct3 != 3'b100
203+
// && ifmt.funct3[15] == 1'b1);
203204

204205
rv32i_types_pkg::stype_t ofmt;
205206
logic [11:0] imm12 = (ifmt.funct3 == RVC_CS_FUNC_SD || ifmt.funct3 == RVC_CS_FUNC_FSD)
@@ -231,22 +232,22 @@ package rv32c_pkg;
231232

232233
function automatic logic [31:0] decompress_ci_load(logic [15:0] compressed);
233234
rvc_ci_t ifmt = compressed;
234-
assert(ifmt.op == RVC_C2);
235-
assert(ifmt.funct3 == RVC_CI_LWSP
236-
|| ifmt.funct3 == RVC_CI_FLWSP
237-
|| ifmt.funct3 == RVC_CI_FLDSP);
235+
//assert(ifmt.op == RVC_C2);
236+
//assert(ifmt.funct3 == RVC_CI_LWSP
237+
// || ifmt.funct3 == RVC_CI_FLWSP
238+
// || ifmt.funct3 == RVC_CI_FLDSP);
238239

239240
// lw -> lw rd, offset(x2)
240241
rv32i_types_pkg::itype_t ofmt;
241242
ofmt.imm11_00 = (ifmt.funct3 == RVC_CI_FUNC_LWSP || ifmt.funct3 == RVC_CI_FUNC_FLWSP)
242-
? {4'h0, ifmt.imm5[3:2], ifmt.imm1, ifmt.imm5[6:4], 2'b00};
243+
? {4'h0, ifmt.imm5[3:2], ifmt.imm1, ifmt.imm5[6:4], 2'b00}
243244
: {3'b000, ifmt.imm5[4:2], ifmt.imm1, ifmt.imm5[6:5], 3'b000};
244245
ofmt.rs1 = 5'd2;
245246
ofmt.funct3 = (ifmt.funct3 == RVC_CI_FUNC_LWSP || ifmt.funct3 == RVC_CI_FUNC_FLWSP)
246247
? rv32i_types_pkg::LW
247248
: 3'b011;
248249
ofmt.rd = ifmt.rd;
249-
ofmt.opcode = (ifmt.funct3 == RVC_CI_LWSP)
250+
ofmt.opcode = (ifmt.funct3 == RVC_CI_FUNC_LWSP)
250251
? rv32i_types_pkg::LOAD
251252
: 7'b000_0111;
252253
endfunction
@@ -271,35 +272,35 @@ package rv32c_pkg;
271272
// imm == 0 -> RESERVED
272273
// rd == x2 -> C.ADDI16SP
273274
// C.NOP -> nop (addi x0, x0, 0)
274-
assert((ifmt.op == RVC_C2 && ifmt.funct3 == RVC_CI_SLLI)
275-
|| ifmt.op == RVC_C1);
275+
//assert((ifmt.op == RVC_C2 && ifmt.funct3 == RVC_CI_SLLI)
276+
// || ifmt.op == RVC_C1);
276277

277-
if(ifmt.funct3 == RVC_CI_ADDI
278-
|| ifmt.funct3 == RVC_CI_NOP
279-
|| ifmt.funct3 == RVC_CI_LI) begin
278+
if(ifmt.funct3 == RVC_CI_FUNC_ADDI
279+
|| ifmt.funct3 == RVC_CI_FUNC_NOP
280+
|| ifmt.funct3 == RVC_CI_FUNC_LI) begin
280281
rv32i_types_pkg::itype_t ofmt;
281282
ofmt.imm11_00 = {6'h0, ofmt.imm1, ofmt.imm5};
282283
ofmt.funct3 = rv32i_types_pkg::ADDI;
283-
ofmt.rs1 = (ifmt.funct3 == RVC_CI_LI) ? 5'h0 : ifmt.rd;
284+
ofmt.rs1 = (ifmt.funct3 == RVC_CI_FUNC_LI) ? 5'h0 : ifmt.rd;
284285
ofmt.rd = ifmt.rd;
285286
ofmt.opcode = rv32i_types_pkg::IMMED;
286287

287288
return ofmt;
288-
end else if(ifmt.funct3 == RVC_CI_SLLI
289-
|| ifmt.funct3 == RVC_CI_SRLI
290-
|| ifmt.funct3 == RVC_CI_SRAI) begin
289+
end else if(ifmt.funct3 == RVC_CI_FUNC_SLLI
290+
|| ifmt.funct3 == RVC_CI_FUNC_SRLI
291+
|| ifmt.funct3 == RVC_CI_FUNC_SRAI) begin
291292
rv32i_types_pkg::itype_t ofmt;
292-
logic is_sra = (ifmt.funct3 == RVC_CI_SRAI) && ifmt.rd[5:4] == 2'b01;
293-
logic is_srl = (ifmt.funct3 == RVC_CI_SRLI) && ifmt.rd[5:4] == 2'b00;
294-
logic is_sll = (ifmt.funct3 == RVC_CI_SRLL) && ifmt.op == RVC_C2;
295-
assert(is_sra || is_srl || is_sll);
293+
logic is_sra = (ifmt.funct3 == RVC_CI_FUNC_SRAI) && ifmt.rd[5:4] == 2'b01;
294+
logic is_srl = (ifmt.funct3 == RVC_CI_FUNC_SRLI) && ifmt.rd[5:4] == 2'b00;
295+
logic is_sll = (ifmt.funct3 == RVC_CI_FUNC_SLLI) && ifmt.op == RVC_C2;
296+
//assert(is_sra || is_srl || is_sll);
296297
ofmt.imm11_00 = is_sra
297298
? {6'b01_0000, ifmt.imm1, ifmt.imm5}
298299
: {6'b00_0000, ifmt.imm1, ifmt.imm5};
299300
ofmt.rs1 = (is_sra || is_srl)
300301
? decompress_regselect(ifmt.rd[2:0])
301302
: ifmt.rd;
302-
ofmt.funct3 = (ifmt.funct3 == RVC_CI_SLLI)
303+
ofmt.funct3 = (ifmt.funct3 == RVC_CI_FUNC_SLLI)
303304
? rv32i_types_pkg::SLLI
304305
: rv32i_types_pkg::SRI;
305306
ofmt.rd = (is_sra || is_srl)
@@ -308,7 +309,7 @@ package rv32c_pkg;
308309
ofmt.opcode = rv32i_types_pkg::IMMED;
309310

310311
return ofmt;
311-
end else if(ifmt.funct3 == RVC_ADDI16SP
312+
end else if(ifmt.funct3 == RVC_CI_FUNC_ADDI16SP
312313
&& ifmt.rd == 5'd2) begin
313314
rv32i_types_pkg::itype_t ofmt;
314315
ofmt.imm11_00 = {2'b00, ifmt.imm1, ifmt.imm[4:3], ifmt.imm[5],
@@ -319,7 +320,7 @@ package rv32c_pkg;
319320
ofmt.opcode = rv32i_types_pkg::IMMED;
320321

321322
return ofmt;
322-
end else if(ifmt.funct3 == RVC_CI_LUI) begin
323+
end else if(ifmt.funct3 == RVC_CI_FUNC_LUI) begin
323324
rv32i_types_pkg::utype_t ofmt;
324325
ofmt.imm31_12 = {14'h0000, ifmt.imm1, ifmt.imm5};
325326
ofmt.rd = ifmt.rd;
@@ -340,15 +341,15 @@ package rv32c_pkg;
340341

341342
function automatic logic [31:0] decompress_css(logic [15:0] compressed);
342343
rvc_ci_t ifmt = compressed;
343-
assert(ifmt.op == RVC_C2);
344-
assert(ifmt.funct3 == RVC_CI_SWSP
345-
|| ifmt.funct3 == RVC_CI_FSWSP
346-
|| ifmt.funct3 == RVC_CI_FSDSP);
344+
//assert(ifmt.op == RVC_C2);
345+
//assert(ifmt.funct3 == RVC_CI_SWSP
346+
// || ifmt.funct3 == RVC_CI_FSWSP
347+
// || ifmt.funct3 == RVC_CI_FSDSP);
347348

348349
// sw -> sw rs2, offset(x2)
349350
rv32i_types_pkg::stype_t ofmt;
350351
logic [11:0] imm = (ifmt.funct3 == RVC_CI_FUNC_SWSP || ifmt.funct3 == RVC_CI_FUNC_FSWSP)
351-
? {4'h0, ifmt.imm[8:7], ifmt.imm[12:9], 2'b00};
352+
? {4'h0, ifmt.imm[8:7], ifmt.imm[12:9], 2'b00}
352353
: {3'b000, ifmt.imm[9:7], ifmt.imm[12:10], 3'b000};
353354
ofmt.imm11_05 = imm[11:5];
354355
ofmt.imm04_00 = imm[4:0];
@@ -373,8 +374,8 @@ package rv32c_pkg;
373374
function automatic logic [31:0] decompress_ca(logic [15:0] compressed);
374375
rvc_ca_t ifmt = compressed;
375376
logic [7:0] funct_ext = {ifmt.funct6, ifmt.funct2};
376-
assert(ifmt.op == RVC_C1);
377-
assert(ifmt.funct6[15:12] == 3'b100);
377+
//assert(ifmt.op == RVC_C1);
378+
//assert(ifmt.funct6[15:12] == 3'b100);
378379

379380
// C.AND, C.OR, C.XOR, C.SUB, C.ADDW, C.SUBW
380381
// -> OP rd', rd', rs2'
@@ -407,17 +408,17 @@ package rv32c_pkg;
407408

408409
function automatic logic [31:0] decompress_cb(logic [15:0] compressed);
409410
rvc_cb_t ifmt = compressed;
410-
assert(ifmt.op == RVC_C1);
411-
assert(ifmt.funct3 == RVC_CB_BEQZ
412-
|| ifmt.funct3 == RVC_CB_BNEZ
413-
|| (ifmt.funct3 == RVC_CB_ANDI && ifmt.funct2 == 2'b10));
411+
//assert(ifmt.op == RVC_C1);
412+
//assert(ifmt.funct3 == RVC_CB_BEQZ
413+
// || ifmt.funct3 == RVC_CB_BNEZ
414+
// || (ifmt.funct3 == RVC_CB_ANDI && ifmt.funct2 == 2'b10));
414415
if(ifmt.funct3 == RVC_CB_ANDI) begin
415416
// C.ANDI -> andi rd', rd', imm
416417
rv32i_types_pkg::itype_t ofmt;
417418
ofmt.imm11_00 = {6'h0, ifmt.imm1, ifmt.imm5};
418-
ofmt.rs1 = decode_regselect(ifmt.rd);
419+
ofmt.rs1 = decompress_regselect(ifmt.rd);
419420
ofmt.funct3 = rv32i_types_pkg::ANDI;
420-
ofmt.rd = decode_regselect(ifmt.rd);
421+
ofmt.rd = decompress_regselect(ifmt.rd);
421422
ofmt.opcode = rv32i_types_pkg::IMMED;
422423

423424
return ofmt;
@@ -432,7 +433,7 @@ package rv32c_pkg;
432433
ofmt.imm12 = imm[12];
433434
ofmt.imm10_05 = imm[10:5];
434435
ofmt.rs2 = 5'd0;
435-
ofmt.rs1 = decode_regselect(ifmt.rd);
436+
ofmt.rs1 = decompress_regselect(ifmt.rd);
436437
ofmt.funct3 = (ifmt.funct3 == RVC_CB_BEQZ) ? rv32i_types_pkg::BEQ : rv32i_types_pkg::BNE;
437438
ofmt.imm04_01 = imm[4:1];
438439
ofmt.imm11 = imm[11];
@@ -450,8 +451,8 @@ package rv32c_pkg;
450451

451452
function automatic logic [31:0] decompress_cj(logic [15:0] compressed);
452453
rvc_cj_t ifmt = compressed;
453-
assert(ifmt.op == RVC_C1);
454-
assert(ifmt.funct3 == RVC_CJ_J || ifmt.funct3 == RVC_CJ_JAL);
454+
//assert(ifmt.op == RVC_C1);
455+
//assert(ifmt.funct3 == RVC_CJ_J || ifmt.funct3 == RVC_CJ_JAL);
455456
rv32i_types_pkg::ujtype_t ofmt;
456457
ofmt.imm20 = 1'b0;
457458
ofmt.imm10_01 = {ifmt.imm[8], ifmt.imm[10:9], ifmt.imm[6], ifmt.imm[7], ifmt.imm[2], ifmt.imm[5:3]};
@@ -462,7 +463,4 @@ package rv32c_pkg;
462463

463464
return ofmt;
464465
endfunction
465-
466-
// MISSING: CI format (SRLI, SRAI, SLLI, LI, LUI, NOP)
467-
468466
endpackage

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