updated emulator to handle p-type instructions

Author: sexton34

gpu/assembler/assembler.py

@@ -21,11 +21,11 @@
 U_TYPE = {'auipc', 'lli', 'lmi', 'lui'}
 C_TYPE = {'csrr'}
 J_TYPE = {'jal'}
-P_TYPE = {'jpnz', 'prr', 'prw'}
+P_TYPE = {'jpnz', 'prsw', 'prlw'}
 H_TYPE = {'halt'}
 
 # Instructions without predication
-NO_PREDICATE = {'halt', 'prw', 'prr', 'jpnz', 'jal', 'jalr'}
+NO_PREDICATE = {'halt', 'jal', 'jalr'}
 
 
 def load_opcodes(opcode_file: str) -> Dict[str, str]:
@@ -272,7 +272,7 @@ def encode_instruction(self, addr: int, opcode: str, operands: List[str]) -> str
         elif opcode in J_TYPE:
             required_ops = 2  # rd, imm/label
         elif opcode in P_TYPE:
-            required_ops = 2  # rs1, rs2
+            required_ops = 3  # prd, rs2, imm
         elif opcode in H_TYPE:
             required_ops = 0  # no operands
         else:
@@ -402,13 +402,33 @@ def encode_instruction(self, addr: int, opcode: str, operands: List[str]) -> str
                    self.to_binary(imm, 17) + self.to_binary(rd, 6) + op_bits)
 
         elif opcode in P_TYPE:
-            # P-type: [end, start, pred, rs2[24:19], rs1[18:13], x[12:7], opcode[6:0]]
-            # Note: No predication for these instructions
-            rs1 = self.parse_register(operands[0])
-            rs2 = self.parse_register(operands[1])
+            # P-type: {end[31], start[30], p[29:25], rs2[24:19], imm[18:13], rd[12:7], opcode[6:0]}	
+            # prd, rs2, imm
+            if(opcode == 'prsw'): # prsw prs, rs2, imm
+                predicate = self.parse_predicate(operands[0])
+                rs2 = self.parse_register(operands[1])
+                imm = self.parse_immediate(operands[2])
+                rd = 0
+            elif(opcode == 'prlw'):
+                rd = self.parse_predicate(operands[0])
+                rs2 = self.parse_register(operands[1])
+                imm = self.parse_immediate(operands[2])
+                predicate = 0
+            elif(opcode == 'jpnz'):
+                predicate = self.parse_predicate(operands[0])
+                if operands[1] in self.labels:
+                    target = self.labels[operands[1]]
+                    imm = target - addr  # PC-relative offset
+                else:
+                    imm = self.parse_immediate(operands[1])
+                rs2 = 0
+                rd = 0
+            else:
+                raise ValueError(f"P-type opcode {opcode} found but implemented")
+            
             return (self.to_binary(end, 1) + self.to_binary(start, 1) + 
-                   '00000' + self.to_binary(rs2, 6) + 
-                   self.to_binary(rs1, 6) + '000000' + op_bits)
+                   self.to_binary(predicate, 5) + self.to_binary(rs2, 6) + 
+                   self.to_binary(imm, 6) + self.to_binary(rd, 6) + op_bits)
 
         elif opcode in H_TYPE:
             # H-type (HALT): [end=1, start=0, 1s[29:7], opcode[6:0]]

gpu/assembler/opcodes.txt

@@ -66,7 +66,7 @@ csrr    1011000
 jal     1100000
 
 jpnz    1101000
-prr     1101100
-prw     1101101
+prsw    1101100
+prlw    1101101
 
 halt    1111111

gpu/common/custom_enums.py

@@ -127,6 +127,9 @@ class J_Op(Op):
 # P-Type Operations (opcode: 1101xxx)
 class P_Op(Op):
     JPNZ = Bits(bin='000', length=3)   # 000
+    PRSW = Bits(bin='100', length=3)   # 100
+    PRLW = Bits(bin='101', length=3)   # 101
+
 
 # H-Type Operations (opcode: 1111xxx)
 class H_Op(Op):

gpu/emulator/src/emulator.py

@@ -79,7 +79,7 @@ def parse_args():
     mem = Mem(args.start_pc, str(args.input_file), args.mem_format)
 
     for block_id, warp_id in [(b, w) for b in range(args.num_blocks) for w in range(warps_per_block)]:
-        pfile = PredicateRegFile(thread_per_warp=32)
+        pfile = PredicateRegFile(threads_per_warp=32)
 
         rfiles = []
         states = []

gpu/emulator/src/instr.py

@@ -135,9 +135,6 @@ def decode(instruction: Bits, pc: Bits) -> 'Instr':
                 op = J_Op(funct3)
                 imm = pred + rs2 + rs1 #rs1 + rs2 + pred #concatenate
                 ret_instr = J_Instr(op=op, rd=rd, imm=imm, pc=pc)
-            case Instr_Type.P_TYPE:
-                # TODO: Create P-Type Instruction Class
-                raise NotImplementedError("P-Type instruction not implemented yet.")
             case Instr_Type.C_TYPE:
                 op = C_Op(funct3)
                 rs1 = rs1[0:5]
@@ -147,6 +144,10 @@ def decode(instruction: Bits, pc: Bits) -> 'Instr':
                 op = F_Op(funct3)
                 print(f"ftype, funct={op},imm={imm.int}")
                 ret_instr = F_Instr(op=op, rs1=rs1, rd=rd)
+            case Instr_Type.P_TYPE:
+                op = P_Op(funct3)
+                print(f"ptype, funct={op}, prd={rd}, rs2={rs2}, imm={rs1}")
+                ret_instr = P_Instr(op, prd=rd, rs2=rs2, imm=rs1, pc=pc)
             case Instr_Type.H_TYPE:
                 op=H_Op(funct3)
                 print(f"halt, funct={op}, {funct3}")
@@ -480,7 +481,7 @@ def eval(self, csr: CsrRegFile, state: State) -> Optional[int]:
         imm_val = self.imm.int  # Sign-extended immediate
 
         # Calculate address
-        addr = rdat1.int + imm_val
+        addr = rdat1.uint + imm_val
         match self.op:
             # Memory Write Operations
             case S_Op_0.SW: # Store Word (32 bits / 4 bytes)
@@ -645,11 +646,38 @@ def eval(self, csr: CsrRegFile, state: State) -> Optional[int]:
         return target_addr & 0xFFFFFFFE  # Ensure LSB is zero (word-aligned)
 
 class P_Instr(Instr):
-    def __init__(self, op: P_Op, rs1: Bits, rs2: Bits, pc: Bits, pred_reg_file: PredicateRegFile) -> None:
-        raise NotImplementedError(f"P-Type operation {self.op} not implemented yet or doesn't exist.")
+    def __init__(self, op: P_Op, prd: Bits, rs2: Bits, imm: Bits, pc: Bits) -> None:
+        super().__init__(op)
+        self.prd = prd[1:6]
+        self.rs2 = rs2
+        self.imm = imm
+        self.pc = pc # Program counter for JPNZ
 
     def eval(self, csr: CsrRegFile, state: State) -> bool:
-        raise NotImplementedError(f"P-Type operation {self.op} not implemented yet or doesn't exist.")
+        # Mark first thread in each warp
+        is_first_thread = True
+        if(csr.get_thread_id() % state.pfile.threads_per_warp):
+            is_first_thread = False
+
+        addr = state.rfile.read(self.rs2).uint + self.imm.int
+
+        match self.op:
+            # Jump Pred
+            case P_Op.JPNZ:
+                if(state.pfile.read(self.pred).uint != 0): # Has at least a predicate bit high
+                    return self.pc.int + self.imm.int
+                else: # No predicate is set, let pass
+                    return None
+
+            # Predicate Access
+            case P_Op.PRSW:
+                if(not is_first_thread): return None
+                state.memory.write(addr, state.pfile.read(self.pred), 4)
+            case P_Op.PRLW:
+                if(not is_first_thread): return None
+                state.pfile.write(self.prd, state.memory.read(addr, 4))
+
+        return None
 
 class H_Instr(Instr): #returns true
     def __init__(self, op: H_Op, funct3: Bits, r_pred: Bits = Bits(bin='11111', length=5)) -> None:

gpu/emulator/src/reg_file.py

@@ -24,32 +24,32 @@ def write(self, rd: Bits, val: Bits) -> None:
 
 
 class PredicateRegFile(RegFile):
-    def __init__(self, size: int=32, thread_per_warp: int=32) -> None:
-        self.thread_per_warp = thread_per_warp
-        super().__init__(num_regs=size, num_bits_per_reg=thread_per_warp, init_value=0)
-        self.write(Bits(uint=0, length=5), Bits(uint=(1 << thread_per_warp) - 1, length=thread_per_warp))  # set p0 to all ones
+    def __init__(self, size: int=32, threads_per_warp: int=32) -> None:
+        self.threads_per_warp = threads_per_warp
+        super().__init__(num_regs=size, num_bits_per_reg=threads_per_warp, init_value=0)
+        self.write(Bits(uint=0, length=5), Bits(uint=(1 << threads_per_warp) - 1, length=threads_per_warp))  # set p0 to all ones
 
     def read(self, rd: Bits) -> Bits:
         return self.arr[rd.uint]
 
     def read_thread(self, rd: Bits, thread_id: int) -> bool:
-        if(thread_id >= self.thread_per_warp):
+        if(thread_id >= self.threads_per_warp):
             # TODO: Remove this behavior after memory system better defined for non linear thread system
-            thread_id = thread_id % self.thread_per_warp
+            thread_id = thread_id % self.threads_per_warp
 
         reg_val = self.arr[rd.uint]
         return (reg_val.uint >> thread_id) & 0x1
 
     def write_thread(self, rd: Bits, thread_id: int, val: bool) -> None:
-        if(thread_id >= self.thread_per_warp):
+        if(thread_id >= self.threads_per_warp):
             # TODO: Remove this behavior after memory system better defined for non linear thread system
-            thread_id = thread_id % self.thread_per_warp
+            thread_id = thread_id % self.threads_per_warp
 
         reg_val = self.arr[rd.uint]
         if(val):
-            self.arr[rd.uint] = Bits(uint=(reg_val.uint | (1 << thread_id)), length=self.thread_per_warp)
+            self.arr[rd.uint] = Bits(uint=(reg_val.uint | (1 << thread_id)), length=self.threads_per_warp)
         else:
-            self.arr[rd.uint] = Bits(uint=(reg_val.uint & ~(1 << thread_id)), length=self.thread_per_warp)
+            self.arr[rd.uint] = Bits(uint=(reg_val.uint & ~(1 << thread_id)), length=self.threads_per_warp)
 
     def write(self, rd: Bits, val: Bits) -> None:
         self.arr[rd.uint] = val