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Better Documentation/Tutorials #19

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@xd009642

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@xd009642

So the examples are useful for somethings but say if I want to have nested if statements or make something that generates this verilog:

reg signed [width:0] x [0:width-1];
always @(posedge clock) begin
    x[0] <= 0
end

I've found myself doing a lot of trial and error, reading the source and scouring the existing examples trying to find something that would use these constructs (it's not always obvious from the example names).

Also, both these issues are still unresolved for me. I'm trying to write a coregen script to generate a cordic IP block.

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