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Better Documentation/Tutorials #19
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I've figured out the issues I currently had. One thing I've failed to figure out how to do is an expression like so: input wire signed [(12-1):0] i_xval;
...
wire signed [(15-1):0] e_xval;
assign e_xval = { {i_xval[(12-1)]}, i_xval, {(3-1){1'b0}} }; |
Hi, this would be something like this:
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That fixed my issue thanks! Is there any appetite for improving the veriloggen docs, and maybe having HTML docs hosted somewhere? Whenever I run into an issue I normally spend time going through tests and examples looking for anything that solves it and then going through the actual code which is less than ideal. |
I should prepare such documents ... |
I've not published any python projects myself that have required docs but pydoc should be able to generate docs from doc comments on classes and methods. It's just a case of doc comments for existing code |
@shtaxxx I am using Sphinx code generator together with readthedocs.io https://hwtlib.readthedocs.io/en/latest/?badge=latest I was relatively good and it usually works however you may have to fix some code style of doc in your code. Sphinx can also generate PDF/epub/... and readthedocs.io also supports any files. |
So the examples are useful for somethings but say if I want to have nested if statements or make something that generates this verilog:
I've found myself doing a lot of trial and error, reading the source and scouring the existing examples trying to find something that would use these constructs (it's not always obvious from the example names).
Also, both these issues are still unresolved for me. I'm trying to write a coregen script to generate a cordic IP block.
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