[Feature]: A Tablegen Description of AMD GPU Backend's ISA

[matinraayai]

Suggestion Description

It would be great to convert the XML ISA semantics available through the XML ISA Project to LLVM Tablegen format because the extra semantics information can complement the ISA description already present in the AMD GPU backend. In the tablegen format, the semantics can be expressed as a DAG of operations (similar to the LLVM instruction selection (ISEL) patterns in upstream LLVM) which can then be consumed by custom tablegen backends.

If successful, we would then like to then use the semantics written in tablegen to automatically generated C++ code that can translate LLVM Machine IR instructions from the AMDGPU backend to low-level LLVM IR instructions. This would have the following benefits for Luthier or any other compiler-based AMD GPU project:

1. It can raise the level of abstraction in Luthier's instrumentation API. For example, a tool writer can opt to inspect the IR view of the lifted code to instrument the target address of all load and store instructions without knowing the exact low-level memory instruction being used (e.g. a global load vs. a scratch load vs. buffer load, or DWORD granularity of the load instruction). Luthier can then use the metadata format we have been developing to correlate the instrumented IR instruction with the low-level MIR instruction it originated from, and perform instrumentation at the MIR level as it has done before.
2. It would make inferring all possible indirect jump and call targets much easier to handle, as LLVM MIR doesn't have any information regarding instruction semantics.
3. Raising to LLVM IR could potentially allow us to profile and optimize kernel code without having access to the source code of the kernel.

This is by no means a short-term project, but could be accelerated by converting the XML ISA semantics to tablegen via a script.

Thanks

Operating System

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GPU

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ROCm Component

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