Segfaults with 64bit addresses

[MintPaw]

I see that 64bit support was added pretty recently. I get a lot of nondeterministic segfaults when trying to use the backend.c by itself.

Randomly on these line:

pycachesim/cachesim/backend.c

Line 187 in 1741d35

self->placement[set_id*self->ways+i] = self->placement[set_id*self->ways+i-1];

pycachesim/cachesim/backend.c

Line 154 in 1741d35

if(self->placement[set_id*self->ways+i].invalid == 0 &&

In cases when it crashes set_id and cl_id are negative while the source addr is positive, I get the feeling that shouldn't be the case.

Cache__get_cacheline_id takes addr as a long long, shifts it to the right, then returns it as a long. This can result in a negative return value, is that ok?

pycachesim/cachesim/backend.c

Lines 109 to 111 in 1741d35

	inline static long Cache__get_cacheline_id(Cache* self, long long addr) {
	return addr >> self->cl_bits;
	}

[JanLJL]

Hi @MintPaw,

thanks for the issue!
From what I can see it looks like you are right and we have to take care of some type conversions or data types, respectively.
Could you provide some test cases or sample code snippets to reproduce the segfaults?