Currently a Write Allocate Miss leads to a LOAD on the same cache level. This in-turn produces a LOAD and MISS in the statics.
A better solution would be to produce a LOAD in the corresponding load_from cache and inject the cacheline into the current level.
Currently a Write Allocate Miss leads to a LOAD on the same cache level. This in-turn produces a LOAD and MISS in the statics.
A better solution would be to produce a LOAD in the corresponding load_from cache and inject the cacheline into the current level.