From 70e380114063944204f236b4f037b480e47077df Mon Sep 17 00:00:00 2001 From: "Tristan F.-R." Date: Mon, 20 Oct 2025 19:22:31 +0000 Subject: [PATCH 1/2] fix(rwr,strwr): directionality conversions --- spras/rwr.py | 7 ++++++- spras/strwr.py | 7 ++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/spras/rwr.py b/spras/rwr.py index 4717aa064..b51418703 100644 --- a/spras/rwr.py +++ b/spras/rwr.py @@ -4,7 +4,10 @@ from spras.containers import prepare_volume, run_container_and_log from spras.dataset import Dataset -from spras.interactome import reinsert_direction_col_directed +from spras.interactome import ( + convert_undirected_to_directed, + reinsert_direction_col_directed, +) from spras.prm import PRM from spras.util import add_rank_column, duplicate_edges, raw_pathway_df @@ -29,6 +32,8 @@ def generate_inputs(data, filename_map): # Get edge data for network file edges = data.get_interactome() + edges = convert_undirected_to_directed(edges) + edges.to_csv(filename_map['network'],sep='|',index=False,columns=['Interactor1','Interactor2'],header=False) @staticmethod diff --git a/spras/strwr.py b/spras/strwr.py index 65ea9f923..5e6b34783 100644 --- a/spras/strwr.py +++ b/spras/strwr.py @@ -2,7 +2,10 @@ from spras.containers import prepare_volume, run_container_and_log from spras.dataset import Dataset -from spras.interactome import reinsert_direction_col_directed +from spras.interactome import ( + convert_undirected_to_directed, + reinsert_direction_col_directed, +) from spras.prm import PRM from spras.util import add_rank_column, duplicate_edges, raw_pathway_df @@ -29,6 +32,8 @@ def generate_inputs(data, filename_map): # Get edge data for network file edges = data.get_interactome() + edges = convert_undirected_to_directed(edges) + edges.to_csv(filename_map['network'],sep='|',index=False,columns=['Interactor1','Interactor2'],header=False) @staticmethod From c52bbca17e602aeb8e7653fb34ada1828b349e6d Mon Sep 17 00:00:00 2001 From: "Tristan F.-R." Date: Mon, 20 Oct 2025 19:33:43 +0000 Subject: [PATCH 2/2] test(generate-inputs): fix rwr,strwr artifacts --- test/generate-inputs/expected/rwr-network-expected.txt | 2 ++ test/generate-inputs/expected/strwr-network-expected.txt | 2 ++ 2 files changed, 4 insertions(+) diff --git a/test/generate-inputs/expected/rwr-network-expected.txt b/test/generate-inputs/expected/rwr-network-expected.txt index cada50c96..721390f8c 100644 --- a/test/generate-inputs/expected/rwr-network-expected.txt +++ b/test/generate-inputs/expected/rwr-network-expected.txt @@ -1,2 +1,4 @@ test_A|B B|C +B|test_A +C|B diff --git a/test/generate-inputs/expected/strwr-network-expected.txt b/test/generate-inputs/expected/strwr-network-expected.txt index cada50c96..721390f8c 100644 --- a/test/generate-inputs/expected/strwr-network-expected.txt +++ b/test/generate-inputs/expected/strwr-network-expected.txt @@ -1,2 +1,4 @@ test_A|B B|C +B|test_A +C|B