adder & subtractor

Author: Sukhendu2002

4-BIT ADDER/4bitAdder.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity full_adder_4b is
+
+  port (
+    a,b : in std_logic_vector(3 downto 0);
+    s : out std_logic_vector(3 downto 0);
+    c : inout std_logic_vector(4 downto 1)
+    );
+ 
+end full_adder_4b;
+
+architecture beh of full_adder_4b is
+constant c0 : std_logic := '0';     
+begin  
+
+  s(0) <= a(0) xor b(0) xor c0;
+  c(1) <= (a(0) and b(0))or(b(0) and c0)or(a(0) and c0);
+  s(1) <= a(1) xor b(1) xor c(1);
+  c(2) <= (a(1) and b(1))or(b(1) and c(1))or(a(1) and c(1));
+  s(2) <= a(2) xor b(2) xor c(2);
+  c(3) <= (a(2) and b(2))or(b(2) and c(2))or(a(2) and c(2));
+  s(3) <= a(3) xor b(3) xor c(3);
+  c(4) <= (a(3) and b(3))or(b(3) and c(3))or(a(3) and c(3));
+
+end beh;

4-BIT ADDER/tb_4bitAdder.vhd

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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity full_adder_4b_tst is
+ 
+end full_adder_4b_tst;
+ architecture beh of full_adder_4b_tst is
+   component full_adder_4b
+       port (
+    a,b: in  std_logic_vector(3 downto 0);   
+     c :inout std_logic_vector(4 downto 1);  
+    s: out std_logic_vector(3 downto 0));  
+
+end component;
+    signal a_s,b_s : std_logic_vector(3 downto 0);  
+    signal s_s : std_logic_vector(3 downto 0); 
+    signal c_s : std_logic_vector(4 downto 1);
+ begin  
+
+u1 : full_adder_4b port map (
+  a => a_s,
+   b => b_s,
+   c => c_s,
+   s => s_s);
+
+tst_p: process
+   begin
+      a_s<="0000";
+       b_s<="0101";
+       wait for 100 ns;
+       a_s<="1100";
+       b_s<="0100";
+       wait for 100 ns;
+       a_s<="1111";
+       b_s<="0000";
+       wait for 100 ns;
+       a_s<="0010";
+       b_s<="1101";
+       wait for 100 ns;
+      end process;
+  end beh;

8-BIT ADDER/8bitAdder.vhd

@@ -0,0 +1,17 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+entity adder_8b is
+port (
+    a : in std_logic_vector(7 downto 0);
+    b : in std_logic_vector(7 downto 0);
+    c: out std_logic_vector(7 downto 0);
+);
+ 
+end adder_8b;
+
+architecture myarc of adder_8b is  
+begin  
+	c(7 downto 0) <= a(7 downto 0) + b(7 downto 0);
+end myarc;

8-BIT ADDER/tb_8bitAdder.vhd

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+
+entity tb_adder_8b is
+end tb_adder_8b;
+
+architecture myarc of tb_adder_8b is
+component adder_8b
+port (
+    a : in std_logic_vector(7 downto 0);
+    b : in std_logic_vector(7 downto 0);
+    c: out std_logic_vector(7 downto 0);
+);
+end adder_8b;
+
+signal a: std_logic_vector (7 downto 0) := (others => '0');
+signal b: std_logic_vector (7 downto 0) := (others => '0');
+signal c: std_logic_vector(7 downto 0);
+begin  
+
+uut: adder_8b PORT MAP(a=>a,b=>b,c=>c);
+tb: process
+begin
+	wait for 10 ns;
+    a<="00000000";
+    b<="01010101";
+    wait for 10 ns;
+    a<="00000001";
+	b<="00000011";
+	wait for 10 ns;
+  end process;
+  end myarc;

8-BIT SUBTRACTOR/8bitSubtractor.vhd

@@ -0,0 +1,17 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+entity subtractor_8b is
+port (
+    a : in std_logic_vector(7 downto 0);
+    b : in std_logic_vector(7 downto 0);
+    d: out std_logic_vector(7 downto 0);
+);
+ 
+end subtractor_8b;
+
+architecture myarc of subtractor_8b is  
+begin  
+	d(7 downto 0) <= a(7 downto 0) - b(7 downto 0);
+end myarc;

8-BIT SUBTRACTOR/tb_8bitSubtractor.vhd

@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+
+entity tb_subtractor_8b is
+end tb_subtractor_8b;
+
+architecture myarc of tb_subtractor_8b is
+component subtractor_8b
+port (
+    a : in std_logic_vector(7 downto 0);
+    b : in std_logic_vector(7 downto 0);
+    d: out std_logic_vector(7 downto 0);
+);
+end subtractor_8b;
+
+signal a: std_logic_vector (7 downto 0) := (others => '0');
+signal b: std_logic_vector (7 downto 0) := (others => '0');
+signal d: std_logic_vector(7 downto 0);
+begin  
+
+uut: subtractor_8b PORT MAP(a=>a,b=>b,d=>d);
+tb: process
+begin
+	wait for 10 ns;
+    a<="00000000";
+    b<="01010101";
+    wait for 10 ns;
+    a<="00000001";
+	b<="00000011";
+	wait for 10 ns;
+  end process;
+  end myarc;