Skip not present nodes when exporting in a standard that does not support them

Author: amykyta3

src/peakrdl_ipxact/__about__.py

@@ -1 +1 @@
-__version__ = "3.4.4"
+__version__ = "3.5.0"

src/peakrdl_ipxact/exporter.py

@@ -22,6 +22,12 @@ class Standard(enum.IntEnum):
     #: IP-XACT - IEEE Std. 1685-2014
     IEEE_1685_2014 = 2014
 
+    @property
+    def supports_isPresent(self) -> bool:
+        # Only 2014 supports ispresent
+        return self == Standard.IEEE_1685_2014
+
+
 #===============================================================================
 class IPXACTExporter:
     def __init__(self, **kwargs: Any) -> None:
@@ -65,6 +71,9 @@ def __init__(self, **kwargs: Any) -> None:
         else:
             self.ns = "spirit:"
 
+        # If standard supports isPresent tags, don't skip them
+        self.skip_not_present = not self.standard.supports_isPresent
+
     #---------------------------------------------------------------------------
     def export(self, node: Union[AddrmapNode, RootNode], path: str, **kwargs: Any) -> None:
         """
@@ -148,7 +157,7 @@ def export(self, node: Union[AddrmapNode, RootNode], path: str, **kwargs: Any) -
             addrblockable_children = 0
             non_addrblockable_children = 0
 
-            for child in node.children(skip_not_present=False):
+            for child in node.children(skip_not_present=self.skip_not_present):
                 if not isinstance(child, AddressableNode):
                     continue
 
@@ -172,7 +181,7 @@ def export(self, node: Union[AddrmapNode, RootNode], path: str, **kwargs: Any) -
             mmaps.appendChild(mmap)
 
             # Top-node's children become their own addressBlocks
-            for child in node.children(skip_not_present=False):
+            for child in node.children(skip_not_present=self.skip_not_present):
                 if not isinstance(child, AddressableNode):
                     continue
 
@@ -214,36 +223,34 @@ def add_nameGroup(self, parent: minidom.Element, name: str, displayName: Optiona
 
     #---------------------------------------------------------------------------
     def add_registerData(self, parent: minidom.Element, node: RegNode) -> None:
-        if self.standard == Standard.IEEE_1685_2014:
-            # registers and registerFiles can be interleaved
-            for child in node.children(skip_not_present=False):
+        if self.standard == Standard.IEEE_1685_2009:
+            # registers must all be listed before register files
+            for child in node.children(skip_not_present=self.skip_not_present):
                 if isinstance(child, RegNode):
                     self.add_register(parent, child)
-                elif isinstance(child, (AddrmapNode, RegfileNode)):
+
+            for child in node.children(skip_not_present=self.skip_not_present):
+                if isinstance(child, (AddrmapNode, RegfileNode)):
                     self.add_registerFile(parent, child)
                 elif isinstance(child, MemNode):
                     self.msg.warning(
                         "IP-XACT does not support 'mem' nodes that are nested in hierarchy. Discarding '%s'"
                         % child.get_path(),
                         child.inst.inst_src_ref
                     )
-        elif self.standard == Standard.IEEE_1685_2009:
-            # registers must all be listed before register files
-            for child in node.children(skip_not_present=False):
+        else:
+            # registers and registerFiles can be interleaved
+            for child in node.children(skip_not_present=self.skip_not_present):
                 if isinstance(child, RegNode):
                     self.add_register(parent, child)
-
-            for child in node.children(skip_not_present=False):
-                if isinstance(child, (AddrmapNode, RegfileNode)):
+                elif isinstance(child, (AddrmapNode, RegfileNode)):
                     self.add_registerFile(parent, child)
                 elif isinstance(child, MemNode):
                     self.msg.warning(
                         "IP-XACT does not support 'mem' nodes that are nested in hierarchy. Discarding '%s'"
                         % child.get_path(),
                         child.inst.inst_src_ref
                     )
-        else:
-            raise RuntimeError
 
     #---------------------------------------------------------------------------
     def hex_str(self, v: int) -> str:
@@ -275,7 +282,7 @@ def add_addressBlock(self, parent: minidom.Element, node: AddressableNode) -> No
             node.get_property("desc")
         )
 
-        if (self.standard >= Standard.IEEE_1685_2014) and not node.get_property("ispresent"):
+        if self.standard.supports_isPresent and not node.get_property("ispresent"):
             self.add_value(addressBlock, self.ns + "isPresent", "0")
 
         self.add_value(addressBlock, self.ns + "baseAddress", self.hex_str(node.absolute_address))
@@ -329,7 +336,7 @@ def add_registerFile(self, parent: minidom.Element, node: Union[RegfileNode, Add
             node.get_property("desc")
         )
 
-        if (self.standard >= Standard.IEEE_1685_2014) and not node.get_property("ispresent"):
+        if self.standard.supports_isPresent and not node.get_property("ispresent"):
             self.add_value(registerFile, self.ns + "isPresent", "0")
 
         if node.is_array:
@@ -367,7 +374,7 @@ def add_register(self, parent: minidom.Element, node: RegNode) -> None:
             node.get_property("desc")
         )
 
-        if (self.standard >= Standard.IEEE_1685_2014) and not node.get_property("ispresent"):
+        if self.standard.supports_isPresent and not node.get_property("ispresent"):
             self.add_value(register, self.ns + "isPresent", "0")
 
         if node.is_array:
@@ -396,7 +403,7 @@ def add_register(self, parent: minidom.Element, node: RegNode) -> None:
         if self.standard <= Standard.IEEE_1685_2009:
             reset = 0
             mask = 0
-            for field in node.fields(skip_not_present=False):
+            for field in node.fields(skip_not_present=self.skip_not_present):
                 field_reset = field.get_property("reset")
                 if isinstance(field_reset, int):
                     field_mask = ((1 << field.width) - 1) << field.lsb
@@ -410,7 +417,7 @@ def add_register(self, parent: minidom.Element, node: RegNode) -> None:
                 self.add_value(reset_el, self.ns + "value", self.hex_str(reset))
                 self.add_value(reset_el, self.ns + "mask", self.hex_str(mask))
 
-        for field in node.fields(skip_not_present=False):
+        for field in node.fields(skip_not_present=self.skip_not_present):
             self.add_field(register, field)
 
         # DNE: <spirit/ipxact:alternateRegisters> [...]
@@ -432,7 +439,7 @@ def add_field(self, parent: minidom.Element, node: FieldNode) -> None:
             node.get_property("desc")
         )
 
-        if (self.standard >= Standard.IEEE_1685_2014) and not node.get_property("ispresent"):
+        if self.standard.supports_isPresent and not node.get_property("ispresent"):
             self.add_value(field, self.ns + "isPresent", "0")
 
         self.add_value(field, self.ns + "bitOffset", "%d" % node.low)

tests/test_import_export.py

@@ -66,7 +66,7 @@ def test_nested_2009(self):
         self.symmetry_check(
             [
                 os.path.join(this_dir, "test_sources/accellera-generic_example.rdl"),
-                os.path.join(this_dir, "test_sources/nested.rdl")
+                os.path.join(this_dir, "test_sources/nested_allpresent.rdl")
             ],
             Standard.IEEE_1685_2009
         )

tests/test_sources/nested_allpresent.rdl

@@ -0,0 +1,37 @@
+
+addrmap nested {
+    name = "nested top-level";
+    desc = "This is a nested top-level block";
+
+    some_register_map srm1 @ 0x0;
+    some_register_map srm2 @ 0x2000;
+
+    addrmap {
+        some_register_map srma @ 0;
+        some_register_map srmb @ 0x2000;
+
+        reg {
+            name = "A register";
+            donttest = true;
+
+            field {
+                name = "untestable field";
+                donttest = true;
+            } f1;
+
+            field {} f2;
+
+            field {
+                onwrite = woclr;
+            } f3 = 0x1;
+
+        } reg1[2][3];
+    } wrapped_srm @ 0x4000;
+
+    external mem {
+        name = "A Memory";
+        desc = "This is a memory block";
+        memwidth = 32;
+        mementries = 128;
+    } mem1 @0x8000;
+};