Q5.a -2017-18 Dsd

Library ieee;
use ieee.std_logic_1164.all;

Entity of FSM is 
port(Clk,Reset,x: in Std_logic;
      y : out Std_logic);
end Fsm; 

Architecture Beh of FSM is 
Type State is (A,B,C,D);
Signal next_state : State;
begin
Process(Clk,Reset)
begin
if (Reset='1') then
next_state<= A;
elsif(Clk='1' and Clk'event) then

Case next_state is 
  when A=>
    if (x='0') then
      next_state<=A;
      y<=0;
    else
      next_state <=B;
      y<=0;
    end if;
    
  when  B=>
    if (x='0') then 
      next_state<=C;
      y<=0;
    else
      next_state<=D;
      y<=1;
    end if;
    
   when C=>
      if (x='0') then 
      next_state<=C;
      y<=0;
    else
      next_state<=D;
      y<=1;
    end if;
  
  when D=>
      if (x='0') then 
      next_state<=B;
      y<=0;
    else
      next_state<=A;
      y<=0;
    end if;
   
  when others=>
    null;
 end case;
 end if;
 end Process;
 end Beh;