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vga.syr
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Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
-->
Reading design: vga.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "vga.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "vga"
Output Format : NGC
Target Device : xc3s500e-5-fg320
---- Source Options
Top Module Name : vga
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "vgaPattern.v" in library work
Module <vga> compiled
No errors in compilation
Analysis of file <"vga.prj"> succeeded.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <vga> in library <work> with parameters.
HB = "00000000000000000000000001000000"
HD = "00000000000000000000001100100000"
HF = "00000000000000000000000000111000"
HR = "00000000000000000000000001111000"
VB = "00000000000000000000000000010111"
VD = "00000000000000000000001001011000"
VF = "00000000000000000000000000100101"
VR = "00000000000000000000000000000110"
h_end = "00000000000000000000010000010000"
sq_x_l = "00000000000000000000000000000000"
sq_x_r = "00000000000000000000001100100000"
sq_y_b = "00000000000000000000001001011000"
sq_y_t = "00000000000000000000000000000000"
v_end = "00000000000000000000001010011010"
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <vga>.
HB = 32'sb00000000000000000000000001000000
HD = 32'sb00000000000000000000001100100000
HF = 32'sb00000000000000000000000000111000
HR = 32'sb00000000000000000000000001111000
VB = 32'sb00000000000000000000000000010111
VD = 32'sb00000000000000000000001001011000
VF = 32'sb00000000000000000000000000100101
VR = 32'sb00000000000000000000000000000110
h_end = 32'sb00000000000000000000010000010000
sq_x_l = 32'sb00000000000000000000000000000000
sq_x_r = 32'sb00000000000000000000001100100000
sq_y_b = 32'sb00000000000000000000001001011000
sq_y_t = 32'sb00000000000000000000000000000000
v_end = 32'sb00000000000000000000001010011010
Module <vga> is correct for synthesis.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <vga>.
Related source file is "vgaPattern.v".
WARNING:Xst:646 - Signal <pixel_y> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <coloroutput<4:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Found 1-bit register for signal <video_on>.
Found 8-bit register for signal <coloroutput>.
Found 10-bit comparator greatequal for signal <coloroutput$cmp_ge0000> created at line 185.
Found 10-bit comparator greatequal for signal <coloroutput$cmp_ge0001> created at line 167.
Found 10-bit comparator greatequal for signal <coloroutput$cmp_ge0002> created at line 170.
Found 10-bit comparator greatequal for signal <coloroutput$cmp_ge0003> created at line 173.
Found 10-bit comparator greatequal for signal <coloroutput$cmp_ge0004> created at line 176.
Found 10-bit comparator greatequal for signal <coloroutput$cmp_ge0005> created at line 179.
Found 10-bit comparator greatequal for signal <coloroutput$cmp_ge0006> created at line 182.
Found 10-bit comparator less for signal <coloroutput$cmp_lt0000> created at line 185.
Found 10-bit comparator less for signal <coloroutput$cmp_lt0001> created at line 164.
Found 10-bit comparator less for signal <coloroutput$cmp_lt0002> created at line 167.
Found 10-bit comparator less for signal <coloroutput$cmp_lt0003> created at line 170.
Found 10-bit comparator less for signal <coloroutput$cmp_lt0004> created at line 173.
Found 10-bit comparator less for signal <coloroutput$cmp_lt0005> created at line 176.
Found 10-bit comparator less for signal <coloroutput$cmp_lt0006> created at line 179.
Found 10-bit comparator less for signal <coloroutput$cmp_lt0007> created at line 182.
Found 11-bit up counter for signal <h_count_next>.
Found 11-bit comparator less for signal <h_count_next$cmp_lt0000> created at line 79.
Found 11-bit register for signal <h_count_reg>.
Found 1-bit register for signal <h_sync_next>.
Found 11-bit comparator less for signal <h_sync_next$cmp_lt0000> created at line 97.
Found 1-bit register for signal <h_video_on>.
Found 11-bit comparator greatequal for signal <h_video_on$cmp_ge0000> created at line 121.
Found 11-bit comparator less for signal <h_video_on$cmp_lt0000> created at line 121.
Found 10-bit register for signal <pixel_x>.
Found 10-bit subtractor for signal <pixel_x$addsub0000> created at line 146.
Found 10-bit subtractor for signal <pixel_x$sub0000> created at line 146.
Found 11-bit up counter for signal <v_count_next>.
Found 11-bit comparator less for signal <v_count_next$cmp_lt0000> created at line 88.
Found 11-bit register for signal <v_count_reg>.
Found 1-bit register for signal <v_sync_next>.
Found 11-bit comparator less for signal <v_sync_next$cmp_lt0000> created at line 106.
Found 1-bit register for signal <v_video_on>.
Found 11-bit comparator greatequal for signal <v_video_on$cmp_ge0000> created at line 130.
Found 11-bit comparator less for signal <v_video_on$cmp_lt0000> created at line 130.
Summary:
inferred 2 Counter(s).
inferred 45 D-type flip-flop(s).
inferred 2 Adder/Subtractor(s).
inferred 23 Comparator(s).
Unit <vga> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 2
10-bit subtractor : 2
# Counters : 2
11-bit up counter : 2
# Registers : 9
1-bit register : 5
10-bit register : 1
11-bit register : 2
8-bit register : 1
# Comparators : 23
10-bit comparator greatequal : 7
10-bit comparator less : 8
11-bit comparator greatequal : 2
11-bit comparator less : 6
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
WARNING:Xst:2677 - Node <coloroutput_0> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <coloroutput_1> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <coloroutput_2> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <coloroutput_3> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <coloroutput_4> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <coloroutput_0> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <coloroutput_1> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <coloroutput_2> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <coloroutput_3> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <coloroutput_4> of sequential type is unconnected in block <vga>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 2
10-bit subtractor : 2
# Counters : 2
11-bit up counter : 2
# Registers : 40
Flip-Flops : 40
# Comparators : 23
10-bit comparator greatequal : 7
10-bit comparator less : 8
11-bit comparator greatequal : 2
11-bit comparator less : 6
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
INFO:Xst:2261 - The FF/Latch <coloroutput_5> in Unit <vga> is equivalent to the following 2 FFs/Latches, which will be removed : <coloroutput_6> <coloroutput_7>
WARNING:Xst:2677 - Node <h_count_reg_0> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <h_count_reg_1> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <pixel_x_0> of sequential type is unconnected in block <vga>.
WARNING:Xst:2677 - Node <pixel_x_1> of sequential type is unconnected in block <vga>.
Optimizing unit <vga> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block vga, actual ratio is 1.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 56
Flip-Flops : 56
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : vga.ngr
Top Level Output File Name : vga
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 8
Cell Usage :
# BELS : 163
# GND : 1
# INV : 13
# LUT1 : 28
# LUT2 : 17
# LUT2_L : 2
# LUT3 : 6
# LUT4 : 20
# LUT4_L : 5
# MUXCY : 46
# MUXF5 : 2
# VCC : 1
# XORCY : 22
# FlipFlops/Latches : 56
# FDC : 20
# FDR : 23
# FDRE : 11
# FDRS : 1
# FDRSE : 1
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 7
# IBUF : 1
# OBUF : 6
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-5
Number of Slices: 56 out of 4656 1%
Number of Slice Flip Flops: 56 out of 9312 0%
Number of 4 input LUTs: 91 out of 9312 0%
Number of IOs: 8
Number of bonded IOBs: 8 out of 232 3%
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP | 56 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
reset | IBUF | 20 |
-----------------------------------+------------------------+-------+
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 5.764ns (Maximum Frequency: 173.488MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 4.134ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 5.764ns (frequency: 173.488MHz)
Total number of paths / destination ports: 778 / 101
-------------------------------------------------------------------------
Delay: 5.764ns (Levels of Logic = 5)
Source: h_count_next_4 (FF)
Destination: v_count_next_0 (FF)
Source Clock: clk rising
Destination Clock: clk rising
Data Path: h_count_next_4 to v_count_next_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 3 0.514 0.603 h_count_next_4 (h_count_next_4)
LUT4:I0->O 1 0.612 0.000 Mcompar_h_count_next_cmp_lt0000_lut<1> (Mcompar_h_count_next_cmp_lt0000_lut<1>)
MUXCY:S->O 1 0.404 0.000 Mcompar_h_count_next_cmp_lt0000_cy<1> (Mcompar_h_count_next_cmp_lt0000_cy<1>)
MUXCY:CI->O 1 0.052 0.000 Mcompar_h_count_next_cmp_lt0000_cy<2> (Mcompar_h_count_next_cmp_lt0000_cy<2>)
MUXCY:CI->O 23 0.289 1.091 Mcompar_h_count_next_cmp_lt0000_cy<3> (Mcompar_h_count_next_cmp_lt0000_cy<3>)
LUT2:I1->O 11 0.612 0.793 v_count_next_and00001 (v_count_next_and0000)
FDRE:R 0.795 v_count_next_0
----------------------------------------
Total 5.764ns (3.277ns logic, 2.487ns route)
(56.9% logic, 43.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Offset: 4.134ns (Levels of Logic = 1)
Source: coloroutput_5 (FF)
Destination: blue (PAD)
Source Clock: clk rising
Data Path: coloroutput_5 to blue
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRSE:C->Q 3 0.514 0.451 coloroutput_5 (coloroutput_5)
OBUF:I->O 3.169 blue_OBUF (blue)
----------------------------------------
Total 4.134ns (3.683ns logic, 0.451ns route)
(89.1% logic, 10.9% route)
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 4.57 secs
-->
Total memory usage is 517480 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 16 ( 0 filtered)
Number of infos : 1 ( 0 filtered)