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| 1 | +.. _how-to-enable-ssc-for-dss: |
| 2 | + |
| 3 | +How to enable spread spectrum clocking for display subsystem |
| 4 | +============================================================ |
| 5 | + |
| 6 | +Introduction |
| 7 | +------------ |
| 8 | + |
| 9 | +Spread Spectrum Clocking (SSC) reduces electromagnetic interference (EMI). It modulates the clock frequency. SSC varies the frequency over time. This spreads energy across many frequencies. This reduces peak emissions. |
| 10 | + |
| 11 | +Digital clock signals are periodic and square-shaped. Most energy focuses at the center frequency and odd harmonics. SSC spreads this energy across a wider range. This reduces the peak amplitude. SSC adds jitter to the clock signal. The voltage amplitude stays unchanged. |
| 12 | + |
| 13 | +Display Subsystem (DSS) supports SSC configuration for its pixel clocks. You configure this through device tree properties. This helps you meet EMI compliance requirements. For DPI, DSS typically uses Phase-locked loop (PLL) 17. You can also use PLL 16 or PLL 18. |
| 14 | + |
| 15 | +This guide shows how to configure SSC for DSS pixel clocks on supported TI SoCs. |
| 16 | + |
| 17 | +.. important:: |
| 18 | + The pixel clock frequency for DPI from the DSS PLL must not exceed 165MHz. Center spread adds a 20% overshoot to the modulation depth. Account for this when you calculate the maximum frequency. |
| 19 | + |
| 20 | +Spread spectrum clocking configuration parameters |
| 21 | +------------------------------------------------- |
| 22 | + |
| 23 | +The ``assigned-clock-sscs`` device tree property is used to configure SSC and takes three parameters: |
| 24 | + |
| 25 | ++-----------------------+----------------------------------------------------------------+ |
| 26 | +| Parameter | Description | |
| 27 | ++=======================+================================================================+ |
| 28 | +|| Modulation Frequency || The frequency at which the spread spectrum modulation occurs | |
| 29 | +|| (Hz) || - Minimum: 32,000 Hz (32 kHz) | |
| 30 | +|| || - Maximum: Reference clock frequency / 200 | |
| 31 | +|| || - Typical values: 32 kHz to 120 kHz | |
| 32 | ++-----------------------+----------------------------------------------------------------+ |
| 33 | +|| Modulation Depth || The amount of frequency spread as a percentage | |
| 34 | +|| - Minimum: 10 (0.1%) || - Maximum: 310 (3.1%) | |
| 35 | +|| || - Adjustable in increments of 10 (0.1%) | |
| 36 | +|| || - Example: 50 = 0.5% spread | |
| 37 | +|| || - Units: 1/10,000 (for example, 50 represents 0.5%) | |
| 38 | ++-----------------------+----------------------------------------------------------------+ |
| 39 | +|| Spread Type || - 1: Center spread (frequency varies on both higher and lower | |
| 40 | +|| || frequencies than nominal) | |
| 41 | +|| || - 3: Down spread (frequency varies only lower than nominal) | |
| 42 | ++-----------------------+----------------------------------------------------------------+ |
| 43 | + |
| 44 | +**Modulation Profile** |
| 45 | + |
| 46 | +The modulation uses a triangular waveform. The Device Manager automatically configures the PLL hardware based on the modulation frequency specified in the device tree. |
| 47 | + |
| 48 | +.. note:: |
| 49 | + Down spread mode (value 3) is commonly used for display interfaces. It ensures the clock never exceeds the specified maximum frequency. This is important for meeting display timing specifications and avoiding over-clocking. |
| 50 | + |
| 51 | +.. note:: |
| 52 | + SSC is currently supported only on display PLL for these SoCs: AM62x, AM62Ax, AM62Dx, AM62Px. The display PLL is typically PLL17. You can also use PLL16 or PLL18 for DPI applications. |
| 53 | + |
| 54 | +.. note:: |
| 55 | + The Device Manager automatically converts the modulation depth values from the device tree to the appropriate hardware register values. |
| 56 | + |
| 57 | +Example 1: Basic SSC configuration (center spread) |
| 58 | +-------------------------------------------------- |
| 59 | + |
| 60 | +This example shows how to enable SSC for the DSS VP2 clock with the following parameters: |
| 61 | + |
| 62 | +- Modulation frequency: 100 kHz |
| 63 | +- Modulation depth: 10 (0.1%) |
| 64 | +- Spread type: Center spread (1) |
| 65 | + |
| 66 | +Add the following properties to the DSS node in your device tree file (for example, ``k3-am62p-j722s-common-main.dtsi``): |
| 67 | + |
| 68 | +.. code-block:: dts |
| 69 | +
|
| 70 | + &dss0 { |
| 71 | + assigned-clocks = <&k3_clks 186 2>; |
| 72 | + assigned-clock-sscs = <100000 10 1>; |
| 73 | + }; |
| 74 | +
|
| 75 | +In this example: |
| 76 | + |
| 77 | +- ``assigned-clocks``: Specifies the clock to configure (DSS VP2 clock, k3_clks 186 2) |
| 78 | +- ``assigned-clock-sscs``: Configures SSC with 100 kHz modulation, 0.1% depth, center spread mode (1) |
| 79 | + |
| 80 | +.. warning:: |
| 81 | + This example uses center spread mode (1). Center spread has a 20% overshoot on the modulation depth. For 0.1% nominal depth, the actual peak deviation is about 0.12%. |
| 82 | + |
| 83 | + When using center spread: |
| 84 | + |
| 85 | + 1. Ensure the display panel can handle the higher peak frequency |
| 86 | + 2. Verify the maximum frequency stays below 165MHz including the overshoot |
| 87 | + 3. Consider down spread mode (Example 2) to avoid exceeding the nominal frequency |
| 88 | + |
| 89 | +Example 2: SSC with down spread mode |
| 90 | +------------------------------------ |
| 91 | + |
| 92 | +This example demonstrates down spread mode, which we recommend for display interfaces to ensure the clock never exceeds the nominal frequency: |
| 93 | + |
| 94 | +- Modulation frequency: 33 kHz |
| 95 | +- Modulation depth: 50 (0.5%) |
| 96 | +- Spread type: Down spread (3) |
| 97 | + |
| 98 | +.. code-block:: dts |
| 99 | +
|
| 100 | + &dss0 { |
| 101 | + assigned-clocks = <&k3_clks 186 2>; |
| 102 | + assigned-clock-sscs = <33000 50 3>; |
| 103 | + }; |
| 104 | +
|
| 105 | +Example 3: Greater modulation depth |
| 106 | +----------------------------------- |
| 107 | + |
| 108 | +This example shows a configuration with greater modulation depth for better EMI reduction: |
| 109 | + |
| 110 | +- Modulation frequency: 50 kHz |
| 111 | +- Modulation depth: 250 (2.5%) |
| 112 | +- Spread type: Down spread (3) |
| 113 | + |
| 114 | +.. code-block:: dts |
| 115 | +
|
| 116 | + &dss0 { |
| 117 | + assigned-clocks = <&k3_clks 186 2>; |
| 118 | + assigned-clock-sscs = <50000 250 3>; |
| 119 | + }; |
| 120 | +
|
| 121 | +.. note:: |
| 122 | + Greater modulation depth provides better EMI reduction but increases clock jitter. Test with your specific display panel to ensure timing margins meet requirements. |
| 123 | + |
| 124 | +Troubleshooting |
| 125 | +--------------- |
| 126 | + |
| 127 | +Display artifacts |
| 128 | +^^^^^^^^^^^^^^^^^ |
| 129 | + |
| 130 | +If you observe display artifacts, flickering, or other visual anomalies after enabling SSC: |
| 131 | + |
| 132 | +1. Reduce the spread percentage to a smaller value (for example, try 0.1% or 10 in device tree) |
| 133 | +2. Try a different modulation frequency (typical range: 32-100 kHz) |
| 134 | +3. Switch from center spread to down spread mode if not already using it |
| 135 | +4. Consult your display panel data sheet for spread spectrum tolerance specifications |
| 136 | + |
| 137 | +Clock not found error |
| 138 | +^^^^^^^^^^^^^^^^^^^^^ |
| 139 | + |
| 140 | +If you experience errors during boot about clock assignment: |
| 141 | + |
| 142 | +1. Verify the clock ID is correct for your SoC (check the technical reference manual) |
| 143 | +2. Ensure the Device Manager supports SSC for the specified clock |
| 144 | +3. Check that the kernel version includes SSC support for the clock subsystem |
| 145 | + |
| 146 | +Requirements and limitations |
| 147 | +---------------------------- |
| 148 | + |
| 149 | +- Configure the display clock by using ``assigned-clocks`` and ``assigned-clock-sscs`` |
| 150 | + |
| 151 | +**Firmware capability** |
| 152 | + |
| 153 | +Check if your firmware supports SSC by using the capability flag: |
| 154 | + |
| 155 | +.. code-block:: console |
| 156 | +
|
| 157 | + # Check firmware capabilities (requires ti-sci driver) |
| 158 | + cat /sys/kernel/debug/ti-sci/fw_caps |
| 159 | +
|
| 160 | +Look for ``TISCI_MSG_FLAG_FW_CAP_CLOCK_SSC`` in the capabilities list. |
| 161 | + |
| 162 | +Best practices and recommendations |
| 163 | +---------------------------------- |
| 164 | + |
| 165 | +- Start with low modulation depth (0.1% to 0.5%) and increase only if needed to meet EMI requirements |
| 166 | +- Use down spread mode (3) for display interfaces to ensure the clock never exceeds the nominal frequency |
| 167 | +- If using center spread mode (1), account for 20% overshoot on the modulation depth |
| 168 | +- Test with your specific display panel to ensure timing margins meet requirements |
| 169 | + |
| 170 | +Important considerations |
| 171 | +------------------------ |
| 172 | + |
| 173 | +.. important:: |
| 174 | + |
| 175 | + - Configure SSC together with ``assigned-clocks`` to specify which clock receives the SSC settings |
| 176 | + - When you enable SSC, the instantaneous clock frequency deviates from the nominal rate |
| 177 | + - Always validate SSC parameters with the specific display panel you use. Some panels might have strict jitter requirements |
| 178 | + |
| 179 | +Customer responsibilities |
| 180 | +------------------------- |
| 181 | + |
| 182 | +.. warning:: |
| 183 | + |
| 184 | + **You assume all responsibility for the configuration and usage of spread-spectrum clocking.** You must: |
| 185 | + |
| 186 | + 1. Research the clock limitations associated with your selected display panel |
| 187 | + 2. Configure SSC to be compatible with that specific display panel |
| 188 | + 3. Verify that the SSC configuration does not cause any system-related issues for any operating condition |
| 189 | + 4. Work with the display panel vendor to resolve any issues caused by enabling SSC |
| 190 | + 5. Validate displays to have enough functional margin with the jitter introduced by spread spectrum modulation |
| 191 | + |
| 192 | + Some display panels have clocking limitations not in their data sheets. Work directly with the display panel manufacturer on any display-related issues from SSC. |
| 193 | + |
| 194 | +References |
| 195 | +---------- |
| 196 | + |
| 197 | +- `DSS Driver Documentation <../../Foundational_Components/Kernel/Kernel_Drivers/Display/DSS7.html>`__ |
| 198 | +- SoC Technical Reference Manual (TRM) |
| 199 | +- System Firmware Documentation - PM Clock API |
| 200 | +- Linux kernel device tree bindings: ``Documentation/devicetree/bindings/display/ti/`` |
| 201 | +- Linux kernel clock framework documentation: ``Documentation/driver-api/clk.rst`` |
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