feat: update project tt_um_dranoel06_SAP1 from dranoel06/tiny_tapeout_dranoel06

Commit: 57c746e473c71f12bf581bc66a642e8ce2ebfe6f
Workflow: https://github.com/dranoel06/tiny_tapeout_dranoel06/actions/runs/21988944131

Author: TinyTapeoutBot

projects/tt_um_dranoel06_SAP1/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout main b4a9e6c7",
+  "app": "Tiny Tapeout main 4d463827",
   "repo": "https://github.com/dranoel06/tiny_tapeout_dranoel06",
-  "commit": "f0b63ce1dcfa54e55e089ee5fb1b9627300e7b4e",
-  "workflow_url": "https://github.com/dranoel06/tiny_tapeout_dranoel06/actions/runs/21911395477",
+  "commit": "57c746e473c71f12bf581bc66a642e8ce2ebfe6f",
+  "workflow_url": "https://github.com/dranoel06/tiny_tapeout_dranoel06/actions/runs/21988944131",
   "project_id": 3579,
   "sort_id": 1770470327345
 }

projects/tt_um_dranoel06_SAP1/docs/info.md

@@ -9,11 +9,12 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-a secret code lets the letter L appear on the 7 seg display
+A programmable 8 Bit CPU based on the SAP-1 ARchitecture. The Core is turing complete so your only limit are the 16 Bytes of Memory :D
 
 ## How to test
 
-change the input combinations
+Programm by pulling reset low and 
+
 ## External hardware
 
 List external hardware used in your project (e.g. PMOD, LED display, etc), if any

projects/tt_um_dranoel06_SAP1/info.yaml

@@ -1,24 +1,25 @@
-# Tiny Tapeout project information (Wokwi project)
-project: 
-  wokwi_id:     0       # Set this to the ID of your Wokwi project (the number from the project's URL)
-  title:        "Programmable 8-Bit CPU"      # Project title
-  author:       "dranoel06"      # Your name
-  discord:      "test"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "Programmable 8 Bit CPU based in the SAP-1 Architecture"      # One line description of what your project does
+# Tiny Tapeout project information
+project:
+  title:        "Programmable 8-BIT CPU"      # Project title
+  author:       "Leonard Finthammer"      # Your name
+  discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
+  description:  "Programmable 8 Bit CPU based on the SAP-1 Architecture"      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     50000000       # Clock frequency in Hz (or 0 if not applicable)
 
+  # How many tiles your design occupies? A single tile is about 167x108 uM.
+  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
+  # Your top module name must start with "tt_um_". Make it unique by including your github username:
   top_module:  "tt_um_dranoel06_SAP1"
-  
+
+  # List your project's source files here.
+  # Source files must be in ./src and you must list each source file separately, one per line.
+  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
   source_files:
     - "cpu.v"
     - "tt_um_dranoel06_SAP1.v"
 
-  # How many tiles your design occupies? A single tile is about 167x108 uM.
-  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
-
-
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 # This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).
 pinout:

projects/tt_um_dranoel06_SAP1/stats/metrics.csv

@@ -3,78 +3,78 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,2232
+design__instance__count,2180
 design__instance__area,28941.5
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_fast_1p32V_m40C,0
 design__max_fanout_violation__count__corner:nom_fast_1p32V_m40C,1
 design__max_cap_violation__count__corner:nom_fast_1p32V_m40C,0
-power__internal__total,0.0008399419602937996
-power__switching__total,0.00018687680130824447
-power__leakage__total,6.134130785540037E-7
-power__total,0.0010274321539327502
-clock__skew__worst_hold__corner:nom_fast_1p32V_m40C,-0.2553991257437523
-clock__skew__worst_setup__corner:nom_fast_1p32V_m40C,0.25555103201339285
-timing__hold__ws__corner:nom_fast_1p32V_m40C,0.13637136250681262
-timing__setup__ws__corner:nom_fast_1p32V_m40C,14.229783976128427
+power__internal__total,0.0008425895357504487
+power__switching__total,0.00018543166515883058
+power__leakage__total,6.264600642680307E-7
+power__total,0.0010286476463079453
+clock__skew__worst_hold__corner:nom_fast_1p32V_m40C,-0.2559326989444776
+clock__skew__worst_setup__corner:nom_fast_1p32V_m40C,0.25509628464964523
+timing__hold__ws__corner:nom_fast_1p32V_m40C,0.15389984167108997
+timing__setup__ws__corner:nom_fast_1p32V_m40C,14.184392728527481
 timing__hold__tns__corner:nom_fast_1p32V_m40C,0.0
 timing__setup__tns__corner:nom_fast_1p32V_m40C,0.0
 timing__hold__wns__corner:nom_fast_1p32V_m40C,0
 timing__setup__wns__corner:nom_fast_1p32V_m40C,0.0
 timing__hold_vio__count__corner:nom_fast_1p32V_m40C,0
-timing__hold_r2r__ws__corner:nom_fast_1p32V_m40C,0.136371
+timing__hold_r2r__ws__corner:nom_fast_1p32V_m40C,0.153900
 timing__hold_r2r_vio__count__corner:nom_fast_1p32V_m40C,0
 timing__setup_vio__count__corner:nom_fast_1p32V_m40C,0
 timing__setup_r2r__ws__corner:nom_fast_1p32V_m40C,Infinity
 timing__setup_r2r_vio__count__corner:nom_fast_1p32V_m40C,0
 design__max_slew_violation__count__corner:nom_slow_1p08V_125C,0
 design__max_fanout_violation__count__corner:nom_slow_1p08V_125C,1
 design__max_cap_violation__count__corner:nom_slow_1p08V_125C,0
-clock__skew__worst_hold__corner:nom_slow_1p08V_125C,-0.2623345226412784
-clock__skew__worst_setup__corner:nom_slow_1p08V_125C,0.2623345226412784
-timing__hold__ws__corner:nom_slow_1p08V_125C,0.6684563647366956
-timing__setup__ws__corner:nom_slow_1p08V_125C,12.12157253325923
+clock__skew__worst_hold__corner:nom_slow_1p08V_125C,-0.25907562939377715
+clock__skew__worst_setup__corner:nom_slow_1p08V_125C,0.2595058963391394
+timing__hold__ws__corner:nom_slow_1p08V_125C,0.7115820356583662
+timing__setup__ws__corner:nom_slow_1p08V_125C,11.998431032777226
 timing__hold__tns__corner:nom_slow_1p08V_125C,0.0
 timing__setup__tns__corner:nom_slow_1p08V_125C,0.0
 timing__hold__wns__corner:nom_slow_1p08V_125C,0
 timing__setup__wns__corner:nom_slow_1p08V_125C,0.0
 timing__hold_vio__count__corner:nom_slow_1p08V_125C,0
-timing__hold_r2r__ws__corner:nom_slow_1p08V_125C,0.668456
+timing__hold_r2r__ws__corner:nom_slow_1p08V_125C,0.711582
 timing__hold_r2r_vio__count__corner:nom_slow_1p08V_125C,0
 timing__setup_vio__count__corner:nom_slow_1p08V_125C,0
 timing__setup_r2r__ws__corner:nom_slow_1p08V_125C,Infinity
 timing__setup_r2r_vio__count__corner:nom_slow_1p08V_125C,0
 design__max_slew_violation__count__corner:nom_typ_1p20V_25C,0
 design__max_fanout_violation__count__corner:nom_typ_1p20V_25C,1
 design__max_cap_violation__count__corner:nom_typ_1p20V_25C,0
-clock__skew__worst_hold__corner:nom_typ_1p20V_25C,-0.25806807421485856
-clock__skew__worst_setup__corner:nom_typ_1p20V_25C,0.25806807421485856
-timing__hold__ws__corner:nom_typ_1p20V_25C,0.32727921299396184
-timing__setup__ws__corner:nom_typ_1p20V_25C,13.47690353016515
+clock__skew__worst_hold__corner:nom_typ_1p20V_25C,-0.2562906348577399
+clock__skew__worst_setup__corner:nom_typ_1p20V_25C,0.2562233553405448
+timing__hold__ws__corner:nom_typ_1p20V_25C,0.36324250191430213
+timing__setup__ws__corner:nom_typ_1p20V_25C,13.378294406507505
 timing__hold__tns__corner:nom_typ_1p20V_25C,0.0
 timing__setup__tns__corner:nom_typ_1p20V_25C,0.0
 timing__hold__wns__corner:nom_typ_1p20V_25C,0
 timing__setup__wns__corner:nom_typ_1p20V_25C,0.0
 timing__hold_vio__count__corner:nom_typ_1p20V_25C,0
-timing__hold_r2r__ws__corner:nom_typ_1p20V_25C,0.327279
+timing__hold_r2r__ws__corner:nom_typ_1p20V_25C,0.363243
 timing__hold_r2r_vio__count__corner:nom_typ_1p20V_25C,0
 timing__setup_vio__count__corner:nom_typ_1p20V_25C,0
 timing__setup_r2r__ws__corner:nom_typ_1p20V_25C,Infinity
 timing__setup_r2r_vio__count__corner:nom_typ_1p20V_25C,0
 design__max_slew_violation__count,0
 design__max_fanout_violation__count,1
 design__max_cap_violation__count,0
-clock__skew__worst_hold,-0.2553991257437523
-clock__skew__worst_setup,0.25555103201339285
-timing__hold__ws,0.13637136250681262
-timing__setup__ws,12.12157253325923
+clock__skew__worst_hold,-0.2559326989444776
+clock__skew__worst_setup,0.25509628464964523
+timing__hold__ws,0.15389984167108997
+timing__setup__ws,11.998431032777226
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
 timing__setup__wns,0.0
 timing__hold_vio__count,0
-timing__hold_r2r__ws,0.136371
+timing__hold_r2r__ws,0.153900
 timing__hold_r2r_vio__count,0
 timing__setup_vio__count,0
 timing__setup_r2r__ws,inf
@@ -84,72 +84,74 @@ design__core__bbox,2.88 3.78 199.2 151.2
 design__io,45
 design__die__area,31318.4
 design__core__area,28941.5
-design__instance__count__stdcell,1312
-design__instance__area__stdcell,23218.9
+design__instance__count__stdcell,1292
+design__instance__area__stdcell,23082.8
 design__instance__count__macros,0
 design__instance__area__macros,0
 design__instance__count__padcells,0
 design__instance__area__padcells,0
 design__instance__count__cover,0
 design__instance__area__cover,0
-design__instance__utilization,0.802269
-design__instance__utilization__stdcell,0.802269
+design__instance__utilization,0.797568
+design__instance__utilization__stdcell,0.797568
 design__rows,39
 design__rows:CoreSite,39
 design__sites,15951
 design__sites:CoreSite,15951
-design__instance__count__class:inverter,31
-design__instance__area__class:inverter,175.997
-design__instance__count__class:sequential_cell,175
-design__instance__area__class:sequential_cell,8623.84
-design__instance__count__class:multi_input_combinational_cell,759
-design__instance__area__class:multi_input_combinational_cell,8340.8
+design__instance__count__class:inverter,23
+design__instance__area__class:inverter,130.637
+design__instance__count__class:sequential_cell,176
+design__instance__area__class:sequential_cell,8672.83
+design__instance__count__class:multi_input_combinational_cell,753
+design__instance__area__class:multi_input_combinational_cell,8311.77
 flow__warnings__count,1
 flow__errors__count,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count,0
-design__instance__count__class:timing_repair_buffer,282
-design__instance__area__class:timing_repair_buffer,4833.56
+design__instance__count__class:timing_repair_buffer,275
+design__instance__area__class:timing_repair_buffer,4724.7
 timing__drv__floating__nets,0
 timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,31799.1
+route__wirelength__estimated,32230.7
 design__violations,0
-design__instance__count__class:clock_buffer,50
-design__instance__area__class:clock_buffer,1163.03
-design__instance__count__class:clock_inverter,15
-design__instance__area__class:clock_inverter,81.648
+design__instance__count__class:clock_buffer,49
+design__instance__area__class:clock_buffer,1155.77
+design__instance__count__class:clock_inverter,16
+design__instance__area__class:clock_inverter,87.0912
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,200
-global_route__vias,8769
-global_route__wirelength,52838
+design__instance__count__hold_buffer,198
+global_route__vias,8538
+global_route__wirelength,52214
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
 antenna_diodes_count,0
-route__net,1315
+route__net,1295
 route__net__special,2
-route__drc_errors__iter:0,366
-route__wirelength__iter:0,34767
-route__drc_errors__iter:1,74
-route__wirelength__iter:1,34486
-route__drc_errors__iter:2,70
-route__wirelength__iter:2,34490
-route__drc_errors__iter:3,0
-route__wirelength__iter:3,34470
+route__drc_errors__iter:0,317
+route__wirelength__iter:0,35066
+route__drc_errors__iter:1,89
+route__wirelength__iter:1,34738
+route__drc_errors__iter:2,73
+route__wirelength__iter:2,34649
+route__drc_errors__iter:3,1
+route__wirelength__iter:3,34670
+route__drc_errors__iter:4,0
+route__wirelength__iter:4,34670
 route__drc_errors,0
-route__wirelength,34470
-route__vias,7574
-route__vias__singlecut,7574
+route__wirelength,34670
+route__vias,7395
+route__vias__singlecut,7395
 route__vias__multicut,0
 design__disconnected_pin__count,4
 design__critical_disconnected_pin__count,0
-route__wirelength__max,420.93
-design__instance__count__class:fill_cell,920
-design__instance__area__class:fill_cell,5722.62
+route__wirelength__max,398.635
+design__instance__count__class:fill_cell,888
+design__instance__area__class:fill_cell,5858.7
 timing__unannotated_net__count__corner:nom_fast_1p32V_m40C,20
 timing__unannotated_net_filtered__count__corner:nom_fast_1p32V_m40C,0
 timing__unannotated_net__count__corner:nom_slow_1p08V_125C,20
@@ -158,21 +160,21 @@ timing__unannotated_net__count__corner:nom_typ_1p20V_25C,20
 timing__unannotated_net_filtered__count__corner:nom_typ_1p20V_25C,0
 timing__unannotated_net__count,20
 timing__unannotated_net_filtered__count,0
-design_powergrid__voltage__worst__net:VPWR__corner:nom_typ_1p20V_25C,1.19972
+design_powergrid__voltage__worst__net:VPWR__corner:nom_typ_1p20V_25C,1.19968
 design_powergrid__drop__average__net:VPWR__corner:nom_typ_1p20V_25C,1.19985
-design_powergrid__drop__worst__net:VPWR__corner:nom_typ_1p20V_25C,0.000283322
-design_powergrid__voltage__worst__net:VGND__corner:nom_typ_1p20V_25C,0.000258937
-design_powergrid__drop__average__net:VGND__corner:nom_typ_1p20V_25C,0.000151768
-design_powergrid__drop__worst__net:VGND__corner:nom_typ_1p20V_25C,0.000258937
-design_powergrid__voltage__worst,0.000258937
-design_powergrid__voltage__worst__net:VPWR,1.19972
-design_powergrid__drop__worst,0.000283322
-design_powergrid__drop__worst__net:VPWR,0.000283322
-design_powergrid__voltage__worst__net:VGND,0.000258937
-design_powergrid__drop__worst__net:VGND,0.000258937
+design_powergrid__drop__worst__net:VPWR__corner:nom_typ_1p20V_25C,0.00032409
+design_powergrid__voltage__worst__net:VGND__corner:nom_typ_1p20V_25C,0.000382608
+design_powergrid__drop__average__net:VGND__corner:nom_typ_1p20V_25C,0.000153364
+design_powergrid__drop__worst__net:VGND__corner:nom_typ_1p20V_25C,0.000382608
+design_powergrid__voltage__worst,0.000382608
+design_powergrid__voltage__worst__net:VPWR,1.19968
+design_powergrid__drop__worst,0.000382608
+design_powergrid__drop__worst__net:VPWR,0.00032409
+design_powergrid__voltage__worst__net:VGND,0.000382608
+design_powergrid__drop__worst__net:VGND,0.000382608
 ir__voltage__worst,1.1999999999999999555910790149937383830547332763671875
 ir__drop__avg,0.0001540000000000000027720881146109377368702553212642669677734375
-ir__drop__worst,0.0002829999999999999941817374615737890053424052894115447998046875
+ir__drop__worst,0.0003240000000000000149845413854876596815302036702632904052734375
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0

projects/tt_um_dranoel06_SAP1/stats/synthesis-stats.txt

@@ -2,45 +2,44 @@
 
 === tt_um_dranoel06_SAP1 ===
 
-   Number of wires:                949
-   Number of wire bits:            984
-   Number of public wires:         171
-   Number of public wire bits:     206
+   Number of wires:                936
+   Number of wire bits:            971
+   Number of public wires:         172
+   Number of public wire bits:     207
    Number of ports:                  8
    Number of port bits:             43
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                965
-     sg13g2_a21o_1                  13
-     sg13g2_a21oi_1                 72
-     sg13g2_a221oi_1                 8
-     sg13g2_a22oi_1                 11
-     sg13g2_and2_1                   6
-     sg13g2_and3_1                   2
-     sg13g2_and4_1                   1
-     sg13g2_dfrbpq_1               175
-     sg13g2_inv_1                   31
-     sg13g2_mux2_1                 133
-     sg13g2_mux4_1                  13
-     sg13g2_nand2_1                 44
-     sg13g2_nand2b_1                14
-     sg13g2_nand3_1                 23
-     sg13g2_nand3b_1                 2
+   Number of cells:                952
+     sg13g2_a21o_1                   5
+     sg13g2_a21oi_1                 74
+     sg13g2_a221oi_1                11
+     sg13g2_a22oi_1                  4
+     sg13g2_and2_1                  10
+     sg13g2_and3_1                   3
+     sg13g2_dfrbpq_1               176
+     sg13g2_inv_1                   23
+     sg13g2_mux2_1                 140
+     sg13g2_mux4_1                  12
+     sg13g2_nand2_1                 57
+     sg13g2_nand2b_1                17
+     sg13g2_nand3_1                 13
+     sg13g2_nand3b_1                 1
      sg13g2_nand4_1                  2
-     sg13g2_nor2_1                  61
-     sg13g2_nor2b_1                 19
-     sg13g2_nor3_1                  12
-     sg13g2_nor4_1                   4
-     sg13g2_o21ai_1                 95
-     sg13g2_or2_1                   14
-     sg13g2_or3_1                    1
+     sg13g2_nor2_1                  43
+     sg13g2_nor2b_1                 20
+     sg13g2_nor3_1                  11
+     sg13g2_nor4_1                   2
+     sg13g2_o21ai_1                 99
+     sg13g2_or2_1                   11
+     sg13g2_or3_1                    4
      sg13g2_or4_1                    1
-     sg13g2_tiehi                  175
+     sg13g2_tiehi                  176
      sg13g2_tielo                   16
-     sg13g2_xnor2_1                 12
-     sg13g2_xor2_1                   5
+     sg13g2_xnor2_1                 13
+     sg13g2_xor2_1                   8
 
-   Chip area for module '\tt_um_dranoel06_SAP1': 16917.049800
-     of which used for sequential elements: 8573.040000 (50.68%)
+   Chip area for module '\tt_um_dranoel06_SAP1': 16908.242400
+     of which used for sequential elements: 8622.028800 (50.99%)