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| 1 | +# Clock speed test, Michael Bell |
| 2 | +# This test clocks the tt_um_test design at a high frequency |
| 3 | +# and checks the counter has incremented by the correct amount |
| 4 | + |
| 5 | +import machine |
| 6 | +import rp2 |
| 7 | +import time |
| 8 | + |
| 9 | +from ttboard.mode import RPMode |
| 10 | +from ttboard.demoboard import DemoBoard |
| 11 | + |
| 12 | +# PIO program to drive the clock. Put a value n and it clocks n+1 times |
| 13 | +# Reads 0 when done. |
| 14 | +@rp2.asm_pio(sideset_init=rp2.PIO.OUT_LOW, autopull=True, pull_thresh=32, autopush=True, push_thresh=32) |
| 15 | +def clock_prog(): |
| 16 | + out(x, 32) .side(0) |
| 17 | + label("clock_loop") |
| 18 | + irq(4) .side(1) |
| 19 | + jmp(x_dec, "clock_loop").side(0) |
| 20 | + irq(clear, 4) .side(0) |
| 21 | + in_(null, 32) .side(0) |
| 22 | + |
| 23 | +@rp2.asm_pio(autopush=True, push_thresh=32, in_shiftdir=rp2.PIO.SHIFT_RIGHT, fifo_join=rp2.PIO.JOIN_RX) |
| 24 | +def read_prog(): |
| 25 | + in_(pins, 2) |
| 26 | + |
| 27 | +# Select design, don't apply config so the PWM doesn't start. |
| 28 | +tt = DemoBoard(apply_user_config=False) |
| 29 | +tt.shuttle.tt_um_test.enable() |
| 30 | + |
| 31 | +# Setup the PIO clock driver |
| 32 | +sm = rp2.StateMachine(0, clock_prog, sideset_base=machine.Pin(0)) |
| 33 | +sm.exec("irq(clear, 4)") |
| 34 | +sm.active(1) |
| 35 | + |
| 36 | +# Setup the PIO counter read |
| 37 | +sm_rx = rp2.StateMachine(1, read_prog, in_base=machine.Pin(3)) |
| 38 | + |
| 39 | +# Setup read DMA |
| 40 | +dst_data = bytearray(8192) |
| 41 | +d = rp2.DMA() |
| 42 | + |
| 43 | +# Read using the SM1 RX DREQ |
| 44 | +c = d.pack_ctrl(inc_read=False, treq_sel=5) |
| 45 | + |
| 46 | +# Read from the SM1 RX FIFO |
| 47 | +d.config( |
| 48 | + read=0x5020_0024, |
| 49 | + write=dst_data, |
| 50 | + count=len(dst_data)//4, |
| 51 | + ctrl=c, |
| 52 | + trigger=False |
| 53 | +) |
| 54 | + |
| 55 | +def start_rx(): |
| 56 | + # Reset the SM |
| 57 | + sm_rx.active(0) |
| 58 | + while sm_rx.rx_fifo() > 0: sm_rx.get() |
| 59 | + sm_rx.restart() |
| 60 | + |
| 61 | + # Wait until out0 changes from its current value |
| 62 | + if machine.Pin(3).value(): |
| 63 | + sm_rx.exec("wait(0, pin, 0)") |
| 64 | + else: |
| 65 | + sm_rx.exec("wait(1, pin, 0)") |
| 66 | + |
| 67 | + # Re-activate SM, it will block until the wait command completes |
| 68 | + sm_rx.active(1) |
| 69 | + |
| 70 | + |
| 71 | +# Frequency for the RP2040, the design is clocked at half this frequency |
| 72 | +def run_test(freq): |
| 73 | + # Multiply requested project clock frequency by 2 to get RP2040 clock |
| 74 | + freq *= 2 |
| 75 | + |
| 76 | + if freq > 266_000_000: |
| 77 | + raise ValueError("Too high a frequency requested") |
| 78 | + |
| 79 | + machine.freq(freq) |
| 80 | + |
| 81 | + try: |
| 82 | + # Run 64 clocks |
| 83 | + print("Clock test... ", end ="") |
| 84 | + start_rx() |
| 85 | + sm.put(63) |
| 86 | + sm.get() |
| 87 | + print(f" done. Value now: {tt.output_byte}") |
| 88 | + |
| 89 | + # Print the values read back for inspection |
| 90 | + for j in range(4): |
| 91 | + readings = sm_rx.get() |
| 92 | + for i in range(16): |
| 93 | + val = (readings >> (i*2)) & 0x3 |
| 94 | + print(val, end = " ") |
| 95 | + print() |
| 96 | + sm_rx.active(0) |
| 97 | + |
| 98 | + total_errors = 0 |
| 99 | + |
| 100 | + for _ in range(10): |
| 101 | + last = tt.output_byte |
| 102 | + |
| 103 | + # Setup the read SM and DMA transfer into the verification buffer |
| 104 | + start_rx() |
| 105 | + d.config(write=dst_data, trigger=True) |
| 106 | + |
| 107 | + # Run clock for enough time to fill the buffer |
| 108 | + t = time.ticks_us() |
| 109 | + sm.put(1024*17) |
| 110 | + sm.get() |
| 111 | + t = time.ticks_us() - t |
| 112 | + print(f"Clocked for {t}us: ", end = "") |
| 113 | + |
| 114 | + # Print the first 16 values in the DMA'd buffer |
| 115 | + for j in range(0,4): |
| 116 | + readings = dst_data[j] |
| 117 | + for i in range(4): |
| 118 | + val = (readings >> (i*2)) & 0x3 |
| 119 | + print(val, end = " ") |
| 120 | + |
| 121 | + # Check the counter has incremented by 1, as we sent a |
| 122 | + # multiple of 256 clocks plus one more |
| 123 | + if tt.output_byte != (last + 1) & 0xFF: |
| 124 | + print("Error: ", end="") |
| 125 | + print(tt.output_byte) |
| 126 | + |
| 127 | + # Check the read data from the counter continuously increases |
| 128 | + def verify(count, expected_val, retry): |
| 129 | + errors = 0 |
| 130 | + |
| 131 | + for j in range(2,len(dst_data)): |
| 132 | + readings = dst_data[j] |
| 133 | + for i in range(4): |
| 134 | + val = (readings >> (i*2)) & 0x3 |
| 135 | + if count == 1 and val != expected_val: |
| 136 | + if retry: |
| 137 | + return -1 |
| 138 | + else: |
| 139 | + print(f"Error at {j}:{i} {val} should be {expected_val}") |
| 140 | + errors += 1 |
| 141 | + count += 1 |
| 142 | + if count == 2: |
| 143 | + expected_val = (expected_val + 1) & 0x3 |
| 144 | + count = 0 |
| 145 | + if errors > 10: break |
| 146 | + return errors |
| 147 | + |
| 148 | + expected_val = dst_data[2] & 0x3 |
| 149 | + errors = verify(1, expected_val, True) |
| 150 | + if errors == -1: |
| 151 | + expected_val = (dst_data[2] >> 2) & 0x3 |
| 152 | + errors = verify(0, expected_val, False) |
| 153 | + |
| 154 | + total_errors += errors |
| 155 | + if errors > 10: |
| 156 | + return total_errors |
| 157 | + |
| 158 | + finally: |
| 159 | + # Remove overclock |
| 160 | + if freq > 133_000_000: |
| 161 | + machine.freq(133_000_000) |
| 162 | + |
| 163 | + return total_errors |
| 164 | + |
| 165 | +if __name__ == "__main__": |
| 166 | + freq = 50_000_000 |
| 167 | + while True: |
| 168 | + print(f"\nRun at {freq/1000000}MHz project clock\n") |
| 169 | + errors = run_test(freq) |
| 170 | + if errors > 10: break |
| 171 | + freq += 1_000_000 |
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