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better handling and naming of POST
1 parent 1fb94cf commit db8db69

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2 files changed

+13
-8
lines changed

2 files changed

+13
-8
lines changed

src/main.py

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,7 @@ def test_neptune():
110110
# take a look at project user button state at startup
111111
# all this "raw" pin access should happen before the DemoBoard object
112112
# is instantiated
113-
run_post_tests = PowerOnSelfTest.both_project_buttons_held()
113+
run_post_tests = PowerOnSelfTest.dotest_buttons_held()
114114
# or get a dict with PowerOnSelfTest.read_all_pins()
115115

116116

@@ -120,12 +120,16 @@ def test_neptune():
120120
# during startup
121121
if run_post_tests:
122122
print('\n\nDoing startup test!')
123+
while PowerOnSelfTest.dotest_buttons_held():
124+
print("Waiting for button release...")
125+
time.sleep_ms(500)
123126

124127
post = PowerOnSelfTest(tt)
125128
if not post.test_bidirs():
126129
print('ERRORS encountered while running POST bidir test!')
127130
else:
128131
print('Startup test GOOD')
132+
tt.load_default_project()
129133
print('\n\n')
130134

131135
#tt.shuttle.tt_um_psychogenic_neptuneproportional.enable()

src/ttboard/boot/post.py

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -68,8 +68,8 @@ def read_pin(cls, pin:str) -> int:
6868

6969

7070
@classmethod
71-
def both_project_buttons_held(cls):
72-
return cls.read_pin('rp_projclk') # and not cls.read_pin('nprojectrst')
71+
def dotest_buttons_held(cls):
72+
return cls.read_pin('rp_projclk') # and not cls.read_pin('sdi_nprojectrst')
7373

7474
# could also check
7575

@@ -102,18 +102,20 @@ def test_bidirs(self) -> bool:
102102
@return: False on any failure, True otherwise
103103
'''
104104
# select the project from the shuttle
105-
update_delay_ms = 1
105+
update_delay_ms = 2
106106
auto_clock_freq = 1e3
107+
self.tt.mode = RPMode.ASIC_ON_BOARD # make sure we're controlling everything
108+
107109
self.tt.shuttle.tt_um_test.enable()
108110
curMode = self.tt.mode
109111
self.tt.mode = RPMode.ASIC_ON_BOARD # make sure we're controlling everything
110-
112+
self.tt.reset_project(False)
111113
self.tt.in0(0) # want this low
112114
self.tt.clock_project_PWM(auto_clock_freq) # clock it real good
113115

114116
log.info('POST: starting bidirection pins tests')
117+
self.tt.bidir_mode = [Pin.OUT] * 8
115118
for bp in self.tt.bidirs:
116-
bp.mode = Pin.OUT
117119
bp(0) # start low
118120

119121
errCount = 0
@@ -126,8 +128,7 @@ def test_bidirs(self) -> bool:
126128
errCount += 1
127129

128130
# reset everything
129-
for bp in self.tt.bidirs:
130-
bp.mode = Pin.IN
131+
self.tt.bidir_mode = [Pin.IN] * 8
131132

132133
self.tt.clock_project_stop()
133134
self.tt.mode = curMode

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