# New Features * More AXI4 Infrastructure components * [x] AXI4 Multiplexer * [x] AXI4 Demultiplexer * [x] AXI4Lite Demultiplexer # Planned (partially braking) Changes: * Rename branch `master` to `main`. * [x] Cleanup entity interfaces (`clk` → `Clock`, `rst` → `Reset`, ...). * [x] Cleanup in legacy PoC entities like FIFOs, OCRAMs, ... * [x] Review new entities for interface naming rules * [x] Move AXI4-Lite and AXI4-Stream modules into `PoC.bus` besides AXI4. * [ ] Style checks using [VSG - VHDL Style Guide](https://github.com/jeremiah-c-leary/vhdl-style-guide) applying PoC's VHDL coding style # Timing Constraints * [ ] Switch some Vivado timing constraints from `XDC` to `TCL`. # Tests * [x] More tests # Documentation * [ ] Review and rewrite of old documentation * [ ] More documentation ----- /cc @stefanunrein, @weilanad
New Features
Planned (partially braking) Changes:
mastertomain.clk→Clock,rst→Reset, ...).PoC.busbesides AXI4.Timing Constraints
XDCtoTCL.Tests
Documentation
/cc @stefanunrein, @weilanad