gt2n: extend backside PDN with BM1/BM2 mesh, add backside RC

BPR followpins on their own do not stitch the per-row vdd/vss rails
together, so the backside grid was a chain of disconnected horizontal
strips. Add a two-layer perpendicular mesh (BM1 vertical, BM2 horizontal)
plus BV0/BV1 connects, modeled on asap7's M5/M6 over M1/M2 followpin
pattern. Top of the standard-cell grid is now BM2.

Also adds resistance values for the backside cut layers (BV0..BV4) to
setRC.tcl so PSM's analyze_power_grid does not error out with PSM-0021
when the PG network includes backside vias. Calls out that every RC
value in this file is a placeholder, not silicon-calibrated.

Verified end-to-end on gt2n/gcd: 873s wall time, 0 DRC violations,
0 ANT violations.

Signed-off-by: Matthew Guthaus <mrg@ucsc.edu>

Author: mguthaus

flow/platforms/gt2n/pdn.tcl

@@ -9,7 +9,15 @@ global_connect
 ####################################
 set_voltage_domain -name {CORE} -power {vdd} -ground {vss}
 ####################################
-# standard cell grid (backside power: just BPR followpins for now)
+# standard cell grid (backside power: BPR followpins + BM1/BM2 mesh)
 ####################################
-define_pdn_grid -name {grid} -voltage_domains {CORE} -pins {BPR}
+define_pdn_grid -name {grid} -voltage_domains {CORE} -pins {BM2}
 add_pdn_stripe -grid {grid} -layer {BPR} -width {0.032} -pitch {0.144} -offset {0} -followpins
+# BM1 perpendicular to BPR; modest mesh density.
+add_pdn_stripe -grid {grid} -layer {BM1} -width {0.224} -spacing {0.112} \
+    -pitch {1.792} -offset {0.896}
+# BM2 perpendicular to BM1, wider for lower IR.
+add_pdn_stripe -grid {grid} -layer {BM2} -width {0.448} -spacing {0.112} \
+    -pitch {1.792} -offset {0.896}
+add_pdn_connect -grid {grid} -layers {BPR BM1}
+add_pdn_connect -grid {grid} -layers {BM1 BM2}

flow/platforms/gt2n/setRC.tcl

@@ -6,32 +6,46 @@
 # R per length is computed as (resistivity [uOhm.cm] * 0.01) / (thickness [um])
 # divided by the minimum wire width, giving ohm / um. Capacitance is a rough
 # guess (no PEX data shipped in the ICT for these layers).
+#
+# WARNING: ALL VALUES BELOW ARE FAKE / PLACEHOLDER.
+# They are dimensional estimates only and are not calibrated against
+# silicon or a vendor extraction model. Use them to exercise the flow
+# (timing closure, IR drop sweeps, routing congestion) but do NOT treat
+# any number derived from them as physically meaningful. Replace with
+# values from a real RCX / QRC model before drawing conclusions.
 
 # Front-side routing
-set_layer_rc -layer M0  -resistance 259    -capacitance 1.5e-4
-set_layer_rc -layer M1  -resistance 156    -capacitance 1.5e-4
-set_layer_rc -layer M2  -resistance 259    -capacitance 1.5e-4
-set_layer_rc -layer M3  -resistance 156    -capacitance 1.5e-4
-set_layer_rc -layer M4  -resistance  40    -capacitance 1.7e-4
-set_layer_rc -layer M5  -resistance  40    -capacitance 1.7e-4
-set_layer_rc -layer M6  -resistance   3.5  -capacitance 2.0e-4
-set_layer_rc -layer M7  -resistance   3.5  -capacitance 2.0e-4
-set_layer_rc -layer M8  -resistance   3.5  -capacitance 2.0e-4
-set_layer_rc -layer M9  -resistance   3.5  -capacitance 2.0e-4
-set_layer_rc -layer M10 -resistance   0.67 -capacitance 2.5e-4
+set_layer_rc -layer M0 -resistance 259 -capacitance 1.5e-4
+set_layer_rc -layer M1 -resistance 156 -capacitance 1.5e-4
+set_layer_rc -layer M2 -resistance 259 -capacitance 1.5e-4
+set_layer_rc -layer M3 -resistance 156 -capacitance 1.5e-4
+set_layer_rc -layer M4 -resistance 40 -capacitance 1.7e-4
+set_layer_rc -layer M5 -resistance 40 -capacitance 1.7e-4
+set_layer_rc -layer M6 -resistance 3.5 -capacitance 2.0e-4
+set_layer_rc -layer M7 -resistance 3.5 -capacitance 2.0e-4
+set_layer_rc -layer M8 -resistance 3.5 -capacitance 2.0e-4
+set_layer_rc -layer M9 -resistance 3.5 -capacitance 2.0e-4
+set_layer_rc -layer M10 -resistance 0.67 -capacitance 2.5e-4
 
-# Backside (no calibration data in ICT; estimate from layer dimensions)
-set_layer_rc -layer BPR -resistance  30    -capacitance 1.0e-4
-set_layer_rc -layer BM1 -resistance   5    -capacitance 1.5e-4
-set_layer_rc -layer BM2 -resistance   5    -capacitance 1.5e-4
+# Backside (fake values; ICT has no backside data, dimensions only)
+set_layer_rc -layer BPR -resistance 30 -capacitance 1.0e-4
+set_layer_rc -layer BM1 -resistance 5 -capacitance 1.5e-4
+set_layer_rc -layer BM2 -resistance 5 -capacitance 1.5e-4
 
-# Via resistances (rough)
+# Via resistances (fake; rough scaling vs. cut size)
 set_layer_rc -via V0 -resistance 10
 set_layer_rc -via V1 -resistance 10
 set_layer_rc -via V2 -resistance 8
 set_layer_rc -via V3 -resistance 8
 set_layer_rc -via V4 -resistance 5
 set_layer_rc -via V5 -resistance 5
 
+# Backside via resistances (fake; same scale as front-side V0..V4)
+set_layer_rc -via BV0 -resistance 10
+set_layer_rc -via BV1 -resistance 8
+set_layer_rc -via BV2 -resistance 8
+set_layer_rc -via BV3 -resistance 5
+set_layer_rc -via BV4 -resistance 5
+
 set_wire_rc -signal -layer M3
-set_wire_rc -clock  -layer M5
+set_wire_rc -clock -layer M5