Create a Verilog Syntetizable QUAD SPI slave interface

[SalmoF]

Minimum Specifications

• just single lane SPI device interface is needed
• Mode 0 or mode 3 operation is preferred
• 10MHz clock speed
• APB 32bit bus interfacing (also wishbone bus 32 bit)
• Verilog is preferred (for simplyfing a possible future tapeout)

Final Specifications

• QUAD SPI Dual Data Rate @ 50MHz / Single Data Rate @ 120MHz
• SPI @ 120MHz
• Configurable SPI mode (all 4)
• Selectability at syntetize time between AXI, APB & wishbone Bus
• Daisy Chaning in SPI mode

Starting point

The repo Verilog-SPI is a good starting point for what is required to achive minimum specifications