WIP VK MT DEBUGGER RUN MULTIPLE SIMULATION STEPS IN A JOB

Author: Zorro666

renderdoc/driver/shaders/spirv/spirv_debug.cpp

@@ -713,7 +713,6 @@ void ThreadState::JumpToLabel(Id target)
   {
     OpLoopMerge merge(it);
 
-    mergeBlock = merge.mergeBlock;
     SetConvergencePoint(merge.mergeBlock);
 
     it++;
@@ -786,7 +785,6 @@ void ThreadState::SkipIgnoredInstructions()
     {
       OpSelectionMerge merge(it);
 
-      mergeBlock = merge.mergeBlock;
       SetConvergencePoint(merge.mergeBlock);
 
       nextInstruction++;
@@ -797,7 +795,6 @@ void ThreadState::SkipIgnoredInstructions()
     {
       OpLoopMerge merge(it);
 
-      mergeBlock = merge.mergeBlock;
       SetConvergencePoint(merge.mergeBlock);
 
       nextInstruction++;
@@ -3359,6 +3356,7 @@ void ThreadState::StepNext(ShaderDebugState *state, const rdcarray<ThreadState>
 
           RDCASSERT(lane < workgroup.size(), lane, workgroup.size());
           ShaderVariable x = workgroup[lane].GetSrc(valueId);
+          RDCASSERTEQUAL(workgroup[lane].currentInstruction, currentInstruction);
 
           switch(opdata.op)
           {
@@ -4114,6 +4112,7 @@ void ThreadState::StepNext(ShaderDebugState *state, const rdcarray<ThreadState>
       }
       else
       {
+        // JAKE TODO: THIS MIGHT NOT BE CORRECT IF THE SetDst GETS DEFERRED
         if(hasReturnValueData)
           SetDst(call.result, returnValue);
         returnValue = ShaderVariable();
@@ -5309,6 +5308,99 @@ void ThreadState::QueueSampleGather(Op opcode, DebugAPIWrapper::TextureType texT
   SetStepNeedsGpuSampleGatherOp();
 }
 
+// The conditions where it is not safe to run another step are based on:
+// the current simulation state and the next instruction to simulate
+bool ThreadState::CanRunAnotherStep() const
+{
+  // Thread has finished
+  if(Finished())
+    return false;
+
+  // Current Simulated State that prevents running another step:
+  // Any control flow state changes i.e. branch, convergence point, function return
+  if(diverged)
+    return false;
+  if(!enteredPoints.empty())
+    return false;
+  if(convergenceInstruction != INVALID_EXECUTION_POINT)
+    return false;
+  if(functionReturnPoint != INVALID_EXECUTION_POINT)
+    return false;
+
+  // Any pending result i.e. pending GPU math operation, need to run on the device thread
+  if(IsPendingResultQueued())
+    return false;
+
+  // Next instructions that prevent running another step:
+  // any instruction that requires threads in the tangle to be in lockstep
+  ConstIter it = debugger.GetIterForInstruction(nextInstruction);
+  OpDecoder opdata(it);
+  switch(opdata.op)
+  {
+    // derivatives require threads in the tangle to be in lockstep
+    case Op::DPdx:
+    case Op::DPdy:
+    case Op::DPdxCoarse:
+    case Op::DPdyCoarse:
+    case Op::DPdxFine:
+    case Op::DPdyFine:
+    case Op::Fwidth:
+    case Op::FwidthCoarse:
+    case Op::FwidthFine: return false;
+    // subgroup ops require threads in the tangle to be in lockstep
+    case Op::GroupNonUniformBallotFindLSB:
+    case Op::GroupNonUniformBallotFindMSB:
+    case Op::GroupNonUniformInverseBallot:
+    case Op::GroupNonUniformBallotBitExtract:
+    case Op::GroupNonUniformBroadcastFirst:
+    case Op::SubgroupFirstInvocationKHR:
+    case Op::GroupNonUniformBroadcast:
+    case Op::GroupNonUniformShuffle:
+    case Op::GroupNonUniformShuffleXor:
+    case Op::GroupNonUniformShuffleUp:
+    case Op::GroupNonUniformShuffleDown:
+    case Op::SubgroupReadInvocationKHR:
+    case Op::GroupNonUniformRotateKHR:
+    case Op::GroupNonUniformQuadBroadcast:
+    case Op::GroupNonUniformQuadSwap:
+    case Op::GroupNonUniformQuadAllKHR:
+    case Op::GroupNonUniformQuadAnyKHR:
+    case Op::SubgroupAllKHR:
+    case Op::SubgroupAnyKHR:
+    case Op::SubgroupAllEqualKHR:
+    case Op::GroupNonUniformAll:
+    case Op::GroupNonUniformAny:
+    case Op::GroupNonUniformAllEqual:
+    case Op::GroupNonUniformIAdd:
+    case Op::GroupNonUniformFAdd:
+    case Op::GroupNonUniformIMul:
+    case Op::GroupNonUniformFMul:
+    case Op::GroupNonUniformSMin:
+    case Op::GroupNonUniformUMin:
+    case Op::GroupNonUniformFMin:
+    case Op::GroupNonUniformSMax:
+    case Op::GroupNonUniformUMax:
+    case Op::GroupNonUniformFMax:
+    case Op::GroupNonUniformBitwiseAnd:
+    case Op::GroupNonUniformBitwiseOr:
+    case Op::GroupNonUniformBitwiseXor:
+    case Op::GroupNonUniformLogicalAnd:
+    case Op::GroupNonUniformLogicalOr:
+    case Op::GroupNonUniformLogicalXor:
+    case Op::GroupNonUniformElect:
+    case Op::GroupNonUniformBallot:
+    case Op::SubgroupBallotKHR:
+    case Op::GroupNonUniformBallotBitCount: return false;
+    // Enter/Exit Functions in lockstep
+    case Op::FunctionCall:
+    case Op::Return:
+    case Op::ReturnValue: return false;
+    default: break;
+  }
+
+  return true;
+}
+
 };    // namespace rdcspv
 
 template <>

renderdoc/driver/shaders/spirv/spirv_debug.h

@@ -291,22 +291,18 @@ struct ThreadState
   };
   rdcarray<GSMIndex> gsmIndexes;
 
-  // the id of the merge block that the last branch targetted
-  Id mergeBlock;
-  uint32_t convergenceInstruction;
-  uint32_t functionReturnPoint;
+  bool IsDiverged() const { return diverged; };
+  const rdcarray<uint32_t> &GetEnteredPoints() const { return enteredPoints; }
+  uint32_t GetConvergenceInstruction() const { return convergenceInstruction; }
+  uint32_t GetFunctionReturnPoint() const { return functionReturnPoint; }
+
   ShaderVariable returnValue;
   bool hasReturnValueData;
   rdcarray<StackFrame *> callstack;
 
   // the list of IDs that are currently valid and live
   rdcarray<Id> live;
 
-  // true if executed an operation which could trigger divergence
-  bool diverged;
-  // list of potential convergence points that were entered in a single step (used for tracking thread convergence)
-  rdcarray<uint32_t> enteredPoints;
-
   std::map<Id, uint32_t> lastWrite;
 
   // quad ID (arbitrary, just used to find neighbours for derivatives)
@@ -399,6 +395,9 @@ struct ThreadState
     return queuedGpuSampleGatherOp;
   }
 
+  bool CanRunAnotherStep() const;
+
+  bool IsQueudedOrBeingSimulated() const { return beingSimulated || inQueue; }
   bool IsBeingSimulated() const { return beingSimulated; }
   void SetBeingSimulated(bool active) { beingSimulated = active; }
 
@@ -425,6 +424,16 @@ struct ThreadState
   void ExecuteMemoryBarrier(Id semanticsId);
   static bool WorkgroupIsDiverged(const rdcarray<ThreadState> &workgroup);
 
+  // Control Flow state variables
+  // true if executed an operation which could trigger divergence
+  bool diverged;
+  // list of potential convergence points that were entered in a single step (used for tracking thread convergence)
+  rdcarray<uint32_t> enteredPoints;
+  // the id of the merge block that the last branch targetted
+  uint32_t convergenceInstruction;
+  // the instruction after a function call is defined to be a convergence point
+  uint32_t functionReturnPoint;
+
   bool stepComplete = false;
   ShaderDebugState pendingDebugState;
   ShaderDebugState *m_State = NULL;
@@ -655,6 +664,7 @@ class Debugger : public Processor, public ShaderDebugger
   ShaderStage stage;
 
   int steps = 0;
+  int curActiveSteps = 0;
 
   /////////////////////////////////////////////////////////
   // parsed data
@@ -752,7 +762,8 @@ class Debugger : public Processor, public ShaderDebugger
   void ProcessQueuedDeviceThreadSteps();
 
   void QueueJob(uint32_t lane, rdcarray<ShaderDebugState> *ret, const rdcarray<bool> &activeMask);
-  void StepThread(uint32_t lane, rdcarray<ShaderDebugState> *ret, const rdcarray<bool> &activeMask);
+  void StepThread(uint32_t lane, bool runMultiple, rdcarray<ShaderDebugState> *ret,
+                  const rdcarray<bool> &activeMask);
   void InternalStepThread(uint32_t lane, rdcarray<ShaderDebugState> *ret,
                           const rdcarray<bool> &activeMask);