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Commit be7e672

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adam-mcdanieladam-mcdaniel
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removed extraneous C code
1 parent b98b3bd commit be7e672

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8 files changed

+306
-220
lines changed

8 files changed

+306
-220
lines changed

‎main.c

-220
This file was deleted.

‎out1.txt

+35
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1+
Configuration
2+
-------------
3+
buffers:
4+
eff addr: 2
5+
fp adds: 3
6+
fp muls: 3
7+
ints: 2
8+
reorder: 5
9+
10+
latencies:
11+
fp add: 2
12+
fp sub: 2
13+
fp mul: 5
14+
fp div: 10
15+
16+
17+
Pipeline Simulation
18+
-----------------------------------------------------------
19+
Memory Writes
20+
Instruction Issues Executes Read Result Commits
21+
--------------------- ------ -------- ------ ------ -------
22+
flw f6,32(x2):0 1 2 - 2 3 4 5
23+
flw f2,48(x3):4 2 3 - 3 4 5 6
24+
fmul.s f0,f2,f4 3 6 - 10 11 12
25+
fsub.s f8,f6,f2 4 6 - 7 8 13
26+
fdiv.s f10,f0,f6 5 12 - 21 22 23
27+
fadd.s f6,f8,f2 6 9 - 10 12 24
28+
29+
30+
Delays
31+
------
32+
reorder buffer delays: 0
33+
reservation station delays: 0
34+
data memory conflict delays: 0
35+
true dependence delays: 11

‎out2.txt

+91
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@@ -0,0 +1,91 @@
1+
Configuration
2+
-------------
3+
buffers:
4+
eff addr: 2
5+
fp adds: 3
6+
fp muls: 3
7+
ints: 2
8+
reorder: 5
9+
10+
latencies:
11+
fp add: 2
12+
fp sub: 2
13+
fp mul: 5
14+
fp div: 10
15+
16+
17+
Pipeline Simulation
18+
-----------------------------------------------------------
19+
Memory Writes
20+
Instruction Issues Executes Read Result Commits
21+
--------------------- ------ -------- ------ ------ -------
22+
add x1,x1,x2 1 2 - 2 3 4
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lw x2,34(x1):1 2 4 - 4 5 6 7
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lw x2,35(x1):2 3 4 - 4 6 7 8
25+
sw x2,36(x1):1 6 7 - 7 9
26+
sw x2,37(x1):1 7 8 - 8 10
27+
lw x2,38(x1):1 8 9 - 9 11 12 13
28+
sw x2,39(x1):1 9 10 - 10 14
29+
add x1,x1,x2 10 13 - 13 14 15
30+
lw x2,34(x1):1 11 15 - 15 16 17 18
31+
lw x2,35(x1):2 12 15 - 15 17 18 19
32+
sw x2,36(x1):1 17 18 - 18 20
33+
sw x2,37(x1):1 18 19 - 19 21
34+
lw x2,38(x1):1 19 20 - 20 22 23 24
35+
sw x2,39(x1):1 20 21 - 21 25
36+
lw x1,33(x1):0 22 23 - 23 24 25 26
37+
lw x2,34(x1):1 23 26 - 26 27 28 29
38+
add x1,x2,x4 24 29 - 29 30 31
39+
sub x2,x1,x4 25 31 - 31 32 33
40+
bne x1,x2,Lstr 30 33 - 33 34
41+
add x3,x2,x4 32 33 - 33 34 35
42+
sub x4,x1,x4 34 35 - 35 36 37
43+
beq x3,x4,Lstr 35 37 - 37 38
44+
sw x3,39(x1):4 36 37 - 37 39
45+
sw x4,40(x1):4 37 38 - 38 40
46+
flw f0,41(x1):5 38 39 - 39 41 42 43
47+
fadd.s f6,f8,f0 39 43 - 44 45 46
48+
fsw f6,41(x1):5 40 41 - 41 47
49+
fmul.s f0,f2,f4 41 42 - 46 47 48
50+
fsw f2,32(x2):0 42 43 - 43 49
51+
flw f2,32(x2):0 43 44 - 44 50 51 52
52+
fdiv.s f0,f0,f6 46 48 - 57 58 59
53+
fadd.s f6,f8,f2 47 52 - 53 54 60
54+
fmul.s f0,f4,f6 48 55 - 59 60 61
55+
fsub.s f8,f6,f2 49 55 - 56 57 62
56+
fadd.s f10,f0,f6 52 61 - 62 63 64
57+
fadd.s f2,f4,f6 59 60 - 61 62 65
58+
fadd.s f2,f0,f5 60 61 - 62 64 66
59+
fsub.s f8,f1,f2 62 65 - 66 67 68
60+
flw f2,32(x2):0 63 64 - 64 65 66 69
61+
fmul.s f0,f2,f4 64 67 - 71 72 73
62+
fsw f0,32(x2):0 65 66 - 66 74
63+
flw f0,32(x1):1 66 67 - 67 68 69 75
64+
fadd.s f6,f8,f2 68 69 - 70 71 76
65+
fsw f3,33(x1):2 69 70 - 70 77
66+
flw f2,32(x2):3 73 74 - 74 75 76 78
67+
fdiv.s f0,f0,f6 74 75 - 84 85 86
68+
fadd.s f6,f8,f2 75 77 - 78 79 87
69+
flw f0,32(x2):0 76 77 - 77 78 80 88
70+
fadd.s f4,f0,f2 77 81 - 82 83 89
71+
fsw f4,32(x1):2 78 79 - 79 90
72+
flw f0,32(x1):3 86 87 - 87 88 89 91
73+
fadd.s f4,f0,f2 87 90 - 91 92 93
74+
fsw f4,32(x1):4 88 89 - 89 94
75+
flw f0,32(x1):5 89 90 - 90 91 93 95
76+
fadd.s f4,f0,f2 90 94 - 95 96 97
77+
fmul.s f0,f4,f6 91 97 -101 102 103
78+
fsub.s f8,f6,f2 93 94 - 95 97 104
79+
fadd.s f10,f0,f6 94 103 -104 105 106
80+
fadd.s f2,f4,f6 96 97 - 98 99 107
81+
fadd.s f2,f0,f5 97 103 -104 106 108
82+
fsub.s f8,f1,f2 103 107 -108 109 110
83+
flw f2,32(x2):0 104 105 -105 106 107 111
84+
85+
86+
Delays
87+
------
88+
reorder buffer delays: 27
89+
reservation station delays: 15
90+
data memory conflict delays: 7
91+
true dependence delays: 86

‎test.txt

98.2 KB
Binary file not shown.

‎test1.txt

+28
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,28 @@
1+
Configuration
2+
-------------
3+
buffers:
4+
eff addr: 2
5+
fp adds: 3
6+
fp muls: 3
7+
ints: 2
8+
reorder: 5
9+
10+
latencies:
11+
fp add: 2
12+
fp sub: 2
13+
fp mul: 5
14+
fp div: 10
15+
16+
17+
Pipeline Simulation
18+
-----------------------------------------------------------
19+
Memory Writes
20+
Instruction Issues Executes Read Result Commits
21+
--------------------- ------ -------- ------ ------ -------
22+
flw f6,32(x2):0 1 2 - 2 3 4 5
23+
flw f2,48(x3):4 2 3 - 3 4 5 6
24+
fmul.s f0,f2,f4 3 6 - 10 11 12
25+
fsub.s f8,f6,f2 4 6 - 7 8 13
26+
fdiv.s f10,f0,f6 5 12 - 21 22 23
27+
fadd.s f6,f8,f2 6 9 - 10 12 24
28+

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