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alexforencichalexforencich
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Enable overtemp shutdown in constraints files
Signed-off-by: Alex Forencich <[email protected]>
1 parent f4a8561 commit 5d349c9

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19 files changed

+47
-28
lines changed

19 files changed

+47
-28
lines changed

‎example/AU200/fpga_25g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
1212
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
1313
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
1414
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
15+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1516

1617
set_operating_conditions -design_power_budget 160
1718

‎example/AU250/fpga_25g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
1212
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
1313
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
1414
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
15+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1516

1617
set_operating_conditions -design_power_budget 160
1718

‎example/AU280/fpga_25g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
1313
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
1414
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
1515
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
16+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1617

1718
set_operating_conditions -design_power_budget 160
1819

‎example/AU50/fpga_25g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
1313
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
1414
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
1515
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
16+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1617

1718
set_operating_conditions -design_power_budget 63
1819

‎example/Arty/fpga/fpga.xdc

+6-5
Original file line numberDiff line numberDiff line change
@@ -2,11 +2,12 @@
22
# part: xc7a35t-csg324-1
33

44
# General configuration
5-
set_property CFGBVS VCCO [current_design]
6-
set_property CONFIG_VOLTAGE 3.3 [current_design]
7-
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
8-
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
9-
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
5+
set_property CFGBVS VCCO [current_design]
6+
set_property CONFIG_VOLTAGE 3.3 [current_design]
7+
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
8+
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
9+
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
10+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1011

1112
# 100 MHz clock
1213
set_property -dict {LOC E3 IOSTANDARD LVCMOS33} [get_ports clk]

‎example/ExaNIC_X10/fpga/fpga.xdc

+8-7
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,14 @@
22
# part: xcku035-fbva676-2-e
33

44
# General configuration
5-
set_property CFGBVS GND [current_design]
6-
set_property CONFIG_VOLTAGE 1.8 [current_design]
7-
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
8-
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
9-
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
10-
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design]
11-
set_property CONFIG_MODE BPI16 [current_design]
5+
set_property CFGBVS GND [current_design]
6+
set_property CONFIG_VOLTAGE 1.8 [current_design]
7+
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
8+
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
9+
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
10+
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type2 [current_design]
11+
set_property CONFIG_MODE BPI16 [current_design]
12+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1213

1314
# 100 MHz system clock
1415
set_property -dict {LOC D18 IOSTANDARD LVDS} [get_ports clk_100mhz_p]

‎example/HTG9200/fpga_25g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
99
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
1010
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
1111
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
12+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1213

1314
# System clocks
1415
# DDR4 clocks from U5 (200 MHz)

‎example/HTG9200/fpga_fmc_htg_6qsfp_25g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
99
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
1010
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
1111
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
12+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1213

1314
# System clocks
1415
# DDR4 clocks from U5 (200 MHz)

‎example/KC705/fpga_gmii/fpga.xdc

+4-3
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,10 @@
22
# part: xc7k325tffg900-2
33

44
# General configuration
5-
set_property CFGBVS VCCO [current_design]
6-
set_property CONFIG_VOLTAGE 2.5 [current_design]
7-
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
5+
set_property CFGBVS VCCO [current_design]
6+
set_property CONFIG_VOLTAGE 2.5 [current_design]
7+
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
8+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
89

910
# System clocks
1011
# 200 MHz

‎example/KC705/fpga_rgmii/fpga.xdc

+4-3
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,10 @@
22
# part: xc7k325tffg900-2
33

44
# General configuration
5-
set_property CFGBVS VCCO [current_design]
6-
set_property CONFIG_VOLTAGE 2.5 [current_design]
7-
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
5+
set_property CFGBVS VCCO [current_design]
6+
set_property CONFIG_VOLTAGE 2.5 [current_design]
7+
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
8+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
89

910
# System clocks
1011
# 200 MHz

‎example/KC705/fpga_sgmii/fpga.xdc

+4-3
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,10 @@
22
# part: xc7k325tffg900-2
33

44
# General configuration
5-
set_property CFGBVS VCCO [current_design]
6-
set_property CONFIG_VOLTAGE 2.5 [current_design]
7-
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
5+
set_property CFGBVS VCCO [current_design]
6+
set_property CONFIG_VOLTAGE 2.5 [current_design]
7+
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
8+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
89

910
# System clocks
1011
# 200 MHz

‎example/NetFPGA_SUME/fpga/fpga.xdc

+5-4
Original file line numberDiff line numberDiff line change
@@ -2,10 +2,11 @@
22
# part: xc7vx690tffg1761-3
33

44
# General configuration
5-
set_property CFGBVS GND [current_design]
6-
set_property CONFIG_VOLTAGE 1.8 [current_design]
7-
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
8-
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
5+
set_property CFGBVS GND [current_design]
6+
set_property CONFIG_VOLTAGE 1.8 [current_design]
7+
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
8+
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
9+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
910

1011
# 200 MHz system clock
1112
set_property -dict {LOC H19 IOSTANDARD LVDS} [get_ports clk_200mhz_p]

‎example/NexysVideo/fpga/fpga.xdc

+4-3
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,10 @@
22
# part: xc7a200tsbg484-1
33

44
# General configuration
5-
set_property CFGBVS VCCO [current_design]
6-
set_property CONFIG_VOLTAGE 3.3 [current_design]
7-
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
5+
set_property CFGBVS VCCO [current_design]
6+
set_property CONFIG_VOLTAGE 3.3 [current_design]
7+
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
8+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
89

910
# 100 MHz clock
1011
set_property -dict {LOC R4 IOSTANDARD LVCMOS33} [get_ports clk]

‎example/VCU108/fpga_10g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
88
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
99
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
1010
set_property CONFIG_MODE BPI16 [current_design]
11+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1112

1213
# System clocks
1314
# 300 MHz

‎example/VCU108/fpga_1g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
88
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
99
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
1010
set_property CONFIG_MODE BPI16 [current_design]
11+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1112

1213
# System clocks
1314
# 300 MHz

‎example/VCU118/fpga_1g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
99
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
1010
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
1111
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
12+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1213

1314
# System clocks
1415
# 300 MHz

‎example/VCU118/fpga_25g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
99
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
1010
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
1111
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
12+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1213

1314
# System clocks
1415
# 300 MHz

‎example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
99
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
1010
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
1111
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
12+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1213

1314
# System clocks
1415
# 300 MHz

‎example/VCU1525/fpga_25g/fpga.xdc

+1
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@ set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
1212
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
1313
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
1414
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
15+
set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
1516

1617
# System clocks
1718
# 300 MHz (DDR 0)

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