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Add ptp_td_rel2tod module for timestamp reconstruction
Signed-off-by: Alex Forencich <[email protected]>
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‎rtl/ptp_td_rel2tod.v

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/*
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Copyright (c) 2024 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1fs
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`default_nettype none
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/*
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* PTP time distribution ToD timestamp reconstruction module
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*/
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module ptp_td_rel2tod #
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(
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parameter TS_FNS_W = 16,
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parameter TS_REL_NS_W = 32,
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parameter TS_TOD_S_W = 48,
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parameter TS_REL_W = TS_REL_NS_W + TS_FNS_W,
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parameter TS_TOD_W = TS_TOD_S_W + 32 + TS_FNS_W,
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parameter TS_TAG_W = 8,
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parameter TD_SDI_PIPELINE = 2
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)
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(
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input wire clk,
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input wire rst,
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/*
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* PTP clock interface
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*/
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input wire ptp_clk,
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input wire ptp_rst,
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input wire ptp_td_sdi,
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/*
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* Timestamp conversion
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*/
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input wire [TS_REL_W-1:0] input_ts_rel,
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input wire [TS_TAG_W-1:0] input_ts_tag,
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input wire input_ts_valid,
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output wire [TS_TOD_W-1:0] output_ts_tod,
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output wire [TS_TAG_W-1:0] output_ts_tag,
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output wire output_ts_valid
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);
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localparam TS_TOD_NS_W = 30;
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localparam TS_NS_W = TS_TOD_NS_W+1;
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localparam [30:0] NS_PER_S = 31'd1_000_000_000;
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// pipeline to facilitate long input path
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wire ptp_td_sdi_pipe[0:TD_SDI_PIPELINE];
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assign ptp_td_sdi_pipe[0] = ptp_td_sdi;
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generate
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genvar n;
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for (n = 0; n < TD_SDI_PIPELINE; n = n + 1) begin : pipe_stage
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(* shreg_extract = "no" *)
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reg ptp_td_sdi_reg = 0;
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assign ptp_td_sdi_pipe[n+1] = ptp_td_sdi_reg;
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always @(posedge ptp_clk) begin
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ptp_td_sdi_reg <= ptp_td_sdi_pipe[n];
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end
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end
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endgenerate
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// deserialize data
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reg [15:0] td_shift_reg = 0;
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reg [4:0] bit_cnt_reg = 0;
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reg td_valid_reg = 1'b0;
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reg [3:0] td_index_reg = 0;
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reg [3:0] td_msg_reg = 0;
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reg [15:0] td_tdata_reg = 0;
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reg td_tvalid_reg = 1'b0;
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reg td_tlast_reg = 1'b0;
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reg [7:0] td_tid_reg = 0;
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reg td_sync_reg = 1'b0;
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always @(posedge ptp_clk) begin
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td_shift_reg <= {ptp_td_sdi_pipe[TD_SDI_PIPELINE], td_shift_reg[15:1]};
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td_tvalid_reg <= 1'b0;
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if (bit_cnt_reg) begin
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bit_cnt_reg <= bit_cnt_reg - 1;
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end else begin
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td_valid_reg <= 1'b0;
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if (td_valid_reg) begin
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td_tdata_reg <= td_shift_reg;
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td_tvalid_reg <= 1'b1;
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td_tlast_reg <= ptp_td_sdi_pipe[TD_SDI_PIPELINE];
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td_tid_reg <= {td_msg_reg, td_index_reg};
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if (td_index_reg == 0) begin
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td_msg_reg <= td_shift_reg[3:0];
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td_tid_reg[7:4] <= td_shift_reg[3:0];
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end
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td_index_reg <= td_index_reg + 1;
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td_sync_reg = !td_sync_reg;
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end
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if (ptp_td_sdi_pipe[TD_SDI_PIPELINE] == 0) begin
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bit_cnt_reg <= 16;
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td_valid_reg <= 1'b1;
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end else begin
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td_index_reg <= 0;
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end
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end
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if (ptp_rst) begin
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bit_cnt_reg <= 0;
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td_valid_reg <= 1'b0;
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td_tvalid_reg <= 1'b0;
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end
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end
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// sync TD data
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reg [15:0] dst_td_tdata_reg = 0;
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reg dst_td_tvalid_reg = 1'b0;
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reg [7:0] dst_td_tid_reg = 0;
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(* shreg_extract = "no" *)
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reg td_sync_sync1_reg = 1'b0;
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(* shreg_extract = "no" *)
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reg td_sync_sync2_reg = 1'b0;
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(* shreg_extract = "no" *)
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reg td_sync_sync3_reg = 1'b0;
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always @(posedge clk) begin
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td_sync_sync1_reg <= td_sync_reg;
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td_sync_sync2_reg <= td_sync_sync1_reg;
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td_sync_sync3_reg <= td_sync_sync2_reg;
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end
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always @(posedge clk) begin
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dst_td_tvalid_reg <= 1'b0;
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if (td_sync_sync3_reg ^ td_sync_sync2_reg) begin
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dst_td_tdata_reg <= td_tdata_reg;
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dst_td_tvalid_reg <= 1'b1;
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dst_td_tid_reg <= td_tid_reg;
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end
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if (rst) begin
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dst_td_tvalid_reg <= 1'b0;
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end
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end
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reg ts_sel_reg = 0;
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reg [47:0] ts_tod_s_0_reg = 0;
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reg [31:0] ts_tod_offset_ns_0_reg = 0;
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reg [47:0] ts_tod_s_1_reg = 0;
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reg [31:0] ts_tod_offset_ns_1_reg = 0;
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reg [TS_TOD_S_W-1:0] output_ts_tod_s_reg = 0, output_ts_tod_s_next;
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reg [TS_TOD_NS_W-1:0] output_ts_tod_ns_reg = 0, output_ts_tod_ns_next;
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reg [TS_FNS_W-1:0] output_ts_fns_reg = 0, output_ts_fns_next;
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reg [TS_TAG_W-1:0] output_ts_tag_reg = 0, output_ts_tag_next;
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reg output_ts_valid_reg = 0, output_ts_valid_next;
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reg [TS_NS_W-1:0] ts_tod_ns_0;
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reg [TS_NS_W-1:0] ts_tod_ns_1;
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assign output_ts_tod = {output_ts_tod_s_reg, 2'b00, output_ts_tod_ns_reg, output_ts_fns_reg};
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assign output_ts_tag = output_ts_tag_reg;
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assign output_ts_valid = output_ts_valid_reg;
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always @* begin
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// reconstruct timestamp
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// apply both offsets
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ts_tod_ns_0 = (input_ts_rel >> TS_FNS_W) + ts_tod_offset_ns_0_reg;
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ts_tod_ns_1 = (input_ts_rel >> TS_FNS_W) + ts_tod_offset_ns_1_reg;
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// pick the correct result
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// 2 MSB clear = lower half of range (0-536,870,911)
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// 1 MSB clear = upper half of range, but could also be over 1 billion (536,870,912-1,073,741,823)
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// 1 MSB set = overflow or underflow
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// prefer 2 MSB clear over 1 MSB clear if neither result was overflow or underflow
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if (ts_tod_ns_0[30:29] == 0 || (ts_tod_ns_0[30] == 0 && ts_tod_ns_1[30:29] != 0)) begin
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output_ts_tod_s_next = ts_tod_s_0_reg;
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output_ts_tod_ns_next = ts_tod_ns_0;
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end else begin
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output_ts_tod_s_next = ts_tod_s_1_reg;
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output_ts_tod_ns_next = ts_tod_ns_1;
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end
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output_ts_fns_next = input_ts_rel;
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output_ts_tag_next = input_ts_tag;
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output_ts_valid_next = input_ts_valid;
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end
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always @(posedge clk) begin
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// extract data
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if (dst_td_tvalid_reg) begin
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if (dst_td_tid_reg[3:0] == 4'd0) begin
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ts_sel_reg <= dst_td_tdata_reg[9];
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end
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// current
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if (dst_td_tid_reg == {4'd1, 4'd1}) begin
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if (ts_sel_reg) begin
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ts_tod_offset_ns_1_reg[15:0] <= dst_td_tdata_reg;
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end else begin
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ts_tod_offset_ns_0_reg[15:0] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd1, 4'd2}) begin
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if (ts_sel_reg) begin
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ts_tod_offset_ns_1_reg[31:16] <= dst_td_tdata_reg;
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end else begin
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ts_tod_offset_ns_0_reg[31:16] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd0, 4'd3}) begin
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if (ts_sel_reg) begin
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ts_tod_s_1_reg[15:0] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_0_reg[15:0] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd0, 4'd4}) begin
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if (ts_sel_reg) begin
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ts_tod_s_1_reg[31:16] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_0_reg[31:16] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd0, 4'd5}) begin
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if (ts_sel_reg) begin
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ts_tod_s_1_reg[47:32] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_0_reg[47:32] <= dst_td_tdata_reg;
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end
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end
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// alternate
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if (dst_td_tid_reg == {4'd2, 4'd1}) begin
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if (ts_sel_reg) begin
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ts_tod_offset_ns_0_reg[15:0] <= dst_td_tdata_reg;
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end else begin
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ts_tod_offset_ns_1_reg[15:0] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd2, 4'd2}) begin
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if (ts_sel_reg) begin
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ts_tod_offset_ns_0_reg[31:16] <= dst_td_tdata_reg;
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end else begin
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ts_tod_offset_ns_1_reg[31:16] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd2, 4'd3}) begin
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if (ts_sel_reg) begin
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ts_tod_s_0_reg[15:0] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_1_reg[15:0] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd2, 4'd4}) begin
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if (ts_sel_reg) begin
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ts_tod_s_0_reg[31:16] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_1_reg[31:16] <= dst_td_tdata_reg;
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end
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end
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if (dst_td_tid_reg == {4'd2, 4'd5}) begin
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if (ts_sel_reg) begin
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ts_tod_s_0_reg[47:32] <= dst_td_tdata_reg;
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end else begin
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ts_tod_s_1_reg[47:32] <= dst_td_tdata_reg;
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end
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end
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end
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output_ts_tod_s_reg <= output_ts_tod_s_next;
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output_ts_tod_ns_reg <= output_ts_tod_ns_next;
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output_ts_fns_reg <= output_ts_fns_next;
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output_ts_tag_reg <= output_ts_tag_next;
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output_ts_valid_reg <= output_ts_valid_next;
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if (rst) begin
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output_ts_valid_reg <= 1'b0;
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end
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end
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endmodule
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`resetall

‎syn/vivado/ptp_td_rel2tod.tcl

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# Copyright (c) 2019-2024 Alex Forencich
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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# THE SOFTWARE.
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# PTP time distribution ToD timestamp reconstruction module
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foreach inst [get_cells -hier -regexp -filter {(ORIG_REF_NAME =~ "ptp_td_rel2tod(__\w+__\d+)?" ||
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REF_NAME =~ "ptp_td_rel2tod(__\w+__\d+)?")}] {
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puts "Inserting timing constraints for ptp_td_rel2tod instance $inst"
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# get clock periods
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set input_clk [get_clocks -of_objects [get_pins "$inst/td_sync_reg_reg/C"]]
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set output_clk [get_clocks -of_objects [get_pins "$inst/td_sync_sync1_reg_reg/C"]]
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set input_clk_period [if {[llength $input_clk]} {get_property -min PERIOD $input_clk} {expr 1.0}]
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set output_clk_period [if {[llength $output_clk]} {get_property -min PERIOD $output_clk} {expr 1.0}]
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# TD data sync
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set_property ASYNC_REG TRUE [get_cells -hier -regexp ".*/dst_td_(tdata|tid)_reg_reg(\\\[\\d+\\\])?" -filter "PARENT == $inst"]
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set_max_delay -from [get_cells "$inst/td_tdata_reg_reg[*]"] -to [get_cells "$inst/dst_td_tdata_reg_reg[*]"] -datapath_only $output_clk_period
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set_bus_skew -from [get_cells "$inst/td_tdata_reg_reg[*]"] -to [get_cells "$inst/dst_td_tdata_reg_reg[*]"] $input_clk_period
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set_max_delay -from [get_cells "$inst/td_tid_reg_reg[*]"] -to [get_cells "$inst/dst_td_tid_reg_reg[*]"] -datapath_only $output_clk_period
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set_bus_skew -from [get_cells "$inst/td_tid_reg_reg[*]"] -to [get_cells "$inst/dst_td_tid_reg_reg[*]"] $input_clk_period
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set sync_ffs [get_cells -quiet -hier -regexp ".*/td_sync_sync\[12\]_reg_reg" -filter "PARENT == $inst"]
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if {[llength $sync_ffs]} {
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set_property ASYNC_REG TRUE $sync_ffs
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set_max_delay -from [get_cells "$inst/td_sync_reg_reg"] -to [get_cells "$inst/td_sync_sync1_reg_reg"] -datapath_only $input_clk_period
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}
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}

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