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Remove recursively-expanded macros for module parameters in makefiles
Signed-off-by: Alex Forencich <[email protected]>
1 parent db818b2 commit c65161e

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‎example/520N_MX/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/ADM_PCIE_9V3/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/ATLYS/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6565
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6666

6767
# module parameters
68-
#export PARAM_A ?= value
68+
#export PARAM_A := value
6969

7070
ifeq ($(SIM), icarus)
7171
PLUSARGS += -fst

‎example/AU200/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/AU250/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/AU280/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/AU50/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/Arty/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6262
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6363

6464
# module parameters
65-
#export PARAM_A ?= value
65+
#export PARAM_A := value
6666

6767
ifeq ($(SIM), icarus)
6868
PLUSARGS += -fst

‎example/C10LP/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6464
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6565

6666
# module parameters
67-
#export PARAM_A ?= value
67+
#export PARAM_A := value
6868

6969
ifeq ($(SIM), icarus)
7070
PLUSARGS += -fst

‎example/DE2-115/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6565
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6666

6767
# module parameters
68-
#export PARAM_A ?= value
68+
#export PARAM_A := value
6969

7070
ifeq ($(SIM), icarus)
7171
PLUSARGS += -fst

‎example/DE5-Net/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/ExaNIC_X10/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/ExaNIC_X25/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/HTG9200/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/HXT100G/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/HXT100G/fpga_cxpt16/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
4141
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_crosspoint.v
4242

4343
# module parameters
44-
#export PARAM_A ?= value
44+
#export PARAM_A := value
4545

4646
ifeq ($(SIM), icarus)
4747
PLUSARGS += -fst

‎example/KC705/fpga_gmii/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6565
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6666

6767
# module parameters
68-
#export PARAM_A ?= value
68+
#export PARAM_A := value
6969

7070
ifeq ($(SIM), icarus)
7171
PLUSARGS += -fst

‎example/KC705/fpga_rgmii/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6464
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6565

6666
# module parameters
67-
#export PARAM_A ?= value
67+
#export PARAM_A := value
6868

6969
ifeq ($(SIM), icarus)
7070
PLUSARGS += -fst

‎example/KC705/fpga_sgmii/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/ML605/fpga_gmii/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6565
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6666

6767
# module parameters
68-
#export PARAM_A ?= value
68+
#export PARAM_A := value
6969

7070
ifeq ($(SIM), icarus)
7171
PLUSARGS += -fst

‎example/ML605/fpga_rgmii/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6464
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6565

6666
# module parameters
67-
#export PARAM_A ?= value
67+
#export PARAM_A := value
6868

6969
ifeq ($(SIM), icarus)
7070
PLUSARGS += -fst

‎example/ML605/fpga_sgmii/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/NetFPGA_SUME/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/NexysVideo/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6464
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6565

6666
# module parameters
67-
#export PARAM_A ?= value
67+
#export PARAM_A := value
6868

6969
ifeq ($(SIM), icarus)
7070
PLUSARGS += -fst

‎example/RV901T/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6464
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6565

6666
# module parameters
67-
#export PARAM_A ?= value
67+
#export PARAM_A := value
6868

6969
ifeq ($(SIM), icarus)
7070
PLUSARGS += -fst

‎example/S10MX_DK/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/VCU108/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6666
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6767

6868
# module parameters
69-
#export PARAM_A ?= value
69+
#export PARAM_A := value
7070

7171
ifeq ($(SIM), icarus)
7272
PLUSARGS += -fst

‎example/VCU108/fpga_1g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/VCU118/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6666
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6767

6868
# module parameters
69-
#export PARAM_A ?= value
69+
#export PARAM_A := value
7070

7171
ifeq ($(SIM), icarus)
7272
PLUSARGS += -fst

‎example/VCU118/fpga_1g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/VCU118/fpga_25g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
6666
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6767

6868
# module parameters
69-
#export PARAM_A ?= value
69+
#export PARAM_A := value
7070

7171
ifeq ($(SIM), icarus)
7272
PLUSARGS += -fst

‎example/VCU1525/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/ZCU102/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/ZCU106/fpga/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎example/fb2CG/fpga_10g/tb/fpga_core/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
5959
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
6060

6161
# module parameters
62-
#export PARAM_A ?= value
62+
#export PARAM_A := value
6363

6464
ifeq ($(SIM), icarus)
6565
PLUSARGS += -fst

‎tb/arp/Makefile

+7-7
Original file line numberDiff line numberDiff line change
@@ -36,13 +36,13 @@ VERILOG_SOURCES += ../../rtl/arp_cache.v
3636
VERILOG_SOURCES += ../../rtl/lfsr.v
3737

3838
# module parameters
39-
export PARAM_DATA_WIDTH ?= 8
40-
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
41-
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
42-
export PARAM_CACHE_ADDR_WIDTH ?= 2
43-
export PARAM_REQUEST_RETRY_COUNT ?= 4
44-
export PARAM_REQUEST_RETRY_INTERVAL ?= 300
45-
export PARAM_REQUEST_TIMEOUT ?= 800
39+
export PARAM_DATA_WIDTH := 8
40+
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
41+
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
42+
export PARAM_CACHE_ADDR_WIDTH := 2
43+
export PARAM_REQUEST_RETRY_COUNT := 4
44+
export PARAM_REQUEST_RETRY_INTERVAL := 300
45+
export PARAM_REQUEST_TIMEOUT := 800
4646

4747
ifeq ($(SIM), icarus)
4848
PLUSARGS += -fst

‎tb/arp_cache/Makefile

+1-1
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
3333
VERILOG_SOURCES += ../../rtl/lfsr.v
3434

3535
# module parameters
36-
export PARAM_CACHE_ADDR_WIDTH ?= 2
36+
export PARAM_CACHE_ADDR_WIDTH := 2
3737

3838
ifeq ($(SIM), icarus)
3939
PLUSARGS += -fst

‎tb/arp_eth_rx/Makefile

+3-3
Original file line numberDiff line numberDiff line change
@@ -32,9 +32,9 @@ MODULE = test_$(DUT)
3232
VERILOG_SOURCES += ../../rtl/$(DUT).v
3333

3434
# module parameters
35-
export PARAM_DATA_WIDTH ?= 8
36-
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
37-
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
35+
export PARAM_DATA_WIDTH := 8
36+
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
37+
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
3838

3939
ifeq ($(SIM), icarus)
4040
PLUSARGS += -fst

‎tb/arp_eth_tx/Makefile

+3-3
Original file line numberDiff line numberDiff line change
@@ -32,9 +32,9 @@ MODULE = test_$(DUT)
3232
VERILOG_SOURCES += ../../rtl/$(DUT).v
3333

3434
# module parameters
35-
export PARAM_DATA_WIDTH ?= 8
36-
export PARAM_KEEP_ENABLE ?= $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
37-
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
35+
export PARAM_DATA_WIDTH := 8
36+
export PARAM_KEEP_ENABLE := $(shell expr $(PARAM_DATA_WIDTH) \> 8 )
37+
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
3838

3939
ifeq ($(SIM), icarus)
4040
PLUSARGS += -fst

‎tb/axis_baser_rx_64/Makefile

+6-6
Original file line numberDiff line numberDiff line change
@@ -33,12 +33,12 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v
3333
VERILOG_SOURCES += ../../rtl/lfsr.v
3434

3535
# module parameters
36-
export PARAM_DATA_WIDTH ?= 64
37-
export PARAM_KEEP_WIDTH ?= $(shell expr $(PARAM_DATA_WIDTH) / 8 )
38-
export PARAM_HDR_WIDTH ?= 2
39-
export PARAM_PTP_TS_ENABLE ?= 1
40-
export PARAM_PTP_TS_WIDTH ?= 96
41-
export PARAM_USER_WIDTH ?= $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
36+
export PARAM_DATA_WIDTH := 64
37+
export PARAM_KEEP_WIDTH := $(shell expr $(PARAM_DATA_WIDTH) / 8 )
38+
export PARAM_HDR_WIDTH := 2
39+
export PARAM_PTP_TS_ENABLE := 1
40+
export PARAM_PTP_TS_WIDTH := 96
41+
export PARAM_USER_WIDTH := $(if $(filter-out 1,$(PARAM_PTP_TS_ENABLE)),1,$(shell expr $(PARAM_PTP_TS_WIDTH) + 1 ))
4242

4343
ifeq ($(SIM), icarus)
4444
PLUSARGS += -fst

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