diff --git a/example/AX7203_ARTIX7/fpga/Makefile b/example/AX7203_ARTIX7/fpga/Makefile
new file mode 100644
index 000000000..f504bd06f
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/Makefile
@@ -0,0 +1,25 @@
+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+	cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+	cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+	-rm -rf $(TARGETS)
+
+program:
+	#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
diff --git a/example/AX7203_ARTIX7/fpga/README.md b/example/AX7203_ARTIX7/fpga/README.md
new file mode 100644
index 000000000..6a3b314f3
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/README.md
@@ -0,0 +1,31 @@
+# Verilog Ethernet ARTIX Example Design
+
+## Introduction
+
+This example design targets the Digilent Nexys Video FPGA board.
+
+The design by default listens to UDP port 1234 at IP address 192.168.1.128 and
+will echo back any packets received.  The design will also respond correctly
+to ARP requests.  
+
+*  FPGA: XC7A200TFBG484-2
+*  PHY:  KSZ9031RNX
+
+## How to build
+
+Run make to build.  Ensure that the Xilinx Vivado toolchain components are
+in PATH.  
+
+## How to test
+
+Run make program to program the Nexys Video board with the Digilent command
+line tools.  Then run
+
+    netcat -u 192.168.1.128 1234
+
+to open a UDP connection to port 1234.  Any text entered into netcat will be
+echoed back after pressing enter.
+
+It is also possible to use hping to test the design by running
+
+    sudo hping3 192.168.1.128 -2 -p 1234 -d 1024
diff --git a/example/AX7203_ARTIX7/fpga/common/vivado.mk b/example/AX7203_ARTIX7/fpga/common/vivado.mk
new file mode 100644
index 000000000..1402e2382
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/common/vivado.mk
@@ -0,0 +1,137 @@
+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+FPGA_TOP ?= fpga
+PROJECT ?= $(FPGA_TOP)
+
+SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
+else
+  XDC_FILES_REL = $(PROJECT).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(PROJECT).bit
+
+vivado: $(PROJECT).xpr
+	vivado $(PROJECT).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+	-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
+	echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
+	echo "open_project -quiet $(PROJECT).xpr" > $@
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+$(PROJECT).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr
+	echo "open_project $(PROJECT).xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
+	echo "open_project $(PROJECT).xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	echo "open_run impl_1" >> run_impl.tcl
+	echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
+	echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
+	echo "open_project $(PROJECT).xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
+	echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
+	if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi
diff --git a/example/AX7203_ARTIX7/fpga/eth.xdc b/example/AX7203_ARTIX7/fpga/eth.xdc
new file mode 100644
index 000000000..4e26ab891
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/eth.xdc
@@ -0,0 +1,7 @@
+# Ethernet constraints
+
+# IDELAY on RGMII from PHY chip
+set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}]
+
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga.xdc b/example/AX7203_ARTIX7/fpga/fpga.xdc
new file mode 100644
index 000000000..d119e8e9a
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga.xdc
@@ -0,0 +1,54 @@
+# XDC constraints for the Digilent Nexys Video board
+# part: xc7a200tfbg484-2
+
+# General configuration
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
+
+# differential clock
+set_property -dict {PACKAGE_PIN R4 IOSTANDARD DIFF_SSTL15} [get_ports clk_p]
+set_property -dict {PACKAGE_PIN T4 IOSTANDARD DIFF_SSTL15} [get_ports clk_n]
+create_clock -period 5.000 -name clk [get_ports clk_p]
+
+# Reset button
+set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS15} [get_ports reset_n]
+
+set_false_path -from [get_ports reset_n]
+set_input_delay 0.000 [get_ports reset_n]
+
+
+# Gigabit Ethernet RGMII PHY
+set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
+set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
+set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
+set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
+set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
+set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports phy_rx_ctl]
+
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports phy_tx_clk]
+set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[0]}]
+set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[1]}]
+set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[2]}]
+set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[3]}]
+set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports phy_tx_ctl]
+set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
+create_clock -period 8.000 -name phy_rx_clk [get_ports phy_rx_clk]
+
+#set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_mdio]
+#set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_mdc]
+#set_false_path -to [get_ports {phy_mdio phy_mdc}]
+#set_output_delay 0.000 [get_ports {phy_mdio phy_mdc}]
+#set_false_path -from [get_ports phy_mdio]
+#set_input_delay 0.000 [get_ports phy_mdio]
+#set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25} [get_ports phy_int_n]
+#set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25} [get_ports phy_pme_n]
+#set_false_path -from [get_ports {phy_int_n phy_pme_n}]
+#set_input_delay 0 [get_ports {phy_int_n phy_pme_n}]
+
+set_false_path -to [get_ports phy_reset_n]
+set_output_delay 0.000 [get_ports phy_reset_n]
+
+
+#new
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/Makefile b/example/AX7203_ARTIX7/fpga/fpga/Makefile
new file mode 100644
index 000000000..9e28d5022
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/Makefile
@@ -0,0 +1,59 @@
+
+# FPGA settings
+FPGA_PART = xc7a200t-fbg484-2
+FPGA_TOP = fpga
+FPGA_ARCH = artix7
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += lib/eth/rtl/iddr.v
+SYN_FILES += lib/eth/rtl/oddr.v
+SYN_FILES += lib/eth/rtl/ssio_ddr_in.v
+SYN_FILES += lib/eth/rtl/ssio_ddr_out.v
+SYN_FILES += lib/eth/rtl/rgmii_phy_if.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii_fifo.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g_rgmii.v
+SYN_FILES += lib/eth/rtl/eth_mac_1g.v
+SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
+SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/eth_axis_rx.v
+SYN_FILES += lib/eth/rtl/eth_axis_tx.v
+SYN_FILES += lib/eth/rtl/udp_complete.v
+SYN_FILES += lib/eth/rtl/udp_checksum_gen.v
+SYN_FILES += lib/eth/rtl/udp.v
+SYN_FILES += lib/eth/rtl/udp_ip_rx.v
+SYN_FILES += lib/eth/rtl/udp_ip_tx.v
+SYN_FILES += lib/eth/rtl/ip_complete.v
+SYN_FILES += lib/eth/rtl/ip.v
+SYN_FILES += lib/eth/rtl/ip_eth_rx.v
+SYN_FILES += lib/eth/rtl/ip_eth_tx.v
+SYN_FILES += lib/eth/rtl/ip_arb_mux.v
+SYN_FILES += lib/eth/rtl/arp.v
+SYN_FILES += lib/eth/rtl/arp_cache.v
+SYN_FILES += lib/eth/rtl/arp_eth_rx.v
+SYN_FILES += lib/eth/rtl/arp_eth_tx.v
+SYN_FILES += lib/eth/rtl/eth_arb_mux.v
+SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
+SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
+SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
+SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+XDC_FILES += eth.xdc
+XDC_FILES += lib/eth/syn/vivado/rgmii_phy_if.tcl
+XDC_FILES += lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl
+XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
+XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	djtgcfg prog -d NexysVideo --index 0 --file $(FPGA_TOP).bit
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/create_project.tcl b/example/AX7203_ARTIX7/fpga/fpga/create_project.tcl
new file mode 100644
index 000000000..964473e85
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/create_project.tcl
@@ -0,0 +1,4 @@
+create_project -force -part xc7a200t-fbg484-2 fpga
+add_files -fileset sources_1 defines.v ../rtl/fpga.v ../rtl/fpga_core.v ../rtl/sync_signal.v ../lib/eth/rtl/iddr.v ../lib/eth/rtl/oddr.v ../lib/eth/rtl/ssio_ddr_in.v ../lib/eth/rtl/ssio_ddr_out.v ../lib/eth/rtl/rgmii_phy_if.v ../lib/eth/rtl/eth_mac_1g_rgmii_fifo.v ../lib/eth/rtl/eth_mac_1g_rgmii.v ../lib/eth/rtl/eth_mac_1g.v ../lib/eth/rtl/axis_gmii_rx.v ../lib/eth/rtl/axis_gmii_tx.v ../lib/eth/rtl/lfsr.v ../lib/eth/rtl/eth_axis_rx.v ../lib/eth/rtl/eth_axis_tx.v ../lib/eth/rtl/udp_complete.v ../lib/eth/rtl/udp_checksum_gen.v ../lib/eth/rtl/udp.v ../lib/eth/rtl/udp_ip_rx.v ../lib/eth/rtl/udp_ip_tx.v ../lib/eth/rtl/ip_complete.v ../lib/eth/rtl/ip.v ../lib/eth/rtl/ip_eth_rx.v ../lib/eth/rtl/ip_eth_tx.v ../lib/eth/rtl/ip_arb_mux.v ../lib/eth/rtl/arp.v ../lib/eth/rtl/arp_cache.v ../lib/eth/rtl/arp_eth_rx.v ../lib/eth/rtl/arp_eth_tx.v ../lib/eth/rtl/eth_arb_mux.v ../lib/eth/lib/axis/rtl/arbiter.v ../lib/eth/lib/axis/rtl/priority_encoder.v ../lib/eth/lib/axis/rtl/axis_fifo.v ../lib/eth/lib/axis/rtl/axis_async_fifo.v ../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v ../lib/eth/lib/axis/rtl/sync_reset.v
+set_property top fpga [current_fileset]
+add_files -fileset constrs_1 ../fpga.xdc ../eth.xdc ../lib/eth/syn/vivado/rgmii_phy_if.tcl ../lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl ../lib/eth/syn/vivado/eth_mac_fifo.tcl ../lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl ../lib/eth/lib/axis/syn/vivado/sync_reset.tcl
diff --git a/example/AX7203_ARTIX7/fpga/fpga/defines.v b/example/AX7203_ARTIX7/fpga/fpga/defines.v
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.bit b/example/AX7203_ARTIX7/fpga/fpga/fpga.bit
new file mode 120000
index 000000000..28a278da2
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.bit
@@ -0,0 +1 @@
+fpga.runs/impl_1/fpga.bit
\ No newline at end of file
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/project.wpc b/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/project.wpc
new file mode 100644
index 000000000..2b172552a
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/project.wpc
@@ -0,0 +1,4 @@
+version:1
+57656254616c6b5472616e736d697373696f6e417474656d70746564:1
+6d6f64655f636f756e7465727c42617463684d6f6465:4
+eof:
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/synthesis.wdf b/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/synthesis.wdf
new file mode 100644
index 000000000..5ea523c71
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/synthesis.wdf
@@ -0,0 +1,48 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761323030746662673438342d32:00:00
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+eof:2762386430
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/synthesis_details.wdf b/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/synthesis_details.wdf
new file mode 100644
index 000000000..78f8d66e5
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/webtalk_pa.xml b/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/webtalk_pa.xml
new file mode 100644
index 000000000..5cdda379b
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt/webtalk_pa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Wed Jan  8 11:24:59 2025">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="934473222dcc4727a88ea328dcfb7456" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.hw/fpga.lpr b/example/AX7203_ARTIX7/fpga/fpga/fpga.hw/fpga.lpr
new file mode 100644
index 000000000..34359e9c5
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.hw/fpga.lpr
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.1 (64-bit)                                     -->
+<!--                                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                        -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.        -->
+
+<labtools version="1" minor="0"/>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.hw/hw_1/hw.xml b/example/AX7203_ARTIX7/fpga/fpga/fpga.hw/hw_1/hw.xml
new file mode 100644
index 000000000..36ffa610e
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.hw/hw_1/hw.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.1 (64-bit)                                     -->
+<!--                                                                              -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                        -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.        -->
+
+<hwsession version="1" minor="2">
+  <device name="xc7a200t_0" gui_info=""/>
+  <ObjectList object_type="hw_device" gui_info="">
+    <Object name="xc7a200t_0" gui_info="">
+      <Properties Property="FULL_PROBES.FILE" value=""/>
+      <Properties Property="PROBES.FILE" value=""/>
+      <Properties Property="PROGRAM.HW_BITSTREAM" value="rev/$_project_name__rev100.bit"/>
+      <Properties Property="SLR.COUNT" value="1"/>
+    </Object>
+  </ObjectList>
+  <ObjectList object_type="hw_ila" gui_info="">
+    <Object name="" gui_info="">
+      <Properties Property="CONTROL.TRIGGER_CONDITION" value="AND"/>
+      <Properties Property="CORE_REFRESH_RATE_MS" value="500"/>
+    </Object>
+  </ObjectList>
+  <probeset name="hw project" active="false"/>
+</hwsession>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/.jobs/vrs_config_1.xml b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 000000000..d86d80ddc
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="synth_1" LaunchDir="/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/.jobs/vrs_config_2.xml b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 000000000..9c060eacd
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+	<Run Id="impl_1" LaunchDir="/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design"/>
+	<Parameters>
+		<Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+		<Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+	</Parameters>
+</Runs>
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.Vivado_Implementation.queue.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.init_design.begin.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 000000000..05f5020f1
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="kavya" Host="" Pid="256738">
+    </Process>
+</ProcessHandle>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.init_design.end.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.init_design.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.opt_design.begin.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 000000000..05f5020f1
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="kavya" Host="" Pid="256738">
+    </Process>
+</ProcessHandle>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.opt_design.end.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.phys_opt_design.begin.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.phys_opt_design.begin.rst
new file mode 100644
index 000000000..05f5020f1
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.phys_opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="kavya" Host="" Pid="256738">
+    </Process>
+</ProcessHandle>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.phys_opt_design.end.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.phys_opt_design.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.place_design.begin.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 000000000..05f5020f1
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="kavya" Host="" Pid="256738">
+    </Process>
+</ProcessHandle>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.place_design.end.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.place_design.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.route_design.begin.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 000000000..05f5020f1
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command=".planAhead." Owner="kavya" Host="" Pid="256738">
+    </Process>
+</ProcessHandle>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.route_design.end.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.route_design.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.vivado.begin.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 000000000..daaa40e41
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado" Owner="kavya" Host="kavya-Precision-Tower-5810" Pid="256694" HostCore="12" HostMemory="65766632">
+    </Process>
+</ProcessHandle>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.vivado.end.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/.vivado.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/ISEWrap.js b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/ISEWrap.js
new file mode 100755
index 000000000..61806d027
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 
+//  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var wbemFlagReturnImmediately = 0x10;
+    var wbemFlagForwardOnly = 0x20;
+    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var NOC = 0;
+    var NOLP = 0;
+    var TPM = 0;
+    var cpuInfos = new Enumerator(processor);
+    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+        var cpuInfo = cpuInfos.item();
+        NOC += cpuInfo.NumberOfCores;
+        NOLP += cpuInfo.NumberOfLogicalProcessors;
+    }
+    var csInfos = new Enumerator(computerSystem);
+    for(;!csInfos.atEnd(); csInfos.moveNext()) {
+        var csInfo = csInfos.item();
+        TPM += csInfo.TotalPhysicalMemory;
+    }
+
+    var ISEHOSTCORE = NOLP
+    var ISEMEMTOTAL = TPM
+
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\" HostCore=\"" + ISEHOSTCORE +
+			    "\" HostMemory=\"" + ISEMEMTOTAL +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/ISEWrap.sh b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/ISEWrap.sh
new file mode 100755
index 000000000..05d538137
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 
+#  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 
+#
+
+cmd_exists()
+{
+  command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.bit b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.bit
new file mode 100644
index 000000000..7fd84efaf
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.bit differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.tcl b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.tcl
new file mode 100644
index 000000000..3dcf5bd65
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.tcl
@@ -0,0 +1,304 @@
+# 
+# Report generation script generated by Vivado
+# 
+
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+namespace eval ::optrace {
+  variable script "/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.tcl"
+  variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+  namespace eval ::dispatch {
+    variable connected false
+    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+      set result "true"
+      if {[catch {
+        if {[lsearch -exact [package names] DispatchTcl] < 0} {
+          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
+        }
+        if {$result eq "false"} {
+          puts "WARNING: Could not load dispatch client library"
+        }
+        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+        if { $connect_id eq "" } {
+          puts "WARNING: Could not initialize dispatch client"
+        } else {
+          puts "INFO: Dispatch client connection id - $connect_id"
+          set connected true
+        }
+      } catch_res]} {
+        puts "WARNING: failed to connect to dispatch server - $catch_res"
+      }
+    }
+  }
+}
+if {$::dispatch::connected} {
+  # Remove the dummy proc if it exists.
+  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+    rename ::OPTRACE ""
+  }
+  proc ::OPTRACE { task action {tags {} } } {
+    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+  }
+  # dispatch is generic. We specifically want to attach logging.
+  ::vitis_log::connect_client
+} else {
+  # Add dummy proc if it doesn't exist.
+  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+        # Do nothing
+    }
+  }
+}
+
+proc start_step { step } {
+  set stopFile ".stop.rst"
+  if {[file isfile .stop.rst]} {
+    puts ""
+    puts "*** Halting run - EA reset detected ***"
+    puts ""
+    puts ""
+    return -code error
+  }
+  set beginFile ".$step.begin.rst"
+  set platform "$::tcl_platform(platform)"
+  set user "$::tcl_platform(user)"
+  set pid [pid]
+  set host ""
+  if { [string equal $platform unix] } {
+    if { [info exist ::env(HOSTNAME)] } {
+      set host $::env(HOSTNAME)
+    } elseif { [info exist ::env(HOST)] } {
+      set host $::env(HOST)
+    }
+  } else {
+    if { [info exist ::env(COMPUTERNAME)] } {
+      set host $::env(COMPUTERNAME)
+    }
+  }
+  set ch [open $beginFile w]
+  puts $ch "<?xml version=\"1.0\"?>"
+  puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+  puts $ch "    <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+  puts $ch "    </Process>"
+  puts $ch "</ProcessHandle>"
+  close $ch
+}
+
+proc end_step { step } {
+  set endFile ".$step.end.rst"
+  set ch [open $endFile w]
+  close $ch
+}
+
+proc step_failed { step } {
+  set endFile ".$step.error.rst"
+  set ch [open $endFile w]
+  close $ch
+OPTRACE "impl_1" END { }
+}
+
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+  create_msg_db init_design.pb
+  set_param chipscope.maxJobs 3
+  set_param runs.launchOptions { -jobs 4  }
+OPTRACE "create in-memory project" START { }
+  create_project -in_memory -part xc7a200tfbg484-2
+  set_property design_mode GateLvl [current_fileset]
+  set_param project.singleFileAddWarning.threshold 0
+OPTRACE "create in-memory project" END { }
+OPTRACE "set parameters" START { }
+  set_property webtalk.parent_dir /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt [current_project]
+  set_property parent.project_path /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.xpr [current_project]
+  set_property ip_output_repo /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/ip [current_project]
+  set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "set parameters" END { }
+OPTRACE "add files" START { }
+  add_files -quiet /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.dcp
+OPTRACE "read constraints: implementation" START { }
+  read_xdc /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc
+  read_xdc /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc
+  read_xdc -unmanaged /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl
+  read_xdc -unmanaged /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl
+  read_xdc -unmanaged /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl
+  read_xdc -unmanaged /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
+  read_xdc -unmanaged /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl
+OPTRACE "read constraints: implementation" END { }
+OPTRACE "add files" END { }
+OPTRACE "link_design" START { }
+  link_design -top fpga -part xc7a200tfbg484-2 
+OPTRACE "link_design" END { }
+OPTRACE "gray box cells" START { }
+OPTRACE "gray box cells" END { }
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+OPTRACE "init_design_write_hwdef" END { }
+  close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+  step_failed init_design
+  return -code error $RESULT
+} else {
+  end_step init_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+  create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+  opt_design 
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "opt_design reports" START { REPORT }
+  create_report "impl_1_opt_report_drc_0" "report_drc -file fpga_drc_opted.rpt -pb fpga_drc_opted.pb -rpx fpga_drc_opted.rpx"
+OPTRACE "opt_design reports" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force fpga_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+  close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+  step_failed opt_design
+  return -code error $RESULT
+} else {
+  end_step opt_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+  create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+  if { [llength [get_debug_cores -quiet] ] > 0 }  { 
+OPTRACE "implement_debug_core" START { }
+    implement_debug_core 
+OPTRACE "implement_debug_core" END { }
+  } 
+OPTRACE "place_design" START { }
+  place_design 
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "place_design reports" START { REPORT }
+  create_report "impl_1_place_report_io_0" "report_io -file fpga_io_placed.rpt"
+  create_report "impl_1_place_report_utilization_0" "report_utilization -file fpga_utilization_placed.rpt -pb fpga_utilization_placed.pb"
+  create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file fpga_control_sets_placed.rpt"
+OPTRACE "place_design reports" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force fpga_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+  close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+  step_failed place_design
+  return -code error $RESULT
+} else {
+  end_step place_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
+start_step phys_opt_design
+set ACTIVE_STEP phys_opt_design
+set rc [catch {
+  create_msg_db phys_opt_design.pb
+OPTRACE "read constraints: phys_opt_design" START { }
+OPTRACE "read constraints: phys_opt_design" END { }
+OPTRACE "phys_opt_design" START { }
+  phys_opt_design 
+OPTRACE "phys_opt_design" END { }
+OPTRACE "read constraints: phys_opt_design_post" START { }
+OPTRACE "read constraints: phys_opt_design_post" END { }
+OPTRACE "phys_opt_design report" START { REPORT }
+OPTRACE "phys_opt_design report" END { }
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force fpga_physopt.dcp
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
+  close_msg_db -file phys_opt_design.pb
+} RESULT]
+if {$rc} {
+  step_failed phys_opt_design
+  return -code error $RESULT
+} else {
+  end_step phys_opt_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "Phase: Physical Opt Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+  create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+  route_design 
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "route_design reports" START { REPORT }
+  create_report "impl_1_route_report_drc_0" "report_drc -file fpga_drc_routed.rpt -pb fpga_drc_routed.pb -rpx fpga_drc_routed.rpx"
+  create_report "impl_1_route_report_methodology_0" "report_methodology -file fpga_methodology_drc_routed.rpt -pb fpga_methodology_drc_routed.pb -rpx fpga_methodology_drc_routed.rpx"
+  create_report "impl_1_route_report_power_0" "report_power -file fpga_power_routed.rpt -pb fpga_power_summary_routed.pb -rpx fpga_power_routed.rpx"
+  create_report "impl_1_route_report_route_status_0" "report_route_status -file fpga_route_status.rpt -pb fpga_route_status.pb"
+  create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file fpga_timing_summary_routed.rpt -pb fpga_timing_summary_routed.pb -rpx fpga_timing_summary_routed.rpx -warn_on_violation "
+  create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file fpga_incremental_reuse_routed.rpt"
+  create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file fpga_clock_utilization_routed.rpt"
+  create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file fpga_bus_skew_routed.rpt -pb fpga_bus_skew_routed.pb -rpx fpga_bus_skew_routed.rpx"
+OPTRACE "route_design reports" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+  write_checkpoint -force fpga_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design misc" START { }
+  close_msg_db -file route_design.pb
+} RESULT]
+if {$rc} {
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+  write_checkpoint -force fpga_routed_error.dcp
+  step_failed route_design
+  return -code error $RESULT
+} else {
+  end_step route_design
+  unset ACTIVE_STEP 
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "impl_1" END { }
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.vdi b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.vdi
new file mode 100644
index 000000000..d91c6dbfd
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.vdi
@@ -0,0 +1,693 @@
+#-----------------------------------------------------------
+# Vivado v2023.1 (64-bit)
+# SW Build 3865809 on Sun May  7 15:04:56 MDT 2023
+# IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
+# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
+# Start of session at: Wed Jan  8 11:25:03 2025
+# Process ID: 256738
+# Current directory: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1
+# Command line: vivado -log fpga.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fpga.tcl -notrace
+# Log file: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.vdi
+# Journal file: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/vivado.jou
+# Running On: kavya-Precision-Tower-5810, OS: Linux, CPU Frequency: 2140.712 MHz, CPU Physical cores: 12, Host memory: 67345 MB
+#-----------------------------------------------------------
+source fpga.tcl -notrace
+create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1298.672 ; gain = 19.023 ; free physical = 51210 ; free virtual = 56217
+Command: link_design -top fpga -part xc7a200tfbg484-2
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tfbg484-2
+Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1696.117 ; gain = 0.000 ; free physical = 50827 ; free virtual = 55834
+INFO: [Netlist 29-17] Analyzing 261 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2023.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+Finished Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]
+Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc]
+Finished Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]
+Inserting timing constraints for rgmii_phy_if instance core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl:23]
+INFO: [Timing 38-2] Deriving generated clocks [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl:23]
+get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2486.605 ; gain = 620.055 ; free physical = 50265 ; free virtual = 55271
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]
+Inserting timing constraints for eth_mac_1g_rgmii instance core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
+Inserting timing constraints for ethernet MAC with FIFO instance core_inst/eth_mac_inst
+WARNING: [Vivado 12-180] No cells matched '.*/rx_sync_reg_[1234]_reg\[\d+\]'. [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl:23]
+WARNING: [Vivado 12-180] No cells matched '.*/tx_sync_reg_[1234]_reg\[\d+\]'. [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl:23]
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
+Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_inst/rx_fifo/fifo_inst
+Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_inst/tx_fifo/fifo_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
+Inserting timing constraints for sync_reset instance sync_reset_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2486.605 ; gain = 0.000 ; free physical = 50265 ; free virtual = 55271
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 23 instances were transformed.
+  RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 4 instances
+  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 19 instances
+
+11 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2486.605 ; gain = 1183.934 ; free physical = 50265 ; free virtual = 55271
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2550.637 ; gain = 64.031 ; free physical = 50241 ; free virtual = 55248
+
+Starting Cache Timing Information Task
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 217aa3e62
+
+Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2550.637 ; gain = 0.000 ; free physical = 50241 ; free virtual = 55248
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 8 pins
+INFO: [Opt 31-138] Pushed 2 inverter(s) to 4 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 17656d86b
+
+Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 4 cells
+INFO: [Opt 31-1021] In phase Retarget, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: 14db90694
+
+Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 11d80edcb
+
+Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+INFO: [Opt 31-1021] In phase Sweep, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 11d80edcb
+
+Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 1451036a6
+
+Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.5 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 1451036a6
+
+Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               4  |                                              2  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              1  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+Ending Logic Optimization Task | Checksum: 1451036a6
+
+Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Running Vector-less Activity Propagation...
+INFO: [Pwropt 34-9] Applying IDT optimizations ...
+INFO: [Pwropt 34-10] Applying ODC optimizations ...
+
+Finished Running Vector-less Activity Propagation
+
+
+Starting PowerOpt Patch Enables Task
+INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 10 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
+INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
+Number of BRAM Ports augmented: 10 newly gated: 3 Total Ports: 20
+Ending PowerOpt Patch Enables Task | Checksum: 199102501
+
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49746 ; free virtual = 54753
+Ending Power Optimization Task | Checksum: 199102501
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 393.367 ; free physical = 49746 ; free virtual = 54753
+
+Starting Final Cleanup Task
+
+Starting Logic Optimization Task
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Logic Optimization Task | Checksum: e9653835
+
+Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.35 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49743 ; free virtual = 54750
+Ending Final Cleanup Task | Checksum: e9653835
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49743 ; free virtual = 54750
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49743 ; free virtual = 54750
+Ending Netlist Obfuscation Task | Checksum: e9653835
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49743 ; free virtual = 54750
+INFO: [Common 17-83] Releasing license: Implementation
+43 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 3153.941 ; gain = 667.336 ; free physical = 49743 ; free virtual = 54750
+INFO: [runtcl-4] Executing : report_drc -file fpga_drc_opted.rpt -pb fpga_drc_opted.pb -rpx fpga_drc_opted.rpx
+Command: report_drc -file fpga_drc_opted.rpt -pb fpga_drc_opted.pb -rpx fpga_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/kavya/Downloads/Downloads/Vivado/2023.1/data/ip'.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49731 ; free virtual = 54738
+INFO: [Common 17-1381] The checkpoint '/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49713 ; free virtual = 54721
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 75944c7a
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49713 ; free virtual = 54721
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49713 ; free virtual = 54721
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cf190ca7
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49720 ; free virtual = 54729
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 16c9ebfb9
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49722 ; free virtual = 54730
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 16c9ebfb9
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49722 ; free virtual = 54730
+Phase 1 Placer Initialization | Checksum: 16c9ebfb9
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49722 ; free virtual = 54730
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 145ffb69b
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49773 ; free virtual = 54781
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: fc643355
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49771 ; free virtual = 54779
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: fc643355
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49771 ; free virtual = 54779
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 111bdd4f4
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49792 ; free virtual = 54800
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 111 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 46 nets or LUTs. Breaked 0 LUT, combined 46 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49791 ; free virtual = 54799
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+|  LUT Combining                                    |            0  |             46  |                    46  |           0  |           1  |  00:00:00  |
+|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  Total                                            |            0  |             46  |                    46  |           0  |           4  |  00:00:00  |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 23f038e7f
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49791 ; free virtual = 54799
+Phase 2.4 Global Placement Core | Checksum: 14ff872b5
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49791 ; free virtual = 54799
+Phase 2 Global Placement | Checksum: 14ff872b5
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49791 ; free virtual = 54799
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 2352324bd
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49790 ; free virtual = 54799
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1f45a4b56
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:12 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49790 ; free virtual = 54798
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1a8ee0a11
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:12 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49790 ; free virtual = 54798
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 24263726a
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:12 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49790 ; free virtual = 54798
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1fa12dbcb
+
+Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49781 ; free virtual = 54789
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 1dae522f8
+
+Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49781 ; free virtual = 54789
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 282e9aeba
+
+Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49781 ; free virtual = 54789
+Phase 3 Detail Placement | Checksum: 282e9aeba
+
+Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49781 ; free virtual = 54789
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 225391a39
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.561 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 227454a20
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 227454a20
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.53 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+Phase 4.1.1.1 BUFG Insertion | Checksum: 225391a39
+
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=0.561. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 27e26f70f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+Phase 4.1 Post Commit Optimization | Checksum: 27e26f70f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 27e26f70f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 27e26f70f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+Phase 4.3 Placer Reporting | Checksum: 27e26f70f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 25ce714f9
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+Ending Placer Task | Checksum: 192347c4f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+INFO: [Common 17-83] Releasing license: Implementation
+84 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+INFO: [runtcl-4] Executing : report_io -file fpga_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49747 ; free virtual = 54755
+INFO: [runtcl-4] Executing : report_utilization -file fpga_utilization_placed.rpt -pb fpga_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file fpga_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49708 ; free virtual = 54716
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.47 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49705 ; free virtual = 54719
+INFO: [Common 17-1381] The checkpoint '/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_placed.dcp' has been generated.
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.81 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49687 ; free virtual = 54697
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+93 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.47 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49651 ; free virtual = 54668
+INFO: [Common 17-1381] The checkpoint '/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: d8edec7a ConstDB: 0 ShapeSum: b9468fd5 RouteDB: 0
+Post Restoration Checksum: NetGraph: e06a7014 | NumContArr: 5223c358 | Constraints: 190a55ad | Timing: 0
+Phase 1 Build RT Design | Checksum: 14b988919
+
+Time (s): cpu = 00:01:22 ; elapsed = 00:01:09 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49598 ; free virtual = 54611
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 14b988919
+
+Time (s): cpu = 00:01:22 ; elapsed = 00:01:09 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49598 ; free virtual = 54611
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 14b988919
+
+Time (s): cpu = 00:01:22 ; elapsed = 00:01:09 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49598 ; free virtual = 54611
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 1a4ea8580
+
+Time (s): cpu = 00:01:29 ; elapsed = 00:01:12 . Memory (MB): peak = 3171.445 ; gain = 17.504 ; free physical = 49559 ; free virtual = 54571
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.485  | TNS=0.000  | WHS=-0.223 | THS=-165.589|
+
+
+Phase 2.4 Update Timing for Bus Skew
+
+Phase 2.4.1 Update Timing
+Phase 2.4.1 Update Timing | Checksum: 1534219d3
+
+Time (s): cpu = 00:01:32 ; elapsed = 00:01:12 . Memory (MB): peak = 3171.445 ; gain = 17.504 ; free physical = 49559 ; free virtual = 54571
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.485  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 2.4 Update Timing for Bus Skew | Checksum: 1511870b8
+
+Time (s): cpu = 00:01:32 ; elapsed = 00:01:13 . Memory (MB): peak = 3171.445 ; gain = 17.504 ; free physical = 49559 ; free virtual = 54572
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0 %
+  Global Horizontal Routing Utilization  = 0 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 4426
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 4426
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: 1db21434d
+
+Time (s): cpu = 00:01:34 ; elapsed = 00:01:13 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49552 ; free virtual = 54565
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: 1db21434d
+
+Time (s): cpu = 00:01:34 ; elapsed = 00:01:13 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49552 ; free virtual = 54565
+Phase 3 Initial Routing | Checksum: 14394818d
+
+Time (s): cpu = 00:01:37 ; elapsed = 00:01:14 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49552 ; free virtual = 54565
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 282
+ Number of Nodes with overlaps = 14
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.478  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 4.1 Global Iteration 0 | Checksum: 216154ec7
+
+Time (s): cpu = 00:01:42 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+Phase 4 Rip-up And Reroute | Checksum: 216154ec7
+
+Time (s): cpu = 00:01:42 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 5 Delay and Skew Optimization
+
+Phase 5.1 Delay CleanUp
+Phase 5.1 Delay CleanUp | Checksum: 216154ec7
+
+Time (s): cpu = 00:01:42 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 5.2 Clock Skew Optimization
+Phase 5.2 Clock Skew Optimization | Checksum: 216154ec7
+
+Time (s): cpu = 00:01:42 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+Phase 5 Delay and Skew Optimization | Checksum: 216154ec7
+
+Time (s): cpu = 00:01:42 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 1838e7ae8
+
+Time (s): cpu = 00:01:43 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.478  | TNS=0.000  | WHS=0.034  | THS=0.000  |
+
+Phase 6.1 Hold Fix Iter | Checksum: 2460eece7
+
+Time (s): cpu = 00:01:43 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+Phase 6 Post Hold Fix | Checksum: 2460eece7
+
+Time (s): cpu = 00:01:43 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.264764 %
+  Global Horizontal Routing Utilization  = 0.306841 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 7 Route finalize | Checksum: 1bf9f7771
+
+Time (s): cpu = 00:01:44 ; elapsed = 00:01:17 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: 1bf9f7771
+
+Time (s): cpu = 00:01:44 ; elapsed = 00:01:17 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 1aee248e0
+
+Time (s): cpu = 00:01:44 ; elapsed = 00:01:17 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 10 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.478  | TNS=0.000  | WHS=0.034  | THS=0.000  |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 10 Post Router Timing | Checksum: 1aee248e0
+
+Time (s): cpu = 00:01:46 ; elapsed = 00:01:17 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+INFO: [Route 35-16] Router Completed Successfully
+
+Phase 11 Post-Route Event Processing
+Phase 11 Post-Route Event Processing | Checksum: 1a4605fd7
+
+Time (s): cpu = 00:01:46 ; elapsed = 00:01:18 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Time (s): cpu = 00:01:46 ; elapsed = 00:01:18 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+108 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:01:49 ; elapsed = 00:01:19 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+INFO: [runtcl-4] Executing : report_drc -file fpga_drc_routed.rpt -pb fpga_drc_routed.pb -rpx fpga_drc_routed.rpx
+Command: report_drc -file fpga_drc_routed.rpt -pb fpga_drc_routed.pb -rpx fpga_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file fpga_methodology_drc_routed.rpt -pb fpga_methodology_drc_routed.pb -rpx fpga_methodology_drc_routed.rpx
+Command: report_methodology -file fpga_methodology_drc_routed.rpt -pb fpga_methodology_drc_routed.pb -rpx fpga_methodology_drc_routed.rpx
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file fpga_power_routed.rpt -pb fpga_power_summary_routed.pb -rpx fpga_power_routed.rpx
+Command: report_power -file fpga_power_routed.rpt -pb fpga_power_summary_routed.pb -rpx fpga_power_routed.rpx
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+122 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file fpga_route_status.rpt -pb fpga_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fpga_timing_summary_routed.rpt -pb fpga_timing_summary_routed.pb -rpx fpga_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
+INFO: [runtcl-4] Executing : report_incremental_reuse -file fpga_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file fpga_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fpga_bus_skew_routed.rpt -pb fpga_bus_skew_routed.pb -rpx fpga_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.53 . Memory (MB): peak = 3259.484 ; gain = 0.000 ; free physical = 49506 ; free virtual = 54529
+INFO: [Common 17-1381] The checkpoint '/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_routed.dcp' has been generated.
+INFO: [Common 17-206] Exiting Vivado at Wed Jan  8 11:27:42 2025...
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_bus_skew_routed.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_bus_skew_routed.pb
new file mode 100644
index 000000000..65d04b1ea
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_bus_skew_routed.pb
@@ -0,0 +1,2 @@
+
+2018.1’Bus skew results˜¥]Øâ@
\ No newline at end of file
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_bus_skew_routed.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_bus_skew_routed.rpt
new file mode 100644
index 000000000..15ade8a8a
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_bus_skew_routed.rpt
@@ -0,0 +1,477 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:27:41 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_bus_skew -warn_on_violation -file fpga_bus_skew_routed.rpt -pb fpga_bus_skew_routed.pb -rpx fpga_bus_skew_routed.rpx
+| Design       : fpga
+| Device       : 7a200t-fbg484
+| Speed File   : -2  PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+Table of Contents
+-----------------
+1. Bus Skew Report Summary
+2. Bus Skew Report Per Constraint
+
+1. Bus Skew Report Summary
+--------------------------
+
+Id  Position  From                            To                              Corner  Requirement(ns)  Actual(ns)  Slack(ns)
+--  --------  ------------------------------  ------------------------------  ------  ---------------  ----------  ---------
+1   16        [get_cells {{core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_reg_reg[*]} {core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[*]}}]
+                                              [get_cells {core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[*]}]
+                                                                              Slow              8.000       0.810      7.190
+2   18        [get_cells -quiet {core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[*]}]
+                                              [get_cells {core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[*]}]
+                                                                              Slow              8.000       0.911      7.089
+3   24        [get_cells {{core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_reg_reg[*]} {core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[*]}}]
+                                              [get_cells {core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[*]}]
+                                                                              Slow              8.000       0.762      7.238
+4   26        [get_cells -quiet {core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[*]}]
+                                              [get_cells {core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[*]}]
+                                                                              Slow              8.000       0.820      7.180
+
+
+2. Bus Skew Report Per Constraint
+---------------------------------
+
+Id: 1
+set_bus_skew -from [get_cells {{core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_reg_reg[*]} {core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[*]}}] -to [get_cells {core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[*]}] 8.000
+Requirement: 8.000ns
+Endpoints: 13
+
+From Clock            To Clock              Endpoint Pin                    Reference Pin                   Corner  Actual(ns)  Slack(ns)
+--------------------  --------------------  ------------------------------  ------------------------------  ------  ----------  ---------
+clk_mmcm_out          phy_rx_clk            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/D
+                                                                            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[5]/D
+                                                                                                            Slow         0.810      7.190
+
+
+Slack (MET) :             7.190ns  (requirement - actual skew)
+  Endpoint Source:        core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[8]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Endpoint Destination:   core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk)
+  Reference Source:       core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[5]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Reference Destination:  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[5]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk)
+  Path Type:              Bus Skew (Max at Slow Process Corner)
+  Requirement:            8.000ns
+  Endpoint Relative Delay:    3.774ns
+  Reference Relative Delay:   2.555ns
+  Relative CRPR:              0.409ns
+  Actual Bus Skew:            0.810ns  (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR)
+
+Endpoint path:
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.725     5.315    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X7Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[8]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y210         FDRE (Prop_fdre_C_Q)         0.348     5.663 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[8]/Q
+                         net (fo=1, routed)           0.637     6.300    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[8]
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     1.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     1.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362     2.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.619     2.736    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/C
+                         clock pessimism              0.000     2.736    
+    SLICE_X5Y211         FDRE (Setup_fdre_C_D)       -0.210     2.526    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]
+  -------------------------------------------------------------------
+                         data arrival                           6.300    
+                         clock arrival                          2.526    
+  -------------------------------------------------------------------
+                         relative delay                         3.774    
+
+Reference path:
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.610     5.021    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X7Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[5]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y209         FDRE (Prop_fdre_C_Q)         0.304     5.325 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[5]/Q
+                         net (fo=1, routed)           0.324     5.648    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[5]
+    SLICE_X6Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[5]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.665     2.904    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[5]/C
+                         clock pessimism              0.000     2.904    
+    SLICE_X6Y211         FDRE (Hold_fdre_C_D)         0.189     3.093    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[5]
+  -------------------------------------------------------------------
+                         data arrival                           5.648    
+                         clock arrival                          3.093    
+  -------------------------------------------------------------------
+                         relative delay                         2.555    
+
+
+
+Id: 2
+set_bus_skew -from [get_cells -quiet {core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[*]}] -to [get_cells {core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[*]}] 8.000
+Requirement: 8.000ns
+Endpoints: 13
+
+From Clock            To Clock              Endpoint Pin                    Reference Pin                   Corner  Actual(ns)  Slack(ns)
+--------------------  --------------------  ------------------------------  ------------------------------  ------  ----------  ---------
+phy_rx_clk            clk_mmcm_out          core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[12]/D
+                                                                            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/D
+                                                                                                            Slow         0.911      7.089
+
+
+Slack (MET) :             7.089ns  (requirement - actual skew)
+  Endpoint Source:        core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[12]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk)
+  Endpoint Destination:   core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[12]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Reference Source:       core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk)
+  Reference Destination:  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Path Type:              Bus Skew (Max at Slow Process Corner)
+  Requirement:            8.000ns
+  Endpoint Relative Delay:   -0.881ns
+  Reference Relative Delay:  -2.167ns
+  Relative CRPR:              0.375ns
+  Actual Bus Skew:            0.911ns  (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR)
+
+Endpoint path:
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.664     2.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y213         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[12]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y213         FDRE (Prop_fdre_C_Q)         0.379     3.282 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[12]/Q
+                         net (fo=1, routed)           0.783     4.065    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]
+    SLICE_X5Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[12]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.609     5.020    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X5Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[12]/C
+                         clock pessimism              0.000     5.020    
+    SLICE_X5Y210         FDRE (Setup_fdre_C_D)       -0.074     4.946    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[12]
+  -------------------------------------------------------------------
+                         data arrival                           4.065    
+                         clock arrival                          4.946    
+  -------------------------------------------------------------------
+                         relative delay                        -0.881    
+
+Reference path:
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     1.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     1.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362     2.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.620     2.737    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.304     3.041 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/Q
+                         net (fo=1, routed)           0.314     3.355    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[2]
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.728     5.318    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/C
+                         clock pessimism              0.000     5.318    
+    SLICE_X2Y209         FDRE (Hold_fdre_C_D)         0.204     5.522    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]
+  -------------------------------------------------------------------
+                         data arrival                           3.355    
+                         clock arrival                          5.522    
+  -------------------------------------------------------------------
+                         relative delay                        -2.167    
+
+
+
+Id: 3
+set_bus_skew -from [get_cells {{core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_reg_reg[*]} {core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[*]}}] -to [get_cells {core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[*]}] 8.000
+Requirement: 8.000ns
+Endpoints: 13
+
+From Clock            To Clock              Endpoint Pin                    Reference Pin                   Corner  Actual(ns)  Slack(ns)
+--------------------  --------------------  ------------------------------  ------------------------------  ------  ----------  ---------
+clk_mmcm_out          clk_mmcm_out          core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/D
+                                                                            core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/D
+                                                                                                            Slow         0.762      7.238
+
+
+Slack (MET) :             7.238ns  (requirement - actual skew)
+  Endpoint Source:        core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[9]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Endpoint Destination:   core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Reference Source:       core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Reference Destination:  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Path Type:              Bus Skew (Max at Slow Process Corner)
+  Requirement:            8.000ns
+  Endpoint Relative Delay:    1.195ns
+  Reference Relative Delay:   0.434ns
+  Relative CRPR:              0.000ns
+  Actual Bus Skew:            0.762ns  (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR)
+
+Endpoint path:
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.548     5.138    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X1Y185         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[9]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y185         FDRE (Prop_fdre_C_Q)         0.348     5.486 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[9]/Q
+                         net (fo=1, routed)           0.613     6.099    core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg[9]
+    SLICE_X0Y185         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.442     4.853    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X0Y185         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/C
+                         clock pessimism              0.261     5.114    
+    SLICE_X0Y185         FDRE (Setup_fdre_C_D)       -0.210     4.904    core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]
+  -------------------------------------------------------------------
+                         data arrival                           6.099    
+                         clock arrival                          4.904    
+  -------------------------------------------------------------------
+                         relative delay                         1.195    
+
+Reference path:
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.438     4.849    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X4Y184         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y184         FDRE (Prop_fdre_C_Q)         0.304     5.153 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[7]/Q
+                         net (fo=1, routed)           0.293     5.446    core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg[7]
+    SLICE_X4Y183         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.544     5.134    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X4Y183         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/C
+                         clock pessimism             -0.260     4.874    
+    SLICE_X4Y183         FDRE (Hold_fdre_C_D)         0.138     5.012    core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]
+  -------------------------------------------------------------------
+                         data arrival                           5.446    
+                         clock arrival                          5.012    
+  -------------------------------------------------------------------
+                         relative delay                         0.434    
+
+
+
+Id: 4
+set_bus_skew -from [get_cells -quiet {core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[*]}] -to [get_cells {core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[*]}] 8.000
+Requirement: 8.000ns
+Endpoints: 13
+
+From Clock            To Clock              Endpoint Pin                    Reference Pin                   Corner  Actual(ns)  Slack(ns)
+--------------------  --------------------  ------------------------------  ------------------------------  ------  ----------  ---------
+clk_mmcm_out          clk_mmcm_out          core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]/D
+                                                                            core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/D
+                                                                                                            Slow         0.820      7.180
+
+
+Slack (MET) :             7.180ns  (requirement - actual skew)
+  Endpoint Source:        core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Endpoint Destination:   core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Reference Source:       core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Reference Destination:  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out)
+  Path Type:              Bus Skew (Max at Slow Process Corner)
+  Requirement:            8.000ns
+  Endpoint Relative Delay:    1.249ns
+  Reference Relative Delay:   0.404ns
+  Relative CRPR:              0.024ns
+  Actual Bus Skew:            0.820ns  (Endpoint Relative Delay - Reference Relative Delay - Relative CRPR)
+
+Endpoint path:
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.551     5.141    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X3Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y187         FDRE (Prop_fdre_C_Q)         0.348     5.489 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[7]/Q
+                         net (fo=1, routed)           0.667     6.155    core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg[7]
+    SLICE_X1Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.444     4.855    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X1Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]/C
+                         clock pessimism              0.259     5.114    
+    SLICE_X1Y187         FDRE (Setup_fdre_C_D)       -0.207     4.907    core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]
+  -------------------------------------------------------------------
+                         data arrival                           6.155    
+                         clock arrival                          4.907    
+  -------------------------------------------------------------------
+                         relative delay                         1.249    
+
+Reference path:
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.444     4.855    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X3Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y187         FDRE (Prop_fdre_C_Q)         0.304     5.159 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/Q
+                         net (fo=1, routed)           0.313     5.472    core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg[2]
+    SLICE_X2Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.551     5.141    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X2Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/C
+                         clock pessimism             -0.262     4.879    
+    SLICE_X2Y187         FDRE (Hold_fdre_C_D)         0.189     5.068    core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]
+  -------------------------------------------------------------------
+                         data arrival                           5.472    
+                         clock arrival                          5.068    
+  -------------------------------------------------------------------
+                         relative delay                         0.404    
+
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_bus_skew_routed.rpx b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_bus_skew_routed.rpx
new file mode 100644
index 000000000..7d20be480
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_bus_skew_routed.rpx differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_clock_utilization_routed.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_clock_utilization_routed.rpt
new file mode 100644
index 000000000..4eb5bf7a4
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_clock_utilization_routed.rpt
@@ -0,0 +1,285 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:27:41 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_clock_utilization -file fpga_clock_utilization_routed.rpt
+| Design       : fpga
+| Device       : 7a200t-fbg484
+| Speed File   : -2  PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Clock Regions: Key Resource Utilization
+5. Clock Regions : Global Clock Summary
+6. Device Cell Placement Summary for Global Clock g0
+7. Device Cell Placement Summary for Global Clock g1
+8. Device Cell Placement Summary for Global Clock g2
+9. Device Cell Placement Summary for Global Clock g3
+10. Clock Region Cell Placement per Global Clock: Region X0Y3
+11. Clock Region Cell Placement per Global Clock: Region X0Y4
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type     | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL |    3 |        32 |   0 |            0 |      0 |
+| BUFH     |    0 |       120 |   0 |            0 |      0 |
+| BUFIO    |    1 |        40 |   1 |            0 |      0 |
+| BUFMR    |    0 |        20 |   0 |            0 |      0 |
+| BUFR     |    1 |        40 |   0 |            0 |      0 |
+| MMCM     |    1 |        10 |   0 |            0 |      0 |
+| PLL      |    0 |        10 |   0 |            0 |      0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site          | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock            | Driver Pin                                                                                 | Net                                                                                        |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+
+| g0        | src0      | BUFG/O          | None       | BUFGCTRL_X0Y0 | n/a          |                 2 |        2606 |               0 |        8.000 | clk_mmcm_out     | clk_bufg_inst/O                                                                            | clk_int                                                                                    |
+| g1        | src1      | BUFR/O          | None       | BUFR_X0Y17    | X0Y4         |                 1 |         195 |               0 |        8.000 | phy_rx_clk       | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk |
+| g2        | src2      | BUFG/O          | None       | BUFGCTRL_X0Y1 | n/a          |                 1 |           1 |               0 |        8.000 | clk90_mmcm_out   | clk90_bufg_inst/O                                                                          | clk90_int                                                                                  |
+| g3        | src3      | BUFG/O          | None       | BUFGCTRL_X0Y2 | n/a          |                 1 |           1 |               0 |        5.000 | clk_200_mmcm_out | clk_200_bufg_inst/O                                                                        | clk_200_int                                                                                |
++-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------------+--------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+--------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------+------------------------+------------------+
+| Source Id | Global Id | Driver Type/Pin    | Constraint | Site            | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock     | Driver Pin             | Net              |
++-----------+-----------+--------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------+------------------------+------------------+
+| src0      | g0        | MMCME2_ADV/CLKOUT0 | None       | MMCME2_ADV_X1Y2 | X1Y2         |           1 |               0 |               8.000 | clk_mmcm_out     | clk_mmcm_inst/CLKOUT0  | clk_mmcm_out     |
+| src1      | g1        | IBUF/O             | IOB_X0Y228 | IOB_X0Y228      | X0Y4         |           2 |               0 |               8.000 | phy_rx_clk       | phy_rx_clk_IBUF_inst/O | phy_rx_clk_IBUF  |
+| src2      | g2        | MMCME2_ADV/CLKOUT1 | None       | MMCME2_ADV_X1Y2 | X1Y2         |           1 |               0 |               8.000 | clk90_mmcm_out   | clk_mmcm_inst/CLKOUT1  | clk90_mmcm_out   |
+| src3      | g3        | MMCME2_ADV/CLKOUT2 | None       | MMCME2_ADV_X1Y2 | X1Y2         |           1 |               0 |               5.000 | clk_200_mmcm_out | clk_mmcm_inst/CLKOUT2  | clk_200_mmcm_out |
++-----------+-----------+--------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+------------------+------------------------+------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+4. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+|                   | Global Clock |     BUFRs    |    BUFMRs    |    BUFIOs    |     MMCM     |      PLL     |      GT      |      PCI     |    ILOGIC    |    OLOGIC    |      FF      |     LUTM     |    RAMB18    |    RAMB36    |    DSP48E2   |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     4 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  2700 |    0 |   800 |    0 |    60 |    0 |    30 |    0 |    60 |
+| X1Y0              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     4 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  2500 |    0 |   800 |    0 |    40 |    0 |    20 |    0 |    40 |
+| X0Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  4200 |    0 |  1400 |    0 |   100 |    0 |    50 |    0 |   100 |
+| X1Y1              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  4000 |    0 |  1400 |    0 |    80 |    0 |    40 |    0 |    80 |
+| X0Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  3600 |    0 |  1400 |    0 |   100 |    0 |    50 |    0 |   100 |
+| X1Y2              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  4000 |    0 |  1400 |    0 |    80 |    0 |    40 |    0 |    80 |
+| X0Y3              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 1119 |  3600 |  585 |  1400 |    0 |   100 |    4 |    50 |    0 |   100 |
+| X1Y3              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  4000 |    0 |  1400 |    0 |    80 |    0 |    40 |    0 |    80 |
+| X0Y4              |    5 |    12 |    1 |     4 |    0 |     2 |    1 |     4 |    0 |     1 |    0 |     1 |    0 |     4 |    0 |     1 |    5 |    50 |    6 |    50 | 1642 |  2550 |  493 |   750 |    0 |    50 |    2 |    25 |    0 |    60 |
+| X1Y4              |    0 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     4 |    0 |     0 |    0 |    50 |    0 |    50 |    0 |  2500 |    0 |   800 |    0 |    40 |    0 |    20 |    0 |    40 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+5. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+|    | X0 | X1 |
++----+----+----+
+| Y4 |  2 |  0 |
+| Y3 |  0 |  0 |
+| Y2 |  0 |  0 |
+| Y1 |  0 |  0 |
+| Y0 |  0 |  0 |
++----+----+----+
+
+
+6. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+---------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock        | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net     |
++-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+---------+
+| g0        | BUFG/O          | n/a               | clk_mmcm_out |       8.000 | {0.000 4.000} |        2583 |        0 |              0 |        0 | clk_int |
++-----------+-----------------+-------------------+--------------+-------------+---------------+-------------+----------+----------------+----------+---------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+-------+----+-----------------------+
+|    | X0    | X1 | HORIZONTAL PROG DELAY |
++----+-------+----+-----------------------+
+| Y4 |  1458 |  0 |                     0 |
+| Y3 |  1125 |  0 |                     0 |
+| Y2 |     0 |  0 |                     - |
+| Y1 |     0 |  0 |                     - |
+| Y0 |     0 |  0 |                     - |
++----+-------+----+-----------------------+
+
+
+7. Device Cell Placement Summary for Global Clock g1
+----------------------------------------------------
+
++-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------------------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock      | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net                                                                                        |
++-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------------------------------+
+| g1        | BUFR/O          | X0Y4              | phy_rx_clk |       8.000 | {0.000 4.000} |         195 |        0 |              0 |        0 | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk |
++-----------+-----------------+-------------------+------------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------------------------------------------------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----------+----+-----------------------+
+|    | X0       | X1 | HORIZONTAL PROG DELAY |
++----+----------+----+-----------------------+
+| Y4 |  (D) 195 |  0 |                     0 |
+| Y3 |        0 |  0 |                     - |
+| Y2 |        0 |  0 |                     - |
+| Y1 |        0 |  0 |                     - |
+| Y0 |        0 |  0 |                     - |
++----+----------+----+-----------------------+
+
+
+8. Device Cell Placement Summary for Global Clock g2
+----------------------------------------------------
+
++-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+-----------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock          | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net       |
++-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+-----------+
+| g2        | BUFG/O          | n/a               | clk90_mmcm_out |       8.000 | {2.000 6.000} |           1 |        0 |              0 |        0 | clk90_int |
++-----------+-----------------+-------------------+----------------+-------------+---------------+-------------+----------+----------------+----------+-----------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+----+-----------------------+
+|    | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+----+-----------------------+
+| Y4 |  1 |  0 |                     0 |
+| Y3 |  0 |  0 |                     - |
+| Y2 |  0 |  0 |                     - |
+| Y1 |  0 |  0 |                     - |
+| Y0 |  0 |  0 |                     - |
++----+----+----+-----------------------+
+
+
+9. Device Cell Placement Summary for Global Clock g3
+----------------------------------------------------
+
++-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock            | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net         |
++-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-------------+
+| g3        | BUFG/O          | n/a               | clk_200_mmcm_out |       5.000 | {0.000 2.500} |           1 |        0 |              0 |        0 | clk_200_int |
++-----------+-----------------+-------------------+------------------+-------------+---------------+-------------+----------+----------------+----------+-------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+----+-----------------------+
+|    | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+----+-----------------------+
+| Y4 |  1 |  0 |                     0 |
+| Y3 |  0 |  0 |                     - |
+| Y2 |  0 |  0 |                     - |
+| Y1 |  0 |  0 |                     - |
+| Y0 |  0 |  0 |                     - |
++----+----+----+-----------------------+
+
+
+10. Clock Region Cell Placement per Global Clock: Region X0Y3
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+---------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net     |
++-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+---------+
+| g0        | n/a   | BUFG/O          | None       |        1125 |               0 | 1119 |           0 |    4 |   0 |  0 |    0 |   0 |       0 | clk_int |
++-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+---------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+11. Clock Region Cell Placement per Global Clock: Region X0Y4
+-------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                                                                        |
++-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------+
+| g0        | n/a   | BUFG/O          | None       |        1458 |               0 | 1449 |           0 |    2 |   0 |  0 |    0 |   0 |       0 | clk_int                                                                                    |
+| g1        | n/a   | BUFR/O          | None       |         195 |               0 |  193 |           0 |    1 |   0 |  0 |    0 |   0 |       0 | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk |
+| g2        | n/a   | BUFG/O          | None       |           1 |               0 |    0 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | clk90_int                                                                                  |
+| g3        | n/a   | BUFG/O          | None       |           1 |               0 |    0 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | clk_200_int                                                                                |
++-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+--------------------------------------------------------------------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives 
+set_property LOC BUFGCTRL_X0Y0 [get_cells clk_bufg_inst]
+set_property LOC BUFGCTRL_X0Y2 [get_cells clk_200_bufg_inst]
+set_property LOC BUFGCTRL_X0Y1 [get_cells clk90_bufg_inst]
+
+# Location of BUFIO Primitives 
+set_property LOC BUFIO_X0Y19 [get_cells core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio]
+
+# Location of BUFR Primitives 
+set_property LOC BUFR_X0Y17 [get_cells core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr]
+
+# Location of IO Primitives which is load of clock spine
+
+# Location of clock ports
+set_property LOC IOB_X1Y124 [get_ports clk_p]
+set_property LOC IOB_X0Y228 [get_ports phy_rx_clk]
+
+# Clock net "core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk" driven by instance "core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr" located at site "BUFR_X0Y17"
+#startgroup
+create_pblock {CLKAG_core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk}
+add_cells_to_pblock [get_pblocks  {CLKAG_core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk}]]]
+resize_pblock [get_pblocks {CLKAG_core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk}] -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4}
+#endgroup
+
+# Clock net "clk_int" driven by instance "clk_bufg_inst" located at site "BUFGCTRL_X0Y0"
+#startgroup
+create_pblock {CLKAG_clk_int}
+add_cells_to_pblock [get_pblocks  {CLKAG_clk_int}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {clk_int}]]]
+resize_pblock [get_pblocks {CLKAG_clk_int}] -add {CLOCKREGION_X0Y3:CLOCKREGION_X0Y3 CLOCKREGION_X0Y4:CLOCKREGION_X0Y4}
+#endgroup
+
+# Clock net "clk_200_int" driven by instance "clk_200_bufg_inst" located at site "BUFGCTRL_X0Y2"
+#startgroup
+create_pblock {CLKAG_clk_200_int}
+add_cells_to_pblock [get_pblocks  {CLKAG_clk_200_int}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {clk_200_int}]]]
+resize_pblock [get_pblocks {CLKAG_clk_200_int}] -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4}
+#endgroup
+
+# Clock net "clk90_int" driven by instance "clk90_bufg_inst" located at site "BUFGCTRL_X0Y1"
+#startgroup
+create_pblock {CLKAG_clk90_int}
+add_cells_to_pblock [get_pblocks  {CLKAG_clk90_int}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -leaf -filter {DIRECTION==IN} -of_objects [get_nets {clk90_int}]]]
+resize_pblock [get_pblocks {CLKAG_clk90_int}] -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4}
+#endgroup
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_control_sets_placed.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_control_sets_placed.rpt
new file mode 100644
index 000000000..566faff60
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_control_sets_placed.rpt
@@ -0,0 +1,229 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:26:12 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_control_sets -verbose -file fpga_control_sets_placed.rpt
+| Design       : fpga
+| Device       : xc7a200t
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+|                          Status                          | Count |
++----------------------------------------------------------+-------+
+| Total control sets                                       |   151 |
+|    Minimum number of control sets                        |   151 |
+|    Addition due to synthesis replication                 |     0 |
+|    Addition due to physical synthesis replication        |     0 |
+| Unused register locations in slices containing registers |   343 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+|       Fanout       | Count |
++--------------------+-------+
+| Total control sets |   151 |
+| >= 0 to < 4        |     3 |
+| >= 4 to < 6        |    18 |
+| >= 6 to < 8        |     4 |
+| >= 8 to < 10       |    59 |
+| >= 10 to < 12      |    16 |
+| >= 12 to < 14      |     9 |
+| >= 14 to < 16      |     4 |
+| >= 16              |    38 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No           | No                    | No                     |              82 |           51 |
+| No           | No                    | Yes                    |              14 |            6 |
+| No           | Yes                   | No                     |             243 |          101 |
+| Yes          | No                    | No                     |            1795 |          494 |
+| Yes          | No                    | Yes                    |               0 |            0 |
+| Yes          | Yes                   | No                     |             627 |          179 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
+|                                         Clock Signal                                        |                                                   Enable Signal                                                   |                                                Set/Reset Signal                                               | Slice Load Count | Bel Load Count | Bels / Slice |
++---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/payload_fifo/state_reg_reg[1]                          |                                                                                                               |                1 |              1 |         1.00 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_min_count_reg[5]_i_2_n_0     | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_min_count_reg[5]_i_1_n_0 |                1 |              2 |         2.00 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_min_count_reg[5]_i_2_n_0     |                                                                                                               |                1 |              2 |         2.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/header_fifo_write0_out__14                             | sync_reset_inst/Q[0]                                                                                          |                2 |              4 |         2.00 |
+|  clk_int                                                                                    | core_inst/eth_axis_tx_inst/ptr_reg[3]_i_1__1_n_0                                                                  | sync_reset_inst/Q[0]                                                                                          |                2 |              4 |         2.00 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_en_reg_2[0]                           |                                                                                                               |                2 |              4 |         2.00 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_en_reg_2[0]                           | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_mii_select_sync_reg[1][0]                   |                1 |              4 |         4.00 |
+|  clk_int                                                                                    |                                                                                                                   | sync_reset_inst/rst0                                                                                          |                1 |              4 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_request_retry_cnt_reg[5]_i_2_n_0                        | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/sync_reg_reg[3]                          |                1 |              4 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/m_udp_length_reg[15]_i_1_n_0                           | sync_reset_inst/Q[0]                                                                                          |                2 |              4 |         2.00 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/speed_reg_reg[1]_inv[0]                            |                                                                                                               |                1 |              4 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0_i_1_n_0              |                                                                                                               |                1 |              4 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_128_255_0_0_i_1_n_0            |                                                                                                               |                1 |              4 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_256_383_0_0_i_1_n_0            |                                                                                                               |                1 |              4 |         4.00 |
+|  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk |                                                                                                                   | sync_reset_inst/Q[0]                                                                                          |                1 |              4 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_384_511_0_0_i_1_n_0            |                                                                                                               |                1 |              4 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_ptr_reg[5]_i_1_n_0                        |                                                                                                               |                2 |              5 |         2.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/ptr_reg[4]_i_2_n_0                          | core_inst/eth_axis_rx_inst/SR[0]                                                                              |                2 |              5 |         2.50 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_en_reg_1                              | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]_0[0]                         |                4 |              5 |         1.25 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_tx_inst/ptr_reg[4]_i_1_n_0                          | sync_reset_inst/Q[0]                                                                                          |                2 |              5 |         2.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_tx_inst/hdr_ptr_next                                  | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_tx_inst/hdr_ptr_reg[5]_i_1__0_n_0                 |                3 |              5 |         1.67 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/speed_int[1]                                                         | sync_reset_inst/Q[0]                                                                                          |                2 |              6 |         3.00 |
+|  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4                        | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]_0[0]                         |                2 |              7 |         3.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/cache_query_request_ip_next                                 | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/cache_query_request_ip_reg[7]_i_1_n_0                   |                2 |              7 |         3.50 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg[7]_i_2_n_0           | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg[7]_i_1_n_0       |                2 |              7 |         3.50 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/m_eth_src_mac_reg[39]_i_1_n_0                                                          |                                                                                                               |                1 |              8 |         8.00 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/m_eth_src_mac_reg[47]_i_1__0_n_0                                                       |                                                                                                               |                1 |              8 |         8.00 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/s_tdata_reg[7]_i_2_n_0             | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/s_tdata_reg[7]_i_1_n_0         |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/m_eth_type_reg[15]_i_1_n_0                                                             |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    |                                                                                                                   | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]_0[0]                         |                5 |              8 |         1.60 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_tx_inst/store_last_word                               |                                                                                                               |                4 |              8 |         2.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/ptr_reg_reg[2]_0[0]                         |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/m_eth_type_reg[7]_i_1_n_0                                                              |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_ptype_reg[7]_i_1_n_0                  |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_sha_reg[15]_i_1_n_0                   |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_tx_inst/store_last_word                                               |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_sha_reg[23]_i_1_n_0                   |                                                                                                               |                1 |              8 |         8.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/store_ip_length_1                             |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/store_udp_length_1                                            |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_spa_reg[23]_i_1_n_0                   |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/store_ip_length_0                             |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_spa_reg[15]_i_1_n_0                   |                                                                                                               |                1 |              8 |         8.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_sha_reg[7]_i_1_n_0                    |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_sha_reg[47]_i_1_n_0                   |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/store_udp_source_port_1                                       |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_udp_source_port_reg[7]_i_1_n_0                              |                                                                                                               |                1 |              8 |         8.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_sha_reg[39]_i_1_n_0                   |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_sha_reg[31]_i_1_n_0                   |                                                                                                               |                4 |              8 |         2.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/store_last_word                                               |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/store_udp_dest_port_0                                         |                                                                                                               |                1 |              8 |         8.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/store_udp_dest_port_1                                         |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/store_udp_length_0                                            |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/store_ip_protocol                             |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_spa_reg[7]_i_1_n_0                    |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_tha_reg[15]_i_1_n_0                   |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/store_ip_source_ip_0                          |                                                                                                               |                4 |              8 |         2.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_ptype_reg[15]_i_1_n_0                 |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/store_ip_source_ip_1                          |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/store_ip_source_ip_2                          |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/store_ip_source_ip_3                          |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/store_ip_version_ihl                          |                                                                                                               |                4 |              8 |         2.00 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/m_eth_src_mac_reg[23]_i_1_n_0                                                          |                                                                                                               |                1 |              8 |         8.00 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/m_eth_src_mac_reg[15]_i_1_n_0                                                          |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_tpa_reg[31]_i_1_n_0                   |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_tha_reg[47]_i_1_n_0                   |                                                                                                               |                1 |              8 |         8.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_tpa_reg[15]_i_1_n_0                   |                                                                                                               |                1 |              8 |         8.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_tpa_reg[23]_i_1_n_0                   |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_tha_reg[7]_i_1_n_0                    |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_tha_reg[31]_i_1_n_0                   |                                                                                                               |                1 |              8 |         8.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_tha_reg[39]_i_1_n_0                   |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_spa_reg[31]_i_1_n_0                   |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_tha_reg[23]_i_1_n_0                   |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_oper_reg[15]_i_1_n_0                  |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/store_last_word                               |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/m_eth_src_mac_reg[7]_i_1_n_0                                                           |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_oper_reg[7]_i_1_n_0                   |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_htype_reg[7]_i_1_n_0                  |                                                                                                               |                3 |              8 |         2.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_htype_reg[15]_i_1_n_0                 |                                                                                                               |                2 |              8 |         4.00 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/m_eth_src_mac_reg[31]_i_1_n_0                                                          |                                                                                                               |                1 |              8 |         8.00 |
+|  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk |                                                                                                                   | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/state_next1                    |                3 |              9 |         3.00 |
+|  clk_int                                                                                    |                                                                                                                   | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_speed_count_2                                                 |                3 |              9 |         3.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/wr_ptr_reg[8]_i_1_n_0                        | sync_reset_inst/Q[0]                                                                                          |                3 |              9 |         3.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/eth_arb_mux_inst/arb_inst/m_eth_payload_axis_tready_int_reg_reg_0[0] |                                                                                                               |                2 |              9 |         4.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/eth_arb_mux_inst/arb_inst/m_eth_payload_axis_tvalid_reg_reg[0]       |                                                                                                               |                2 |              9 |         4.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/temp_m_udp_payload_axis_tvalid_next29_out                     |                                                                                                               |                3 |             10 |         3.33 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_arb_mux_inst/temp_m_ip_payload_axis_tvalid_next0_out                               |                                                                                                               |                5 |             10 |         2.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/eth_arb_mux_inst/m_eth_payload_axis_tdata_reg[7]_i_1__1_n_0          |                                                                                                               |                4 |             10 |         2.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/eth_arb_mux_inst/temp_m_eth_payload_axis_tvalid_next0_out            |                                                                                                               |                2 |             10 |         5.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_payload_axis_tdata_reg[7]_i_1__0_n_0     |                                                                                                               |                3 |             10 |         3.33 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/store_eth_payload_int_to_temp                                                          |                                                                                                               |                2 |             10 |         5.00 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/tx_fifo/fifo_inst/m_axis_tready_int_reg_reg[0]                                             |                                                                                                               |                2 |             10 |         5.00 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/tx_fifo/fifo_inst/E[0]                                                                     |                                                                                                               |                3 |             10 |         3.33 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_arb_mux_inst/m_ip_payload_axis_tdata_reg[7]_i_1_n_0                                |                                                                                                               |                3 |             10 |         3.33 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/temp_m_ip_payload_axis_tvalid_next59_out      |                                                                                                               |                3 |             10 |         3.33 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_arb_mux_inst/arb_inst/E[0]                                                         |                                                                                                               |                4 |             10 |         2.50 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/m_eth_payload_axis_tdata_reg[7]_i_1__2_n_0                                             |                                                                                                               |                3 |             10 |         3.33 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/eth_arb_mux_inst/arb_inst/E[0]                                       |                                                                                                               |                2 |             10 |         5.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_tx_inst/m_ip_payload_axis_tdata_reg[7]_i_1__1_n_0                     |                                                                                                               |                4 |             10 |         2.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/eth_arb_mux_inst/arb_inst/grant_encoded_reg_reg[0]_4[0]              |                                                                                                               |                2 |             10 |         5.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_udp_payload_axis_tdata_reg[7]_i_1_n_0                       |                                                                                                               |                4 |             10 |         2.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/payload_fifo/p_0_in_0                                  | sync_reset_inst/Q[0]                                                                                          |                3 |             12 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_tx_inst/hdr_sum_next                                  | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_tx_inst/hdr_sum_reg[15]_i_1_n_0                   |                4 |             13 |         3.25 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/query_response_valid_reg_reg_2               | sync_reset_inst/Q[0]                                                                                          |                5 |             13 |         2.60 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg0                                                  | sync_reset_inst/Q[0]                                                                                          |                4 |             13 |         3.25 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1_n_0                                       | sync_reset_inst/SR[0]                                                                                         |                2 |             13 |         6.50 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg0                                                  | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]_0[0]                         |                3 |             13 |         4.33 |
+|  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk | core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0_n_0                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/SR[0]                                          |                3 |             13 |         4.33 |
+|  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk | core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg[12]_i_1_n_0                                            | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/SR[0]                                          |                3 |             13 |         4.33 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_reg[12]_i_1__0_n_0                                         | sync_reset_inst/SR[0]                                                                                         |                2 |             13 |         6.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/p_0_in_0                                                      | sync_reset_inst/Q[0]                                                                                          |                4 |             14 |         3.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_htype_reg_reg[10]_0                   |                                                                                                               |                4 |             14 |         3.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/payload_fifo/state_reg_reg[1]                          | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/payload_fifo/state_reg_reg[2]                      |                4 |             14 |         3.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/word_count_reg[15]_i_1_n_0                    |                                                                                                               |                3 |             15 |         5.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/read_eth_header_next16_out                  |                                                                                                               |                5 |             16 |         3.20 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_tx_inst/word_count_next                                               |                                                                                                               |                4 |             16 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_tx_inst/word_count_next                               |                                                                                                               |                8 |             16 |         2.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/word_count_next_0                                             |                                                                                                               |                5 |             16 |         3.20 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_ptr_reg[5]_i_1_n_0                        | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_ptr_reg[0]_i_1_n_0                    |                5 |             17 |         3.40 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_htype_reg_reg[10]_0                   | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/outgoing_arp_tha_next                    |                5 |             18 |         3.60 |
+|  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk |                                                                                                                   |                                                                                                               |                9 |             20 |         2.22 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/payload_fifo/rd_ptr_reg_rep[10]_i_1_n_0                | sync_reset_inst/Q[0]                                                                                          |                7 |             23 |         3.29 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_request_operation_reg                                   | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/sync_reg_reg[3]                          |                5 |             23 |         4.60 |
+|  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk | core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_reg__0                                                            | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/SR[0]                                          |                5 |             25 |         5.00 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_reg__0                                                            | sync_reset_inst/SR[0]                                                                                         |                8 |             25 |         3.12 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/query_request_ready_reg_reg_1                |                                                                                                               |                7 |             27 |         3.86 |
+|  clk_int                                                                                    | core_inst/udp_payload_fifo/rd_ptr_reg_rep[12]_i_1_n_0                                                             | sync_reset_inst/Q[0]                                                                                          |                8 |             27 |         3.38 |
+|  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tvalid_reg_i_1_n_0          | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/reset_crc7_out                 |                8 |             32 |         4.00 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/payload_fifo/E[0]                                      |                                                                                                               |               15 |             32 |         2.13 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/store_ip_hdr                                                  |                                                                                                               |                9 |             32 |         3.56 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/update_crc4_out                    | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/crc_state[31]_i_1__0_n_0       |               11 |             32 |         2.91 |
+|  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk |                                                                                                                   | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]_0[0]                         |                9 |             34 |         3.78 |
+|  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/output_clk | core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4                        |                                                                                                               |                7 |             36 |         5.14 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_reg_rep[11]_i_2__0_n_0                                            | sync_reset_inst/rd_ptr_gray_reg                                                                               |               10 |             38 |         3.80 |
+|  clk_int                                                                                    | core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_reg_rep[11]_i_2_n_0                                               | core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_0                                                    |               10 |             38 |         3.80 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/outgoing_eth_dest_mac_next                                   |                                                                                                               |               10 |             48 |         4.80 |
+|  clk_int                                                                                    |                                                                                                                   | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_response_mac_reg[47]_i_1_n_0                        |               16 |             48 |         3.00 |
+|  clk_int                                                                                    | core_inst/eth_axis_rx_inst/m_eth_hdr_valid_reg_reg_1[0]                                                           |                                                                                                               |                9 |             49 |         5.44 |
+|  clk_int                                                                                    | core_inst/eth_axis_tx_inst/store_eth_hdr                                                                          |                                                                                                               |               13 |             50 |         3.85 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/eth_arb_mux_inst/arb_inst/frame_reg0                                 |                                                                                                               |               10 |             50 |         5.00 |
+|  clk_int                                                                                    |                                                                                                                   |                                                                                                               |               42 |             62 |         1.48 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_arb_mux_inst/arb_inst/grant_valid_reg_reg_2[0]                                     |                                                                                                               |               20 |             63 |         3.15 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/store_udp_hdr                                          |                                                                                                               |               24 |             65 |         2.71 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/store_write                                  |                                                                                                               |               18 |             80 |         4.44 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_htype_reg_reg[10]_1[0]                |                                                                                                               |               27 |             80 |         2.96 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_rx_inst/m_arp_oper_reg_reg[1]_0[0]                  | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/outgoing_arp_tha_next                    |               27 |             99 |         3.67 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/m_udp_length_reg[15]_i_1_n_0                           |                                                                                                               |               19 |            110 |         5.79 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_tx_inst/store_ip_hdr                                  |                                                                                                               |               37 |            112 |         3.03 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_ip_tx_inst/store_udp_hdr                                                 |                                                                                                               |               36 |            126 |         3.50 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_eth_tx_inst/store_frame                                 |                                                                                                               |               31 |            132 |         4.26 |
+|  clk_int                                                                                    |                                                                                                                   | sync_reset_inst/Q[0]                                                                                          |               69 |            141 |         2.04 |
+|  clk_int                                                                                    | core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/header_fifo_write0_out__14                             |                                                                                                               |               19 |            152 |         8.00 |
++---------------------------------------------------------------------------------------------+-------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.pb
new file mode 100644
index 000000000..8ebaa7886
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.rpt
new file mode 100644
index 000000000..681e347c2
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.rpt
@@ -0,0 +1,35 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:25:53 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_drc -file fpga_drc_opted.rpt -pb fpga_drc_opted.pb -rpx fpga_drc_opted.rpx
+| Design       : fpga
+| Device       : xc7a200tfbg484-2
+| Speed File   : -2
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 0
++------+----------+-------------+------------+
+| Rule | Severity | Description | Violations |
++------+----------+-------------+------------+
++------+----------+-------------+------------+
+
+2. REPORT DETAILS
+-----------------
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.rpx b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.rpx
new file mode 100644
index 000000000..06cbbd6a5
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.rpx differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.pb
new file mode 100644
index 000000000..8ebaa7886
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.rpt
new file mode 100644
index 000000000..0321fa4b5
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.rpt
@@ -0,0 +1,35 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:27:34 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_drc -file fpga_drc_routed.rpt -pb fpga_drc_routed.pb -rpx fpga_drc_routed.rpx
+| Design       : fpga
+| Device       : xc7a200tfbg484-2
+| Speed File   : -2
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+           Ruledeck: default
+             Max violations: <unlimited>
+             Violations found: 0
++------+----------+-------------+------------+
+| Rule | Severity | Description | Violations |
++------+----------+-------------+------------+
++------+----------+-------------+------------+
+
+2. REPORT DETAILS
+-----------------
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.rpx b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.rpx
new file mode 100644
index 000000000..030c55db8
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.rpx differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_io_placed.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_io_placed.rpt
new file mode 100644
index 000000000..27e492f16
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_io_placed.rpt
@@ -0,0 +1,526 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version              : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date                      : Wed Jan  8 11:26:11 2025
+| Host                      : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command                   : report_io -file fpga_io_placed.rpt
+| Design                    : fpga
+| Device                    : xc7a200t
+| Speed File                : -2
+| Package                   : fbg484
+| Package Version           : FINAL 2012-11-08
+| Package Pin Delay Version : VERS. 2.0 2012-11-08
+----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+|            16 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type  | Pin Name                     | Use           | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1         |             | High Range | IO_L1N_T0_AD4N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A4         |             |            | MGTPTXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A6         |             |            | MGTPTXN2_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A8         |             |            | MGTPRXN0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A10        |             |            | MGTPRXN2_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| A13        |             | High Range | IO_L10P_T1_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A14        |             | High Range | IO_L10N_T1_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A15        | phy_rx_ctl  | High Range | IO_L9P_T1_DQS_16             | INPUT         | LVCMOS33    |      16 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| A16        | phy_rxd[0]  | High Range | IO_L9N_T1_DQS_16             | INPUT         | LVCMOS33    |      16 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| A17        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| A18        | phy_txd[3]  | High Range | IO_L17P_T2_16                | OUTPUT        | LVCMOS33    |      16 |         16 | FAST |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| A19        | phy_txd[2]  | High Range | IO_L17N_T2_16                | OUTPUT        | LVCMOS33    |      16 |         16 | FAST |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| A20        |             | High Range | IO_L16N_T2_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A21        |             | High Range | IO_L21N_T3_DQS_16            | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| A22        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| AA1        |             | High Range | IO_L7P_T1_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA2        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| AA3        |             | High Range | IO_L9N_T1_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA4        |             | High Range | IO_L11N_T1_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA5        |             | High Range | IO_L10P_T1_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA6        |             | High Range | IO_L18N_T2_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA7        |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    1.50 |            |           |          |      |                  |              |                   |              |
+| AA8        |             | High Range | IO_L22P_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA9        |             | High Range | IO_L8P_T1_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA10       |             | High Range | IO_L9P_T1_DQS_13             | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA11       |             | High Range | IO_L9N_T1_DQS_13             | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA12       |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| AA13       |             | High Range | IO_L3P_T0_DQS_13             | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA14       |             | High Range | IO_L5N_T0_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA15       |             | High Range | IO_L4P_T0_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA16       |             | High Range | IO_L1N_T0_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA17       |             | High Range | VCCO_13                      | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| AA18       |             | High Range | IO_L17P_T2_A14_D30_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA19       |             | High Range | IO_L15P_T2_DQS_RDWR_B_14     | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA20       |             | High Range | IO_L8P_T1_D11_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA21       |             | High Range | IO_L8N_T1_D12_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AA22       |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| AB1        |             | High Range | IO_L7N_T1_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB2        |             | High Range | IO_L8N_T1_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB3        |             | High Range | IO_L8P_T1_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB4        |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    1.50 |            |           |          |      |                  |              |                   |              |
+| AB5        |             | High Range | IO_L10N_T1_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB6        |             | High Range | IO_L20N_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB7        |             | High Range | IO_L20P_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB8        |             | High Range | IO_L22N_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB9        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| AB10       |             | High Range | IO_L8N_T1_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB11       |             | High Range | IO_L7P_T1_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB12       |             | High Range | IO_L7N_T1_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB13       |             | High Range | IO_L3N_T0_DQS_13             | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB14       |             | High Range | VCCO_13                      | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| AB15       |             | High Range | IO_L4N_T0_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB16       |             | High Range | IO_L2P_T0_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB17       |             | High Range | IO_L2N_T0_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB18       |             | High Range | IO_L17N_T2_A13_D29_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB19       |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| AB20       |             | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB21       |             | High Range | IO_L10P_T1_D14_14            | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| AB22       |             | High Range | IO_L10N_T1_D15_14            | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B1         |             | High Range | IO_L1P_T0_AD4P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B2         |             | High Range | IO_L2N_T0_AD12N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B4         |             |            | MGTPTXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B5         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B6         |             |            | MGTPTXP2_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B7         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B8         |             |            | MGTPRXP0_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B9         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B10        |             |            | MGTPRXP2_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B11        |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B13        |             | High Range | IO_L8N_T1_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B14        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| B15        |             | High Range | IO_L7P_T1_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B16        |             | High Range | IO_L7N_T1_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B17        | phy_rx_clk  | High Range | IO_L11P_T1_SRCC_16           | INPUT         | LVCMOS33    |      16 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| B18        | phy_rxd[1]  | High Range | IO_L11N_T1_SRCC_16           | INPUT         | LVCMOS33    |      16 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| B19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| B20        |             | High Range | IO_L16P_T2_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B21        |             | High Range | IO_L21P_T3_DQS_16            | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| B22        |             | High Range | IO_L20N_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C1         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| C2         |             | High Range | IO_L2P_T0_AD12P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C4         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C5         |             |            | MGTPTXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C6         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C7         |             |            | MGTPTXN3_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C8         |             |            | MGTAVTT                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C9         |             |            | MGTPRXN3_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C10        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C11        |             |            | MGTPRXN1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C13        |             | High Range | IO_L8P_T1_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C14        |             | High Range | IO_L3P_T0_DQS_16             | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C15        |             | High Range | IO_L3N_T0_DQS_16             | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C16        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| C17        |             | High Range | IO_L12N_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| C18        | phy_rxd[2]  | High Range | IO_L13P_T2_MRCC_16           | INPUT         | LVCMOS33    |      16 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| C19        | phy_rxd[3]  | High Range | IO_L13N_T2_MRCC_16           | INPUT         | LVCMOS33    |      16 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| C20        | phy_txd[0]  | High Range | IO_L19N_T3_VREF_16           | OUTPUT        | LVCMOS33    |      16 |         16 | FAST |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| C21        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| C22        |             | High Range | IO_L20P_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D1         |             | High Range | IO_L3N_T0_DQS_AD5N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D2         |             | High Range | IO_L4N_T0_35                 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D4         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D5         |             |            | MGTPTXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D6         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D7         |             |            | MGTPTXP3_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D9         |             |            | MGTPRXP3_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D10        |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D11        |             |            | MGTPRXP1_216                 | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D13        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| D14        |             | High Range | IO_L6P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D15        |             | High Range | IO_L6N_T0_VREF_16            | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D16        | phy_reset_n | High Range | IO_L5N_T0_16                 | OUTPUT        | LVCMOS33    |      16 |         12 | SLOW |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| D17        |             | High Range | IO_L12P_T1_MRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D18        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| D19        |             | High Range | IO_L14N_T2_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D20        | phy_txd[1]  | High Range | IO_L19P_T3_16                | OUTPUT        | LVCMOS33    |      16 |         16 | FAST |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| D21        |             | High Range | IO_L23N_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| D22        |             | High Range | IO_L22N_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E1         |             | High Range | IO_L3P_T0_DQS_AD5P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E2         |             | High Range | IO_L4P_T0_35                 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E3         |             | High Range | IO_L6N_T0_VREF_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E4         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E6         |             |            | MGTREFCLK0N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E8         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E10        |             |            | MGTREFCLK1N_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E12        |             | Dedicated  | VCCBATT_0                    | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E13        |             | High Range | IO_L4P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E14        |             | High Range | IO_L4N_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E15        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| E16        |             | High Range | IO_L5P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E17        |             | High Range | IO_L2N_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E18        | phy_tx_clk  | High Range | IO_L15N_T2_DQS_16            | OUTPUT        | LVCMOS33    |      16 |         16 | FAST |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| E19        |             | High Range | IO_L14P_T2_SRCC_16           | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E20        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| E21        |             | High Range | IO_L23P_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| E22        |             | High Range | IO_L22P_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F1         |             | High Range | IO_L5N_T0_AD13N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F2         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| F3         |             | High Range | IO_L6P_T0_35                 | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F4         |             | High Range | IO_0_35                      | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F6         |             |            | MGTREFCLK0P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F7         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F8         |             |            | MGTRREF_216                  | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F9         |             |            | MGTAVCC                      | Gigabit Power |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F10        |             |            | MGTREFCLK1P_216              | Gigabit       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F12        |             | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| F13        |             | High Range | IO_L1P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F14        |             | High Range | IO_L1N_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F15        |             | High Range | IO_0_16                      | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F16        |             | High Range | IO_L2P_T0_16                 | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F17        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| F18        | phy_tx_ctl  | High Range | IO_L15P_T2_DQS_16            | OUTPUT        | LVCMOS33    |      16 |         16 | FAST |                     |            FP_VTT_50 |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| F19        |             | High Range | IO_L18P_T2_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F20        |             | High Range | IO_L18N_T2_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F21        |             | High Range | IO_25_16                     | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| F22        |             | High Range | VCCO_16                      | VCCO          |             |      16 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| G1         |             | High Range | IO_L5P_T0_AD13P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G2         |             | High Range | IO_L8N_T1_AD14N_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G3         |             | High Range | IO_L11N_T1_SRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G4         |             | High Range | IO_L12N_T1_MRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G6         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G10        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G11        |             | Dedicated  | DONE_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G13        |             | High Range | IO_L1N_T0_AD0N_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G14        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| G15        |             | High Range | IO_L2P_T0_AD8P_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G16        |             | High Range | IO_L2N_T0_AD8N_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G17        |             | High Range | IO_L4P_T0_15                 | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G18        |             | High Range | IO_L4N_T0_15                 | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G19        |             | High Range | VCCO_15                      | VCCO          |             |      15 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| G20        |             | High Range | IO_L8N_T1_AD10N_15           | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G21        |             | High Range | IO_L24P_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| G22        |             | High Range | IO_L24N_T3_16                | User IO       |             |      16 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H2         |             | High Range | IO_L8P_T1_AD14P_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H3         |             | High Range | IO_L11P_T1_SRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H4         |             | High Range | IO_L12P_T1_MRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H5         |             | High Range | IO_L10N_T1_AD15N_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H6         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| H7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H8         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H12        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| H13        |             | High Range | IO_L1P_T0_AD0P_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H14        |             | High Range | IO_L3N_T0_DQS_AD1N_15        | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H15        |             | High Range | IO_L5N_T0_AD9N_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H16        |             | High Range | VCCO_15                      | VCCO          |             |      15 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| H17        |             | High Range | IO_L6P_T0_15                 | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H18        |             | High Range | IO_L6N_T0_VREF_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H19        |             | High Range | IO_L12N_T1_MRCC_15           | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H20        |             | High Range | IO_L8P_T1_AD10P_15           | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| H21        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| H22        |             | High Range | IO_L7N_T1_AD2N_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J1         |             | High Range | IO_L7N_T1_AD6N_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J2         |             | High Range | IO_L9N_T1_DQS_AD7N_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J3         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| J4         |             | High Range | IO_L13N_T2_MRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J5         |             | High Range | IO_L10P_T1_AD15P_35          | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J6         |             | High Range | IO_L17N_T2_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J7         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J9         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J10        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J11        |             |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J13        |             | High Range | VCCO_15                      | VCCO          |             |      15 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| J14        |             | High Range | IO_L3P_T0_DQS_AD1P_15        | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J15        |             | High Range | IO_L5P_T0_AD9P_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J16        |             | High Range | IO_0_15                      | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J17        |             | High Range | IO_L21N_T3_DQS_A18_15        | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J18        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| J19        |             | High Range | IO_L12P_T1_MRCC_15           | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J20        |             | High Range | IO_L11P_T1_SRCC_15           | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J21        |             | High Range | IO_L11N_T1_SRCC_15           | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| J22        |             | High Range | IO_L7P_T1_AD2P_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K1         |             | High Range | IO_L7P_T1_AD6P_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K2         |             | High Range | IO_L9P_T1_DQS_AD7P_35        | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K3         |             | High Range | IO_L14N_T2_SRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K4         |             | High Range | IO_L13P_T2_MRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K6         |             | High Range | IO_L17P_T2_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K8         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K9         |             | Dedicated  | GNDADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K10        |             | Dedicated  | VCCADC_0                     | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K12        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| K13        |             | High Range | IO_L19P_T3_A22_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K14        |             | High Range | IO_L19N_T3_A21_VREF_15       | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K15        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| K16        |             | High Range | IO_L23N_T3_FWE_B_15          | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K17        |             | High Range | IO_L21P_T3_DQS_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K18        |             | High Range | IO_L13P_T2_MRCC_15           | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K19        |             | High Range | IO_L13N_T2_MRCC_15           | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K20        |             | High Range | VCCO_15                      | VCCO          |             |      15 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| K21        |             | High Range | IO_L9P_T1_DQS_AD3P_15        | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| K22        |             | High Range | IO_L9N_T1_DQS_AD3N_15        | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L1         |             | High Range | IO_L15N_T2_DQS_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L2         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L3         |             | High Range | IO_L14P_T2_SRCC_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L4         |             | High Range | IO_L18N_T2_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L5         |             | High Range | IO_L18P_T2_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L6         |             | High Range | IO_25_35                     | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L7         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| L9         |             | Dedicated  | VREFN_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L10        |             | Dedicated  | VP_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L11        |             |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L12        |             | Dedicated  | CCLK_0                       | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L13        |             | High Range | IO_L20N_T3_A19_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L14        |             | High Range | IO_L22P_T3_A17_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L15        |             | High Range | IO_L22N_T3_A16_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L16        |             | High Range | IO_L23P_T3_FOE_B_15          | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L17        |             | High Range | VCCO_15                      | VCCO          |             |      15 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| L18        |             | High Range | IO_L16N_T2_A27_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L19        |             | High Range | IO_L14P_T2_SRCC_15           | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L20        |             | High Range | IO_L14N_T2_SRCC_15           | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L21        |             | High Range | IO_L10N_T1_AD11N_15          | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| L22        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M1         |             | High Range | IO_L15P_T2_DQS_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M2         |             | High Range | IO_L16N_T2_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M3         |             | High Range | IO_L16P_T2_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M4         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| M5         |             | High Range | IO_L23N_T3_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M6         |             | High Range | IO_L23P_T3_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M8         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M9         |             | Dedicated  | VN_0                         | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M10        |             | Dedicated  | VREFP_0                      | XADC          |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M12        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| M13        |             | High Range | IO_L20P_T3_A20_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M14        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| M15        |             | High Range | IO_L24P_T3_RS1_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M16        |             | High Range | IO_L24N_T3_RS0_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M17        |             | High Range | IO_25_15                     | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M18        |             | High Range | IO_L16P_T2_A28_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M19        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| M20        |             | High Range | IO_L18N_T2_A23_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M21        |             | High Range | IO_L10P_T1_AD11P_15          | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| M22        |             | High Range | IO_L15N_T2_DQS_ADV_B_15      | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N1         |             | High Range | VCCO_35                      | VCCO          |             |      35 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| N2         |             | High Range | IO_L22N_T3_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N3         |             | High Range | IO_L19N_T3_VREF_35           | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N4         |             | High Range | IO_L19P_T3_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N5         |             | High Range | IO_L24N_T3_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N6         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N7         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N9         |             | Dedicated  | DXN_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N10        |             | Dedicated  | DXP_0                        | Temp Sensor   |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N11        |             |            | VCCBRAM                      | VCCBRAM       |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N12        |             | Dedicated  | PROGRAM_B_0                  | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N13        |             | High Range | IO_L23P_T3_A03_D19_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N14        |             | High Range | IO_L23N_T3_A02_D18_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N15        |             | High Range | IO_25_14                     | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N16        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| N17        |             | High Range | IO_L21P_T3_DQS_14            | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N18        |             | High Range | IO_L17P_T2_A26_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N19        |             | High Range | IO_L17N_T2_A25_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N20        |             | High Range | IO_L18P_T2_A24_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| N21        |             | High Range | VCCO_15                      | VCCO          |             |      15 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| N22        |             | High Range | IO_L15P_T2_DQS_15            | User IO       |             |      15 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P1         |             | High Range | IO_L20N_T3_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P2         |             | High Range | IO_L22P_T3_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P3         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P4         |             | High Range | IO_L21N_T3_DQS_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P5         |             | High Range | IO_L21P_T3_DQS_35            | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P6         |             | High Range | IO_L24P_T3_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P8         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P12        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| P13        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| P14        |             | High Range | IO_L19P_T3_A10_D26_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P15        |             | High Range | IO_L22P_T3_A05_D21_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P16        |             | High Range | IO_L24P_T3_A01_D17_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P17        |             | High Range | IO_L21N_T3_DQS_A06_D22_14    | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P18        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| P19        |             | High Range | IO_L5P_T0_D06_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P20        |             | High Range | IO_0_14                      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P21        |             | High Range | IO_L2P_T0_D02_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| P22        |             | High Range | IO_L1P_T0_D00_MOSI_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R1         |             | High Range | IO_L20P_T3_35                | User IO       |             |      35 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R2         |             | High Range | IO_L3N_T0_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R3         |             | High Range | IO_L3P_T0_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R4         | clk_p       | High Range | IO_L13P_T2_MRCC_34           | INPUT         | DIFF_SSTL15 |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| R5         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    1.50 |            |           |          |      |                  |              |                   |              |
+| R6         |             | High Range | IO_L17P_T2_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R7         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| R9         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R10        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| R11        |             |            | VCCAUX                       | VCCAUX        |             |         |            |      |                     |                      |    1.80 |            |           |          |      |                  |              |                   |              |
+| R12        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| R13        |             | Dedicated  | TDI_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R14        |             | High Range | IO_L19N_T3_A09_D25_VREF_14   | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R15        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| R16        |             | High Range | IO_L22N_T3_A04_D20_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R17        |             | High Range | IO_L24N_T3_A00_D16_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R18        |             | High Range | IO_L20P_T3_A08_D24_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R19        |             | High Range | IO_L5N_T0_D07_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R20        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| R21        |             | High Range | IO_L2N_T0_D03_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| R22        |             | High Range | IO_L1N_T0_D01_DIN_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T1         |             | High Range | IO_L1P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T2         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    1.50 |            |           |          |      |                  |              |                   |              |
+| T3         |             | High Range | IO_0_34                      | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T4         | clk_n       | High Range | IO_L13N_T2_MRCC_34           | INPUT         | DIFF_SSTL15 |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| T5         |             | High Range | IO_L14P_T2_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T6         | reset_n     | High Range | IO_L17N_T2_34                | INPUT         | LVCMOS15    |      34 |            |      |                     |                 NONE |         | FIXED      |           |          |      | NONE             |              |                   |              |
+| T7         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T8         |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T9         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T10        |             |            | VCCINT                       | VCCINT        |             |         |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T12        |             | Dedicated  | VCCO_0                       | VCCO          |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| T13        |             | Dedicated  | TMS_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T14        |             | High Range | IO_L15P_T2_DQS_13            | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T15        |             | High Range | IO_L15N_T2_DQS_13            | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T16        |             | High Range | IO_L17P_T2_13                | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T17        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| T18        |             | High Range | IO_L20N_T3_A07_D23_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T19        |             | High Range | IO_L6P_T0_FCS_B_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T20        |             | High Range | IO_L6N_T0_D08_VREF_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T21        |             | High Range | IO_L4P_T0_D04_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| T22        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| U1         |             | High Range | IO_L1N_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U2         |             | High Range | IO_L2P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U3         |             | High Range | IO_L6P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U4         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U5         |             | High Range | IO_L14N_T2_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U6         |             | High Range | IO_L16P_T2_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U7         |             | High Range | IO_25_34                     | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U8         |             | Dedicated  | CFGBVS_0                     | Config        |             |       0 |            |      |                     |                      |    3.30 |            |           |          |      |                  |              |                   |              |
+| U9         |             | Dedicated  | M2_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U10        |             | Dedicated  | M1_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U11        |             | Dedicated  | M0_0                         | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U12        |             | Dedicated  | INIT_B_0                     | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U13        |             | Dedicated  | TDO_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U14        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| U15        |             | High Range | IO_L14P_T2_SRCC_13           | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U16        |             | High Range | IO_L17N_T2_13                | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U17        |             | High Range | IO_L18P_T2_A12_D28_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U18        |             | High Range | IO_L18N_T2_A11_D27_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U19        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| U20        |             | High Range | IO_L11P_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U21        |             | High Range | IO_L4N_T0_D05_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| U22        |             | High Range | IO_L3P_T0_DQS_PUDC_B_14      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V1         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| V2         |             | High Range | IO_L2N_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V3         |             | High Range | IO_L6N_T0_VREF_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V4         |             | High Range | IO_L12P_T1_MRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V5         |             | High Range | IO_L16N_T2_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V6         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    1.50 |            |           |          |      |                  |              |                   |              |
+| V7         |             | High Range | IO_L19P_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V8         |             | High Range | IO_L21N_T3_DQS_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V9         |             | High Range | IO_L21P_T3_DQS_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V10        |             | High Range | IO_L10P_T1_13                | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V11        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| V12        |             | Dedicated  | TCK_0                        | Config        |             |       0 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V13        |             | High Range | IO_L13P_T2_MRCC_13           | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V14        |             | High Range | IO_L13N_T2_MRCC_13           | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V15        |             | High Range | IO_L14N_T2_SRCC_13           | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V16        |             | High Range | VCCO_13                      | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| V17        |             | High Range | IO_L16P_T2_CSI_B_14          | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V18        |             | High Range | IO_L14P_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V19        |             | High Range | IO_L14N_T2_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V20        |             | High Range | IO_L11N_T1_SRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| V21        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| V22        |             | High Range | IO_L3N_T0_DQS_EMCCLK_14      | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W1         |             | High Range | IO_L5P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W2         |             | High Range | IO_L4P_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W3         |             | High Range | VCCO_34                      | VCCO          |             |      34 |            |      |                     |                      |    1.50 |            |           |          |      |                  |              |                   |              |
+| W4         |             | High Range | IO_L12N_T1_MRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W5         |             | High Range | IO_L15N_T2_DQS_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W6         |             | High Range | IO_L15P_T2_DQS_34            | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W7         |             | High Range | IO_L19N_T3_VREF_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W8         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| W9         |             | High Range | IO_L24P_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W10        |             | High Range | IO_L10N_T1_13                | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W11        |             | High Range | IO_L12P_T1_MRCC_13           | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W12        |             | High Range | IO_L12N_T1_MRCC_13           | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W13        |             | High Range | VCCO_13                      | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| W14        |             | High Range | IO_L6P_T0_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W15        |             | High Range | IO_L16P_T2_13                | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W16        |             | High Range | IO_L16N_T2_13                | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W17        |             | High Range | IO_L16N_T2_A15_D31_14        | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W18        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| W19        |             | High Range | IO_L12P_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W20        |             | High Range | IO_L12N_T1_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W21        |             | High Range | IO_L7P_T1_D09_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| W22        |             | High Range | IO_L7N_T1_D10_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y1         |             | High Range | IO_L5N_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y2         |             | High Range | IO_L4N_T0_34                 | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y3         |             | High Range | IO_L9P_T1_DQS_34             | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y4         |             | High Range | IO_L11P_T1_SRCC_34           | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y5         |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| Y6         |             | High Range | IO_L18P_T2_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y7         |             | High Range | IO_L23N_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y8         |             | High Range | IO_L23P_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y9         |             | High Range | IO_L24N_T3_34                | User IO       |             |      34 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y10        |             | High Range | VCCO_13                      | VCCO          |             |      13 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| Y11        |             | High Range | IO_L11P_T1_SRCC_13           | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y12        |             | High Range | IO_L11N_T1_SRCC_13           | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y13        |             | High Range | IO_L5P_T0_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y14        |             | High Range | IO_L6N_T0_VREF_13            | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y15        |             |            | GND                          | GND           |             |         |            |      |                     |                      |     0.0 |            |           |          |      |                  |              |                   |              |
+| Y16        |             | High Range | IO_L1P_T0_13                 | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y17        |             | High Range | IO_0_13                      | User IO       |             |      13 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y18        |             | High Range | IO_L13P_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y19        |             | High Range | IO_L13N_T2_MRCC_14           | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y20        |             | High Range | VCCO_14                      | VCCO          |             |      14 |            |      |                     |                      |   any** |            |           |          |      |                  |              |                   |              |
+| Y21        |             | High Range | IO_L9P_T1_DQS_14             | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
+| Y22        |             | High Range | IO_L9N_T1_DQS_D13_14         | User IO       |             |      14 |            |      |                     |                      |         |            |           |          |      |                  |              |                   |              |
++------------+-------------+------------+------------------------------+---------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_methodology_drc_routed.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_methodology_drc_routed.pb
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index 000000000..ca92ea030
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diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_methodology_drc_routed.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_methodology_drc_routed.rpt
new file mode 100644
index 000000000..5b5343a86
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_methodology_drc_routed.rpt
@@ -0,0 +1,113 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:27:37 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_methodology -file fpga_methodology_drc_routed.rpt -pb fpga_methodology_drc_routed.pb -rpx fpga_methodology_drc_routed.rpx
+| Design       : fpga
+| Device       : xc7a200tfbg484-2
+| Speed File   : -2
+| Design State : Fully Routed
+--------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+            Netlist: netlist
+          Floorplan: design_1
+      Design limits: <entire design considered>
+             Max violations: <unlimited>
+             Violations found: 14
++-----------+----------+-----------------------------------------------------------+------------+
+| Rule      | Severity | Description                                               | Violations |
++-----------+----------+-----------------------------------------------------------+------------+
+| SYNTH-5   | Warning  | Mapped onto distributed RAM because of timing constraints | 4          |
+| SYNTH-16  | Warning  | Address collision                                         | 1          |
+| TIMING-11 | Warning  | Inappropriate max delay with datapath only option         | 2          |
+| TIMING-18 | Warning  | Missing input or output delay                             | 5          |
+| XDCH-2    | Warning  | Same min and max delay values on IO port                  | 2          |
++-----------+----------+-----------------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+SYNTH-5#1 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-5#2 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_128_255_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-5#3 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_256_383_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-5#4 Warning
+Mapped onto distributed RAM because of timing constraints  
+The instance core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_384_511_0_0 is implemented as distributed LUT RAM for the following reason: The timing constraints suggest that the chosen mapping will yield a better timing.
+Related violations: <none>
+
+SYNTH-16#1 Warning
+Address collision  
+Block RAM core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/ip_addr_mem_reg may get memory collision error if read and write address collide. Use of address collision resolution circuitry is recommended.
+Related violations: <none>
+
+TIMING-11#1 Warning
+Inappropriate max delay with datapath only option  
+A max delay constraint with -datapath_only has been applied between core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_1_reg/C and core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/D1. The startpoint(s) and endpoint(s) either belong to the same clock domain or belong to two clock domains that can safely be timed together (without valid synchronizer). It is only recommended to use the -datapath_only option on paths between clocks that do not have a known phase relationship. This DRC is waived when a synchronizer is found on the path endpoint
+Related violations: <none>
+
+TIMING-11#2 Warning
+Inappropriate max delay with datapath only option  
+A max delay constraint with -datapath_only has been applied between core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_2_reg/C and core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/D2. The startpoint(s) and endpoint(s) either belong to the same clock domain or belong to two clock domains that can safely be timed together (without valid synchronizer). It is only recommended to use the -datapath_only option on paths between clocks that do not have a known phase relationship. This DRC is waived when a synchronizer is found on the path endpoint
+Related violations: <none>
+
+TIMING-18#1 Warning
+Missing input or output delay  
+An input delay is missing on phy_rx_ctl relative to the rising and/or falling clock edge(s) of phy_rx_clk.
+Related violations: <none>
+
+TIMING-18#2 Warning
+Missing input or output delay  
+An input delay is missing on phy_rxd[0] relative to the rising and/or falling clock edge(s) of phy_rx_clk.
+Related violations: <none>
+
+TIMING-18#3 Warning
+Missing input or output delay  
+An input delay is missing on phy_rxd[1] relative to the rising and/or falling clock edge(s) of phy_rx_clk.
+Related violations: <none>
+
+TIMING-18#4 Warning
+Missing input or output delay  
+An input delay is missing on phy_rxd[2] relative to the rising and/or falling clock edge(s) of phy_rx_clk.
+Related violations: <none>
+
+TIMING-18#5 Warning
+Missing input or output delay  
+An input delay is missing on phy_rxd[3] relative to the rising and/or falling clock edge(s) of phy_rx_clk.
+Related violations: <none>
+
+XDCH-2#1 Warning
+Same min and max delay values on IO port  
+The same input delay of 0.000 ns has been defined on port 'reset_n' for both max and min. Make sure this reflects the design intent.
+set_input_delay 0.000 [get_ports reset_n]
+/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc (Line: 18)
+Related violations: <none>
+
+XDCH-2#2 Warning
+Same min and max delay values on IO port  
+The same output delay of 0.000 ns has been defined on port 'phy_reset_n' for both max and min. Make sure this reflects the design intent.
+set_output_delay 0.000 [get_ports phy_reset_n]
+/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc (Line: 50)
+Related violations: <none>
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_methodology_drc_routed.rpx b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_methodology_drc_routed.rpx
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diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_opt.dcp b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_opt.dcp
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diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_physopt.dcp b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_physopt.dcp
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diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_placed.dcp b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_placed.dcp
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diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_power_routed.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_power_routed.rpt
new file mode 100644
index 000000000..8f59c170b
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_power_routed.rpt
@@ -0,0 +1,163 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version     : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date             : Wed Jan  8 11:27:39 2025
+| Host             : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command          : report_power -file fpga_power_routed.rpt -pb fpga_power_summary_routed.pb -rpx fpga_power_routed.rpx
+| Design           : fpga
+| Device           : xc7a200tfbg484-2
+| Design State     : routed
+| Grade            : commercial
+| Process          : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W)  | 0.319        |
+| Design Power Budget (W)  | Unspecified* |
+| Power Budget Margin (W)  | NA           |
+| Dynamic (W)              | 0.180        |
+| Device Static (W)        | 0.139        |
+| Effective TJA (C/W)      | 2.5          |
+| Max Ambient (C)          | 84.2         |
+| Junction Temperature (C) | 25.8         |
+| Confidence Level         | Medium       |
+| Setting File             | ---          |
+| Simulation Activity File | ---          |
+| Design Nets Matched      | NA           |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++--------------------------+-----------+----------+-----------+-----------------+
+| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
++--------------------------+-----------+----------+-----------+-----------------+
+| Clocks                   |     0.014 |        8 |       --- |             --- |
+| Slice Logic              |     0.007 |     5299 |       --- |             --- |
+|   LUT as Logic           |     0.006 |     1725 |    133800 |            1.29 |
+|   CARRY4                 |    <0.001 |      200 |     33450 |            0.60 |
+|   Register               |    <0.001 |     2761 |    269200 |            1.03 |
+|   LUT as Distributed RAM |    <0.001 |       92 |     46200 |            0.20 |
+|   F7/F8 Muxes            |    <0.001 |       17 |    133800 |            0.01 |
+|   Others                 |     0.000 |       67 |       --- |             --- |
+| Signals                  |     0.008 |     4425 |       --- |             --- |
+| Block RAM                |     0.012 |        8 |       365 |            2.19 |
+| MMCM                     |     0.108 |        1 |        10 |           10.00 |
+| I/O                      |     0.031 |       16 |       285 |            5.61 |
+| Static Power             |     0.139 |          |           |                 |
+| Total                    |     0.319 |          |           |                 |
++--------------------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint    |       1.000 |     0.074 |       0.043 |      0.031 |       NA    | Unspecified | NA         |
+| Vccaux    |       1.800 |     0.094 |       0.063 |      0.031 |       NA    | Unspecified | NA         |
+| Vcco33    |       3.300 |     0.012 |       0.007 |      0.005 |       NA    | Unspecified | NA         |
+| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccbram   |       1.000 |     0.002 |       0.001 |      0.001 |       NA    | Unspecified | NA         |
+| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
+| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data             | Confidence | Details                                               | Action                                                                                                     |
++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High       | Design is routed                                      |                                                                                                            |
+| Clock nodes activity        | High       | User specified more than 95% of clocks                |                                                                                                            |
+| I/O nodes activity          | Medium     | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
+| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes        | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models               | High       | Device models are Production                          |                                                                                                            |
+|                             |            |                                                       |                                                                                                            |
+| Overall confidence level    | Medium     |                                                       |                                                                                                            |
++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C)      | 25.0                     |
+| ThetaJA (C/W)         | 2.5                      |
+| Airflow (LFM)         | 250                      |
+| Heat Sink             | medium (Medium Profile)  |
+| ThetaSA (C/W)         | 4.2                      |
+| Board Selection       | medium (10"x10")         |
+| # of Board Layers     | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0                     |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++------------------+------------------+-----------------+
+| Clock            | Domain           | Constraint (ns) |
++------------------+------------------+-----------------+
+| clk              | clk_p            |             5.0 |
+| clk90_mmcm_out   | clk90_mmcm_out   |             8.0 |
+| clk_200_mmcm_out | clk_200_mmcm_out |             5.0 |
+| clk_mmcm_out     | clk_mmcm_out     |             8.0 |
+| mmcm_clkfb       | mmcm_clkfb       |             5.0 |
+| phy_rx_clk       | phy_rx_clk       |             8.0 |
++------------------+------------------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++-----------------------------+-----------+
+| Name                        | Power (W) |
++-----------------------------+-----------+
+| fpga                        |     0.180 |
+|   core_inst                 |     0.039 |
+|     eth_mac_inst            |     0.012 |
+|       eth_mac_1g_rgmii_inst |     0.005 |
+|       rx_fifo               |     0.005 |
+|       tx_fifo               |     0.002 |
+|     udp_complete_inst       |     0.025 |
+|       ip_complete_inst      |     0.017 |
+|       udp_inst              |     0.007 |
++-----------------------------+-----------+
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_power_routed.rpx b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_power_routed.rpx
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diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_route_status.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_route_status.pb
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diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_route_status.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_route_status.rpt
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index 000000000..09e74adf7
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_route_status.rpt
@@ -0,0 +1,12 @@
+Design Route Status
+                                               :      # nets :
+   ------------------------------------------- : ----------- :
+   # of logical nets.......................... :        5987 :
+       # of nets not needing routing.......... :        1548 :
+           # of internally routed nets........ :        1502 :
+           # of nets with no loads............ :          46 :
+       # of routable nets..................... :        4439 :
+           # of fully routed nets............. :        4439 :
+       # of nets with routing errors.......... :           0 :
+   ------------------------------------------- : ----------- :
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_routed.dcp b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_routed.dcp
new file mode 100644
index 000000000..921ed3055
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_routed.dcp differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_timing_summary_routed.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_timing_summary_routed.pb
new file mode 100644
index 000000000..0964496a1
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_timing_summary_routed.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_timing_summary_routed.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_timing_summary_routed.rpt
new file mode 100644
index 000000000..b0091e014
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_timing_summary_routed.rpt
@@ -0,0 +1,7373 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:27:40 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_timing_summary -max_paths 10 -report_unconstrained -file fpga_timing_summary_routed.rpt -pb fpga_timing_summary_routed.pb -rpx fpga_timing_summary_routed.rpx -warn_on_violation
+| Design       : fpga
+| Device       : 7a200t-fbg484
+| Speed File   : -2  PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+  Enable Multi Corner Analysis               :  Yes
+  Enable Pessimism Removal                   :  Yes
+  Pessimism Removal Resolution               :  Nearest Common Node
+  Enable Input Delay Default Clock           :  No
+  Enable Preset / Clear Arcs                 :  No
+  Disable Flight Delays                      :  No
+  Ignore I/O Paths                           :  No
+  Timing Early Launch at Borrowing Latches   :  No
+  Borrow Time for Max Delay Exceptions       :  Yes
+  Merge Timing Exceptions                    :  Yes
+
+  Corner  Analyze    Analyze    
+  Name    Max Paths  Min Paths  
+  ------  ---------  ---------  
+  Slow    Yes        Yes        
+  Fast    Yes        Yes        
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule       Severity  Description                                                Violations  
+---------  --------  ---------------------------------------------------------  ----------  
+SYNTH-5    Warning   Mapped onto distributed RAM because of timing constraints  4           
+SYNTH-16   Warning   Address collision                                          1           
+TIMING-11  Warning   Inappropriate max delay with datapath only option          2           
+TIMING-18  Warning   Missing input or output delay                              5           
+XDCH-2     Warning   Same min and max delay values on IO port                   2           
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (0)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (0)
+5. checking no_input_delay (5)
+6. checking no_output_delay (6)
+7. checking multiple_clock (0)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (0)
+------------------------
+ There are 0 register/latch pins with no clock.
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (0)
+------------------------------------------------
+ There are 0 pins that are not constrained for maximum delay.
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (5)
+------------------------------
+ There are 5 input ports with no input delay specified. (HIGH)
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (6)
+-------------------------------
+ There are 6 ports with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (0)
+------------------------------
+ There are 0 register/latch pins with multiple clocks.
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+      0.478        0.000                      0                 7313        0.034        0.000                      0                 7248        0.264        0.000                       0                  2972  
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock               Waveform(ns)         Period(ns)      Frequency(MHz)
+-----               ------------         ----------      --------------
+clk                 {0.000 2.500}        5.000           200.000         
+  clk90_mmcm_out    {2.000 6.000}        8.000           125.000         
+  clk_200_mmcm_out  {0.000 2.500}        5.000           200.000         
+  clk_mmcm_out      {0.000 4.000}        8.000           125.000         
+  mmcm_clkfb        {0.000 2.500}        5.000           200.000         
+phy_rx_clk          {0.000 4.000}        8.000           125.000         
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock                   WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
+-----                   -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
+clk                                                                                                                                                                   1.100        0.000                       0                     1  
+  clk90_mmcm_out                                                                                                                                                      6.408        0.000                       0                     3  
+  clk_200_mmcm_out                                                                                                                                                    0.264        0.000                       0                     3  
+  clk_mmcm_out            1.395        0.000                      0                 6806        0.034        0.000                      0                 6775        2.870        0.000                       0                  2761  
+  mmcm_clkfb                                                                                                                                                          3.751        0.000                       0                     2  
+phy_rx_clk                3.041        0.000                      0                  471        0.118        0.000                      0                  471        3.500        0.000                       0                   202  
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock      To Clock            WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------      --------            -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+clk_mmcm_out    clk90_mmcm_out        0.478        0.000                      0                    2                                                                        
+phy_rx_clk      clk_mmcm_out          6.764        0.000                      0                   16                                                                        
+clk_mmcm_out    phy_rx_clk            6.805        0.000                      0                   16                                                                        
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group         From Clock         To Clock               WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
+----------         ----------         --------               -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
+**async_default**  clk_mmcm_out       clk_mmcm_out             6.806        0.000                      0                    1        0.385        0.000                      0                    1  
+**async_default**  phy_rx_clk         phy_rx_clk               6.626        0.000                      0                    1        0.515        0.000                      0                    1  
+
+
+------------------------------------------------------------------------------------------------
+| User Ignored Path Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group      From Clock      To Clock      
+----------      ----------      --------      
+(none)          clk_mmcm_out                    
+(none)          clk_mmcm_out    clk90_mmcm_out  
+(none)                          clk_mmcm_out    
+(none)          clk_mmcm_out    clk_mmcm_out    
+(none)          phy_rx_clk      clk_mmcm_out    
+(none)          clk_mmcm_out    phy_rx_clk      
+
+
+------------------------------------------------------------------------------------------------
+| Unconstrained Path Table
+| ------------------------
+------------------------------------------------------------------------------------------------
+
+Path Group        From Clock        To Clock        
+----------        ----------        --------        
+(none)            clk90_mmcm_out                      
+(none)            clk_200_mmcm_out                    
+(none)            clk_mmcm_out                        
+(none)            mmcm_clkfb                          
+(none)                              phy_rx_clk        
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  clk
+  To Clock:  clk
+
+Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+PW    :            0  Failing Endpoints,  Worst Slack        1.100ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         clk
+Waveform(ns):       { 0.000 2.500 }
+Period(ns):         5.000
+Sources:            { clk_p }
+
+Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
+Min Period        n/a     MMCME2_ADV/CLKIN1  n/a            1.249         5.000       3.751      MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKIN1
+Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000       5.000       95.000     MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKIN1
+Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            1.400         2.500       1.100      MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKIN1
+Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            1.400         2.500       1.100      MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKIN1
+High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            1.400         2.500       1.100      MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKIN1
+High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            1.400         2.500       1.100      MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKIN1
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  clk90_mmcm_out
+  To Clock:  clk90_mmcm_out
+
+Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+PW    :            0  Failing Endpoints,  Worst Slack        6.408ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         clk90_mmcm_out
+Waveform(ns):       { 2.000 6.000 }
+Period(ns):         8.000
+Sources:            { clk_mmcm_inst/CLKOUT1 }
+
+Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
+Min Period  n/a     BUFG/I              n/a            1.592         8.000       6.408      BUFGCTRL_X0Y1    clk90_bufg_inst/I
+Min Period  n/a     ODDR/C              n/a            1.474         8.000       6.526      OLOGIC_X0Y219    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/C
+Min Period  n/a     MMCME2_ADV/CLKOUT1  n/a            1.249         8.000       6.751      MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKOUT1
+Max Period  n/a     MMCME2_ADV/CLKOUT1  n/a            213.360       8.000       205.360    MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKOUT1
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  clk_200_mmcm_out
+  To Clock:  clk_200_mmcm_out
+
+Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+PW    :            0  Failing Endpoints,  Worst Slack        0.264ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         clk_200_mmcm_out
+Waveform(ns):       { 0.000 2.500 }
+Period(ns):         5.000
+Sources:            { clk_mmcm_inst/CLKOUT2 }
+
+Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
+Min Period  n/a     IDELAYCTRL/REFCLK   n/a            2.438         5.000       2.562      IDELAYCTRL_X0Y4  idelayctrl_inst/REFCLK
+Min Period  n/a     BUFG/I              n/a            1.592         5.000       3.408      BUFGCTRL_X0Y2    clk_200_bufg_inst/I
+Min Period  n/a     MMCME2_ADV/CLKOUT2  n/a            1.249         5.000       3.751      MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKOUT2
+Max Period  n/a     IDELAYCTRL/REFCLK   n/a            5.264         5.000       0.264      IDELAYCTRL_X0Y4  idelayctrl_inst/REFCLK
+Max Period  n/a     MMCME2_ADV/CLKOUT2  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKOUT2
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  clk_mmcm_out
+  To Clock:  clk_mmcm_out
+
+Setup :            0  Failing Endpoints,  Worst Slack        1.395ns,  Total Violation        0.000ns
+Hold  :            0  Failing Endpoints,  Worst Slack        0.034ns,  Total Violation        0.000ns
+PW    :            0  Failing Endpoints,  Worst Slack        2.870ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             1.395ns  (required time - arrival time)
+  Source:                 core_inst/eth_axis_rx_inst/m_eth_payload_axis_tdata_reg_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/s_eth_payload_axis_tready_reg_reg/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        6.346ns  (logic 2.890ns (45.538%)  route 3.456ns (54.462%))
+  Logic Levels:           12  (CARRY4=7 LUT2=1 LUT4=1 LUT5=1 LUT6=2)
+  Clock Path Skew:        -0.271ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.787ns = ( 12.787 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.244ns
+    Clock Pessimism Removal (CPR):    0.186ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.654     5.244    core_inst/eth_axis_rx_inst/clk_int
+    SLICE_X12Y214        FDRE                                         r  core_inst/eth_axis_rx_inst/m_eth_payload_axis_tdata_reg_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y214        FDRE (Prop_fdre_C_Q)         0.433     5.677 r  core_inst/eth_axis_rx_inst/m_eth_payload_axis_tdata_reg_reg[4]/Q
+                         net (fo=40, routed)          1.109     6.786    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_version_reg_reg[3]_0[4]
+    SLICE_X21Y198        LUT2 (Prop_lut2_I1_O)        0.105     6.891 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[7]_i_10/O
+                         net (fo=1, routed)           0.000     6.891    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[7]_i_10_n_0
+    SLICE_X21Y198        CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     7.331 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_6__0/CO[3]
+                         net (fo=1, routed)           0.000     7.331    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_6__0_n_0
+    SLICE_X21Y199        CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.098     7.429 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[11]_i_6__0/CO[3]
+                         net (fo=1, routed)           0.001     7.430    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[11]_i_6__0_n_0
+    SLICE_X21Y200        CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.098     7.528 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[15]_i_6/CO[3]
+                         net (fo=1, routed)           0.000     7.528    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[15]_i_6_n_0
+    SLICE_X21Y201        CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     7.744 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_7/CO[0]
+                         net (fo=2, routed)           0.630     8.374    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_7_n_3
+    SLICE_X20Y197        LUT5 (Prop_lut5_I1_O)        0.309     8.683 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[3]_i_6__0/O
+                         net (fo=1, routed)           0.000     8.683    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[3]_i_6__0_n_0
+    SLICE_X20Y197        CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.423     9.106 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_1__0/CO[3]
+                         net (fo=1, routed)           0.000     9.106    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_1__0_n_0
+    SLICE_X20Y198        CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.100     9.206 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_1__0/CO[3]
+                         net (fo=1, routed)           0.000     9.206    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_1__0_n_0
+    SLICE_X20Y199        CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.214     9.420 f  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[11]_i_1__0/O[2]
+                         net (fo=2, routed)           0.549     9.969    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/in29[10]
+    SLICE_X22Y198        LUT4 (Prop_lut4_I0_O)        0.244    10.213 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_8/O
+                         net (fo=1, routed)           0.658    10.870    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_8_n_0
+    SLICE_X22Y198        LUT6 (Prop_lut6_I1_O)        0.105    10.975 f  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_4/O
+                         net (fo=3, routed)           0.510    11.485    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_4_n_0
+    SLICE_X18Y197        LUT6 (Prop_lut6_I3_O)        0.105    11.590 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/s_eth_payload_axis_tready_reg_i_1/O
+                         net (fo=1, routed)           0.000    11.590    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/s_eth_payload_axis_tready_next
+    SLICE_X18Y197        FDRE                                         r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/s_eth_payload_axis_tready_reg_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.376    12.787    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/clk_int
+    SLICE_X18Y197        FDRE                                         r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/s_eth_payload_axis_tready_reg_reg/C
+                         clock pessimism              0.186    12.973    
+                         clock uncertainty           -0.064    12.909    
+    SLICE_X18Y197        FDRE (Setup_fdre_C_D)        0.076    12.985    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/s_eth_payload_axis_tready_reg_reg
+  -------------------------------------------------------------------
+                         required time                         12.985    
+                         arrival time                         -11.590    
+  -------------------------------------------------------------------
+                         slack                                  1.395    
+
+Slack (MET) :             1.472ns  (required time - arrival time)
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/mii_select_reg_reg/R
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        6.177ns  (logic 0.433ns (7.010%)  route 5.744ns (92.990%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.136ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    5.019ns = ( 13.019 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.186ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 r  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.744    11.246    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/Q[0]
+    SLICE_X2Y216         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/mii_select_reg_reg/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.608    13.019    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/clk_int
+    SLICE_X2Y216         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/mii_select_reg_reg/C
+                         clock pessimism              0.186    13.205    
+                         clock uncertainty           -0.064    13.140    
+    SLICE_X2Y216         FDRE (Setup_fdre_C_R)       -0.423    12.717    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/mii_select_reg_reg
+  -------------------------------------------------------------------
+                         required time                         12.717    
+                         arrival time                         -11.246    
+  -------------------------------------------------------------------
+                         slack                                  1.472    
+
+Slack (MET) :             1.472ns  (required time - arrival time)
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/speed_reg_reg[0]/R
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        6.177ns  (logic 0.433ns (7.010%)  route 5.744ns (92.990%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.136ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    5.019ns = ( 13.019 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.186ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 r  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.744    11.246    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/Q[0]
+    SLICE_X2Y216         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/speed_reg_reg[0]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.608    13.019    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/clk_int
+    SLICE_X2Y216         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/speed_reg_reg[0]/C
+                         clock pessimism              0.186    13.205    
+                         clock uncertainty           -0.064    13.140    
+    SLICE_X2Y216         FDRE (Setup_fdre_C_R)       -0.423    12.717    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/speed_reg_reg[0]
+  -------------------------------------------------------------------
+                         required time                         12.717    
+                         arrival time                         -11.246    
+  -------------------------------------------------------------------
+                         slack                                  1.472    
+
+Slack (MET) :             1.472ns  (required time - arrival time)
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/speed_reg_reg[1]_inv/R
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        6.177ns  (logic 0.433ns (7.010%)  route 5.744ns (92.990%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.136ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    5.019ns = ( 13.019 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.186ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 r  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.744    11.246    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/Q[0]
+    SLICE_X2Y216         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/speed_reg_reg[1]_inv/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.608    13.019    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/clk_int
+    SLICE_X2Y216         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/speed_reg_reg[1]_inv/C
+                         clock pessimism              0.186    13.205    
+                         clock uncertainty           -0.064    13.140    
+    SLICE_X2Y216         FDRE (Setup_fdre_C_R)       -0.423    12.717    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/speed_reg_reg[1]_inv
+  -------------------------------------------------------------------
+                         required time                         12.717    
+                         arrival time                         -11.246    
+  -------------------------------------------------------------------
+                         slack                                  1.472    
+
+Slack (MET) :             1.495ns  (required time - arrival time)
+  Source:                 core_inst/eth_axis_rx_inst/m_eth_payload_axis_tdata_reg_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        6.241ns  (logic 2.890ns (46.304%)  route 3.351ns (53.696%))
+  Logic Levels:           12  (CARRY4=7 LUT2=1 LUT4=1 LUT5=1 LUT6=2)
+  Clock Path Skew:        -0.271ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.787ns = ( 12.787 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.244ns
+    Clock Pessimism Removal (CPR):    0.186ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.654     5.244    core_inst/eth_axis_rx_inst/clk_int
+    SLICE_X12Y214        FDRE                                         r  core_inst/eth_axis_rx_inst/m_eth_payload_axis_tdata_reg_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y214        FDRE (Prop_fdre_C_Q)         0.433     5.677 r  core_inst/eth_axis_rx_inst/m_eth_payload_axis_tdata_reg_reg[4]/Q
+                         net (fo=40, routed)          1.109     6.786    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_version_reg_reg[3]_0[4]
+    SLICE_X21Y198        LUT2 (Prop_lut2_I1_O)        0.105     6.891 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[7]_i_10/O
+                         net (fo=1, routed)           0.000     6.891    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[7]_i_10_n_0
+    SLICE_X21Y198        CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     7.331 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_6__0/CO[3]
+                         net (fo=1, routed)           0.000     7.331    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_6__0_n_0
+    SLICE_X21Y199        CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.098     7.429 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[11]_i_6__0/CO[3]
+                         net (fo=1, routed)           0.001     7.430    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[11]_i_6__0_n_0
+    SLICE_X21Y200        CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.098     7.528 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[15]_i_6/CO[3]
+                         net (fo=1, routed)           0.000     7.528    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[15]_i_6_n_0
+    SLICE_X21Y201        CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     7.744 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_7/CO[0]
+                         net (fo=2, routed)           0.630     8.374    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_7_n_3
+    SLICE_X20Y197        LUT5 (Prop_lut5_I1_O)        0.309     8.683 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[3]_i_6__0/O
+                         net (fo=1, routed)           0.000     8.683    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[3]_i_6__0_n_0
+    SLICE_X20Y197        CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.423     9.106 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_1__0/CO[3]
+                         net (fo=1, routed)           0.000     9.106    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_1__0_n_0
+    SLICE_X20Y198        CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.100     9.206 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_1__0/CO[3]
+                         net (fo=1, routed)           0.000     9.206    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_1__0_n_0
+    SLICE_X20Y199        CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.214     9.420 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[11]_i_1__0/O[2]
+                         net (fo=2, routed)           0.549     9.969    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/in29[10]
+    SLICE_X22Y198        LUT4 (Prop_lut4_I0_O)        0.244    10.213 f  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_8/O
+                         net (fo=1, routed)           0.658    10.870    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_8_n_0
+    SLICE_X22Y198        LUT6 (Prop_lut6_I1_O)        0.105    10.975 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_4/O
+                         net (fo=3, routed)           0.405    11.380    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_4_n_0
+    SLICE_X18Y198        LUT6 (Prop_lut6_I3_O)        0.105    11.485 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_1__3/O
+                         net (fo=1, routed)           0.000    11.485    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_1__3_n_0
+    SLICE_X18Y198        FDRE                                         r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.376    12.787    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/clk_int
+    SLICE_X18Y198        FDRE                                         r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg_reg[0]/C
+                         clock pessimism              0.186    12.973    
+                         clock uncertainty           -0.064    12.909    
+    SLICE_X18Y198        FDRE (Setup_fdre_C_D)        0.072    12.981    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg_reg[0]
+  -------------------------------------------------------------------
+                         required time                         12.981    
+                         arrival time                         -11.485    
+  -------------------------------------------------------------------
+                         slack                                  1.495    
+
+Slack (MET) :             1.511ns  (required time - arrival time)
+  Source:                 core_inst/eth_axis_rx_inst/m_eth_payload_axis_tdata_reg_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_hdr_valid_reg_reg/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        6.225ns  (logic 2.890ns (46.429%)  route 3.335ns (53.571%))
+  Logic Levels:           12  (CARRY4=7 LUT2=1 LUT4=1 LUT5=1 LUT6=2)
+  Clock Path Skew:        -0.272ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.786ns = ( 12.786 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.244ns
+    Clock Pessimism Removal (CPR):    0.186ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.654     5.244    core_inst/eth_axis_rx_inst/clk_int
+    SLICE_X12Y214        FDRE                                         r  core_inst/eth_axis_rx_inst/m_eth_payload_axis_tdata_reg_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y214        FDRE (Prop_fdre_C_Q)         0.433     5.677 r  core_inst/eth_axis_rx_inst/m_eth_payload_axis_tdata_reg_reg[4]/Q
+                         net (fo=40, routed)          1.109     6.786    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_version_reg_reg[3]_0[4]
+    SLICE_X21Y198        LUT2 (Prop_lut2_I1_O)        0.105     6.891 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[7]_i_10/O
+                         net (fo=1, routed)           0.000     6.891    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[7]_i_10_n_0
+    SLICE_X21Y198        CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     7.331 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_6__0/CO[3]
+                         net (fo=1, routed)           0.000     7.331    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_6__0_n_0
+    SLICE_X21Y199        CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.098     7.429 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[11]_i_6__0/CO[3]
+                         net (fo=1, routed)           0.001     7.430    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[11]_i_6__0_n_0
+    SLICE_X21Y200        CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.098     7.528 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[15]_i_6/CO[3]
+                         net (fo=1, routed)           0.000     7.528    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[15]_i_6_n_0
+    SLICE_X21Y201        CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     7.744 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_7/CO[0]
+                         net (fo=2, routed)           0.630     8.374    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_7_n_3
+    SLICE_X20Y197        LUT5 (Prop_lut5_I1_O)        0.309     8.683 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[3]_i_6__0/O
+                         net (fo=1, routed)           0.000     8.683    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg[3]_i_6__0_n_0
+    SLICE_X20Y197        CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.423     9.106 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_1__0/CO[3]
+                         net (fo=1, routed)           0.000     9.106    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[3]_i_1__0_n_0
+    SLICE_X20Y198        CARRY4 (Prop_carry4_CI_CO[3])
+                                                      0.100     9.206 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_1__0/CO[3]
+                         net (fo=1, routed)           0.000     9.206    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[7]_i_1__0_n_0
+    SLICE_X20Y199        CARRY4 (Prop_carry4_CI_O[2])
+                                                      0.214     9.420 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/hdr_sum_reg_reg[11]_i_1__0/O[2]
+                         net (fo=2, routed)           0.549     9.969    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/in29[10]
+    SLICE_X22Y198        LUT4 (Prop_lut4_I0_O)        0.244    10.213 f  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_8/O
+                         net (fo=1, routed)           0.658    10.870    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_8_n_0
+    SLICE_X22Y198        LUT6 (Prop_lut6_I1_O)        0.105    10.975 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_4/O
+                         net (fo=3, routed)           0.388    11.363    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/FSM_sequential_state_reg[0]_i_4_n_0
+    SLICE_X20Y196        LUT6 (Prop_lut6_I1_O)        0.105    11.468 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_hdr_valid_reg_i_1/O
+                         net (fo=1, routed)           0.000    11.468    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_hdr_valid_next
+    SLICE_X20Y196        FDRE                                         r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_hdr_valid_reg_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.375    12.786    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/clk_int
+    SLICE_X20Y196        FDRE                                         r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_hdr_valid_reg_reg/C
+                         clock pessimism              0.186    12.972    
+                         clock uncertainty           -0.064    12.908    
+    SLICE_X20Y196        FDRE (Setup_fdre_C_D)        0.072    12.980    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_hdr_valid_reg_reg
+  -------------------------------------------------------------------
+                         required time                         12.980    
+                         arrival time                         -11.468    
+  -------------------------------------------------------------------
+                         slack                                  1.511    
+
+Slack (MET) :             1.527ns  (required time - arrival time)
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[10]/R
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        6.127ns  (logic 0.433ns (7.067%)  route 5.694ns (92.933%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.141ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    5.024ns = ( 13.024 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.186ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 r  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.694    11.196    core_inst/eth_mac_inst/rx_fifo/fifo_inst/Q[0]
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[10]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.613    13.024    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[10]/C
+                         clock pessimism              0.186    13.210    
+                         clock uncertainty           -0.064    13.145    
+    SLICE_X2Y209         FDRE (Setup_fdre_C_R)       -0.423    12.722    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[10]
+  -------------------------------------------------------------------
+                         required time                         12.722    
+                         arrival time                         -11.196    
+  -------------------------------------------------------------------
+                         slack                                  1.527    
+
+Slack (MET) :             1.527ns  (required time - arrival time)
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/R
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        6.127ns  (logic 0.433ns (7.067%)  route 5.694ns (92.933%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.141ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    5.024ns = ( 13.024 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.186ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 r  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.694    11.196    core_inst/eth_mac_inst/rx_fifo/fifo_inst/Q[0]
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.613    13.024    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/C
+                         clock pessimism              0.186    13.210    
+                         clock uncertainty           -0.064    13.145    
+    SLICE_X2Y209         FDRE (Setup_fdre_C_R)       -0.423    12.722    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]
+  -------------------------------------------------------------------
+                         required time                         12.722    
+                         arrival time                         -11.196    
+  -------------------------------------------------------------------
+                         slack                                  1.527    
+
+Slack (MET) :             1.527ns  (required time - arrival time)
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/R
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        6.127ns  (logic 0.433ns (7.067%)  route 5.694ns (92.933%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.141ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    5.024ns = ( 13.024 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.186ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 r  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.694    11.196    core_inst/eth_mac_inst/rx_fifo/fifo_inst/Q[0]
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.613    13.024    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/C
+                         clock pessimism              0.186    13.210    
+                         clock uncertainty           -0.064    13.145    
+    SLICE_X2Y209         FDRE (Setup_fdre_C_R)       -0.423    12.722    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]
+  -------------------------------------------------------------------
+                         required time                         12.722    
+                         arrival time                         -11.196    
+  -------------------------------------------------------------------
+                         slack                                  1.527    
+
+Slack (MET) :             1.527ns  (required time - arrival time)
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[3]/R
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        6.127ns  (logic 0.433ns (7.067%)  route 5.694ns (92.933%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.141ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    5.024ns = ( 13.024 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.186ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 r  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.694    11.196    core_inst/eth_mac_inst/rx_fifo/fifo_inst/Q[0]
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[3]/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.613    13.024    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[3]/C
+                         clock pessimism              0.186    13.210    
+                         clock uncertainty           -0.064    13.145    
+    SLICE_X2Y209         FDRE (Setup_fdre_C_R)       -0.423    12.722    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[3]
+  -------------------------------------------------------------------
+                         required time                         12.722    
+                         arrival time                         -11.196    
+  -------------------------------------------------------------------
+                         slack                                  1.527    
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             0.034ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_reg_reg/R
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.377ns  (logic 0.141ns (37.395%)  route 0.236ns (62.605%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.361ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.551ns
+    Source Clock Delay      (SCD):    2.060ns
+    Clock Pessimism Removal (CPR):    0.130ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.653     2.060    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_int
+    SLICE_X4Y199         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y199         FDPE (Prop_fdpe_C_Q)         0.141     2.201 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/Q
+                         net (fo=30, routed)          0.236     2.437    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/FSM_sequential_state_reg_reg[0]_0[0]
+    SLICE_X4Y200         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_reg_reg/R
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.019     2.551    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/clk_int
+    SLICE_X4Y200         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_reg_reg/C
+                         clock pessimism             -0.130     2.422    
+    SLICE_X4Y200         FDRE (Hold_fdre_C_R)        -0.018     2.404    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_reg_reg
+  -------------------------------------------------------------------
+                         required time                         -2.404    
+                         arrival time                           2.437    
+  -------------------------------------------------------------------
+                         slack                                  0.034    
+
+Slack (MET) :             0.082ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg_reg[6]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.565ns  (logic 0.246ns (43.506%)  route 0.319ns (56.494%))
+  Logic Levels:           1  (LUT6=1)
+  Clock Path Skew:        0.362ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.553ns
+    Source Clock Delay      (SCD):    2.061ns
+    Clock Pessimism Removal (CPR):    0.130ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.654     2.061    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/clk_int
+    SLICE_X2Y199         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X2Y199         FDRE (Prop_fdre_C_Q)         0.148     2.209 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg_reg[4]/Q
+                         net (fo=7, routed)           0.319     2.529    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg[4]
+    SLICE_X2Y200         LUT6 (Prop_lut6_I4_O)        0.098     2.627 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg[6]_i_1/O
+                         net (fo=1, routed)           0.000     2.627    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg[6]_i_1_n_0
+    SLICE_X2Y200         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg_reg[6]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.021     2.553    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/clk_int
+    SLICE_X2Y200         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg_reg[6]/C
+                         clock pessimism             -0.130     2.424    
+    SLICE_X2Y200         FDRE (Hold_fdre_C_D)         0.121     2.545    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_tx_inst/frame_ptr_reg_reg[6]
+  -------------------------------------------------------------------
+                         required time                         -2.545    
+                         arrival time                           2.627    
+  -------------------------------------------------------------------
+                         slack                                  0.082    
+
+Slack (MET) :             0.086ns  (arrival time - required time)
+  Source:                 core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/frame_ptr_reg_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_0_5/RAMC/I
+                            (rising edge-triggered cell RAMD32 clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.266ns  (logic 0.141ns (53.086%)  route 0.125ns (46.914%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.420ns
+    Source Clock Delay      (SCD):    2.025ns
+    Clock Pessimism Removal (CPR):    0.358ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.618     2.025    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/clk_int
+    SLICE_X9Y181         FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/frame_ptr_reg_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X9Y181         FDRE (Prop_fdre_C_Q)         0.141     2.166 r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/frame_ptr_reg_reg[4]/Q
+                         net (fo=2, routed)           0.125     2.291    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_0_5/DIC0
+    SLICE_X10Y181        RAMD32                                       r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_0_5/RAMC/I
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.888     2.420    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_0_5/WCLK
+    SLICE_X10Y181        RAMD32                                       r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_0_5/RAMC/CLK
+                         clock pessimism             -0.358     2.061    
+    SLICE_X10Y181        RAMD32 (Hold_ramd32_CLK_I)
+                                                      0.144     2.205    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_0_5/RAMC
+  -------------------------------------------------------------------
+                         required time                         -2.205    
+                         arrival time                           2.291    
+  -------------------------------------------------------------------
+                         slack                                  0.086    
+
+Slack (MET) :             0.086ns  (arrival time - required time)
+  Source:                 core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_source_ip_reg_reg[13]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[13]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.335ns  (logic 0.164ns (48.994%)  route 0.171ns (51.006%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.178ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.430ns
+    Source Clock Delay      (SCD):    2.122ns
+    Clock Pessimism Removal (CPR):    0.130ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.714     2.122    core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/clk_int
+    SLICE_X14Y200        FDRE                                         r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_source_ip_reg_reg[13]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X14Y200        FDRE (Prop_fdre_C_Q)         0.164     2.286 r  core_inst/udp_complete_inst/ip_complete_inst/ip_inst/ip_eth_rx_inst/m_ip_source_ip_reg_reg[13]/Q
+                         net (fo=1, routed)           0.171     2.457    core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[31]_1[13]
+    SLICE_X15Y199        FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[13]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.898     2.430    core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/clk_int
+    SLICE_X15Y199        FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[13]/C
+                         clock pessimism             -0.130     2.300    
+    SLICE_X15Y199        FDRE (Hold_fdre_C_D)         0.070     2.370    core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[13]
+  -------------------------------------------------------------------
+                         required time                         -2.370    
+                         arrival time                           2.457    
+  -------------------------------------------------------------------
+                         slack                                  0.086    
+
+Slack (MET) :             0.087ns  (arrival time - required time)
+  Source:                 core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/frame_ptr_reg_reg[8]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/RAMB/I
+                            (rising edge-triggered cell RAMD32 clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.270ns  (logic 0.141ns (52.269%)  route 0.129ns (47.731%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.037ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.422ns
+    Source Clock Delay      (SCD):    2.026ns
+    Clock Pessimism Removal (CPR):    0.358ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.619     2.026    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/clk_int
+    SLICE_X9Y182         FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/frame_ptr_reg_reg[8]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X9Y182         FDRE (Prop_fdre_C_Q)         0.141     2.167 r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/frame_ptr_reg_reg[8]/Q
+                         net (fo=2, routed)           0.129     2.296    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/DIB0
+    SLICE_X10Y183        RAMD32                                       r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/RAMB/I
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.890     2.422    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/WCLK
+    SLICE_X10Y183        RAMD32                                       r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/RAMB/CLK
+                         clock pessimism             -0.358     2.063    
+    SLICE_X10Y183        RAMD32 (Hold_ramd32_CLK_I)
+                                                      0.146     2.209    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/RAMB
+  -------------------------------------------------------------------
+                         required time                         -2.209    
+                         arrival time                           2.296    
+  -------------------------------------------------------------------
+                         slack                                  0.087    
+
+Slack (MET) :             0.087ns  (arrival time - required time)
+  Source:                 core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[10]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/ip_dest_ip_reg_reg[10]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.336ns  (logic 0.141ns (42.008%)  route 0.195ns (57.992%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.178ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.428ns
+    Source Clock Delay      (SCD):    2.120ns
+    Clock Pessimism Removal (CPR):    0.130ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.712     2.120    core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/clk_int
+    SLICE_X19Y201        FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[10]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X19Y201        FDRE (Prop_fdre_C_Q)         0.141     2.261 r  core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[10]/Q
+                         net (fo=1, routed)           0.195     2.455    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/ip_dest_ip_reg_reg[31]_0[10]
+    SLICE_X19Y194        FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/ip_dest_ip_reg_reg[10]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.896     2.428    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/clk_int
+    SLICE_X19Y194        FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/ip_dest_ip_reg_reg[10]/C
+                         clock pessimism             -0.130     2.298    
+    SLICE_X19Y194        FDRE (Hold_fdre_C_D)         0.070     2.368    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/ip_dest_ip_reg_reg[10]
+  -------------------------------------------------------------------
+                         required time                         -2.368    
+                         arrival time                           2.455    
+  -------------------------------------------------------------------
+                         slack                                  0.087    
+
+Slack (MET) :             0.090ns  (arrival time - required time)
+  Source:                 core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/frame_ptr_reg_reg[10]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/RAMC/I
+                            (rising edge-triggered cell RAMD32 clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.270ns  (logic 0.141ns (52.269%)  route 0.129ns (47.731%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.036ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.422ns
+    Source Clock Delay      (SCD):    2.027ns
+    Clock Pessimism Removal (CPR):    0.358ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.620     2.027    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/clk_int
+    SLICE_X9Y183         FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/frame_ptr_reg_reg[10]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X9Y183         FDRE (Prop_fdre_C_Q)         0.141     2.168 r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/frame_ptr_reg_reg[10]/Q
+                         net (fo=2, routed)           0.129     2.297    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/DIC0
+    SLICE_X10Y183        RAMD32                                       r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/RAMC/I
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.890     2.422    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/WCLK
+    SLICE_X10Y183        RAMD32                                       r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/RAMC/CLK
+                         clock pessimism             -0.358     2.063    
+    SLICE_X10Y183        RAMD32 (Hold_ramd32_CLK_I)
+                                                      0.144     2.207    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/udp_length_mem_reg_0_7_6_11/RAMC
+  -------------------------------------------------------------------
+                         required time                         -2.207    
+                         arrival time                           2.297    
+  -------------------------------------------------------------------
+                         slack                                  0.090    
+
+Slack (MET) :             0.091ns  (arrival time - required time)
+  Source:                 core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[11]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/ip_dest_ip_reg_reg[11]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.336ns  (logic 0.141ns (42.008%)  route 0.195ns (57.992%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.178ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.428ns
+    Source Clock Delay      (SCD):    2.120ns
+    Clock Pessimism Removal (CPR):    0.130ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.712     2.120    core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/clk_int
+    SLICE_X19Y201        FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[11]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X19Y201        FDRE (Prop_fdre_C_Q)         0.141     2.261 r  core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_ip_source_ip_reg_reg[11]/Q
+                         net (fo=1, routed)           0.195     2.455    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/ip_dest_ip_reg_reg[31]_0[11]
+    SLICE_X19Y194        FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/ip_dest_ip_reg_reg[11]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.896     2.428    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/clk_int
+    SLICE_X19Y194        FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/ip_dest_ip_reg_reg[11]/C
+                         clock pessimism             -0.130     2.298    
+    SLICE_X19Y194        FDRE (Hold_fdre_C_D)         0.066     2.364    core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/ip_dest_ip_reg_reg[11]
+  -------------------------------------------------------------------
+                         required time                         -2.364    
+                         arrival time                           2.455    
+  -------------------------------------------------------------------
+                         slack                                  0.091    
+
+Slack (MET) :             0.092ns  (arrival time - required time)
+  Source:                 core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_udp_payload_axis_tdata_reg_reg[5]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_payload_fifo/mem_reg_1/DIADI[1]
+                            (rising edge-triggered cell RAMB36E1 clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.299ns  (logic 0.164ns (54.795%)  route 0.135ns (45.205%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.452ns
+    Source Clock Delay      (SCD):    2.019ns
+    Clock Pessimism Removal (CPR):    0.380ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.612     2.019    core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/clk_int
+    SLICE_X22Y177        FDRE                                         r  core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_udp_payload_axis_tdata_reg_reg[5]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X22Y177        FDRE (Prop_fdre_C_Q)         0.164     2.183 r  core_inst/udp_complete_inst/udp_inst/udp_ip_rx_inst/m_udp_payload_axis_tdata_reg_reg[5]/Q
+                         net (fo=1, routed)           0.135     2.319    core_inst/udp_payload_fifo/s_axis[5]
+    RAMB36_X1Y35         RAMB36E1                                     r  core_inst/udp_payload_fifo/mem_reg_1/DIADI[1]
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.920     2.452    core_inst/udp_payload_fifo/clk_int
+    RAMB36_X1Y35         RAMB36E1                                     r  core_inst/udp_payload_fifo/mem_reg_1/CLKARDCLK
+                         clock pessimism             -0.380     2.072    
+    RAMB36_X1Y35         RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[1])
+                                                      0.155     2.227    core_inst/udp_payload_fifo/mem_reg_1
+  -------------------------------------------------------------------
+                         required time                         -2.227    
+                         arrival time                           2.319    
+  -------------------------------------------------------------------
+                         slack                                  0.092    
+
+Slack (MET) :             0.095ns  (arrival time - required time)
+  Source:                 core_inst/udp_payload_fifo/rd_ptr_reg_reg_rep[9]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/udp_payload_fifo/mem_reg_2/ADDRBWRADDR[10]
+                            (rising edge-triggered cell RAMB18E1 clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.355ns  (logic 0.141ns (39.719%)  route 0.214ns (60.281%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.077ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.457ns
+    Source Clock Delay      (SCD):    2.022ns
+    Clock Pessimism Removal (CPR):    0.358ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.615     2.022    core_inst/udp_payload_fifo/clk_int
+    SLICE_X21Y168        FDRE                                         r  core_inst/udp_payload_fifo/rd_ptr_reg_reg_rep[9]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X21Y168        FDRE (Prop_fdre_C_Q)         0.141     2.163 r  core_inst/udp_payload_fifo/rd_ptr_reg_reg_rep[9]/Q
+                         net (fo=3, routed)           0.214     2.377    core_inst/udp_payload_fifo/rd_ptr_reg_reg_rep[9]
+    RAMB18_X1Y66         RAMB18E1                                     r  core_inst/udp_payload_fifo/mem_reg_2/ADDRBWRADDR[10]
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.925     2.457    core_inst/udp_payload_fifo/clk_int
+    RAMB18_X1Y66         RAMB18E1                                     r  core_inst/udp_payload_fifo/mem_reg_2/CLKBWRCLK
+                         clock pessimism             -0.358     2.099    
+    RAMB18_X1Y66         RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[10])
+                                                      0.183     2.282    core_inst/udp_payload_fifo/mem_reg_2
+  -------------------------------------------------------------------
+                         required time                         -2.282    
+                         arrival time                           2.377    
+  -------------------------------------------------------------------
+                         slack                                  0.095    
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         clk_mmcm_out
+Waveform(ns):       { 0.000 4.000 }
+Period(ns):         8.000
+Sources:            { clk_mmcm_inst/CLKOUT0 }
+
+Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
+Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.472         8.000       5.528      RAMB36_X0Y38     core_inst/eth_mac_inst/tx_fifo/fifo_inst/mem_reg_0/CLKARDCLK
+Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.472         8.000       5.528      RAMB18_X0Y74     core_inst/eth_mac_inst/tx_fifo/fifo_inst/mem_reg_1/CLKARDCLK
+Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.472         8.000       5.528      RAMB18_X1Y80     core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/ip_addr_mem_reg/CLKARDCLK
+Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.472         8.000       5.528      RAMB18_X1Y80     core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/ip_addr_mem_reg/CLKBWRCLK
+Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.472         8.000       5.528      RAMB36_X1Y41     core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/mac_addr_mem_reg/CLKARDCLK
+Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.472         8.000       5.528      RAMB36_X1Y41     core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/mac_addr_mem_reg/CLKBWRCLK
+Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.472         8.000       5.528      RAMB36_X0Y34     core_inst/udp_complete_inst/udp_inst/udp_checksum_gen_inst/payload_fifo/mem_reg/CLKARDCLK
+Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.472         8.000       5.528      RAMB36_X1Y34     core_inst/udp_payload_fifo/mem_reg_0/CLKARDCLK
+Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.472         8.000       5.528      RAMB36_X1Y35     core_inst/udp_payload_fifo/mem_reg_1/CLKARDCLK
+Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.472         8.000       5.528      RAMB18_X1Y66     core_inst/udp_payload_fifo/mem_reg_2/CLKARDCLK
+Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       8.000       205.360    MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKOUT0
+Low Pulse Width   Slow    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/DP.HIGH/CLK
+Low Pulse Width   Fast    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/DP.HIGH/CLK
+Low Pulse Width   Slow    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/DP.LOW/CLK
+Low Pulse Width   Fast    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/DP.LOW/CLK
+Low Pulse Width   Slow    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/SP.HIGH/CLK
+Low Pulse Width   Fast    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/SP.HIGH/CLK
+Low Pulse Width   Slow    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/SP.LOW/CLK
+Low Pulse Width   Fast    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/SP.LOW/CLK
+Low Pulse Width   Slow    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X22Y204    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_128_255_0_0/DP.HIGH/CLK
+Low Pulse Width   Fast    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X22Y204    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_128_255_0_0/DP.HIGH/CLK
+High Pulse Width  Slow    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/DP.HIGH/CLK
+High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/DP.HIGH/CLK
+High Pulse Width  Slow    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/DP.LOW/CLK
+High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/DP.LOW/CLK
+High Pulse Width  Slow    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/SP.HIGH/CLK
+High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/SP.HIGH/CLK
+High Pulse Width  Slow    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/SP.LOW/CLK
+High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X20Y205    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_0_127_0_0/SP.LOW/CLK
+High Pulse Width  Slow    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X22Y204    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_128_255_0_0/DP.HIGH/CLK
+High Pulse Width  Fast    RAMD64E/CLK         n/a            1.130         4.000       2.870      SLICE_X22Y204    core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/valid_mem_reg_128_255_0_0/DP.HIGH/CLK
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  mmcm_clkfb
+  To Clock:  mmcm_clkfb
+
+Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+PW    :            0  Failing Endpoints,  Worst Slack        3.751ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         mmcm_clkfb
+Waveform(ns):       { 0.000 2.500 }
+Period(ns):         5.000
+Sources:            { clk_mmcm_inst/CLKFBOUT }
+
+Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
+Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         5.000       3.751      MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKFBOUT
+Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249         5.000       3.751      MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKFBIN
+Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       5.000       95.000     MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKFBIN
+Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360       5.000       208.360    MMCME2_ADV_X1Y2  clk_mmcm_inst/CLKFBOUT
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  phy_rx_clk
+  To Clock:  phy_rx_clk
+
+Setup :            0  Failing Endpoints,  Worst Slack        3.041ns,  Total Violation        0.000ns
+Hold  :            0  Failing Endpoints,  Worst Slack        0.118ns,  Total Violation        0.000ns
+PW    :            0  Failing Endpoints,  Worst Slack        3.500ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             3.041ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/crc_state_reg[2]/C
+                            (rising edge-triggered cell FDSE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tuser_reg_reg/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        4.956ns  (logic 1.978ns (39.910%)  route 2.978ns (60.090%))
+  Logic Levels:           7  (CARRY4=1 LUT4=1 LUT5=2 LUT6=3)
+  Clock Path Skew:        -0.040ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.730ns = ( 10.730 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.892ns
+    Clock Pessimism Removal (CPR):    0.122ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.653     2.892    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/output_clk
+    SLICE_X7Y222         FDSE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/crc_state_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y222         FDSE (Prop_fdse_C_Q)         0.379     3.271 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/crc_state_reg[2]/Q
+                         net (fo=10, routed)          0.682     3.953    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/eth_crc_8/Q[2]
+    SLICE_X5Y222         LUT4 (Prop_lut4_I2_O)        0.105     4.058 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/eth_crc_8/i_/crc_state[26]_i_2/O
+                         net (fo=5, routed)           0.544     4.602    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/eth_crc_8/i_/crc_state[26]_i_2_n_0
+    SLICE_X7Y223         LUT5 (Prop_lut5_I4_O)        0.124     4.726 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/eth_crc_8/i_/crc_state[25]_i_2/O
+                         net (fo=2, routed)           0.466     5.192    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/eth_crc_8/i_/crc_state[25]_i_2_n_0
+    SLICE_X7Y222         LUT5 (Prop_lut5_I4_O)        0.290     5.482 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/eth_crc_8/i_/crc_state[25]_i_1/O
+                         net (fo=2, routed)           0.454     5.936    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/crc_next[25]
+    SLICE_X4Y224         LUT6 (Prop_lut6_I2_O)        0.268     6.204 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/i__carry__1_i_3/O
+                         net (fo=1, routed)           0.000     6.204    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/i__carry__1_i_3_n_0
+    SLICE_X4Y224         CARRY4 (Prop_carry4_S[0]_CO[2])
+                                                      0.446     6.650 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tuser_next1_inferred__0/i__carry__1/CO[2]
+                         net (fo=1, routed)           0.467     7.116    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tuser_next1
+    SLICE_X4Y220         LUT6 (Prop_lut6_I0_O)        0.261     7.377 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tuser_reg_i_2/O
+                         net (fo=1, routed)           0.366     7.743    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tuser_reg_i_2_n_0
+    SLICE_X2Y219         LUT6 (Prop_lut6_I2_O)        0.105     7.848 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tuser_reg_i_1/O
+                         net (fo=1, routed)           0.000     7.848    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tuser_next4_out
+    SLICE_X2Y219         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tuser_reg_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.613    10.730    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/output_clk
+    SLICE_X2Y219         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tuser_reg_reg/C
+                         clock pessimism              0.122    10.852    
+                         clock uncertainty           -0.035    10.817    
+    SLICE_X2Y219         FDRE (Setup_fdre_C_D)        0.072    10.889    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/m_axis_tuser_reg_reg
+  -------------------------------------------------------------------
+                         required time                         10.889    
+                         arrival time                          -7.848    
+  -------------------------------------------------------------------
+                         slack                                  3.041    
+
+Slack (MET) :             3.118ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[10]/CE
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        4.635ns  (logic 1.808ns (39.009%)  route 2.827ns (60.991%))
+  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.737ns = ( 10.737 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.903ns
+    Clock Pessimism Removal (CPR):    0.122ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.664     2.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y213         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y213         FDRE (Prop_fdre_C_Q)         0.398     3.301 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/Q
+                         net (fo=6, routed)           1.058     4.360    core_inst/eth_mac_inst/rx_fifo/fifo_inst/bin2gray0_return00_in[1]
+    SLICE_X3Y211         LUT6 (Prop_lut6_I0_O)        0.235     4.595 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0/O
+                         net (fo=1, routed)           0.000     4.595    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0_n_0
+    SLICE_X3Y211         CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     5.035 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry/CO[3]
+                         net (fo=1, routed)           0.000     5.035    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_n_0
+    SLICE_X3Y212         CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     5.251 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry__0/CO[0]
+                         net (fo=5, routed)           0.535     5.786    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr
+    SLICE_X5Y213         LUT3 (Prop_lut3_I0_O)        0.309     6.095 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_i_3__0/O
+                         net (fo=5, routed)           0.398     6.493    core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_reg_0
+    SLICE_X5Y214         LUT5 (Prop_lut5_I2_O)        0.105     6.598 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0/O
+                         net (fo=15, routed)          0.305     6.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0_n_0
+    SLICE_X4Y214         LUT4 (Prop_lut4_I3_O)        0.105     7.008 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0/O
+                         net (fo=13, routed)          0.530     7.538    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0_n_0
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[10]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.620    10.737    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[10]/C
+                         clock pessimism              0.122    10.859    
+                         clock uncertainty           -0.035    10.824    
+    SLICE_X3Y210         FDRE (Setup_fdre_C_CE)      -0.168    10.656    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[10]
+  -------------------------------------------------------------------
+                         required time                         10.656    
+                         arrival time                          -7.538    
+  -------------------------------------------------------------------
+                         slack                                  3.118    
+
+Slack (MET) :             3.118ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/CE
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        4.635ns  (logic 1.808ns (39.009%)  route 2.827ns (60.991%))
+  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.737ns = ( 10.737 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.903ns
+    Clock Pessimism Removal (CPR):    0.122ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.664     2.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y213         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y213         FDRE (Prop_fdre_C_Q)         0.398     3.301 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/Q
+                         net (fo=6, routed)           1.058     4.360    core_inst/eth_mac_inst/rx_fifo/fifo_inst/bin2gray0_return00_in[1]
+    SLICE_X3Y211         LUT6 (Prop_lut6_I0_O)        0.235     4.595 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0/O
+                         net (fo=1, routed)           0.000     4.595    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0_n_0
+    SLICE_X3Y211         CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     5.035 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry/CO[3]
+                         net (fo=1, routed)           0.000     5.035    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_n_0
+    SLICE_X3Y212         CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     5.251 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry__0/CO[0]
+                         net (fo=5, routed)           0.535     5.786    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr
+    SLICE_X5Y213         LUT3 (Prop_lut3_I0_O)        0.309     6.095 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_i_3__0/O
+                         net (fo=5, routed)           0.398     6.493    core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_reg_0
+    SLICE_X5Y214         LUT5 (Prop_lut5_I2_O)        0.105     6.598 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0/O
+                         net (fo=15, routed)          0.305     6.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0_n_0
+    SLICE_X4Y214         LUT4 (Prop_lut4_I3_O)        0.105     7.008 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0/O
+                         net (fo=13, routed)          0.530     7.538    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0_n_0
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.620    10.737    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/C
+                         clock pessimism              0.122    10.859    
+                         clock uncertainty           -0.035    10.824    
+    SLICE_X3Y210         FDRE (Setup_fdre_C_CE)      -0.168    10.656    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]
+  -------------------------------------------------------------------
+                         required time                         10.656    
+                         arrival time                          -7.538    
+  -------------------------------------------------------------------
+                         slack                                  3.118    
+
+Slack (MET) :             3.118ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/CE
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        4.635ns  (logic 1.808ns (39.009%)  route 2.827ns (60.991%))
+  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.737ns = ( 10.737 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.903ns
+    Clock Pessimism Removal (CPR):    0.122ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.664     2.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y213         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y213         FDRE (Prop_fdre_C_Q)         0.398     3.301 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/Q
+                         net (fo=6, routed)           1.058     4.360    core_inst/eth_mac_inst/rx_fifo/fifo_inst/bin2gray0_return00_in[1]
+    SLICE_X3Y211         LUT6 (Prop_lut6_I0_O)        0.235     4.595 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0/O
+                         net (fo=1, routed)           0.000     4.595    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0_n_0
+    SLICE_X3Y211         CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     5.035 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry/CO[3]
+                         net (fo=1, routed)           0.000     5.035    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_n_0
+    SLICE_X3Y212         CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     5.251 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry__0/CO[0]
+                         net (fo=5, routed)           0.535     5.786    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr
+    SLICE_X5Y213         LUT3 (Prop_lut3_I0_O)        0.309     6.095 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_i_3__0/O
+                         net (fo=5, routed)           0.398     6.493    core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_reg_0
+    SLICE_X5Y214         LUT5 (Prop_lut5_I2_O)        0.105     6.598 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0/O
+                         net (fo=15, routed)          0.305     6.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0_n_0
+    SLICE_X4Y214         LUT4 (Prop_lut4_I3_O)        0.105     7.008 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0/O
+                         net (fo=13, routed)          0.530     7.538    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0_n_0
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.620    10.737    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/C
+                         clock pessimism              0.122    10.859    
+                         clock uncertainty           -0.035    10.824    
+    SLICE_X3Y210         FDRE (Setup_fdre_C_CE)      -0.168    10.656    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]
+  -------------------------------------------------------------------
+                         required time                         10.656    
+                         arrival time                          -7.538    
+  -------------------------------------------------------------------
+                         slack                                  3.118    
+
+Slack (MET) :             3.118ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[3]/CE
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        4.635ns  (logic 1.808ns (39.009%)  route 2.827ns (60.991%))
+  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.737ns = ( 10.737 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.903ns
+    Clock Pessimism Removal (CPR):    0.122ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.664     2.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y213         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y213         FDRE (Prop_fdre_C_Q)         0.398     3.301 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/Q
+                         net (fo=6, routed)           1.058     4.360    core_inst/eth_mac_inst/rx_fifo/fifo_inst/bin2gray0_return00_in[1]
+    SLICE_X3Y211         LUT6 (Prop_lut6_I0_O)        0.235     4.595 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0/O
+                         net (fo=1, routed)           0.000     4.595    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0_n_0
+    SLICE_X3Y211         CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     5.035 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry/CO[3]
+                         net (fo=1, routed)           0.000     5.035    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_n_0
+    SLICE_X3Y212         CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     5.251 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry__0/CO[0]
+                         net (fo=5, routed)           0.535     5.786    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr
+    SLICE_X5Y213         LUT3 (Prop_lut3_I0_O)        0.309     6.095 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_i_3__0/O
+                         net (fo=5, routed)           0.398     6.493    core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_reg_0
+    SLICE_X5Y214         LUT5 (Prop_lut5_I2_O)        0.105     6.598 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0/O
+                         net (fo=15, routed)          0.305     6.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0_n_0
+    SLICE_X4Y214         LUT4 (Prop_lut4_I3_O)        0.105     7.008 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0/O
+                         net (fo=13, routed)          0.530     7.538    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0_n_0
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[3]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.620    10.737    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[3]/C
+                         clock pessimism              0.122    10.859    
+                         clock uncertainty           -0.035    10.824    
+    SLICE_X3Y210         FDRE (Setup_fdre_C_CE)      -0.168    10.656    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[3]
+  -------------------------------------------------------------------
+                         required time                         10.656    
+                         arrival time                          -7.538    
+  -------------------------------------------------------------------
+                         slack                                  3.118    
+
+Slack (MET) :             3.118ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[4]/CE
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        4.635ns  (logic 1.808ns (39.009%)  route 2.827ns (60.991%))
+  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.737ns = ( 10.737 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.903ns
+    Clock Pessimism Removal (CPR):    0.122ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.664     2.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y213         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y213         FDRE (Prop_fdre_C_Q)         0.398     3.301 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/Q
+                         net (fo=6, routed)           1.058     4.360    core_inst/eth_mac_inst/rx_fifo/fifo_inst/bin2gray0_return00_in[1]
+    SLICE_X3Y211         LUT6 (Prop_lut6_I0_O)        0.235     4.595 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0/O
+                         net (fo=1, routed)           0.000     4.595    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0_n_0
+    SLICE_X3Y211         CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     5.035 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry/CO[3]
+                         net (fo=1, routed)           0.000     5.035    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_n_0
+    SLICE_X3Y212         CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     5.251 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry__0/CO[0]
+                         net (fo=5, routed)           0.535     5.786    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr
+    SLICE_X5Y213         LUT3 (Prop_lut3_I0_O)        0.309     6.095 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_i_3__0/O
+                         net (fo=5, routed)           0.398     6.493    core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_reg_0
+    SLICE_X5Y214         LUT5 (Prop_lut5_I2_O)        0.105     6.598 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0/O
+                         net (fo=15, routed)          0.305     6.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0_n_0
+    SLICE_X4Y214         LUT4 (Prop_lut4_I3_O)        0.105     7.008 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0/O
+                         net (fo=13, routed)          0.530     7.538    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0_n_0
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[4]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.620    10.737    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[4]/C
+                         clock pessimism              0.122    10.859    
+                         clock uncertainty           -0.035    10.824    
+    SLICE_X3Y210         FDRE (Setup_fdre_C_CE)      -0.168    10.656    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[4]
+  -------------------------------------------------------------------
+                         required time                         10.656    
+                         arrival time                          -7.538    
+  -------------------------------------------------------------------
+                         slack                                  3.118    
+
+Slack (MET) :             3.118ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/CE
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        4.635ns  (logic 1.808ns (39.009%)  route 2.827ns (60.991%))
+  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.737ns = ( 10.737 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.903ns
+    Clock Pessimism Removal (CPR):    0.122ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.664     2.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y213         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y213         FDRE (Prop_fdre_C_Q)         0.398     3.301 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/Q
+                         net (fo=6, routed)           1.058     4.360    core_inst/eth_mac_inst/rx_fifo/fifo_inst/bin2gray0_return00_in[1]
+    SLICE_X3Y211         LUT6 (Prop_lut6_I0_O)        0.235     4.595 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0/O
+                         net (fo=1, routed)           0.000     4.595    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0_n_0
+    SLICE_X3Y211         CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     5.035 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry/CO[3]
+                         net (fo=1, routed)           0.000     5.035    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_n_0
+    SLICE_X3Y212         CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     5.251 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry__0/CO[0]
+                         net (fo=5, routed)           0.535     5.786    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr
+    SLICE_X5Y213         LUT3 (Prop_lut3_I0_O)        0.309     6.095 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_i_3__0/O
+                         net (fo=5, routed)           0.398     6.493    core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_reg_0
+    SLICE_X5Y214         LUT5 (Prop_lut5_I2_O)        0.105     6.598 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0/O
+                         net (fo=15, routed)          0.305     6.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0_n_0
+    SLICE_X4Y214         LUT4 (Prop_lut4_I3_O)        0.105     7.008 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0/O
+                         net (fo=13, routed)          0.530     7.538    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0_n_0
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.620    10.737    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/C
+                         clock pessimism              0.122    10.859    
+                         clock uncertainty           -0.035    10.824    
+    SLICE_X3Y210         FDRE (Setup_fdre_C_CE)      -0.168    10.656    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]
+  -------------------------------------------------------------------
+                         required time                         10.656    
+                         arrival time                          -7.538    
+  -------------------------------------------------------------------
+                         slack                                  3.118    
+
+Slack (MET) :             3.118ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[8]/CE
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        4.635ns  (logic 1.808ns (39.009%)  route 2.827ns (60.991%))
+  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.737ns = ( 10.737 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.903ns
+    Clock Pessimism Removal (CPR):    0.122ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.664     2.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y213         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y213         FDRE (Prop_fdre_C_Q)         0.398     3.301 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/Q
+                         net (fo=6, routed)           1.058     4.360    core_inst/eth_mac_inst/rx_fifo/fifo_inst/bin2gray0_return00_in[1]
+    SLICE_X3Y211         LUT6 (Prop_lut6_I0_O)        0.235     4.595 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0/O
+                         net (fo=1, routed)           0.000     4.595    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0_n_0
+    SLICE_X3Y211         CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     5.035 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry/CO[3]
+                         net (fo=1, routed)           0.000     5.035    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_n_0
+    SLICE_X3Y212         CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     5.251 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry__0/CO[0]
+                         net (fo=5, routed)           0.535     5.786    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr
+    SLICE_X5Y213         LUT3 (Prop_lut3_I0_O)        0.309     6.095 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_i_3__0/O
+                         net (fo=5, routed)           0.398     6.493    core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_reg_0
+    SLICE_X5Y214         LUT5 (Prop_lut5_I2_O)        0.105     6.598 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0/O
+                         net (fo=15, routed)          0.305     6.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0_n_0
+    SLICE_X4Y214         LUT4 (Prop_lut4_I3_O)        0.105     7.008 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0/O
+                         net (fo=13, routed)          0.530     7.538    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0_n_0
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[8]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.620    10.737    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[8]/C
+                         clock pessimism              0.122    10.859    
+                         clock uncertainty           -0.035    10.824    
+    SLICE_X3Y210         FDRE (Setup_fdre_C_CE)      -0.168    10.656    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[8]
+  -------------------------------------------------------------------
+                         required time                         10.656    
+                         arrival time                          -7.538    
+  -------------------------------------------------------------------
+                         slack                                  3.118    
+
+Slack (MET) :             3.118ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[9]/CE
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        4.635ns  (logic 1.808ns (39.009%)  route 2.827ns (60.991%))
+  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.044ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.737ns = ( 10.737 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.903ns
+    Clock Pessimism Removal (CPR):    0.122ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.664     2.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y213         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y213         FDRE (Prop_fdre_C_Q)         0.398     3.301 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/Q
+                         net (fo=6, routed)           1.058     4.360    core_inst/eth_mac_inst/rx_fifo/fifo_inst/bin2gray0_return00_in[1]
+    SLICE_X3Y211         LUT6 (Prop_lut6_I0_O)        0.235     4.595 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0/O
+                         net (fo=1, routed)           0.000     4.595    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0_n_0
+    SLICE_X3Y211         CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     5.035 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry/CO[3]
+                         net (fo=1, routed)           0.000     5.035    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_n_0
+    SLICE_X3Y212         CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     5.251 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry__0/CO[0]
+                         net (fo=5, routed)           0.535     5.786    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr
+    SLICE_X5Y213         LUT3 (Prop_lut3_I0_O)        0.309     6.095 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_i_3__0/O
+                         net (fo=5, routed)           0.398     6.493    core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_reg_0
+    SLICE_X5Y214         LUT5 (Prop_lut5_I2_O)        0.105     6.598 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0/O
+                         net (fo=15, routed)          0.305     6.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0_n_0
+    SLICE_X4Y214         LUT4 (Prop_lut4_I3_O)        0.105     7.008 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0/O
+                         net (fo=13, routed)          0.530     7.538    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0_n_0
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[9]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.620    10.737    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[9]/C
+                         clock pessimism              0.122    10.859    
+                         clock uncertainty           -0.035    10.824    
+    SLICE_X3Y210         FDRE (Setup_fdre_C_CE)      -0.168    10.656    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[9]
+  -------------------------------------------------------------------
+                         required time                         10.656    
+                         arrival time                          -7.538    
+  -------------------------------------------------------------------
+                         slack                                  3.118    
+
+Slack (MET) :             3.241ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[0]/CE
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        4.509ns  (logic 1.808ns (40.100%)  route 2.701ns (59.900%))
+  Logic Levels:           6  (CARRY4=2 LUT3=1 LUT4=1 LUT5=1 LUT6=1)
+  Clock Path Skew:        -0.047ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.734ns = ( 10.734 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.903ns
+    Clock Pessimism Removal (CPR):    0.122ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.664     2.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y213         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y213         FDRE (Prop_fdre_C_Q)         0.398     3.301 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_reg_reg[2]/Q
+                         net (fo=6, routed)           1.058     4.360    core_inst/eth_mac_inst/rx_fifo/fifo_inst/bin2gray0_return00_in[1]
+    SLICE_X3Y211         LUT6 (Prop_lut6_I0_O)        0.235     4.595 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0/O
+                         net (fo=1, routed)           0.000     4.595    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_i_4__0_n_0
+    SLICE_X3Y211         CARRY4 (Prop_carry4_S[0]_CO[3])
+                                                      0.440     5.035 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry/CO[3]
+                         net (fo=1, routed)           0.000     5.035    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry_n_0
+    SLICE_X3Y212         CARRY4 (Prop_carry4_CI_CO[0])
+                                                      0.216     5.251 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr_carry__0/CO[0]
+                         net (fo=5, routed)           0.535     5.786    core_inst/eth_mac_inst/rx_fifo/fifo_inst/full_wr
+    SLICE_X5Y213         LUT3 (Prop_lut3_I0_O)        0.309     6.095 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_i_3__0/O
+                         net (fo=5, routed)           0.398     6.493    core_inst/eth_mac_inst/rx_fifo/fifo_inst/drop_frame_reg_reg_0
+    SLICE_X5Y214         LUT5 (Prop_lut5_I2_O)        0.105     6.598 f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0/O
+                         net (fo=15, routed)          0.305     6.903    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_3__0_n_0
+    SLICE_X4Y214         LUT4 (Prop_lut4_I3_O)        0.105     7.008 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0/O
+                         net (fo=13, routed)          0.404     7.412    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]_i_1__0_n_0
+    SLICE_X3Y214         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[0]/CE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.617    10.734    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y214         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[0]/C
+                         clock pessimism              0.122    10.856    
+                         clock uncertainty           -0.035    10.821    
+    SLICE_X3Y214         FDRE (Setup_fdre_C_CE)      -0.168    10.653    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[0]
+  -------------------------------------------------------------------
+                         required time                         10.653    
+                         arrival time                          -7.412    
+  -------------------------------------------------------------------
+                         slack                                  3.241    
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             0.118ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[9]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.196ns  (logic 0.141ns (71.838%)  route 0.055ns (28.162%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    0.492ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y211         FDRE (Prop_fdre_C_Q)         0.141     0.943 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/Q
+                         net (fo=1, routed)           0.055     0.998    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg[9]
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[9]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[9]/C
+                         clock pessimism             -0.492     0.802    
+    SLICE_X5Y211         FDRE (Hold_fdre_C_D)         0.078     0.880    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[9]
+  -------------------------------------------------------------------
+                         required time                         -0.880    
+                         arrival time                           0.998    
+  -------------------------------------------------------------------
+                         slack                                  0.118    
+
+Slack (MET) :             0.120ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[8]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.196ns  (logic 0.141ns (71.838%)  route 0.055ns (28.162%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    0.492ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y211         FDRE (Prop_fdre_C_Q)         0.141     0.943 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/Q
+                         net (fo=1, routed)           0.055     0.998    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg[8]
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[8]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[8]/C
+                         clock pessimism             -0.492     0.802    
+    SLICE_X5Y211         FDRE (Hold_fdre_C_D)         0.076     0.878    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[8]
+  -------------------------------------------------------------------
+                         required time                         -0.878    
+                         arrival time                           0.998    
+  -------------------------------------------------------------------
+                         slack                                  0.120    
+
+Slack (MET) :             0.121ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[10]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[10]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.196ns  (logic 0.141ns (71.838%)  route 0.055ns (28.162%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    0.492ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[10]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y211         FDRE (Prop_fdre_C_Q)         0.141     0.943 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[10]/Q
+                         net (fo=1, routed)           0.055     0.998    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg[10]
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[10]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[10]/C
+                         clock pessimism             -0.492     0.802    
+    SLICE_X5Y211         FDRE (Hold_fdre_C_D)         0.075     0.877    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[10]
+  -------------------------------------------------------------------
+                         required time                         -0.877    
+                         arrival time                           0.998    
+  -------------------------------------------------------------------
+                         slack                                  0.121    
+
+Slack (MET) :             0.121ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.196ns  (logic 0.141ns (71.838%)  route 0.055ns (28.162%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    0.492ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X7Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y211         FDRE (Prop_fdre_C_Q)         0.141     0.943 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[2]/Q
+                         net (fo=1, routed)           0.055     0.998    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg[2]
+    SLICE_X7Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X7Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[2]/C
+                         clock pessimism             -0.492     0.802    
+    SLICE_X7Y211         FDRE (Hold_fdre_C_D)         0.075     0.877    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[2]
+  -------------------------------------------------------------------
+                         required time                         -0.877    
+                         arrival time                           0.998    
+  -------------------------------------------------------------------
+                         slack                                  0.121    
+
+Slack (MET) :             0.125ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[3]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[3]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.196ns  (logic 0.141ns (71.838%)  route 0.055ns (28.162%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    0.492ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X7Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y211         FDRE (Prop_fdre_C_Q)         0.141     0.943 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[3]/Q
+                         net (fo=1, routed)           0.055     0.998    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg[3]
+    SLICE_X7Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X7Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[3]/C
+                         clock pessimism             -0.492     0.802    
+    SLICE_X7Y211         FDRE (Hold_fdre_C_D)         0.071     0.873    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[3]
+  -------------------------------------------------------------------
+                         required time                         -0.873    
+                         arrival time                           0.998    
+  -------------------------------------------------------------------
+                         slack                                  0.125    
+
+Slack (MET) :             0.125ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[7]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.196ns  (logic 0.141ns (71.838%)  route 0.055ns (28.162%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    0.492ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y211         FDRE (Prop_fdre_C_Q)         0.141     0.943 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/Q
+                         net (fo=1, routed)           0.055     0.998    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg[7]
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[7]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[7]/C
+                         clock pessimism             -0.492     0.802    
+    SLICE_X5Y211         FDRE (Hold_fdre_C_D)         0.071     0.873    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg[7]
+  -------------------------------------------------------------------
+                         required time                         -0.873    
+                         arrival time                           0.998    
+  -------------------------------------------------------------------
+                         slack                                  0.125    
+
+Slack (MET) :             0.127ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[2]/D
+                            (rising edge-triggered cell FDPE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.198ns  (logic 0.141ns (71.201%)  route 0.057ns (28.799%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.289ns
+    Source Clock Delay      (SCD):    0.799ns
+    Clock Pessimism Removal (CPR):    0.490ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.258     0.799    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/output_clk
+    SLICE_X4Y216         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y216         FDPE (Prop_fdpe_C_Q)         0.141     0.940 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[3]/Q
+                         net (fo=1, routed)           0.057     0.997    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg_n_0_[3]
+    SLICE_X4Y216         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.293     1.289    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/output_clk
+    SLICE_X4Y216         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[2]/C
+                         clock pessimism             -0.490     0.799    
+    SLICE_X4Y216         FDPE (Hold_fdpe_C_D)         0.071     0.870    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[2]
+  -------------------------------------------------------------------
+                         required time                         -0.870    
+                         arrival time                           0.997    
+  -------------------------------------------------------------------
+                         slack                                  0.127    
+
+Slack (MET) :             0.130ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3_reg[6]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[6]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.208ns  (logic 0.141ns (67.835%)  route 0.067ns (32.165%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.284ns
+    Source Clock Delay      (SCD):    0.794ns
+    Clock Pessimism Removal (CPR):    0.490ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.253     0.794    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/output_clk
+    SLICE_X5Y221         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3_reg[6]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y221         FDRE (Prop_fdre_C_Q)         0.141     0.935 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3_reg[6]/Q
+                         net (fo=2, routed)           0.067     1.002    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3[6]
+    SLICE_X5Y221         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[6]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.288     1.284    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/output_clk
+    SLICE_X5Y221         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[6]/C
+                         clock pessimism             -0.490     0.794    
+    SLICE_X5Y221         FDRE (Hold_fdre_C_D)         0.078     0.872    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[6]
+  -------------------------------------------------------------------
+                         required time                         -0.872    
+                         arrival time                           1.002    
+  -------------------------------------------------------------------
+                         slack                                  0.130    
+
+Slack (MET) :             0.132ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[4]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.208ns  (logic 0.141ns (67.807%)  route 0.067ns (32.193%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.284ns
+    Source Clock Delay      (SCD):    0.794ns
+    Clock Pessimism Removal (CPR):    0.490ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.253     0.794    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/output_clk
+    SLICE_X5Y221         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y221         FDRE (Prop_fdre_C_Q)         0.141     0.935 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3_reg[4]/Q
+                         net (fo=2, routed)           0.067     1.002    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3[4]
+    SLICE_X5Y221         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.288     1.284    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/output_clk
+    SLICE_X5Y221         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[4]/C
+                         clock pessimism             -0.490     0.794    
+    SLICE_X5Y221         FDRE (Hold_fdre_C_D)         0.076     0.870    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[4]
+  -------------------------------------------------------------------
+                         required time                         -0.870    
+                         arrival time                           1.002    
+  -------------------------------------------------------------------
+                         slack                                  0.132    
+
+Slack (MET) :             0.137ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Hold (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.208ns  (logic 0.141ns (67.807%)  route 0.067ns (32.193%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.284ns
+    Source Clock Delay      (SCD):    0.794ns
+    Clock Pessimism Removal (CPR):    0.490ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.253     0.794    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/output_clk
+    SLICE_X5Y221         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y221         FDRE (Prop_fdre_C_Q)         0.141     0.935 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3_reg[2]/Q
+                         net (fo=2, routed)           0.067     1.002    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d3[2]
+    SLICE_X5Y221         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.288     1.284    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/output_clk
+    SLICE_X5Y221         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[2]/C
+                         clock pessimism             -0.490     0.794    
+    SLICE_X5Y221         FDRE (Hold_fdre_C_D)         0.071     0.865    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/eth_mac_1g_inst/axis_gmii_rx_inst/gmii_rxd_d4_reg[2]
+  -------------------------------------------------------------------
+                         required time                         -0.865    
+                         arrival time                           1.002    
+  -------------------------------------------------------------------
+                         slack                                  0.137    
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name:         phy_rx_clk
+Waveform(ns):       { 0.000 4.000 }
+Period(ns):         8.000
+Sources:            { phy_rx_clk }
+
+Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
+Min Period        n/a     BUFR/I              n/a            2.666         8.000       5.334      BUFR_X0Y17     core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/I
+Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.170         8.000       5.830      RAMB36_X0Y43   core_inst/eth_mac_inst/rx_fifo/fifo_inst/mem_reg_0/CLKARDCLK
+Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.170         8.000       5.830      RAMB18_X0Y84   core_inst/eth_mac_inst/rx_fifo/fifo_inst/mem_reg_1/CLKARDCLK
+Min Period        n/a     IDDR/C              n/a            1.474         8.000       6.526      ILOGIC_X0Y232  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[0].iddr_inst/C
+Min Period        n/a     IDDR/C              n/a            1.474         8.000       6.526      ILOGIC_X0Y231  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[1].iddr_inst/C
+Min Period        n/a     IDDR/C              n/a            1.474         8.000       6.526      ILOGIC_X0Y227  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[2].iddr_inst/C
+Min Period        n/a     IDDR/C              n/a            1.474         8.000       6.526      ILOGIC_X0Y224  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[3].iddr_inst/C
+Min Period        n/a     IDDR/C              n/a            1.474         8.000       6.526      ILOGIC_X0Y223  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[4].iddr_inst/C
+Min Period        n/a     BUFIO/I             n/a            1.470         8.000       6.530      BUFIO_X0Y19    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/I
+Min Period        n/a     FDRE/C              n/a            1.000         8.000       7.000      SLICE_X2Y218   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[0]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X2Y218   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[0]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X2Y218   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[0]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X2Y218   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[1]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X2Y218   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[1]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[0]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[0]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[1]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[1]/C
+Low Pulse Width   Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[2]/C
+Low Pulse Width   Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[2]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X2Y218   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[0]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X2Y218   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[0]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X2Y218   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[1]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X2Y218   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[1]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[0]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[0]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[1]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[1]/C
+High Pulse Width  Slow    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[2]/C
+High Pulse Width  Fast    FDRE/C              n/a            0.500         4.000       3.500      SLICE_X4Y215   core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[2]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  clk_mmcm_out
+  To Clock:  clk90_mmcm_out
+
+Setup :            0  Failing Endpoints,  Worst Slack        0.478ns,  Total Violation        0.000ns
+Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             0.478ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_1_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/D1
+                            (rising edge-triggered cell ODDR clocked by clk90_mmcm_out  {rise@2.000ns fall@6.000ns period=8.000ns})
+  Path Group:             clk90_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            2.000ns  (MaxDelay Path 2.000ns)
+  Data Path Delay:        0.815ns  (logic 0.379ns (46.513%)  route 0.436ns (53.487%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 2.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y218                                      0.000     0.000 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_1_reg/C
+    SLICE_X0Y218         FDRE (Prop_fdre_C_Q)         0.379     0.379 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_1_reg/Q
+                         net (fo=3, routed)           0.436     0.815    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/rgmii_tx_clk_1
+    OLOGIC_X0Y219        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/D1
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    2.000     2.000    
+    OLOGIC_X0Y219        ODDR (Setup_oddr_C_D1)      -0.707     1.293    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst
+  -------------------------------------------------------------------
+                         required time                          1.293    
+                         arrival time                          -0.815    
+  -------------------------------------------------------------------
+                         slack                                  0.478    
+
+Slack (MET) :             0.484ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_2_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/D2
+                            (rising edge-triggered cell ODDR clocked by clk90_mmcm_out  {rise@2.000ns fall@6.000ns period=8.000ns})
+  Path Group:             clk90_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            2.000ns  (MaxDelay Path 2.000ns)
+  Data Path Delay:        0.809ns  (logic 0.379ns (46.841%)  route 0.430ns (53.159%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 2.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y218                                      0.000     0.000 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_2_reg/C
+    SLICE_X1Y218         FDRE (Prop_fdre_C_Q)         0.379     0.379 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_2_reg/Q
+                         net (fo=3, routed)           0.430     0.809    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst_0
+    OLOGIC_X0Y219        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/D2
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    2.000     2.000    
+    OLOGIC_X0Y219        ODDR (Setup_oddr_C_D2)      -0.707     1.293    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst
+  -------------------------------------------------------------------
+                         required time                          1.293    
+                         arrival time                          -0.809    
+  -------------------------------------------------------------------
+                         slack                                  0.484    
+
+
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  phy_rx_clk
+  To Clock:  clk_mmcm_out
+
+Setup :            0  Failing Endpoints,  Worst Slack        6.764ns,  Total Violation        0.000ns
+Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             6.764ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[12]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[12]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        1.162ns  (logic 0.379ns (32.625%)  route 0.783ns (67.375%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y213                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[12]/C
+    SLICE_X5Y213         FDRE (Prop_fdre_C_Q)         0.379     0.379 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[12]/Q
+                         net (fo=1, routed)           0.783     1.162    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[12]
+    SLICE_X5Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[12]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X5Y210         FDRE (Setup_fdre_C_D)       -0.074     7.926    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[12]
+  -------------------------------------------------------------------
+                         required time                          7.926    
+                         arrival time                          -1.162    
+  -------------------------------------------------------------------
+                         slack                                  6.764    
+
+Slack (MET) :             6.772ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        1.017ns  (logic 0.348ns (34.216%)  route 0.669ns (65.784%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y214                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[1]/C
+    SLICE_X3Y214         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[1]/Q
+                         net (fo=1, routed)           0.669     1.017    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[1]
+    SLICE_X3Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X3Y212         FDRE (Setup_fdre_C_D)       -0.211     7.789    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[1]
+  -------------------------------------------------------------------
+                         required time                          7.789    
+                         arrival time                          -1.017    
+  -------------------------------------------------------------------
+                         slack                                  6.772    
+
+Slack (MET) :             6.882ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[6]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[6]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        1.043ns  (logic 0.379ns (36.342%)  route 0.664ns (63.658%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y214                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[6]/C
+    SLICE_X3Y214         FDRE (Prop_fdre_C_Q)         0.379     0.379 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[6]/Q
+                         net (fo=1, routed)           0.664     1.043    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[6]
+    SLICE_X3Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[6]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X3Y212         FDRE (Setup_fdre_C_D)       -0.075     7.925    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[6]
+  -------------------------------------------------------------------
+                         required time                          7.925    
+                         arrival time                          -1.043    
+  -------------------------------------------------------------------
+                         slack                                  6.882    
+
+Slack (MET) :             6.923ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.867ns  (logic 0.348ns (40.132%)  route 0.519ns (59.868%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y214                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[7]/C
+    SLICE_X3Y214         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[7]/Q
+                         net (fo=1, routed)           0.519     0.867    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[7]
+    SLICE_X3Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X3Y212         FDRE (Setup_fdre_C_D)       -0.210     7.790    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]
+  -------------------------------------------------------------------
+                         required time                          7.790    
+                         arrival time                          -0.867    
+  -------------------------------------------------------------------
+                         slack                                  6.923    
+
+Slack (MET) :             6.962ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_sync_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.826ns  (logic 0.348ns (42.136%)  route 0.478ns (57.864%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y215                                      0.000     0.000 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[2]/C
+    SLICE_X4Y215         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_reg[2]/Q
+                         net (fo=2, routed)           0.478     0.826    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale[2]
+    SLICE_X3Y217         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_sync_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X3Y217         FDRE (Setup_fdre_C_D)       -0.212     7.788    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_sync_reg[0]
+  -------------------------------------------------------------------
+                         required time                          7.788    
+                         arrival time                          -0.826    
+  -------------------------------------------------------------------
+                         slack                                  6.962    
+
+Slack (MET) :             6.992ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[9]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[9]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.832ns  (logic 0.348ns (41.824%)  route 0.484ns (58.176%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[9]/C
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[9]/Q
+                         net (fo=1, routed)           0.484     0.832    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[9]
+    SLICE_X3Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[9]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X3Y209         FDRE (Setup_fdre_C_D)       -0.176     7.824    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[9]
+  -------------------------------------------------------------------
+                         required time                          7.824    
+                         arrival time                          -0.832    
+  -------------------------------------------------------------------
+                         slack                                  6.992    
+
+Slack (MET) :             7.061ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_reg_reg/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync1_reg_reg/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.907ns  (logic 0.379ns (41.779%)  route 0.528ns (58.221%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y215                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_reg_reg/C
+    SLICE_X4Y215         FDRE (Prop_fdre_C_Q)         0.379     0.379 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_reg_reg/Q
+                         net (fo=6, routed)           0.528     0.907    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_reg_reg_0
+    SLICE_X3Y215         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync1_reg_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X3Y215         FDRE (Setup_fdre_C_D)       -0.032     7.968    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync1_reg_reg
+  -------------------------------------------------------------------
+                         required time                          7.968    
+                         arrival time                          -0.907    
+  -------------------------------------------------------------------
+                         slack                                  7.061    
+
+Slack (MET) :             7.068ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[4]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.885ns  (logic 0.379ns (42.842%)  route 0.506ns (57.158%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[4]/C
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.379     0.379 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[4]/Q
+                         net (fo=1, routed)           0.506     0.885    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[4]
+    SLICE_X3Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X3Y209         FDRE (Setup_fdre_C_D)       -0.047     7.953    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[4]
+  -------------------------------------------------------------------
+                         required time                          7.953    
+                         arrival time                          -0.885    
+  -------------------------------------------------------------------
+                         slack                                  7.068    
+
+Slack (MET) :             7.079ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[5]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.727ns  (logic 0.348ns (47.895%)  route 0.379ns (52.105%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/C
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/Q
+                         net (fo=1, routed)           0.379     0.727    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[5]
+    SLICE_X3Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[5]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X3Y209         FDRE (Setup_fdre_C_D)       -0.194     7.806    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[5]
+  -------------------------------------------------------------------
+                         required time                          7.806    
+                         arrival time                          -0.727    
+  -------------------------------------------------------------------
+                         slack                                  7.079    
+
+Slack (MET) :             7.114ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             clk_mmcm_out
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.722ns  (logic 0.348ns (48.168%)  route 0.374ns (51.832%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/C
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/Q
+                         net (fo=1, routed)           0.374     0.722    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[11]
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X2Y209         FDRE (Setup_fdre_C_D)       -0.164     7.836    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]
+  -------------------------------------------------------------------
+                         required time                          7.836    
+                         arrival time                          -0.722    
+  -------------------------------------------------------------------
+                         slack                                  7.114    
+
+
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock:  clk_mmcm_out
+  To Clock:  phy_rx_clk
+
+Setup :            0  Failing Endpoints,  Worst Slack        6.805ns,  Total Violation        0.000ns
+Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             6.805ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[8]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.985ns  (logic 0.348ns (35.313%)  route 0.637ns (64.687%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y210                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[8]/C
+    SLICE_X7Y210         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[8]/Q
+                         net (fo=1, routed)           0.637     0.985    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[8]
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X5Y211         FDRE (Setup_fdre_C_D)       -0.210     7.790    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]
+  -------------------------------------------------------------------
+                         required time                          7.790    
+                         arrival time                          -0.985    
+  -------------------------------------------------------------------
+                         slack                                  6.805    
+
+Slack (MET) :             6.902ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.889ns  (logic 0.348ns (39.133%)  route 0.541ns (60.867%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y209                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[2]/C
+    SLICE_X7Y209         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[2]/Q
+                         net (fo=1, routed)           0.541     0.889    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[2]
+    SLICE_X7Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X7Y211         FDRE (Setup_fdre_C_D)       -0.209     7.791    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[2]
+  -------------------------------------------------------------------
+                         required time                          7.791    
+                         arrival time                          -0.889    
+  -------------------------------------------------------------------
+                         slack                                  6.902    
+
+Slack (MET) :             6.946ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        1.023ns  (logic 0.379ns (37.046%)  route 0.644ns (62.954%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y209                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[1]/C
+    SLICE_X7Y209         FDRE (Prop_fdre_C_Q)         0.379     0.379 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[1]/Q
+                         net (fo=1, routed)           0.644     1.023    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[1]
+    SLICE_X6Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X6Y211         FDRE (Setup_fdre_C_D)       -0.031     7.969    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[1]
+  -------------------------------------------------------------------
+                         required time                          7.969    
+                         arrival time                          -1.023    
+  -------------------------------------------------------------------
+                         slack                                  6.946    
+
+Slack (MET) :             6.971ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[4]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.865ns  (logic 0.348ns (40.230%)  route 0.517ns (59.770%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y209                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[4]/C
+    SLICE_X7Y209         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[4]/Q
+                         net (fo=1, routed)           0.517     0.865    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[4]
+    SLICE_X6Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X6Y212         FDRE (Setup_fdre_C_D)       -0.164     7.836    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[4]
+  -------------------------------------------------------------------
+                         required time                          7.836    
+                         arrival time                          -0.865    
+  -------------------------------------------------------------------
+                         slack                                  6.971    
+
+Slack (MET) :             7.005ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[6]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[6]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.827ns  (logic 0.348ns (42.092%)  route 0.479ns (57.908%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y209                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[6]/C
+    SLICE_X7Y209         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[6]/Q
+                         net (fo=1, routed)           0.479     0.827    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[6]
+    SLICE_X6Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[6]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X6Y212         FDRE (Setup_fdre_C_D)       -0.168     7.832    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[6]
+  -------------------------------------------------------------------
+                         required time                          7.832    
+                         arrival time                          -0.827    
+  -------------------------------------------------------------------
+                         slack                                  7.005    
+
+Slack (MET) :             7.040ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[11]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[11]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.927ns  (logic 0.433ns (46.729%)  route 0.494ns (53.271%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y210                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[11]/C
+    SLICE_X6Y210         FDRE (Prop_fdre_C_Q)         0.433     0.433 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[11]/Q
+                         net (fo=1, routed)           0.494     0.927    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[11]
+    SLICE_X6Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[11]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X6Y212         FDRE (Setup_fdre_C_D)       -0.033     7.967    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[11]
+  -------------------------------------------------------------------
+                         required time                          7.967    
+                         arrival time                          -0.927    
+  -------------------------------------------------------------------
+                         slack                                  7.040    
+
+Slack (MET) :             7.067ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[9]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.734ns  (logic 0.398ns (54.204%)  route 0.336ns (45.796%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y210                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[9]/C
+    SLICE_X6Y210         FDRE (Prop_fdre_C_Q)         0.398     0.398 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[9]/Q
+                         net (fo=1, routed)           0.336     0.734    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[9]
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X5Y211         FDRE (Setup_fdre_C_D)       -0.199     7.801    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]
+  -------------------------------------------------------------------
+                         required time                          7.801    
+                         arrival time                          -0.734    
+  -------------------------------------------------------------------
+                         slack                                  7.067    
+
+Slack (MET) :             7.069ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_rst_sync2_reg_reg/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.762ns  (logic 0.348ns (45.694%)  route 0.414ns (54.306%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y206                                      0.000     0.000 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[3]/C
+    SLICE_X5Y206         FDPE (Prop_fdpe_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[3]/Q
+                         net (fo=3, routed)           0.414     0.762    core_inst/eth_mac_inst/rx_fifo/fifo_inst/D[0]
+    SLICE_X5Y207         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_rst_sync2_reg_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X5Y207         FDRE (Setup_fdre_C_D)       -0.169     7.831    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_rst_sync2_reg_reg
+  -------------------------------------------------------------------
+                         required time                          7.831    
+                         arrival time                          -0.762    
+  -------------------------------------------------------------------
+                         slack                                  7.069    
+
+Slack (MET) :             7.074ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync3_reg_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_ack_sync1_reg_reg/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.760ns  (logic 0.348ns (45.799%)  route 0.412ns (54.201%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y215                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync3_reg_reg/C
+    SLICE_X3Y215         FDRE (Prop_fdre_C_Q)         0.348     0.348 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync3_reg_reg/Q
+                         net (fo=2, routed)           0.412     0.760    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync3_reg
+    SLICE_X3Y216         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_ack_sync1_reg_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X3Y216         FDRE (Setup_fdre_C_D)       -0.166     7.834    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_ack_sync1_reg_reg
+  -------------------------------------------------------------------
+                         required time                          7.834    
+                         arrival time                          -0.760    
+  -------------------------------------------------------------------
+                         slack                                  7.074    
+
+Slack (MET) :             7.089ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[0]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             phy_rx_clk
+  Path Type:              Setup (Max at Slow Process Corner)
+  Requirement:            8.000ns  (MaxDelay Path 8.000ns)
+  Data Path Delay:        0.878ns  (logic 0.379ns (43.145%)  route 0.499ns (56.855%))
+  Logic Levels:           0  
+  Timing Exception:       MaxDelay Path 8.000ns -datapath_only
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y209                                      0.000     0.000 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[0]/C
+    SLICE_X7Y209         FDRE (Prop_fdre_C_Q)         0.379     0.379 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[0]/Q
+                         net (fo=1, routed)           0.499     0.878    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[0]
+    SLICE_X6Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         max delay                    8.000     8.000    
+    SLICE_X6Y211         FDRE (Setup_fdre_C_D)       -0.033     7.967    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[0]
+  -------------------------------------------------------------------
+                         required time                          7.967    
+                         arrival time                          -0.878    
+  -------------------------------------------------------------------
+                         slack                                  7.089    
+
+
+
+
+
+---------------------------------------------------------------------------------------------------
+Path Group:  **async_default**
+From Clock:  clk_mmcm_out
+  To Clock:  clk_mmcm_out
+
+Setup :            0  Failing Endpoints,  Worst Slack        6.806ns,  Total Violation        0.000ns
+Hold  :            0  Failing Endpoints,  Worst Slack        0.385ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             6.806ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg/PRE
+                            (recovery check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             **async_default**
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Requirement:            8.000ns  (clk_mmcm_out rise@8.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.810ns  (logic 0.379ns (46.789%)  route 0.431ns (53.211%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns = ( 12.855 - 8.000 ) 
+    Source Clock Delay      (SCD):    5.143ns
+    Clock Pessimism Removal (CPR):    0.260ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.553     5.143    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_int
+    SLICE_X4Y199         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y199         FDPE (Prop_fdpe_C_Q)         0.379     5.522 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/Q
+                         net (fo=30, routed)          0.431     5.953    core_inst/eth_mac_inst/tx_fifo/fifo_inst/m_axis_tvalid_pipe_reg_reg[1]_2[0]
+    SLICE_X6Y199         FDPE                                         f  core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      8.000     8.000 r  
+    R4                                                0.000     8.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     8.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     8.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     9.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     9.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452    11.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077    11.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.444    12.855    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X6Y199         FDPE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg/C
+                         clock pessimism              0.260    13.115    
+                         clock uncertainty           -0.064    13.051    
+    SLICE_X6Y199         FDPE (Recov_fdpe_C_PRE)     -0.292    12.759    core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg
+  -------------------------------------------------------------------
+                         required time                         12.759    
+                         arrival time                          -5.953    
+  -------------------------------------------------------------------
+                         slack                                  6.806    
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             0.385ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg/PRE
+                            (removal check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             **async_default**
+  Path Type:              Removal (Min at Fast Process Corner)
+  Requirement:            0.000ns  (clk_mmcm_out rise@0.000ns - clk_mmcm_out rise@0.000ns)
+  Data Path Delay:        0.330ns  (logic 0.141ns (42.725%)  route 0.189ns (57.275%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.459ns
+    Source Clock Delay      (SCD):    2.060ns
+    Clock Pessimism Removal (CPR):    0.382ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.653     2.060    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_int
+    SLICE_X4Y199         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y199         FDPE (Prop_fdpe_C_Q)         0.141     2.201 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/Q
+                         net (fo=30, routed)          0.189     2.390    core_inst/eth_mac_inst/tx_fifo/fifo_inst/m_axis_tvalid_pipe_reg_reg[1]_2[0]
+    SLICE_X6Y199         FDPE                                         f  core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.927     2.459    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X6Y199         FDPE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg/C
+                         clock pessimism             -0.382     2.076    
+    SLICE_X6Y199         FDPE (Remov_fdpe_C_PRE)     -0.071     2.005    core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg
+  -------------------------------------------------------------------
+                         required time                         -2.005    
+                         arrival time                           2.390    
+  -------------------------------------------------------------------
+                         slack                                  0.385    
+
+
+
+
+
+---------------------------------------------------------------------------------------------------
+Path Group:  **async_default**
+From Clock:  phy_rx_clk
+  To Clock:  phy_rx_clk
+
+Setup :            0  Failing Endpoints,  Worst Slack        6.626ns,  Total Violation        0.000ns
+Hold  :            0  Failing Endpoints,  Worst Slack        0.515ns,  Total Violation        0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             6.626ns  (required time - arrival time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]/C
+                            (rising edge-triggered cell FDPE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg/PRE
+                            (recovery check against rising-edge clock phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             **async_default**
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Requirement:            8.000ns  (phy_rx_clk rise@8.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        1.021ns  (logic 0.379ns (37.127%)  route 0.642ns (62.873%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.732ns = ( 10.732 - 8.000 ) 
+    Source Clock Delay      (SCD):    2.899ns
+    Clock Pessimism Removal (CPR):    0.141ns
+  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.449     1.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.384     2.239 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.660     2.899    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/output_clk
+    SLICE_X4Y216         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y216         FDPE (Prop_fdpe_C_Q)         0.379     3.278 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]/Q
+                         net (fo=44, routed)          0.642     3.920    core_inst/eth_mac_inst/rx_fifo/fifo_inst/SR[0]
+    SLICE_X6Y217         FDPE                                         f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      8.000     8.000 r  
+    B17                                               0.000     8.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     8.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     9.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     9.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362    10.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.615    10.732    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y217         FDPE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg/C
+                         clock pessimism              0.141    10.873    
+                         clock uncertainty           -0.035    10.838    
+    SLICE_X6Y217         FDPE (Recov_fdpe_C_PRE)     -0.292    10.546    core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg
+  -------------------------------------------------------------------
+                         required time                         10.546    
+                         arrival time                          -3.920    
+  -------------------------------------------------------------------
+                         slack                                  6.626    
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) :             0.515ns  (arrival time - required time)
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]/C
+                            (rising edge-triggered cell FDPE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg/PRE
+                            (removal check against rising-edge clock phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             **async_default**
+  Path Type:              Removal (Min at Fast Process Corner)
+  Requirement:            0.000ns  (phy_rx_clk rise@0.000ns - phy_rx_clk rise@0.000ns)
+  Data Path Delay:        0.457ns  (logic 0.141ns (30.866%)  route 0.316ns (69.134%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.288ns
+    Source Clock Delay      (SCD):    0.799ns
+    Clock Pessimism Removal (CPR):    0.476ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.258     0.799    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/output_clk
+    SLICE_X4Y216         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y216         FDPE (Prop_fdpe_C_Q)         0.141     0.940 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]/Q
+                         net (fo=44, routed)          0.316     1.256    core_inst/eth_mac_inst/rx_fifo/fifo_inst/SR[0]
+    SLICE_X6Y217         FDPE                                         f  core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.292     1.288    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y217         FDPE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg/C
+                         clock pessimism             -0.476     0.812    
+    SLICE_X6Y217         FDPE (Remov_fdpe_C_PRE)     -0.071     0.741    core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg
+  -------------------------------------------------------------------
+                         required time                         -0.741    
+                         arrival time                           1.256    
+  -------------------------------------------------------------------
+                         slack                                  0.515    
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  clk_mmcm_out
+  To Clock:  
+
+Max Delay             1 Endpoint
+Min Delay             1 Endpoint
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_reset_n
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        8.783ns  (logic 3.790ns (43.157%)  route 4.992ns (56.843%))
+  Logic Levels:           2  (LUT1=1 OBUF=1)
+  Output Delay:           0.000ns
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 f  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         3.450     8.952    sync_reset_inst/Q[0]
+    SLICE_X0Y231         LUT1 (Prop_lut1_I0_O)        0.105     9.057 r  sync_reset_inst/phy_reset_n_OBUF_inst_i_1/O
+                         net (fo=1, routed)           1.542    10.599    phy_reset_n_OBUF
+    D16                  OBUF (Prop_obuf_I_O)         3.252    13.852 r  phy_reset_n_OBUF_inst/O
+                         net (fo=0)                   0.000    13.852    phy_reset_n
+    D16                                                               r  phy_reset_n (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_reset_n
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        3.727ns  (logic 1.417ns (38.015%)  route 2.310ns (61.985%))
+  Logic Levels:           2  (LUT1=1 OBUF=1)
+  Output Delay:           0.000ns
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.621     2.028    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.164     2.192 f  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         1.894     4.087    sync_reset_inst/Q[0]
+    SLICE_X0Y231         LUT1 (Prop_lut1_I0_O)        0.045     4.132 r  sync_reset_inst/phy_reset_n_OBUF_inst_i_1/O
+                         net (fo=1, routed)           0.416     4.548    phy_reset_n_OBUF
+    D16                  OBUF (Prop_obuf_I_O)         1.208     5.756 r  phy_reset_n_OBUF_inst/O
+                         net (fo=0)                   0.000     5.756    phy_reset_n
+    D16                                                               r  phy_reset_n (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  clk_mmcm_out
+  To Clock:  clk90_mmcm_out
+
+Max Delay             0 Endpoints
+Min Delay             2 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_1_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/D1
+                            (rising edge-triggered cell ODDR clocked by clk90_mmcm_out  {rise@2.000ns fall@6.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.367ns  (logic 0.141ns (38.439%)  route 0.226ns (61.561%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.395ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.537ns = ( 4.537 - 2.000 ) 
+    Source Clock Delay      (SCD):    2.143ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.184ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.120ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.735     2.143    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_int
+    SLICE_X0Y218         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_1_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X0Y218         FDRE (Prop_fdre_C_Q)         0.141     2.284 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_1_reg/Q
+                         net (fo=3, routed)           0.226     2.510    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/rgmii_tx_clk_1
+    OLOGIC_X0Y219        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/D1
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk90_mmcm_out rise edge)
+                                                      2.000     2.000 r  
+    R4                                                0.000     2.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     2.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     2.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     2.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
+                                                      0.054     2.925 r  clk_mmcm_inst/CLKOUT1
+                         net (fo=1, routed)           0.579     3.503    clk90_mmcm_out
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     3.532 r  clk90_bufg_inst/O
+                         net (fo=1, routed)           1.005     4.537    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/clk90_int
+    OLOGIC_X0Y219        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_2_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/D2
+                            (rising edge-triggered cell ODDR clocked by clk90_mmcm_out  {rise@2.000ns fall@6.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.390ns  (logic 0.141ns (36.143%)  route 0.249ns (63.857%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.395ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.537ns = ( 4.537 - 2.000 ) 
+    Source Clock Delay      (SCD):    2.143ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.184ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.120ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.735     2.143    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_int
+    SLICE_X1Y218         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_2_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X1Y218         FDRE (Prop_fdre_C_Q)         0.141     2.284 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_2_reg/Q
+                         net (fo=3, routed)           0.249     2.533    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst_0
+    OLOGIC_X0Y219        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/D2
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk90_mmcm_out rise edge)
+                                                      2.000     2.000 r  
+    R4                                                0.000     2.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     2.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     2.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     2.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
+                                                      0.054     2.925 r  clk_mmcm_inst/CLKOUT1
+                         net (fo=1, routed)           0.579     3.503    clk90_mmcm_out
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029     3.532 r  clk90_bufg_inst/O
+                         net (fo=1, routed)           1.005     4.537    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/clk90_int
+    OLOGIC_X0Y219        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/C
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  
+  To Clock:  clk_mmcm_out
+
+Max Delay             4 Endpoints
+Min Delay             4 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 clk_mmcm_inst/LOCKED
+                            (internal pin)
+  Destination:            sync_reset_inst/sync_reg_reg[0]/PRE
+                            (recovery check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        6.646ns  (logic 0.105ns (1.580%)  route 6.541ns (98.420%))
+  Logic Levels:           1  (LUT1=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV                   0.000     0.000 r  clk_mmcm_inst/LOCKED
+                         net (fo=1, routed)           6.139     6.139    sync_reset_inst/mmcm_locked
+    SLICE_X12Y165        LUT1 (Prop_lut1_I0_O)        0.105     6.244 f  sync_reset_inst/sync_reg[3]_i_1/O
+                         net (fo=4, routed)           0.402     6.646    sync_reset_inst/rst0
+    SLICE_X12Y165        FDPE                                         f  sync_reset_inst/sync_reg_reg[0]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.371     4.782    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[0]/C
+
+Slack:                    inf
+  Source:                 clk_mmcm_inst/LOCKED
+                            (internal pin)
+  Destination:            sync_reset_inst/sync_reg_reg[1]/PRE
+                            (recovery check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        6.646ns  (logic 0.105ns (1.580%)  route 6.541ns (98.420%))
+  Logic Levels:           1  (LUT1=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV                   0.000     0.000 r  clk_mmcm_inst/LOCKED
+                         net (fo=1, routed)           6.139     6.139    sync_reset_inst/mmcm_locked
+    SLICE_X12Y165        LUT1 (Prop_lut1_I0_O)        0.105     6.244 f  sync_reset_inst/sync_reg[3]_i_1/O
+                         net (fo=4, routed)           0.402     6.646    sync_reset_inst/rst0
+    SLICE_X12Y165        FDPE                                         f  sync_reset_inst/sync_reg_reg[1]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.371     4.782    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[1]/C
+
+Slack:                    inf
+  Source:                 clk_mmcm_inst/LOCKED
+                            (internal pin)
+  Destination:            sync_reset_inst/sync_reg_reg[2]/PRE
+                            (recovery check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        6.646ns  (logic 0.105ns (1.580%)  route 6.541ns (98.420%))
+  Logic Levels:           1  (LUT1=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV                   0.000     0.000 r  clk_mmcm_inst/LOCKED
+                         net (fo=1, routed)           6.139     6.139    sync_reset_inst/mmcm_locked
+    SLICE_X12Y165        LUT1 (Prop_lut1_I0_O)        0.105     6.244 f  sync_reset_inst/sync_reg[3]_i_1/O
+                         net (fo=4, routed)           0.402     6.646    sync_reset_inst/rst0
+    SLICE_X12Y165        FDPE                                         f  sync_reset_inst/sync_reg_reg[2]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.371     4.782    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[2]/C
+
+Slack:                    inf
+  Source:                 clk_mmcm_inst/LOCKED
+                            (internal pin)
+  Destination:            sync_reset_inst/sync_reg_reg[3]/PRE
+                            (recovery check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        6.646ns  (logic 0.105ns (1.580%)  route 6.541ns (98.420%))
+  Logic Levels:           1  (LUT1=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV                   0.000     0.000 r  clk_mmcm_inst/LOCKED
+                         net (fo=1, routed)           6.139     6.139    sync_reset_inst/mmcm_locked
+    SLICE_X12Y165        LUT1 (Prop_lut1_I0_O)        0.105     6.244 f  sync_reset_inst/sync_reg[3]_i_1/O
+                         net (fo=4, routed)           0.402     6.646    sync_reset_inst/rst0
+    SLICE_X12Y165        FDPE                                         f  sync_reset_inst/sync_reg_reg[3]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.371     4.782    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 clk_mmcm_inst/LOCKED
+                            (internal pin)
+  Destination:            sync_reset_inst/sync_reg_reg[0]/PRE
+                            (removal check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        3.624ns  (logic 0.045ns (1.242%)  route 3.579ns (98.758%))
+  Logic Levels:           1  (LUT1=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV                   0.000     0.000 r  clk_mmcm_inst/LOCKED
+                         net (fo=1, routed)           3.409     3.409    sync_reset_inst/mmcm_locked
+    SLICE_X12Y165        LUT1 (Prop_lut1_I0_O)        0.045     3.454 f  sync_reset_inst/sync_reg[3]_i_1/O
+                         net (fo=4, routed)           0.170     3.624    sync_reset_inst/rst0
+    SLICE_X12Y165        FDPE                                         f  sync_reset_inst/sync_reg_reg[0]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.891     2.423    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[0]/C
+
+Slack:                    inf
+  Source:                 clk_mmcm_inst/LOCKED
+                            (internal pin)
+  Destination:            sync_reset_inst/sync_reg_reg[1]/PRE
+                            (removal check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        3.624ns  (logic 0.045ns (1.242%)  route 3.579ns (98.758%))
+  Logic Levels:           1  (LUT1=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV                   0.000     0.000 r  clk_mmcm_inst/LOCKED
+                         net (fo=1, routed)           3.409     3.409    sync_reset_inst/mmcm_locked
+    SLICE_X12Y165        LUT1 (Prop_lut1_I0_O)        0.045     3.454 f  sync_reset_inst/sync_reg[3]_i_1/O
+                         net (fo=4, routed)           0.170     3.624    sync_reset_inst/rst0
+    SLICE_X12Y165        FDPE                                         f  sync_reset_inst/sync_reg_reg[1]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.891     2.423    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[1]/C
+
+Slack:                    inf
+  Source:                 clk_mmcm_inst/LOCKED
+                            (internal pin)
+  Destination:            sync_reset_inst/sync_reg_reg[2]/PRE
+                            (removal check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        3.624ns  (logic 0.045ns (1.242%)  route 3.579ns (98.758%))
+  Logic Levels:           1  (LUT1=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV                   0.000     0.000 r  clk_mmcm_inst/LOCKED
+                         net (fo=1, routed)           3.409     3.409    sync_reset_inst/mmcm_locked
+    SLICE_X12Y165        LUT1 (Prop_lut1_I0_O)        0.045     3.454 f  sync_reset_inst/sync_reg[3]_i_1/O
+                         net (fo=4, routed)           0.170     3.624    sync_reset_inst/rst0
+    SLICE_X12Y165        FDPE                                         f  sync_reset_inst/sync_reg_reg[2]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.891     2.423    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[2]/C
+
+Slack:                    inf
+  Source:                 clk_mmcm_inst/LOCKED
+                            (internal pin)
+  Destination:            sync_reset_inst/sync_reg_reg[3]/PRE
+                            (removal check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Removal (Min at Fast Process Corner)
+  Data Path Delay:        3.624ns  (logic 0.045ns (1.242%)  route 3.579ns (98.758%))
+  Logic Levels:           1  (LUT1=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV                   0.000     0.000 r  clk_mmcm_inst/LOCKED
+                         net (fo=1, routed)           3.409     3.409    sync_reset_inst/mmcm_locked
+    SLICE_X12Y165        LUT1 (Prop_lut1_I0_O)        0.045     3.454 f  sync_reset_inst/sync_reg[3]_i_1/O
+                         net (fo=4, routed)           0.170     3.624    sync_reset_inst/rst0
+    SLICE_X12Y165        FDPE                                         f  sync_reset_inst/sync_reg_reg[3]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.891     2.423    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  clk_mmcm_out
+  To Clock:  clk_mmcm_out
+
+Max Delay             4 Endpoints
+Min Delay            35 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[3]/PRE
+                            (recovery check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        6.178ns  (logic 0.433ns (7.008%)  route 5.745ns (92.992%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.047ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    5.022ns
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 f  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.745    11.247    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/Q[0]
+    SLICE_X5Y206         FDPE                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[3]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.611     5.022    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_int
+    SLICE_X5Y206         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[3]/C
+
+Slack:                    inf
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/PRE
+                            (recovery check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        2.952ns  (logic 0.433ns (14.667%)  route 2.519ns (85.333%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 f  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         2.519     8.021    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/Q[0]
+    SLICE_X4Y199         FDPE                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.444     4.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_int
+    SLICE_X4Y199         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[0]/C
+
+Slack:                    inf
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[1]/PRE
+                            (recovery check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        2.952ns  (logic 0.433ns (14.667%)  route 2.519ns (85.333%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 f  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         2.519     8.021    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/Q[0]
+    SLICE_X4Y199         FDPE                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[1]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.444     4.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_int
+    SLICE_X4Y199         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[1]/C
+
+Slack:                    inf
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[2]/PRE
+                            (recovery check against rising-edge clock clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        2.952ns  (logic 0.433ns (14.667%)  route 2.519ns (85.333%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.214ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    4.855ns
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 f  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         2.519     8.021    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/Q[0]
+    SLICE_X4Y199         FDPE                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[2]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.804     0.804 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.004     1.808    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.074     1.882 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.452     3.334    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.077     3.411 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.444     4.855    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_int
+    SLICE_X4Y199         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[2]/C
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[5]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.273ns  (logic 0.128ns (46.905%)  route 0.145ns (53.095%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.397ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.455ns
+    Source Clock Delay      (SCD):    2.057ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.650     2.057    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X3Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y187         FDRE (Prop_fdre_C_Q)         0.128     2.185 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/Q
+                         net (fo=1, routed)           0.145     2.330    core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg[5]
+    SLICE_X2Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[5]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.923     2.455    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X2Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[5]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.273ns  (logic 0.128ns (46.905%)  route 0.145ns (53.095%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.398ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.457ns
+    Source Clock Delay      (SCD):    2.058ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.651     2.058    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X3Y188         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y188         FDRE (Prop_fdre_C_Q)         0.128     2.186 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/Q
+                         net (fo=1, routed)           0.145     2.331    core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg[11]
+    SLICE_X2Y188         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.925     2.457    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X2Y188         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync2_reg_reg/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.275ns  (logic 0.164ns (59.730%)  route 0.111ns (40.270%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.398ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.459ns
+    Source Clock Delay      (SCD):    2.060ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.653     2.060    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X6Y199         FDPE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y199         FDPE (Prop_fdpe_C_Q)         0.164     2.224 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg_reg/Q
+                         net (fo=1, routed)           0.111     2.335    core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync1_reg
+    SLICE_X6Y198         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync2_reg_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.927     2.459    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X6Y198         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync2_reg_reg/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[4]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[4]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.284ns  (logic 0.128ns (45.133%)  route 0.156ns (54.867%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.397ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.453ns
+    Source Clock Delay      (SCD):    2.055ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.648     2.055    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X4Y184         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[4]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y184         FDRE (Prop_fdre_C_Q)         0.128     2.183 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[4]/Q
+                         net (fo=1, routed)           0.156     2.339    core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg[4]
+    SLICE_X7Y185         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[4]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.920     2.453    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X7Y185         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[4]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[6]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[6]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.293ns  (logic 0.128ns (43.653%)  route 0.165ns (56.347%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.396ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.452ns
+    Source Clock Delay      (SCD):    2.055ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.648     2.055    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X4Y184         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[6]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y184         FDRE (Prop_fdre_C_Q)         0.128     2.183 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[6]/Q
+                         net (fo=1, routed)           0.165     2.349    core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg[6]
+    SLICE_X5Y184         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[6]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.920     2.452    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X5Y184         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[6]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[1]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[1]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.297ns  (logic 0.128ns (43.106%)  route 0.169ns (56.894%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.396ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.455ns
+    Source Clock Delay      (SCD):    2.058ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.651     2.058    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X3Y188         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[1]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y188         FDRE (Prop_fdre_C_Q)         0.128     2.186 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[1]/Q
+                         net (fo=1, routed)           0.169     2.355    core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg[1]
+    SLICE_X2Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[1]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.923     2.455    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X2Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[1]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[8]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.306ns  (logic 0.128ns (41.776%)  route 0.178ns (58.224%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.395ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.451ns
+    Source Clock Delay      (SCD):    2.055ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.648     2.055    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X4Y184         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[8]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y184         FDRE (Prop_fdre_C_Q)         0.128     2.183 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[8]/Q
+                         net (fo=1, routed)           0.178     2.362    core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg[8]
+    SLICE_X4Y183         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.919     2.451    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X4Y183         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[8]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.306ns  (logic 0.141ns (46.040%)  route 0.165ns (53.960%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.397ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.455ns
+    Source Clock Delay      (SCD):    2.057ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.650     2.057    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X3Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y187         FDRE (Prop_fdre_C_Q)         0.141     2.198 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/Q
+                         net (fo=1, routed)           0.165     2.364    core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_sync_commit_reg[2]
+    SLICE_X2Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.923     2.455    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X2Y187         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[0]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.309ns  (logic 0.141ns (45.589%)  route 0.168ns (54.411%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.396ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.451ns
+    Source Clock Delay      (SCD):    2.054ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.647     2.054    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X5Y183         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y183         FDRE (Prop_fdre_C_Q)         0.141     2.195 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[0]/Q
+                         net (fo=1, routed)           0.168     2.364    core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg[0]
+    SLICE_X4Y183         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.919     2.451    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X4Y183         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[0]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.310ns  (logic 0.141ns (45.489%)  route 0.169ns (54.511%))
+  Logic Levels:           0  
+  Clock Path Skew:        0.395ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.451ns
+    Source Clock Delay      (SCD):    2.055ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.064ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.000ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.648     2.055    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X4Y184         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X4Y184         FDRE (Prop_fdre_C_Q)         0.141     2.196 r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg_reg[7]/Q
+                         net (fo=1, routed)           0.169     2.365    core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_reg[7]
+    SLICE_X4Y183         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.919     2.451    core_inst/eth_mac_inst/tx_fifo/fifo_inst/clk_int
+    SLICE_X4Y183         FDRE                                         r  core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/C
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  phy_rx_clk
+  To Clock:  clk_mmcm_out
+
+Max Delay             0 Endpoints
+Min Delay            16 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg/C
+                            (rising edge-triggered cell FDPE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync2_reg_reg/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.268ns  (logic 0.164ns (61.293%)  route 0.104ns (38.707%))
+  Logic Levels:           0  
+  Clock Path Skew:        1.744ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.542ns
+    Source Clock Delay      (SCD):    0.798ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.257     0.798    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y217         FDPE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y217         FDPE (Prop_fdpe_C_Q)         0.164     0.962 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg_reg/Q
+                         net (fo=1, routed)           0.104     1.066    core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync1_reg
+    SLICE_X7Y217         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync2_reg_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.010     2.542    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X7Y217         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync2_reg_reg/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[5]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.273ns  (logic 0.128ns (46.957%)  route 0.145ns (53.043%))
+  Logic Levels:           0  
+  Clock Path Skew:        1.749ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.551ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.128     0.930 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[5]/Q
+                         net (fo=1, routed)           0.145     1.075    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[5]
+    SLICE_X3Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[5]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.019     2.551    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X3Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[5]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[0]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.282ns  (logic 0.141ns (50.024%)  route 0.141ns (49.976%))
+  Logic Levels:           0  
+  Clock Path Skew:        1.748ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.548ns
+    Source Clock Delay      (SCD):    0.800ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.259     0.800    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y214         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[0]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y214         FDRE (Prop_fdre_C_Q)         0.141     0.941 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[0]/Q
+                         net (fo=1, routed)           0.141     1.082    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[0]
+    SLICE_X3Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.016     2.548    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X3Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[0]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.284ns  (logic 0.141ns (49.716%)  route 0.143ns (50.284%))
+  Logic Levels:           0  
+  Clock Path Skew:        1.749ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.551ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.141     0.943 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[2]/Q
+                         net (fo=1, routed)           0.143     1.086    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[2]
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.019     2.551    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[2]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.296ns  (logic 0.128ns (43.174%)  route 0.168ns (56.826%))
+  Logic Levels:           0  
+  Clock Path Skew:        1.749ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.551ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.128     0.930 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[11]/Q
+                         net (fo=1, routed)           0.168     1.099    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[11]
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.019     2.551    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[11]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[3]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[3]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.299ns  (logic 0.128ns (42.825%)  route 0.171ns (57.175%))
+  Logic Levels:           0  
+  Clock Path Skew:        1.749ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.551ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.128     0.930 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[3]/Q
+                         net (fo=1, routed)           0.171     1.101    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[3]
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.019     2.551    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[3]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[10]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[10]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.311ns  (logic 0.141ns (45.394%)  route 0.170ns (54.606%))
+  Logic Levels:           0  
+  Clock Path Skew:        1.749ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.551ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[10]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.141     0.943 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[10]/Q
+                         net (fo=1, routed)           0.170     1.113    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[10]
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[10]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.019     2.551    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X2Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[10]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[8]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[8]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.316ns  (logic 0.141ns (44.641%)  route 0.175ns (55.359%))
+  Logic Levels:           0  
+  Clock Path Skew:        1.749ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.551ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[8]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.141     0.943 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[8]/Q
+                         net (fo=1, routed)           0.175     1.118    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[8]
+    SLICE_X3Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[8]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.019     2.551    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X3Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[8]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[9]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[9]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.330ns  (logic 0.128ns (38.782%)  route 0.202ns (61.218%))
+  Logic Levels:           0  
+  Clock Path Skew:        1.749ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.551ns
+    Source Clock Delay      (SCD):    0.802ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.261     0.802    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[9]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y210         FDRE (Prop_fdre_C_Q)         0.128     0.930 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[9]/Q
+                         net (fo=1, routed)           0.202     1.132    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[9]
+    SLICE_X3Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[9]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.019     2.551    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X3Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[9]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]/D
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.346ns  (logic 0.128ns (36.979%)  route 0.218ns (63.021%))
+  Logic Levels:           0  
+  Clock Path Skew:        1.748ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    2.548ns
+    Source Clock Delay      (SCD):    0.800ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.206     0.449    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.092     0.541 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.259     0.800    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y214         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y214         FDRE (Prop_fdre_C_Q)         0.128     0.928 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg_reg[7]/Q
+                         net (fo=1, routed)           0.218     1.146    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_sync_commit_reg[7]
+    SLICE_X3Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.391     0.391 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.480     0.871    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.054     0.925 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.579     1.503    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.532 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.016     2.548    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X3Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg[7]/C
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  clk_mmcm_out
+  To Clock:  phy_rx_clk
+
+Max Delay             4 Endpoints
+Min Delay            20 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]/PRE
+                            (recovery check against rising-edge clock phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        5.701ns  (logic 0.433ns (7.596%)  route 5.268ns (92.404%))
+  Logic Levels:           0  
+  Clock Path Skew:        -2.336ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.733ns
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 f  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.268    10.769    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/Q[0]
+    SLICE_X4Y216         FDPE                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     1.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     1.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362     2.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.616     2.733    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/output_clk
+    SLICE_X4Y216         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[0]/C
+
+Slack:                    inf
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[1]/PRE
+                            (recovery check against rising-edge clock phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        5.701ns  (logic 0.433ns (7.596%)  route 5.268ns (92.404%))
+  Logic Levels:           0  
+  Clock Path Skew:        -2.336ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.733ns
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 f  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.268    10.769    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/Q[0]
+    SLICE_X4Y216         FDPE                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[1]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     1.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     1.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362     2.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.616     2.733    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/output_clk
+    SLICE_X4Y216         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[1]/C
+
+Slack:                    inf
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[2]/PRE
+                            (recovery check against rising-edge clock phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        5.701ns  (logic 0.433ns (7.596%)  route 5.268ns (92.404%))
+  Logic Levels:           0  
+  Clock Path Skew:        -2.336ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.733ns
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 f  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.268    10.769    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/Q[0]
+    SLICE_X4Y216         FDPE                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[2]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     1.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     1.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362     2.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.616     2.733    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/output_clk
+    SLICE_X4Y216         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[2]/C
+
+Slack:                    inf
+  Source:                 sync_reset_inst/sync_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[3]/PRE
+                            (recovery check against rising-edge clock phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Recovery (Max at Slow Process Corner)
+  Data Path Delay:        5.701ns  (logic 0.433ns (7.596%)  route 5.268ns (92.404%))
+  Logic Levels:           0  
+  Clock Path Skew:        -2.336ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    2.733ns
+    Source Clock Delay      (SCD):    5.069ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     0.842 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     1.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     1.985 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     3.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     3.590 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.479     5.069    sync_reset_inst/clk_int
+    SLICE_X12Y165        FDPE                                         r  sync_reset_inst/sync_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X12Y165        FDPE (Prop_fdpe_C_Q)         0.433     5.502 f  sync_reset_inst/sync_reg_reg[3]/Q
+                         net (fo=311, routed)         5.268    10.769    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/Q[0]
+    SLICE_X4Y216         FDPE                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[3]/PRE
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     1.340 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.415     1.755    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.362     2.117 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.616     2.733    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/output_clk
+    SLICE_X4Y216         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg[3]/C
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[7]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.288ns  (logic 0.141ns (49.009%)  route 0.147ns (50.991%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.852ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    2.146ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.738     2.146    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X7Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[7]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y210         FDRE (Prop_fdre_C_Q)         0.141     2.287 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[7]/Q
+                         net (fo=1, routed)           0.147     2.434    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[7]
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[7]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[9]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.297ns  (logic 0.148ns (49.787%)  route 0.149ns (50.213%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.852ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    2.146ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.738     2.146    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X6Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[9]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y210         FDRE (Prop_fdre_C_Q)         0.148     2.294 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[9]/Q
+                         net (fo=1, routed)           0.149     2.443    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[9]
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[9]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[3]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[3]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.300ns  (logic 0.141ns (46.934%)  route 0.159ns (53.066%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.853ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    2.147ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.739     2.147    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X7Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y209         FDRE (Prop_fdre_C_Q)         0.141     2.288 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[3]/Q
+                         net (fo=1, routed)           0.159     2.447    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[3]
+    SLICE_X7Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[3]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X7Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[3]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[10]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[10]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.310ns  (logic 0.164ns (52.947%)  route 0.146ns (47.053%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.852ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    2.146ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.738     2.146    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X6Y210         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[10]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y210         FDRE (Prop_fdre_C_Q)         0.164     2.310 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[10]/Q
+                         net (fo=1, routed)           0.146     2.456    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[10]
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[10]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[10]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync3_reg_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_ack_sync1_reg_reg/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.310ns  (logic 0.128ns (41.311%)  route 0.182ns (58.689%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.858ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.288ns
+    Source Clock Delay      (SCD):    2.146ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.738     2.146    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X3Y215         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync3_reg_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X3Y215         FDRE (Prop_fdre_C_Q)         0.128     2.274 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync3_reg_reg/Q
+                         net (fo=2, routed)           0.182     2.456    core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync3_reg
+    SLICE_X3Y216         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_ack_sync1_reg_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.292     1.288    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X3Y216         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_ack_sync1_reg_reg/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[5]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[5]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.311ns  (logic 0.141ns (45.403%)  route 0.170ns (54.597%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.853ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    2.147ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.739     2.147    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X7Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[5]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y209         FDRE (Prop_fdre_C_Q)         0.141     2.288 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[5]/Q
+                         net (fo=1, routed)           0.170     2.457    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[5]
+    SLICE_X6Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[5]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[5]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[3]/C
+                            (rising edge-triggered cell FDPE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_rst_sync2_reg_reg/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.314ns  (logic 0.128ns (40.818%)  route 0.186ns (59.182%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.853ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.295ns
+    Source Clock Delay      (SCD):    2.148ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.740     2.148    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_int
+    SLICE_X5Y206         FDPE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[3]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X5Y206         FDPE (Prop_fdpe_C_Q)         0.128     2.276 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg[3]/Q
+                         net (fo=3, routed)           0.186     2.461    core_inst/eth_mac_inst/rx_fifo/fifo_inst/D[0]
+    SLICE_X5Y207         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_rst_sync2_reg_reg/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.299     1.295    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X5Y207         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_rst_sync2_reg_reg/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[12]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[12]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.325ns  (logic 0.164ns (50.396%)  route 0.161ns (49.604%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.853ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.294ns
+    Source Clock Delay      (SCD):    2.147ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.739     2.147    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X6Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[12]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X6Y209         FDRE (Prop_fdre_C_Q)         0.164     2.311 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[12]/Q
+                         net (fo=1, routed)           0.161     2.472    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[12]
+    SLICE_X6Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[12]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.298     1.294    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y211         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[12]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[6]/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[6]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.330ns  (logic 0.128ns (38.816%)  route 0.202ns (61.184%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.855ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.292ns
+    Source Clock Delay      (SCD):    2.147ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.739     2.147    core_inst/eth_mac_inst/rx_fifo/fifo_inst/clk_int
+    SLICE_X7Y209         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[6]/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X7Y209         FDRE (Prop_fdre_C_Q)         0.128     2.275 r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_reg[6]/Q
+                         net (fo=1, routed)           0.202     2.477    core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_reg_0[6]
+    SLICE_X6Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[6]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.296     1.292    core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_clk
+    SLICE_X6Y212         FDRE                                         r  core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg[6]/C
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/mii_select_reg_reg/C
+                            (rising edge-triggered cell FDRE clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[0]/D
+                            (rising edge-triggered cell FDRE clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.360ns  (logic 0.164ns (45.598%)  route 0.196ns (54.402%))
+  Logic Levels:           0  
+  Clock Path Skew:        -0.859ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.286ns
+    Source Clock Delay      (SCD):    2.145ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+  Clock Uncertainty:      0.154ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.071ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+  Timing Exception:       False Path
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.737     2.145    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/clk_int
+    SLICE_X2Y216         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/mii_select_reg_reg/C
+  -------------------------------------------------------------------    -------------------
+    SLICE_X2Y216         FDRE (Prop_fdre_C_Q)         0.164     2.309 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/mii_select_reg_reg/Q
+                         net (fo=3, routed)           0.196     2.504    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/mii_select_reg_reg_n_0
+    SLICE_X2Y218         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[0]/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk rise edge)
+                                                      0.000     0.000 r  
+    B17                                               0.000     0.000 r  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     0.431 r  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.311     0.742    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFR_X0Y17           BUFR (Prop_bufr_I_O)         0.254     0.996 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufr/O
+                         net (fo=195, routed)         0.290     1.286    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/output_clk
+    SLICE_X2Y218         FDRE                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg[0]/C
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  clk90_mmcm_out
+  To Clock:  
+
+Max Delay             1 Endpoint
+Min Delay             1 Endpoint
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/C
+                            (falling edge-triggered cell ODDR clocked by clk90_mmcm_out  {rise@2.000ns fall@6.000ns period=8.000ns})
+  Destination:            phy_tx_clk
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.156ns  (logic 3.155ns (99.968%)  route 0.001ns (0.032%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk90_mmcm_out fall edge)
+                                                      6.000     6.000 f  
+    R4                                                0.000     6.000 f  clk_p (IN)
+                         net (fo=0)                   0.000     6.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     6.842 f  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     7.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
+                                                      0.078     7.985 f  clk_mmcm_inst/CLKOUT1
+                         net (fo=1, routed)           1.524     9.509    clk90_mmcm_out
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.081     9.590 f  clk90_bufg_inst/O
+                         net (fo=1, routed)           1.734    11.324    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/clk90_int
+    OLOGIC_X0Y219        ODDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y219        ODDR (Prop_oddr_C_Q)         0.418    11.742 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/Q
+                         net (fo=1, routed)           0.001    11.743    phy_tx_clk_OBUF
+    E18                  OBUF (Prop_obuf_I_O)         2.737    14.480 r  phy_tx_clk_OBUF_inst/O
+                         net (fo=0)                   0.000    14.480    phy_tx_clk
+    E18                                                               r  phy_tx_clk (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/C
+                            (rising edge-triggered cell ODDR clocked by clk90_mmcm_out  {rise@2.000ns fall@6.000ns period=8.000ns})
+  Destination:            phy_tx_clk
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.290ns  (logic 1.289ns (99.922%)  route 0.001ns (0.078%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk90_mmcm_out rise edge)
+                                                      2.000     2.000 r  
+    R4                                                0.000     2.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     2.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     2.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     2.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
+                                                      0.051     2.851 r  clk_mmcm_inst/CLKOUT1
+                         net (fo=1, routed)           0.531     3.382    clk90_mmcm_out
+    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026     3.408 r  clk90_bufg_inst/O
+                         net (fo=1, routed)           0.727     4.135    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/clk90_int
+    OLOGIC_X0Y219        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y219        ODDR (Prop_oddr_C_Q)         0.177     4.312 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/oddr[0].oddr_inst/Q
+                         net (fo=1, routed)           0.001     4.313    phy_tx_clk_OBUF
+    E18                  OBUF (Prop_obuf_I_O)         1.112     5.425 r  phy_tx_clk_OBUF_inst/O
+                         net (fo=0)                   0.000     5.425    phy_tx_clk
+    E18                                                               r  phy_tx_clk (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  clk_200_mmcm_out
+  To Clock:  
+
+Max Delay             1 Endpoint
+Min Delay             1 Endpoint
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 clk_mmcm_inst/CLKOUT2
+                            (clock source 'clk_200_mmcm_out'  {rise@0.000ns fall@2.500ns period=5.000ns})
+  Destination:            idelayctrl_inst/REFCLK
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.077ns  (logic 0.081ns (2.633%)  route 2.996ns (97.367%))
+  Logic Levels:           1  (BUFG=1)
+  Clock Uncertainty:      0.145ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.098ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_200_mmcm_out fall edge)
+                                                      2.500     2.500 f  
+    R4                                                0.000     2.500 f  clk_p (IN)
+                         net (fo=0)                   0.000     2.500    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     3.342 f  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     4.407    clk_ibufg
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
+                                                      0.078     4.485 f  clk_mmcm_inst/CLKOUT2
+                         net (fo=1, routed)           1.524     6.009    clk_200_mmcm_out
+    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.081     6.090 f  clk_200_bufg_inst/O
+                         net (fo=1, routed)           1.472     7.562    clk_200_int
+    IDELAYCTRL_X0Y4      IDELAYCTRL                                   f  idelayctrl_inst/REFCLK
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 clk_mmcm_inst/CLKOUT2
+                            (clock source 'clk_200_mmcm_out'  {rise@0.000ns fall@2.500ns period=5.000ns})
+  Destination:            idelayctrl_inst/REFCLK
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.198ns  (logic 0.026ns (2.170%)  route 1.172ns (97.830%))
+  Logic Levels:           1  (BUFG=1)
+  Clock Uncertainty:      0.145ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.098ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_200_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT2
+                         net (fo=1, routed)           0.531     1.382    clk_200_mmcm_out
+    BUFGCTRL_X0Y2        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_200_bufg_inst/O
+                         net (fo=1, routed)           0.641     2.049    clk_200_int
+    IDELAYCTRL_X0Y4      IDELAYCTRL                                   r  idelayctrl_inst/REFCLK
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  clk_mmcm_out
+  To Clock:  
+
+Max Delay             5 Endpoints
+Min Delay             5 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[4].oddr_inst/C
+                            (falling edge-triggered cell ODDR clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_txd[3]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.189ns  (logic 3.188ns (99.969%)  route 0.001ns (0.031%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out fall edge)
+                                                      4.000     4.000 f  
+    R4                                                0.000     4.000 f  clk_p (IN)
+                         net (fo=0)                   0.000     4.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     4.842 f  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     5.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     5.985 f  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     7.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     7.590 f  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.740     9.330    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/clk_int
+    OLOGIC_X0Y216        ODDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[4].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y216        ODDR (Prop_oddr_C_Q)         0.418     9.748 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[4].oddr_inst/Q
+                         net (fo=1, routed)           0.001     9.749    phy_txd_OBUF[3]
+    A18                  OBUF (Prop_obuf_I_O)         2.770    12.518 r  phy_txd_OBUF[3]_inst/O
+                         net (fo=0)                   0.000    12.518    phy_txd[3]
+    A18                                                               r  phy_txd[3] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[3].oddr_inst/C
+                            (falling edge-triggered cell ODDR clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_txd[2]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.183ns  (logic 3.182ns (99.969%)  route 0.001ns (0.031%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out fall edge)
+                                                      4.000     4.000 f  
+    R4                                                0.000     4.000 f  clk_p (IN)
+                         net (fo=0)                   0.000     4.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     4.842 f  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     5.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     5.985 f  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     7.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     7.590 f  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.740     9.330    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/clk_int
+    OLOGIC_X0Y215        ODDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[3].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y215        ODDR (Prop_oddr_C_Q)         0.418     9.748 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[3].oddr_inst/Q
+                         net (fo=1, routed)           0.001     9.749    phy_txd_OBUF[2]
+    A19                  OBUF (Prop_obuf_I_O)         2.764    12.512 r  phy_txd_OBUF[2]_inst/O
+                         net (fo=0)                   0.000    12.512    phy_txd[2]
+    A19                                                               r  phy_txd[2] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[1].oddr_inst/C
+                            (falling edge-triggered cell ODDR clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_txd[0]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.172ns  (logic 3.171ns (99.968%)  route 0.001ns (0.032%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out fall edge)
+                                                      4.000     4.000 f  
+    R4                                                0.000     4.000 f  clk_p (IN)
+                         net (fo=0)                   0.000     4.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     4.842 f  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     5.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     5.985 f  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     7.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     7.590 f  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.743     9.333    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/clk_int
+    OLOGIC_X0Y211        ODDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[1].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y211        ODDR (Prop_oddr_C_Q)         0.418     9.751 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[1].oddr_inst/Q
+                         net (fo=1, routed)           0.001     9.752    phy_txd_OBUF[0]
+    C20                  OBUF (Prop_obuf_I_O)         2.753    12.505 r  phy_txd_OBUF[0]_inst/O
+                         net (fo=0)                   0.000    12.505    phy_txd[0]
+    C20                                                               r  phy_txd[0] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[2].oddr_inst/C
+                            (falling edge-triggered cell ODDR clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_txd[1]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.170ns  (logic 3.169ns (99.968%)  route 0.001ns (0.032%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out fall edge)
+                                                      4.000     4.000 f  
+    R4                                                0.000     4.000 f  clk_p (IN)
+                         net (fo=0)                   0.000     4.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     4.842 f  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     5.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     5.985 f  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     7.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     7.590 f  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.743     9.333    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/clk_int
+    OLOGIC_X0Y212        ODDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[2].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y212        ODDR (Prop_oddr_C_Q)         0.418     9.751 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[2].oddr_inst/Q
+                         net (fo=1, routed)           0.001     9.752    phy_txd_OBUF[1]
+    D20                  OBUF (Prop_obuf_I_O)         2.751    12.503 r  phy_txd_OBUF[1]_inst/O
+                         net (fo=0)                   0.000    12.503    phy_txd[1]
+    D20                                                               r  phy_txd[1] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[0].oddr_inst/C
+                            (falling edge-triggered cell ODDR clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_tx_ctl
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        3.159ns  (logic 3.158ns (99.968%)  route 0.001ns (0.032%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out fall edge)
+                                                      4.000     4.000 f  
+    R4                                                0.000     4.000 f  clk_p (IN)
+                         net (fo=0)                   0.000     4.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     4.842 f  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     5.907    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.078     5.985 f  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           1.524     7.509    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.081     7.590 f  clk_bufg_inst/O
+                         net (fo=2759, routed)        1.734     9.324    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/clk_int
+    OLOGIC_X0Y220        ODDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[0].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y220        ODDR (Prop_oddr_C_Q)         0.418     9.742 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[0].oddr_inst/Q
+                         net (fo=1, routed)           0.001     9.743    phy_tx_ctl_OBUF
+    F18                  OBUF (Prop_obuf_I_O)         2.740    12.483 r  phy_tx_ctl_OBUF_inst/O
+                         net (fo=0)                   0.000    12.483    phy_tx_ctl
+    F18                                                               r  phy_tx_ctl (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[0].oddr_inst/C
+                            (rising edge-triggered cell ODDR clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_tx_ctl
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.293ns  (logic 1.292ns (99.923%)  route 0.001ns (0.077%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.727     2.135    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/clk_int
+    OLOGIC_X0Y220        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[0].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y220        ODDR (Prop_oddr_C_Q)         0.177     2.312 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[0].oddr_inst/Q
+                         net (fo=1, routed)           0.001     2.313    phy_tx_ctl_OBUF
+    F18                  OBUF (Prop_obuf_I_O)         1.115     3.428 r  phy_tx_ctl_OBUF_inst/O
+                         net (fo=0)                   0.000     3.428    phy_tx_ctl
+    F18                                                               r  phy_tx_ctl (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[2].oddr_inst/C
+                            (rising edge-triggered cell ODDR clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_txd[1]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.303ns  (logic 1.302ns (99.923%)  route 0.001ns (0.077%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.732     2.140    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/clk_int
+    OLOGIC_X0Y212        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[2].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y212        ODDR (Prop_oddr_C_Q)         0.177     2.317 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[2].oddr_inst/Q
+                         net (fo=1, routed)           0.001     2.318    phy_txd_OBUF[1]
+    D20                  OBUF (Prop_obuf_I_O)         1.125     3.443 r  phy_txd_OBUF[1]_inst/O
+                         net (fo=0)                   0.000     3.443    phy_txd[1]
+    D20                                                               r  phy_txd[1] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[1].oddr_inst/C
+                            (rising edge-triggered cell ODDR clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_txd[0]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.306ns  (logic 1.305ns (99.923%)  route 0.001ns (0.077%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.732     2.140    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/clk_int
+    OLOGIC_X0Y211        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[1].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y211        ODDR (Prop_oddr_C_Q)         0.177     2.317 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[1].oddr_inst/Q
+                         net (fo=1, routed)           0.001     2.318    phy_txd_OBUF[0]
+    C20                  OBUF (Prop_obuf_I_O)         1.128     3.445 r  phy_txd_OBUF[0]_inst/O
+                         net (fo=0)                   0.000     3.445    phy_txd[0]
+    C20                                                               r  phy_txd[0] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[3].oddr_inst/C
+                            (rising edge-triggered cell ODDR clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_txd[2]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.316ns  (logic 1.315ns (99.924%)  route 0.001ns (0.076%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.730     2.138    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/clk_int
+    OLOGIC_X0Y215        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[3].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y215        ODDR (Prop_oddr_C_Q)         0.177     2.315 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[3].oddr_inst/Q
+                         net (fo=1, routed)           0.001     2.316    phy_txd_OBUF[2]
+    A19                  OBUF (Prop_obuf_I_O)         1.138     3.454 r  phy_txd_OBUF[2]_inst/O
+                         net (fo=0)                   0.000     3.454    phy_txd[2]
+    A19                                                               r  phy_txd[2] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+Slack:                    inf
+  Source:                 core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[4].oddr_inst/C
+                            (rising edge-triggered cell ODDR clocked by clk_mmcm_out  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Destination:            phy_txd[3]
+                            (output port)
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        1.322ns  (logic 1.321ns (99.924%)  route 0.001ns (0.076%))
+  Logic Levels:           1  (OBUF=1)
+  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.107ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock clk_mmcm_out rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKOUT0
+                         net (fo=1, routed)           0.531     1.382    clk_mmcm_out
+    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     1.408 r  clk_bufg_inst/O
+                         net (fo=2759, routed)        0.730     2.138    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/clk_int
+    OLOGIC_X0Y216        ODDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[4].oddr_inst/C
+  -------------------------------------------------------------------    -------------------
+    OLOGIC_X0Y216        ODDR (Prop_oddr_C_Q)         0.177     2.315 r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/data_oddr_inst/oddr[4].oddr_inst/Q
+                         net (fo=1, routed)           0.001     2.316    phy_txd_OBUF[3]
+    A18                  OBUF (Prop_obuf_I_O)         1.144     3.459 r  phy_txd_OBUF[3]_inst/O
+                         net (fo=0)                   0.000     3.459    phy_txd[3]
+    A18                                                               r  phy_txd[3] (OUT)
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  mmcm_clkfb
+  To Clock:  
+
+Max Delay             1 Endpoint
+Min Delay             1 Endpoint
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 clk_mmcm_inst/CLKFBOUT
+                            (clock source 'mmcm_clkfb'  {rise@0.000ns fall@2.500ns period=5.000ns})
+  Destination:            clk_mmcm_inst/CLKFBIN
+  Path Group:             (none)
+  Path Type:              Max at Slow Process Corner
+  Data Path Delay:        0.012ns  (logic 0.000ns (0.000%)  route 0.012ns (99.999%))
+  Logic Levels:           0  
+  Clock Uncertainty:      0.133ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.071ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock mmcm_clkfb fall edge)
+                                                      2.500     2.500 f  
+    R4                                                0.000     2.500 f  clk_p (IN)
+                         net (fo=0)                   0.000     2.500    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.842     3.342 f  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           1.065     4.407    clk_ibufg
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT)
+                                                      0.078     4.485 f  clk_mmcm_inst/CLKFBOUT
+                         net (fo=1, routed)           0.012     4.497    mmcm_clkfb
+    MMCME2_ADV_X1Y2      MMCME2_ADV                                   f  clk_mmcm_inst/CLKFBIN
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 clk_mmcm_inst/CLKFBOUT
+                            (clock source 'mmcm_clkfb'  {rise@0.000ns fall@2.500ns period=5.000ns})
+  Destination:            clk_mmcm_inst/CLKFBIN
+  Path Group:             (none)
+  Path Type:              Min at Fast Process Corner
+  Data Path Delay:        0.005ns  (logic 0.000ns (0.000%)  route 0.005ns (100.000%))
+  Logic Levels:           0  
+  Clock Uncertainty:      0.133ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Discrete Jitter          (DJ):    0.071ns
+    Phase Error              (PE):    0.090ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+                         (clock mmcm_clkfb rise edge)
+                                                      0.000     0.000 r  
+    R4                                                0.000     0.000 r  clk_p (IN)
+                         net (fo=0)                   0.000     0.000    clk_p
+    R4                   IBUFDS (Prop_ibufds_I_O)     0.360     0.360 r  clk_200mhz_ibufgds_inst/O
+                         net (fo=1, routed)           0.440     0.800    clk_ibufg
+  -------------------------------------------------------------------    -------------------
+    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT)
+                                                      0.051     0.851 r  clk_mmcm_inst/CLKFBOUT
+                         net (fo=1, routed)           0.005     0.856    mmcm_clkfb
+    MMCME2_ADV_X1Y2      MMCME2_ADV                                   r  clk_mmcm_inst/CLKFBIN
+  -------------------------------------------------------------------    -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group:  (none)
+From Clock:  
+  To Clock:  phy_rx_clk
+
+Max Delay             5 Endpoints
+Min Delay             5 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 phy_rxd[0]
+                            (input port)
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[1].iddr_inst/D
+                            (rising edge-triggered cell IDDR clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        2.097ns  (logic 2.097ns (100.000%)  route 0.000ns (0.000%))
+  Logic Levels:           2  (IBUF=1 IDELAYE2=1)
+  Clock Path Skew:        3.143ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    3.143ns = ( 7.143 - 4.000 ) 
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    A16                                               0.000     0.000 r  phy_rxd[0] (IN)
+                         net (fo=0)                   0.000     0.000    phy_rxd[0]
+    A16                  IBUF (Prop_ibuf_I_O)         1.418     1.418 r  phy_rxd_IBUF[0]_inst/O
+                         net (fo=1, routed)           0.000     1.418    phy_rxd_IBUF[0]
+    IDELAY_X0Y231        IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT)
+                                                      0.679     2.097 r  phy_rxd_idelay_0/DATAOUT
+                         net (fo=1, routed)           0.000     2.097    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/input_d[1]
+    ILOGIC_X0Y231        IDDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[1].iddr_inst/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk fall edge)
+                                                      4.000     4.000 f  
+    B17                                               0.000     4.000 f  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     4.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     5.340 f  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.341     5.681    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFIO_X0Y19          BUFIO (Prop_bufio_I_O)       1.223     6.904 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/O
+                         net (fo=5, routed)           0.239     7.143    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/clk_io
+    ILOGIC_X0Y231        IDDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[1].iddr_inst/C
+
+Slack:                    inf
+  Source:                 phy_rx_ctl
+                            (input port)
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[0].iddr_inst/D
+                            (rising edge-triggered cell IDDR clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        2.095ns  (logic 2.095ns (100.000%)  route 0.000ns (0.000%))
+  Logic Levels:           2  (IBUF=1 IDELAYE2=1)
+  Clock Path Skew:        3.143ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    3.143ns = ( 7.143 - 4.000 ) 
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    A15                                               0.000     0.000 r  phy_rx_ctl (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_ctl
+    A15                  IBUF (Prop_ibuf_I_O)         1.416     1.416 r  phy_rx_ctl_IBUF_inst/O
+                         net (fo=1, routed)           0.000     1.416    phy_rx_ctl_IBUF
+    IDELAY_X0Y232        IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT)
+                                                      0.679     2.095 r  phy_rx_ctl_idelay/DATAOUT
+                         net (fo=1, routed)           0.000     2.095    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/input_d[0]
+    ILOGIC_X0Y232        IDDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[0].iddr_inst/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk fall edge)
+                                                      4.000     4.000 f  
+    B17                                               0.000     4.000 f  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     4.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     5.340 f  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.341     5.681    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFIO_X0Y19          BUFIO (Prop_bufio_I_O)       1.223     6.904 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/O
+                         net (fo=5, routed)           0.239     7.143    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/clk_io
+    ILOGIC_X0Y232        IDDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[0].iddr_inst/C
+
+Slack:                    inf
+  Source:                 phy_rxd[2]
+                            (input port)
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[3].iddr_inst/D
+                            (rising edge-triggered cell IDDR clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        2.088ns  (logic 2.088ns (100.000%)  route 0.000ns (0.000%))
+  Logic Levels:           2  (IBUF=1 IDELAYE2=1)
+  Clock Path Skew:        3.135ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    3.135ns = ( 7.135 - 4.000 ) 
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    C18                                               0.000     0.000 r  phy_rxd[2] (IN)
+                         net (fo=0)                   0.000     0.000    phy_rxd[2]
+    C18                  IBUF (Prop_ibuf_I_O)         1.409     1.409 r  phy_rxd_IBUF[2]_inst/O
+                         net (fo=1, routed)           0.000     1.409    phy_rxd_IBUF[2]
+    IDELAY_X0Y224        IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT)
+                                                      0.679     2.088 r  phy_rxd_idelay_2/DATAOUT
+                         net (fo=1, routed)           0.000     2.088    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/input_d[3]
+    ILOGIC_X0Y224        IDDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[3].iddr_inst/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk fall edge)
+                                                      4.000     4.000 f  
+    B17                                               0.000     4.000 f  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     4.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     5.340 f  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.341     5.681    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFIO_X0Y19          BUFIO (Prop_bufio_I_O)       1.223     6.904 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/O
+                         net (fo=5, routed)           0.231     7.135    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/clk_io
+    ILOGIC_X0Y224        IDDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[3].iddr_inst/C
+
+Slack:                    inf
+  Source:                 phy_rxd[1]
+                            (input port)
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[2].iddr_inst/D
+                            (rising edge-triggered cell IDDR clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        2.088ns  (logic 2.088ns (100.000%)  route 0.000ns (0.000%))
+  Logic Levels:           2  (IBUF=1 IDELAYE2=1)
+  Clock Path Skew:        3.137ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    3.137ns = ( 7.137 - 4.000 ) 
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    B18                                               0.000     0.000 r  phy_rxd[1] (IN)
+                         net (fo=0)                   0.000     0.000    phy_rxd[1]
+    B18                  IBUF (Prop_ibuf_I_O)         1.409     1.409 r  phy_rxd_IBUF[1]_inst/O
+                         net (fo=1, routed)           0.000     1.409    phy_rxd_IBUF[1]
+    IDELAY_X0Y227        IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT)
+                                                      0.679     2.088 r  phy_rxd_idelay_1/DATAOUT
+                         net (fo=1, routed)           0.000     2.088    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/input_d[2]
+    ILOGIC_X0Y227        IDDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[2].iddr_inst/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk fall edge)
+                                                      4.000     4.000 f  
+    B17                                               0.000     4.000 f  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     4.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     5.340 f  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.341     5.681    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFIO_X0Y19          BUFIO (Prop_bufio_I_O)       1.223     6.904 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/O
+                         net (fo=5, routed)           0.233     7.137    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/clk_io
+    ILOGIC_X0Y227        IDDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[2].iddr_inst/C
+
+Slack:                    inf
+  Source:                 phy_rxd[3]
+                            (input port)
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[4].iddr_inst/D
+                            (rising edge-triggered cell IDDR clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Setup (Max at Slow Process Corner)
+  Data Path Delay:        2.085ns  (logic 2.085ns (100.000%)  route 0.000ns (0.000%))
+  Logic Levels:           2  (IBUF=1 IDELAYE2=1)
+  Clock Path Skew:        3.135ns (DCD - SCD + CPR)
+    Destination Clock Delay (DCD):    3.135ns = ( 7.135 - 4.000 ) 
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    0.000ns
+  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
+    Total System Jitter     (TSJ):    0.050ns
+    Total Input Jitter      (TIJ):    0.000ns
+    Discrete Jitter          (DJ):    0.000ns
+    Phase Error              (PE):    0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    C19                                               0.000     0.000 r  phy_rxd[3] (IN)
+                         net (fo=0)                   0.000     0.000    phy_rxd[3]
+    C19                  IBUF (Prop_ibuf_I_O)         1.406     1.406 r  phy_rxd_IBUF[3]_inst/O
+                         net (fo=1, routed)           0.000     1.406    phy_rxd_IBUF[3]
+    IDELAY_X0Y223        IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT)
+                                                      0.679     2.085 r  phy_rxd_idelay_3/DATAOUT
+                         net (fo=1, routed)           0.000     2.085    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/input_d[4]
+    ILOGIC_X0Y223        IDDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[4].iddr_inst/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk fall edge)
+                                                      4.000     4.000 f  
+    B17                                               0.000     4.000 f  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     4.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         1.340     5.340 f  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.341     5.681    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFIO_X0Y19          BUFIO (Prop_bufio_I_O)       1.223     6.904 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/O
+                         net (fo=5, routed)           0.231     7.135    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/clk_io
+    ILOGIC_X0Y223        IDDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[4].iddr_inst/C
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack:                    inf
+  Source:                 phy_rxd[3]
+                            (input port)
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[4].iddr_inst/D
+                            (rising edge-triggered cell IDDR clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.486ns  (logic 0.486ns (100.000%)  route 0.000ns (0.000%))
+  Logic Levels:           2  (IBUF=1 IDELAYE2=1)
+  Clock Path Skew:        1.324ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.324ns = ( 5.324 - 4.000 ) 
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    C19                                               0.000     0.000 r  phy_rxd[3] (IN)
+                         net (fo=0)                   0.000     0.000    phy_rxd[3]
+    C19                  IBUF (Prop_ibuf_I_O)         0.243     0.243 r  phy_rxd_IBUF[3]_inst/O
+                         net (fo=1, routed)           0.000     0.243    phy_rxd_IBUF[3]
+    IDELAY_X0Y223        IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT)
+                                                      0.243     0.486 r  phy_rxd_idelay_3/DATAOUT
+                         net (fo=1, routed)           0.000     0.486    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/input_d[4]
+    ILOGIC_X0Y223        IDDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[4].iddr_inst/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk fall edge)
+                                                      4.000     4.000 f  
+    B17                                               0.000     4.000 f  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     4.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     4.431 f  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.280     4.711    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFIO_X0Y19          BUFIO (Prop_bufio_I_O)       0.516     5.227 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/O
+                         net (fo=5, routed)           0.097     5.324    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/clk_io
+    ILOGIC_X0Y223        IDDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[4].iddr_inst/C
+
+Slack:                    inf
+  Source:                 phy_rxd[1]
+                            (input port)
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[2].iddr_inst/D
+                            (rising edge-triggered cell IDDR clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.489ns  (logic 0.489ns (100.000%)  route 0.000ns (0.000%))
+  Logic Levels:           2  (IBUF=1 IDELAYE2=1)
+  Clock Path Skew:        1.327ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.327ns = ( 5.327 - 4.000 ) 
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    B18                                               0.000     0.000 r  phy_rxd[1] (IN)
+                         net (fo=0)                   0.000     0.000    phy_rxd[1]
+    B18                  IBUF (Prop_ibuf_I_O)         0.246     0.246 r  phy_rxd_IBUF[1]_inst/O
+                         net (fo=1, routed)           0.000     0.246    phy_rxd_IBUF[1]
+    IDELAY_X0Y227        IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT)
+                                                      0.243     0.489 r  phy_rxd_idelay_1/DATAOUT
+                         net (fo=1, routed)           0.000     0.489    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/input_d[2]
+    ILOGIC_X0Y227        IDDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[2].iddr_inst/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk fall edge)
+                                                      4.000     4.000 f  
+    B17                                               0.000     4.000 f  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     4.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     4.431 f  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.280     4.711    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFIO_X0Y19          BUFIO (Prop_bufio_I_O)       0.516     5.227 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/O
+                         net (fo=5, routed)           0.100     5.327    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/clk_io
+    ILOGIC_X0Y227        IDDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[2].iddr_inst/C
+
+Slack:                    inf
+  Source:                 phy_rxd[2]
+                            (input port)
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[3].iddr_inst/D
+                            (rising edge-triggered cell IDDR clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.489ns  (logic 0.489ns (100.000%)  route 0.000ns (0.000%))
+  Logic Levels:           2  (IBUF=1 IDELAYE2=1)
+  Clock Path Skew:        1.324ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.324ns = ( 5.324 - 4.000 ) 
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    C18                                               0.000     0.000 r  phy_rxd[2] (IN)
+                         net (fo=0)                   0.000     0.000    phy_rxd[2]
+    C18                  IBUF (Prop_ibuf_I_O)         0.246     0.246 r  phy_rxd_IBUF[2]_inst/O
+                         net (fo=1, routed)           0.000     0.246    phy_rxd_IBUF[2]
+    IDELAY_X0Y224        IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT)
+                                                      0.243     0.489 r  phy_rxd_idelay_2/DATAOUT
+                         net (fo=1, routed)           0.000     0.489    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/input_d[3]
+    ILOGIC_X0Y224        IDDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[3].iddr_inst/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk fall edge)
+                                                      4.000     4.000 f  
+    B17                                               0.000     4.000 f  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     4.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     4.431 f  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.280     4.711    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFIO_X0Y19          BUFIO (Prop_bufio_I_O)       0.516     5.227 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/O
+                         net (fo=5, routed)           0.097     5.324    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/clk_io
+    ILOGIC_X0Y224        IDDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[3].iddr_inst/C
+
+Slack:                    inf
+  Source:                 phy_rx_ctl
+                            (input port)
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[0].iddr_inst/D
+                            (rising edge-triggered cell IDDR clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.496ns  (logic 0.496ns (100.000%)  route 0.000ns (0.000%))
+  Logic Levels:           2  (IBUF=1 IDELAYE2=1)
+  Clock Path Skew:        1.332ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.332ns = ( 5.332 - 4.000 ) 
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    A15                                               0.000     0.000 r  phy_rx_ctl (IN)
+                         net (fo=0)                   0.000     0.000    phy_rx_ctl
+    A15                  IBUF (Prop_ibuf_I_O)         0.253     0.253 r  phy_rx_ctl_IBUF_inst/O
+                         net (fo=1, routed)           0.000     0.253    phy_rx_ctl_IBUF
+    IDELAY_X0Y232        IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT)
+                                                      0.243     0.496 r  phy_rx_ctl_idelay/DATAOUT
+                         net (fo=1, routed)           0.000     0.496    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/input_d[0]
+    ILOGIC_X0Y232        IDDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[0].iddr_inst/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk fall edge)
+                                                      4.000     4.000 f  
+    B17                                               0.000     4.000 f  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     4.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     4.431 f  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.280     4.711    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFIO_X0Y19          BUFIO (Prop_bufio_I_O)       0.516     5.227 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/O
+                         net (fo=5, routed)           0.105     5.332    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/clk_io
+    ILOGIC_X0Y232        IDDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[0].iddr_inst/C
+
+Slack:                    inf
+  Source:                 phy_rxd[0]
+                            (input port)
+  Destination:            core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[1].iddr_inst/D
+                            (rising edge-triggered cell IDDR clocked by phy_rx_clk  {rise@0.000ns fall@4.000ns period=8.000ns})
+  Path Group:             (none)
+  Path Type:              Hold (Min at Fast Process Corner)
+  Data Path Delay:        0.498ns  (logic 0.498ns (100.000%)  route 0.000ns (0.000%))
+  Logic Levels:           2  (IBUF=1 IDELAYE2=1)
+  Clock Path Skew:        1.332ns (DCD - SCD - CPR)
+    Destination Clock Delay (DCD):    1.332ns = ( 5.332 - 4.000 ) 
+    Source Clock Delay      (SCD):    0.000ns
+    Clock Pessimism Removal (CPR):    -0.000ns
+
+    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
+  -------------------------------------------------------------------    -------------------
+    A16                                               0.000     0.000 r  phy_rxd[0] (IN)
+                         net (fo=0)                   0.000     0.000    phy_rxd[0]
+    A16                  IBUF (Prop_ibuf_I_O)         0.255     0.255 r  phy_rxd_IBUF[0]_inst/O
+                         net (fo=1, routed)           0.000     0.255    phy_rxd_IBUF[0]
+    IDELAY_X0Y231        IDELAYE2 (Prop_idelaye2_IDATAIN_DATAOUT)
+                                                      0.243     0.498 r  phy_rxd_idelay_0/DATAOUT
+                         net (fo=1, routed)           0.000     0.498    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/input_d[1]
+    ILOGIC_X0Y231        IDDR                                         r  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[1].iddr_inst/D
+  -------------------------------------------------------------------    -------------------
+
+                         (clock phy_rx_clk fall edge)
+                                                      4.000     4.000 f  
+    B17                                               0.000     4.000 f  phy_rx_clk (IN)
+                         net (fo=0)                   0.000     4.000    phy_rx_clk
+    B17                  IBUF (Prop_ibuf_I_O)         0.431     4.431 f  phy_rx_clk_IBUF_inst/O
+                         net (fo=2, routed)           0.280     4.711    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/input_clk
+    BUFIO_X0Y19          BUFIO (Prop_bufio_I_O)       0.516     5.227 f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/clk_bufio/O
+                         net (fo=5, routed)           0.105     5.332    core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/clk_io
+    ILOGIC_X0Y231        IDDR                                         f  core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_ssio_ddr_inst/data_iddr_inst/iddr[1].iddr_inst/C
+
+
+
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_timing_summary_routed.rpx b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_timing_summary_routed.rpx
new file mode 100644
index 000000000..b1c81335f
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_timing_summary_routed.rpx differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_utilization_placed.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_utilization_placed.pb
new file mode 100644
index 000000000..27f508284
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_utilization_placed.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_utilization_placed.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_utilization_placed.rpt
new file mode 100644
index 000000000..569897b8a
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_utilization_placed.rpt
@@ -0,0 +1,238 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:26:11 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_utilization -file fpga_utilization_placed.rpt -pb fpga_utilization_placed.pb
+| Design       : fpga
+| Device       : xc7a200tfbg484-2
+| Speed File   : -2
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++----------------------------+------+-------+------------+-----------+-------+
+|          Site Type         | Used | Fixed | Prohibited | Available | Util% |
++----------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs                 | 1817 |     0 |        800 |    133800 |  1.36 |
+|   LUT as Logic             | 1725 |     0 |        800 |    133800 |  1.29 |
+|   LUT as Memory            |   92 |     0 |          0 |     46200 |  0.20 |
+|     LUT as Distributed RAM |   92 |     0 |            |           |       |
+|     LUT as Shift Register  |    0 |     0 |            |           |       |
+| Slice Registers            | 2761 |     0 |          0 |    269200 |  1.03 |
+|   Register as Flip Flop    | 2761 |     0 |          0 |    269200 |  1.03 |
+|   Register as Latch        |    0 |     0 |          0 |    269200 |  0.00 |
+| F7 Muxes                   |   17 |     0 |        400 |     66900 |  0.03 |
+| F8 Muxes                   |    0 |     0 |        200 |     33450 |  0.00 |
++----------------------------+------+-------+------------+-----------+-------+
+* Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 14    |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 166   |          Yes |         Set |            - |
+| 2581  |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+------+-------+------------+-----------+-------+
+|                  Site Type                 | Used | Fixed | Prohibited | Available | Util% |
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Slice                                      |  955 |     0 |        200 |     33450 |  2.86 |
+|   SLICEL                                   |  582 |     0 |            |           |       |
+|   SLICEM                                   |  373 |     0 |            |           |       |
+| LUT as Logic                               | 1725 |     0 |        800 |    133800 |  1.29 |
+|   using O5 output only                     |    0 |       |            |           |       |
+|   using O6 output only                     | 1364 |       |            |           |       |
+|   using O5 and O6                          |  361 |       |            |           |       |
+| LUT as Memory                              |   92 |     0 |          0 |     46200 |  0.20 |
+|   LUT as Distributed RAM                   |   92 |     0 |            |           |       |
+|     using O5 output only                   |    0 |       |            |           |       |
+|     using O6 output only                   |   16 |       |            |           |       |
+|     using O5 and O6                        |   76 |       |            |           |       |
+|   LUT as Shift Register                    |    0 |     0 |            |           |       |
+| Slice Registers                            | 2761 |     0 |          0 |    269200 |  1.03 |
+|   Register driven from within the Slice    | 1125 |       |            |           |       |
+|   Register driven from outside the Slice   | 1636 |       |            |           |       |
+|     LUT in front of the register is unused | 1237 |       |            |           |       |
+|     LUT in front of the register is used   |  399 |       |            |           |       |
+| Unique Control Sets                        |  151 |       |        200 |     33450 |  0.45 |
++--------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++-------------------+------+-------+------------+-----------+-------+
+|     Site Type     | Used | Fixed | Prohibited | Available | Util% |
++-------------------+------+-------+------------+-----------+-------+
+| Block RAM Tile    |    8 |     0 |          0 |       365 |  2.19 |
+|   RAMB36/FIFO*    |    6 |     0 |          0 |       365 |  1.64 |
+|     RAMB36E1 only |    6 |       |            |           |       |
+|   RAMB18          |    4 |     0 |          0 |       730 |  0.55 |
+|     RAMB18E1 only |    4 |       |            |           |       |
++-------------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |       740 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |   16 |    16 |          0 |       285 |  5.61 |
+|   IOB Master Pads           |    7 |       |            |           |       |
+|   IOB Slave Pads            |    9 |       |            |           |       |
+| Bonded IPADs                |    0 |     0 |          0 |        14 |  0.00 |
+| Bonded OPADs                |    0 |     0 |          0 |         8 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |        10 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |        10 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |        40 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |        40 |  0.00 |
+| IDELAYCTRL                  |    1 |     0 |          0 |        10 | 10.00 |
+| IBUFDS                      |    1 |     1 |          0 |       274 |  0.36 |
+| GTPE2_CHANNEL               |    0 |     0 |          0 |         4 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |        40 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |        40 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    5 |     5 |          0 |       500 |  1.00 |
+|   IDELAYE2 only             |    5 |     5 |            |           |       |
+| IBUFDS_GTE2                 |    0 |     0 |          0 |         2 |  0.00 |
+| ILOGIC                      |    5 |     5 |          0 |       285 |  1.75 |
+|   IFF_IDDR_Register         |    5 |     5 |            |           |       |
+| OLOGIC                      |    6 |     6 |          0 |       285 |  2.11 |
+|   OUTFF_ODDR_Register       |    6 |     6 |            |           |       |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++--------------+------+-------+------------+-----------+-------+
+|   Site Type  | Used | Fixed | Prohibited | Available | Util% |
++--------------+------+-------+------------+-----------+-------+
+| BUFGCTRL     |    3 |     0 |          0 |        32 |  9.38 |
+| BUFIO        |    1 |     1 |          0 |        40 |  2.50 |
+|   BUFIO only |    1 |     1 |            |           |       |
+| MMCME2_ADV   |    1 |     0 |          0 |        10 | 10.00 |
+| PLLE2_ADV    |    0 |     0 |          0 |        10 |  0.00 |
+| BUFMRCE      |    0 |     0 |          0 |        20 |  0.00 |
+| BUFHCE       |    0 |     0 |          0 |       120 |  0.00 |
+| BUFR         |    1 |     0 |          0 |        40 |  2.50 |
++--------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |          0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++------------+------+---------------------+
+|  Ref Name  | Used | Functional Category |
++------------+------+---------------------+
+| FDRE       | 2581 |        Flop & Latch |
+| LUT6       |  649 |                 LUT |
+| LUT3       |  403 |                 LUT |
+| LUT5       |  355 |                 LUT |
+| LUT2       |  264 |                 LUT |
+| LUT4       |  246 |                 LUT |
+| CARRY4     |  200 |          CarryLogic |
+| LUT1       |  169 |                 LUT |
+| FDSE       |  166 |        Flop & Latch |
+| RAMD32     |  114 |  Distributed Memory |
+| RAMS32     |   38 |  Distributed Memory |
+| MUXF7      |   17 |               MuxFx |
+| RAMD64E    |   16 |  Distributed Memory |
+| FDPE       |   14 |        Flop & Latch |
+| OBUF       |    7 |                  IO |
+| IBUF       |    7 |                  IO |
+| RAMB36E1   |    6 |        Block Memory |
+| ODDR       |    6 |                  IO |
+| IDELAYE2   |    5 |                  IO |
+| IDDR       |    5 |                  IO |
+| RAMB18E1   |    4 |        Block Memory |
+| BUFG       |    3 |               Clock |
+| MMCME2_ADV |    1 |               Clock |
+| IDELAYCTRL |    1 |                  IO |
+| IBUFDS     |    1 |                  IO |
+| BUFR       |    1 |               Clock |
+| BUFIO      |    1 |               Clock |
++------------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/gen_run.xml b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/gen_run.xml
new file mode 100644
index 000000000..6276d1888
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/gen_run.xml
@@ -0,0 +1,434 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7a200tfbg484-2" LaunchTime="1736315699">
+  <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-RQS" Name="fpga_postroute_physopted.rqs"/>
+  <File Type="ROUTE-RQS" Name="fpga_routed.rqs"/>
+  <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+  <File Type="BG-BGN" Name="fpga.bgn"/>
+  <File Type="BITSTR-SYSDEF" Name="fpga.sysdef"/>
+  <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+  <File Type="BITSTR-LTX" Name="fpga.ltx"/>
+  <File Type="RBD_FILE" Name="fpga.rbd"/>
+  <File Type="NPI_FILE" Name="fpga.npi"/>
+  <File Type="RNPI_FILE" Name="fpga.rnpi"/>
+  <File Type="CFI_FILE" Name="fpga.cfi"/>
+  <File Type="RCFI_FILE" Name="fpga.rcfi"/>
+  <File Type="PL-PDI-FILE" Name="fpga_pld.pdi"/>
+  <File Type="BOOT-PDI-FILE" Name="fpga_soc.pdi"/>
+  <File Type="RDI-RDI" Name="fpga.vdi"/>
+  <File Type="PDI-FILE" Name="fpga.pdi"/>
+  <File Type="BITSTR-MMI" Name="fpga.mmi"/>
+  <File Type="BITSTR-BMM" Name="fpga_bd.bmm"/>
+  <File Type="BITSTR-NKY" Name="fpga.nky"/>
+  <File Type="BITSTR-RBT" Name="fpga.rbt"/>
+  <File Type="BITSTR-MSK" Name="fpga.msk"/>
+  <File Type="BG-BIN" Name="fpga.bin"/>
+  <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
+  <File Type="BG-BIT" Name="fpga.bit"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="fpga_bus_skew_postroute_physopted.rpx"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="fpga_bus_skew_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="fpga_bus_skew_postroute_physopted.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="fpga_timing_summary_postroute_physopted.rpx"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="fpga_timing_summary_postroute_physopted.pb"/>
+  <File Type="POSTROUTE-PHYSOPT-TIMING" Name="fpga_timing_summary_postroute_physopted.rpt"/>
+  <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="fpga_postroute_physopt_bb.dcp"/>
+  <File Type="POSTROUTE-PHYSOPT-DCP" Name="fpga_postroute_physopt.dcp"/>
+  <File Type="BG-DRC" Name="fpga.drc"/>
+  <File Type="ROUTE-RQS-PB" Name="fpga_rqs_routed.pb"/>
+  <File Type="ROUTE-BUS-SKEW-RPX" Name="fpga_bus_skew_routed.rpx"/>
+  <File Type="ROUTE-BUS-SKEW-PB" Name="fpga_bus_skew_routed.pb"/>
+  <File Type="ROUTE-BUS-SKEW" Name="fpga_bus_skew_routed.rpt"/>
+  <File Type="PA-TCL" Name="fpga.tcl"/>
+  <File Type="INIT-TIMING" Name="fpga_timing_summary_init.rpt"/>
+  <File Type="OPT-DCP" Name="fpga_opt.dcp"/>
+  <File Type="OPT-RQA-PB" Name="fpga_rqa_opted.pb"/>
+  <File Type="OPT-DRC" Name="fpga_drc_opted.rpt"/>
+  <File Type="PLACE-TIMING" Name="fpga_timing_summary_placed.rpt"/>
+  <File Type="OPT-METHODOLOGY-DRC" Name="fpga_methodology_drc_opted.rpt"/>
+  <File Type="PLACE-UTIL-PB" Name="fpga_utilization_placed.pb"/>
+  <File Type="OPT-HWDEF" Name="fpga.hwdef"/>
+  <File Type="POSTPLACE-PWROPT-TIMING" Name="fpga_timing_summary_postplace_pwropted.rpt"/>
+  <File Type="REPORTS-TCL" Name="fpga_reports.tcl"/>
+  <File Type="OPT-TIMING" Name="fpga_timing_summary_opted.rpt"/>
+  <File Type="PWROPT-DCP" Name="fpga_pwropt.dcp"/>
+  <File Type="PWROPT-DRC" Name="fpga_drc_pwropted.rpt"/>
+  <File Type="PWROPT-TIMING" Name="fpga_timing_summary_pwropted.rpt"/>
+  <File Type="PLACE-DCP" Name="fpga_placed.dcp"/>
+  <File Type="PLACE-RQA-PB" Name="fpga_rqa_placed.pb"/>
+  <File Type="PLACE-IO" Name="fpga_io_placed.rpt"/>
+  <File Type="PHYSOPT-TIMING" Name="fpga_timing_summary_physopted.rpt"/>
+  <File Type="PLACE-CLK" Name="fpga_clock_utilization_placed.rpt"/>
+  <File Type="PLACE-UTIL" Name="fpga_utilization_placed.rpt"/>
+  <File Type="PLACE-CTRL" Name="fpga_control_sets_placed.rpt"/>
+  <File Type="ROUTE-METHODOLOGY-DRC" Name="fpga_methodology_drc_routed.rpt"/>
+  <File Type="PLACE-SIMILARITY" Name="fpga_incremental_reuse_placed.rpt"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="fpga_methodology_drc_routed.pb"/>
+  <File Type="PLACE-PRE-SIMILARITY" Name="fpga_incremental_reuse_pre_placed.rpt"/>
+  <File Type="ROUTE-DRC-RPX" Name="fpga_drc_routed.rpx"/>
+  <File Type="POSTPLACE-PWROPT-DCP" Name="fpga_postplace_pwropt.dcp"/>
+  <File Type="PHYSOPT-DCP" Name="fpga_physopt.dcp"/>
+  <File Type="PHYSOPT-DRC" Name="fpga_drc_physopted.rpt"/>
+  <File Type="ROUTE-ERROR-DCP" Name="fpga_routed_error.dcp"/>
+  <File Type="ROUTE-DCP" Name="fpga_routed.dcp"/>
+  <File Type="ROUTE-BLACKBOX-DCP" Name="fpga_routed_bb.dcp"/>
+  <File Type="ROUTE-DRC" Name="fpga_drc_routed.rpt"/>
+  <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="fpga_methodology_drc_routed.rpx"/>
+  <File Type="ROUTE-DRC-PB" Name="fpga_drc_routed.pb"/>
+  <File Type="ROUTE-PWR" Name="fpga_power_routed.rpt"/>
+  <File Type="ROUTE-PWR-SUM" Name="fpga_power_summary_routed.pb"/>
+  <File Type="ROUTE-PWR-RPX" Name="fpga_power_routed.rpx"/>
+  <File Type="ROUTE-STATUS" Name="fpga_route_status.rpt"/>
+  <File Type="ROUTE-STATUS-PB" Name="fpga_route_status.pb"/>
+  <File Type="ROUTE-TIMINGSUMMARY" Name="fpga_timing_summary_routed.rpt"/>
+  <File Type="ROUTE-TIMING-PB" Name="fpga_timing_summary_routed.pb"/>
+  <File Type="ROUTE-TIMING-RPX" Name="fpga_timing_summary_routed.rpx"/>
+  <File Type="ROUTE-SIMILARITY" Name="fpga_incremental_reuse_routed.rpt"/>
+  <File Type="ROUTE-CLK" Name="fpga_clock_utilization_routed.rpt"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/arbiter.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/arp.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/arp_cache.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/arp_eth_rx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/arp_eth_tx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/axis_async_fifo.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/axis_fifo.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/axis_gmii_rx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/axis_gmii_tx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_arb_mux.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_axis_rx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_axis_tx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_mac_1g.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_mac_1g_rgmii.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_mac_1g_rgmii_fifo.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../rtl/fpga_core.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/iddr.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ip.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ip_arb_mux.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ip_complete.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ip_eth_rx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ip_eth_tx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/lfsr.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/oddr.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/priority_encoder.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/rgmii_phy_if.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ssio_ddr_in.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/sync_reset.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/udp.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/udp_checksum_gen.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/udp_complete.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/udp_ip_rx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/udp_ip_tx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../rtl/fpga.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/defines.v">
+      <FileInfo>
+        <Attr Name="AutoDisabled" Val="1"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../rtl/sync_signal.v">
+      <FileInfo>
+        <Attr Name="AutoDisabled" Val="1"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ssio_ddr_out.v">
+      <FileInfo>
+        <Attr Name="AutoDisabled" Val="1"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="fpga"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../fpga.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../eth.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/syn/vivado/rgmii_phy_if.tcl">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/syn/vivado/eth_mac_fifo.tcl">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/syn/vivado/sync_reset.tcl">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+    <Filter Type="Utils"/>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
+    <Step Id="init_design"/>
+    <Step Id="opt_design"/>
+    <Step Id="power_opt_design"/>
+    <Step Id="place_design"/>
+    <Step Id="post_place_power_opt_design"/>
+    <Step Id="phys_opt_design"/>
+    <Step Id="route_design"/>
+    <Step Id="post_route_phys_opt_design"/>
+    <Step Id="write_bitstream"/>
+  </Strategy>
+</GenRun>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/htr.txt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/htr.txt
new file mode 100644
index 000000000..1d7c08268
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+#          the basic steps of a run.  Note that runme.bat/sh needs
+#          to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log fpga.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fpga.tcl -notrace
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/init_design.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/init_design.pb
new file mode 100644
index 000000000..85aa2680b
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/init_design.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/opt_design.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/opt_design.pb
new file mode 100644
index 000000000..53e1ac2aa
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/opt_design.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/phys_opt_design.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/phys_opt_design.pb
new file mode 100644
index 000000000..71e5ce728
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/phys_opt_design.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/place_design.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/place_design.pb
new file mode 100644
index 000000000..e8dbfadb4
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/place_design.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/project.wdf b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/project.wdf
new file mode 100644
index 000000000..6e3eea8e5
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/project.wdf
@@ -0,0 +1,31 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3338:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:37:00:00
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diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/route_design.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/route_design.pb
new file mode 100644
index 000000000..f21c1e470
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/route_design.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/rundef.js b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/rundef.js
new file mode 100644
index 000000000..ca76b9010
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/rundef.js
@@ -0,0 +1,45 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "/home/kavya/Downloads/Downloads/Vivado/2023.1/ids_lite/ISE/bin/lin64;/home/kavya/Downloads/Downloads/Vivado/2023.1/bin;";
+} else {
+  PathVal = "/home/kavya/Downloads/Downloads/Vivado/2023.1/ids_lite/ISE/bin/lin64;/home/kavya/Downloads/Downloads/Vivado/2023.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "init_design", "begin" );
+ISEStep( "vivado",
+         "-log fpga.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fpga.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/runme.bat b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/runme.bat
new file mode 100644
index 000000000..3a5f85351
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/runme.log b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/runme.log
new file mode 100644
index 000000000..8ca6a29f3
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/runme.log
@@ -0,0 +1,692 @@
+
+*** Running vivado
+    with args -log fpga.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fpga.tcl -notrace
+
+
+****** Vivado v2023.1 (64-bit)
+  **** SW Build 3865809 on Sun May  7 15:04:56 MDT 2023
+  **** IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
+  **** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
+    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source fpga.tcl -notrace
+create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1298.672 ; gain = 19.023 ; free physical = 51210 ; free virtual = 56217
+Command: link_design -top fpga -part xc7a200tfbg484-2
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a200tfbg484-2
+Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1696.117 ; gain = 0.000 ; free physical = 50827 ; free virtual = 55834
+INFO: [Netlist 29-17] Analyzing 261 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2023.1
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+Finished Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]
+Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc]
+Finished Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]
+Inserting timing constraints for rgmii_phy_if instance core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl:23]
+INFO: [Timing 38-2] Deriving generated clocks [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl:23]
+get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2486.605 ; gain = 620.055 ; free physical = 50265 ; free virtual = 55271
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]
+Inserting timing constraints for eth_mac_1g_rgmii instance core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
+Inserting timing constraints for ethernet MAC with FIFO instance core_inst/eth_mac_inst
+WARNING: [Vivado 12-180] No cells matched '.*/rx_sync_reg_[1234]_reg\[\d+\]'. [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl:23]
+WARNING: [Vivado 12-180] No cells matched '.*/tx_sync_reg_[1234]_reg\[\d+\]'. [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl:23]
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
+Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_inst/rx_fifo/fifo_inst
+Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_inst/tx_fifo/fifo_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
+Inserting timing constraints for sync_reset instance sync_reset_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2486.605 ; gain = 0.000 ; free physical = 50265 ; free virtual = 55271
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 23 instances were transformed.
+  RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 4 instances
+  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 19 instances
+
+11 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:21 . Memory (MB): peak = 2486.605 ; gain = 1183.934 ; free physical = 50265 ; free virtual = 55271
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2550.637 ; gain = 64.031 ; free physical = 50241 ; free virtual = 55248
+
+Starting Cache Timing Information Task
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Cache Timing Information Task | Checksum: 217aa3e62
+
+Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2550.637 ; gain = 0.000 ; free physical = 50241 ; free virtual = 55248
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-1566] Pulled 2 inverters resulting in an inversion of 8 pins
+INFO: [Opt 31-138] Pushed 2 inverter(s) to 4 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 17656d86b
+
+Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.2 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 4 cells
+INFO: [Opt 31-1021] In phase Retarget, 2 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: 14db90694
+
+Time (s): cpu = 00:00:00.6 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 11d80edcb
+
+Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells
+INFO: [Opt 31-1021] In phase Sweep, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 11d80edcb
+
+Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 1451036a6
+
+Time (s): cpu = 00:00:00.9 ; elapsed = 00:00:00.5 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 1451036a6
+
+Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.52 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
+-------------------------------------------------------------------------------------------------------------------------
+|  Retarget                     |               0  |               4  |                                              2  |
+|  Constant propagation         |               0  |               0  |                                              0  |
+|  Sweep                        |               0  |               0  |                                              1  |
+|  BUFG optimization            |               0  |               0  |                                              0  |
+|  Shift Register Optimization  |               0  |               0  |                                              0  |
+|  Post Processing Netlist      |               0  |               0  |                                              0  |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+Ending Logic Optimization Task | Checksum: 1451036a6
+
+Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.53 . Memory (MB): peak = 2760.574 ; gain = 0.000 ; free physical = 49966 ; free virtual = 54973
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Running Vector-less Activity Propagation...
+INFO: [Pwropt 34-9] Applying IDT optimizations ...
+INFO: [Pwropt 34-10] Applying ODC optimizations ...
+
+Finished Running Vector-less Activity Propagation
+
+
+Starting PowerOpt Patch Enables Task
+INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 10 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
+INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
+Number of BRAM Ports augmented: 10 newly gated: 3 Total Ports: 20
+Ending PowerOpt Patch Enables Task | Checksum: 199102501
+
+Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.07 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49746 ; free virtual = 54753
+Ending Power Optimization Task | Checksum: 199102501
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 393.367 ; free physical = 49746 ; free virtual = 54753
+
+Starting Final Cleanup Task
+
+Starting Logic Optimization Task
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Ending Logic Optimization Task | Checksum: e9653835
+
+Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.35 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49743 ; free virtual = 54750
+Ending Final Cleanup Task | Checksum: e9653835
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49743 ; free virtual = 54750
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49743 ; free virtual = 54750
+Ending Netlist Obfuscation Task | Checksum: e9653835
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49743 ; free virtual = 54750
+INFO: [Common 17-83] Releasing license: Implementation
+43 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:11 . Memory (MB): peak = 3153.941 ; gain = 667.336 ; free physical = 49743 ; free virtual = 54750
+INFO: [runtcl-4] Executing : report_drc -file fpga_drc_opted.rpt -pb fpga_drc_opted.pb -rpx fpga_drc_opted.rpx
+Command: report_drc -file fpga_drc_opted.rpt -pb fpga_drc_opted.pb -rpx fpga_drc_opted.rpx
+INFO: [IP_Flow 19-234] Refreshing IP repositories
+INFO: [IP_Flow 19-1704] No user IP repositories specified
+INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/kavya/Downloads/Downloads/Vivado/2023.1/data/ip'.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_opted.rpt.
+report_drc completed successfully
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.04 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49731 ; free virtual = 54738
+INFO: [Common 17-1381] The checkpoint '/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_opt.dcp' has been generated.
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49713 ; free virtual = 54721
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 75944c7a
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49713 ; free virtual = 54721
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49713 ; free virtual = 54721
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: cf190ca7
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49720 ; free virtual = 54729
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 16c9ebfb9
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49722 ; free virtual = 54730
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 16c9ebfb9
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49722 ; free virtual = 54730
+Phase 1 Placer Initialization | Checksum: 16c9ebfb9
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49722 ; free virtual = 54730
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 145ffb69b
+
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:03 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49773 ; free virtual = 54781
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: fc643355
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49771 ; free virtual = 54779
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: fc643355
+
+Time (s): cpu = 00:00:08 ; elapsed = 00:00:04 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49771 ; free virtual = 54779
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 111bdd4f4
+
+Time (s): cpu = 00:00:24 ; elapsed = 00:00:09 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49792 ; free virtual = 54800
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 111 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 46 nets or LUTs. Breaked 0 LUT, combined 46 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49791 ; free virtual = 54799
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+|  LUT Combining                                    |            0  |             46  |                    46  |           0  |           1  |  00:00:00  |
+|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
+|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
+|  Total                                            |            0  |             46  |                    46  |           0  |           4  |  00:00:00  |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 23f038e7f
+
+Time (s): cpu = 00:00:25 ; elapsed = 00:00:10 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49791 ; free virtual = 54799
+Phase 2.4 Global Placement Core | Checksum: 14ff872b5
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49791 ; free virtual = 54799
+Phase 2 Global Placement | Checksum: 14ff872b5
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:11 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49791 ; free virtual = 54799
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 2352324bd
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:11 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49790 ; free virtual = 54799
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1f45a4b56
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:12 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49790 ; free virtual = 54798
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1a8ee0a11
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:12 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49790 ; free virtual = 54798
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 24263726a
+
+Time (s): cpu = 00:00:30 ; elapsed = 00:00:12 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49790 ; free virtual = 54798
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1fa12dbcb
+
+Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49781 ; free virtual = 54789
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 1dae522f8
+
+Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49781 ; free virtual = 54789
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 282e9aeba
+
+Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49781 ; free virtual = 54789
+Phase 3 Detail Placement | Checksum: 282e9aeba
+
+Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49781 ; free virtual = 54789
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 225391a39
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.561 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 227454a20
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.46 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
+Ending Physical Synthesis Task | Checksum: 227454a20
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.53 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+Phase 4.1.1.1 BUFG Insertion | Checksum: 225391a39
+
+Time (s): cpu = 00:00:37 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=0.561. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 27e26f70f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+Phase 4.1 Post Commit Optimization | Checksum: 27e26f70f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 27e26f70f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion 
+ ____________________________________________________
+|           | Global Congestion | Short Congestion  |
+| Direction | Region Size       | Region Size       |
+|___________|___________________|___________________|
+|      North|                1x1|                1x1|
+|___________|___________________|___________________|
+|      South|                1x1|                1x1|
+|___________|___________________|___________________|
+|       East|                1x1|                1x1|
+|___________|___________________|___________________|
+|       West|                1x1|                1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 27e26f70f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+Phase 4.3 Placer Reporting | Checksum: 27e26f70f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 25ce714f9
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+Ending Placer Task | Checksum: 192347c4f
+
+Time (s): cpu = 00:00:38 ; elapsed = 00:00:16 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+INFO: [Common 17-83] Releasing license: Implementation
+84 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+place_design: Time (s): cpu = 00:00:40 ; elapsed = 00:00:17 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49779 ; free virtual = 54788
+INFO: [runtcl-4] Executing : report_io -file fpga_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49747 ; free virtual = 54755
+INFO: [runtcl-4] Executing : report_utilization -file fpga_utilization_placed.rpt -pb fpga_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file fpga_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.17 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49708 ; free virtual = 54716
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.47 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49705 ; free virtual = 54719
+INFO: [Common 17-1381] The checkpoint '/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_placed.dcp' has been generated.
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:00.81 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49687 ; free virtual = 54697
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+93 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.47 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49651 ; free virtual = 54668
+INFO: [Common 17-1381] The checkpoint '/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a200t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: d8edec7a ConstDB: 0 ShapeSum: b9468fd5 RouteDB: 0
+Post Restoration Checksum: NetGraph: e06a7014 | NumContArr: 5223c358 | Constraints: 190a55ad | Timing: 0
+Phase 1 Build RT Design | Checksum: 14b988919
+
+Time (s): cpu = 00:01:22 ; elapsed = 00:01:09 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49598 ; free virtual = 54611
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 14b988919
+
+Time (s): cpu = 00:01:22 ; elapsed = 00:01:09 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49598 ; free virtual = 54611
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 14b988919
+
+Time (s): cpu = 00:01:22 ; elapsed = 00:01:09 . Memory (MB): peak = 3153.941 ; gain = 0.000 ; free physical = 49598 ; free virtual = 54611
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 1a4ea8580
+
+Time (s): cpu = 00:01:29 ; elapsed = 00:01:12 . Memory (MB): peak = 3171.445 ; gain = 17.504 ; free physical = 49559 ; free virtual = 54571
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.485  | TNS=0.000  | WHS=-0.223 | THS=-165.589|
+
+
+Phase 2.4 Update Timing for Bus Skew
+
+Phase 2.4.1 Update Timing
+Phase 2.4.1 Update Timing | Checksum: 1534219d3
+
+Time (s): cpu = 00:01:32 ; elapsed = 00:01:12 . Memory (MB): peak = 3171.445 ; gain = 17.504 ; free physical = 49559 ; free virtual = 54571
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.485  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 2.4 Update Timing for Bus Skew | Checksum: 1511870b8
+
+Time (s): cpu = 00:01:32 ; elapsed = 00:01:13 . Memory (MB): peak = 3171.445 ; gain = 17.504 ; free physical = 49559 ; free virtual = 54572
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0 %
+  Global Horizontal Routing Utilization  = 0 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 4426
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 4426
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 2 Router Initialization | Checksum: 1db21434d
+
+Time (s): cpu = 00:01:34 ; elapsed = 00:01:13 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49552 ; free virtual = 54565
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: 1db21434d
+
+Time (s): cpu = 00:01:34 ; elapsed = 00:01:13 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49552 ; free virtual = 54565
+Phase 3 Initial Routing | Checksum: 14394818d
+
+Time (s): cpu = 00:01:37 ; elapsed = 00:01:14 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49552 ; free virtual = 54565
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 282
+ Number of Nodes with overlaps = 14
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 1
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.478  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+
+Phase 4.1 Global Iteration 0 | Checksum: 216154ec7
+
+Time (s): cpu = 00:01:42 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+Phase 4 Rip-up And Reroute | Checksum: 216154ec7
+
+Time (s): cpu = 00:01:42 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 5 Delay and Skew Optimization
+
+Phase 5.1 Delay CleanUp
+Phase 5.1 Delay CleanUp | Checksum: 216154ec7
+
+Time (s): cpu = 00:01:42 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 5.2 Clock Skew Optimization
+Phase 5.2 Clock Skew Optimization | Checksum: 216154ec7
+
+Time (s): cpu = 00:01:42 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+Phase 5 Delay and Skew Optimization | Checksum: 216154ec7
+
+Time (s): cpu = 00:01:42 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: 1838e7ae8
+
+Time (s): cpu = 00:01:43 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.478  | TNS=0.000  | WHS=0.034  | THS=0.000  |
+
+Phase 6.1 Hold Fix Iter | Checksum: 2460eece7
+
+Time (s): cpu = 00:01:43 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+Phase 6 Post Hold Fix | Checksum: 2460eece7
+
+Time (s): cpu = 00:01:43 ; elapsed = 00:01:16 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+  Global Vertical Routing Utilization    = 0.264764 %
+  Global Horizontal Routing Utilization  = 0.306841 %
+  Routable Net Status*
+  *Does not include unroutable nets such as driverless and loadless.
+  Run report_route_status for detailed report.
+  Number of Failed Nets               = 0
+    (Failed Nets is the sum of unrouted and partially routed nets)
+  Number of Unrouted Nets             = 0
+  Number of Partially Routed Nets     = 0
+  Number of Node Overlaps             = 0
+
+Phase 7 Route finalize | Checksum: 1bf9f7771
+
+Time (s): cpu = 00:01:44 ; elapsed = 00:01:17 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: 1bf9f7771
+
+Time (s): cpu = 00:01:44 ; elapsed = 00:01:17 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: 1aee248e0
+
+Time (s): cpu = 00:01:44 ; elapsed = 00:01:17 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Phase 10 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=0.478  | TNS=0.000  | WHS=0.034  | THS=0.000  |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 10 Post Router Timing | Checksum: 1aee248e0
+
+Time (s): cpu = 00:01:46 ; elapsed = 00:01:17 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+INFO: [Route 35-16] Router Completed Successfully
+
+Phase 11 Post-Route Event Processing
+Phase 11 Post-Route Event Processing | Checksum: 1a4605fd7
+
+Time (s): cpu = 00:01:46 ; elapsed = 00:01:18 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Time (s): cpu = 00:01:46 ; elapsed = 00:01:18 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+108 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:01:49 ; elapsed = 00:01:19 . Memory (MB): peak = 3179.445 ; gain = 25.504 ; free physical = 49554 ; free virtual = 54567
+INFO: [runtcl-4] Executing : report_drc -file fpga_drc_routed.rpt -pb fpga_drc_routed.pb -rpx fpga_drc_routed.rpx
+Command: report_drc -file fpga_drc_routed.rpt -pb fpga_drc_routed.pb -rpx fpga_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file fpga_methodology_drc_routed.rpt -pb fpga_methodology_drc_routed.pb -rpx fpga_methodology_drc_routed.rpx
+Command: report_methodology -file fpga_methodology_drc_routed.rpt -pb fpga_methodology_drc_routed.pb -rpx fpga_methodology_drc_routed.rpx
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file fpga_power_routed.rpt -pb fpga_power_summary_routed.pb -rpx fpga_power_routed.rpx
+Command: report_power -file fpga_power_routed.rpt -pb fpga_power_summary_routed.pb -rpx fpga_power_routed.rpx
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+122 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file fpga_route_status.rpt -pb fpga_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file fpga_timing_summary_routed.rpt -pb fpga_timing_summary_routed.pb -rpx fpga_timing_summary_routed.rpx -warn_on_violation 
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
+INFO: [runtcl-4] Executing : report_incremental_reuse -file fpga_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file fpga_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file fpga_bus_skew_routed.rpt -pb fpga_bus_skew_routed.pb -rpx fpga_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.53 . Memory (MB): peak = 3259.484 ; gain = 0.000 ; free physical = 49506 ; free virtual = 54529
+INFO: [Common 17-1381] The checkpoint '/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga_routed.dcp' has been generated.
+INFO: [Common 17-206] Exiting Vivado at Wed Jan  8 11:27:42 2025...
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/runme.sh b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/runme.sh
new file mode 100755
index 000000000..e76563127
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/runme.sh
@@ -0,0 +1,44 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+# 
+
+if [ -z "$PATH" ]; then
+  PATH=/home/kavya/Downloads/Downloads/Vivado/2023.1/ids_lite/ISE/bin/lin64:/home/kavya/Downloads/Downloads/Vivado/2023.1/bin
+else
+  PATH=/home/kavya/Downloads/Downloads/Vivado/2023.1/ids_lite/ISE/bin/lin64:/home/kavya/Downloads/Downloads/Vivado/2023.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+# pre-commands:
+/bin/touch .init_design.begin.rst
+EAStep vivado -log fpga.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source fpga.tcl -notrace
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/vivado.jou b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/vivado.jou
new file mode 100644
index 000000000..3c27cb7aa
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/vivado.jou
@@ -0,0 +1,14 @@
+#-----------------------------------------------------------
+# Vivado v2023.1 (64-bit)
+# SW Build 3865809 on Sun May  7 15:04:56 MDT 2023
+# IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
+# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
+# Start of session at: Wed Jan  8 11:25:03 2025
+# Process ID: 256738
+# Current directory: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1
+# Command line: vivado -log fpga.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source fpga.tcl -notrace
+# Log file: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/fpga.vdi
+# Journal file: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/vivado.jou
+# Running On: kavya-Precision-Tower-5810, OS: Linux, CPU Frequency: 2140.712 MHz, CPU Physical cores: 12, Host memory: 67345 MB
+#-----------------------------------------------------------
+source fpga.tcl -notrace
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/vivado.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/vivado.pb
new file mode 100644
index 000000000..4a3927a04
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/impl_1/vivado.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/.Vivado_Synthesis.queue.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/.Xil/fpga_propImpl.xdc b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/.Xil/fpga_propImpl.xdc
new file mode 100644
index 000000000..caf143677
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/.Xil/fpga_propImpl.xdc
@@ -0,0 +1,33 @@
+set_property SRC_FILE_INFO {cfile:/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc rfile:../../../../fpga.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN R4 IOSTANDARD DIFF_SSTL15} [get_ports clk_p]
+set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN T4 IOSTANDARD DIFF_SSTL15} [get_ports clk_n]
+set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN T6 IOSTANDARD LVCMOS15} [get_ports reset_n]
+set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS33} [get_ports phy_rx_clk]
+set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[0]}]
+set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN B18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[1]}]
+set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[2]}]
+set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS33} [get_ports {phy_rxd[3]}]
+set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports phy_rx_ctl]
+set_property src_info {type:XDC file:1 line:29 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports phy_tx_clk]
+set_property src_info {type:XDC file:1 line:30 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[0]}]
+set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[1]}]
+set_property src_info {type:XDC file:1 line:32 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[2]}]
+set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports {phy_txd[3]}]
+set_property src_info {type:XDC file:1 line:34 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 16} [get_ports phy_tx_ctl]
+set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design]
+set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports phy_reset_n]
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/.vivado.begin.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 000000000..a18bc0d86
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+    <Process Command="vivado" Owner="kavya" Host="kavya-Precision-Tower-5810" Pid="256265" HostCore="12" HostMemory="65766632">
+    </Process>
+</ProcessHandle>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/.vivado.end.rst b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/.vivado.end.rst
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/ISEWrap.js b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/ISEWrap.js
new file mode 100755
index 000000000..61806d027
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/ISEWrap.js
@@ -0,0 +1,270 @@
+//
+//  Vivado(TM)
+//  ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+//  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 
+//  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+  // 1. RUN DIR setup
+  var ISEScrFP = WScript.ScriptFullName;
+  var ISEScrN = WScript.ScriptName;
+  ISERunDir = 
+    ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+  // 2. LOG file setup
+  ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  // 3. LOG echo?
+  var ISEScriptArgs = WScript.Arguments;
+  for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+    if ( ISEScriptArgs(loopi) == "-quiet" ) {
+      ISELogEcho = false;
+      break;
+    }
+  }
+
+  // 4. WSH version check
+  var ISEOptimalVersionWSH = 5.6;
+  var ISECurrentVersionWSH = WScript.Version;
+  if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+    ISEStdErr( "" );
+    ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+	       ISEOptimalVersionWSH + " or higher. Downloads" );
+    ISEStdErr( "         for upgrading your Windows Scripting Host can be found here: " );
+    ISEStdErr( "             http://msdn.microsoft.com/downloads/list/webdev.asp" );
+    ISEStdErr( "" );
+
+    ISEOldVersionWSH = true;
+  }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+  // CHECK for a STOP FILE
+  if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+    ISEStdErr( "" );
+    ISEStdErr( "*** Halting run - EA reset detected ***" );
+    ISEStdErr( "" );
+    WScript.Quit( 1 );
+  }
+
+  // WRITE STEP HEADER to LOG
+  ISEStdOut( "" );
+  ISEStdOut( "*** Running " + ISEProg );
+  ISEStdOut( "    with args " + ISEArgs );
+  ISEStdOut( "" );
+
+  // LAUNCH!
+  var ISEExitCode = ISEExec( ISEProg, ISEArgs );  
+  if ( ISEExitCode != 0 ) {
+    WScript.Quit( ISEExitCode );
+  }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+  var ISEStep = ISEProg;
+  if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+    ISEProg += ".bat";
+  }
+
+  var ISECmdLine = ISEProg + " " + ISEArgs;
+  var ISEExitCode = 1;
+
+  if ( ISEOldVersionWSH ) { // WSH 5.1
+
+    // BEGIN file creation
+    ISETouchFile( ISEStep, "begin" );
+
+    // LAUNCH!
+    ISELogFileStr.Close();
+    ISECmdLine = 
+      "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+    ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+    ISELogFileStr = ISEOpenFile( ISELogFile );
+
+  } else {  // WSH 5.6
+
+    // LAUNCH!
+    ISEShell.CurrentDirectory = ISERunDir;
+
+    // Redirect STDERR to STDOUT
+    ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+    var ISEProcess = ISEShell.Exec( ISECmdLine );
+    
+    // BEGIN file creation
+    var wbemFlagReturnImmediately = 0x10;
+    var wbemFlagForwardOnly = 0x20;
+    var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+    var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+    var NOC = 0;
+    var NOLP = 0;
+    var TPM = 0;
+    var cpuInfos = new Enumerator(processor);
+    for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+        var cpuInfo = cpuInfos.item();
+        NOC += cpuInfo.NumberOfCores;
+        NOLP += cpuInfo.NumberOfLogicalProcessors;
+    }
+    var csInfos = new Enumerator(computerSystem);
+    for(;!csInfos.atEnd(); csInfos.moveNext()) {
+        var csInfo = csInfos.item();
+        TPM += csInfo.TotalPhysicalMemory;
+    }
+
+    var ISEHOSTCORE = NOLP
+    var ISEMEMTOTAL = TPM
+
+    var ISENetwork = WScript.CreateObject( "WScript.Network" );
+    var ISEHost = ISENetwork.ComputerName;
+    var ISEUser = ISENetwork.UserName;
+    var ISEPid = ISEProcess.ProcessID;
+    var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+    ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+    ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+    ISEBeginFile.WriteLine( "    <Process Command=\"" + ISEProg + 
+			    "\" Owner=\"" + ISEUser + 
+			    "\" Host=\"" + ISEHost + 
+			    "\" Pid=\"" + ISEPid +
+			    "\" HostCore=\"" + ISEHOSTCORE +
+			    "\" HostMemory=\"" + ISEMEMTOTAL +
+			    "\">" );
+    ISEBeginFile.WriteLine( "    </Process>" );
+    ISEBeginFile.WriteLine( "</ProcessHandle>" );
+    ISEBeginFile.Close();
+    
+    var ISEOutStr = ISEProcess.StdOut;
+    var ISEErrStr = ISEProcess.StdErr;
+    
+    // WAIT for ISEStep to finish
+    while ( ISEProcess.Status == 0 ) {
+      
+      // dump stdout then stderr - feels a little arbitrary
+      while ( !ISEOutStr.AtEndOfStream ) {
+        ISEStdOut( ISEOutStr.ReadLine() );
+      }  
+      
+      WScript.Sleep( 100 );
+    }
+
+    ISEExitCode = ISEProcess.ExitCode;
+  }
+
+  ISELogFileStr.Close();
+
+  // END/ERROR file creation
+  if ( ISEExitCode != 0 ) {    
+    ISETouchFile( ISEStep, "error" );
+    
+  } else {
+    ISETouchFile( ISEStep, "end" );
+  }
+
+  return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+  ISELogFileStr.WriteLine( ISELine );
+  
+  if ( ISELogEcho ) {
+    WScript.StdOut.WriteLine( ISELine );
+  }
+}
+
+function ISEStdErr( ISELine ) {
+  
+  ISELogFileStr.WriteLine( ISELine );
+
+  if ( ISELogEcho ) {
+    WScript.StdErr.WriteLine( ISELine );
+  }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+  var ISETFile = 
+    ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+  ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+  // This function has been updated to deal with a problem seen in CR #870871.
+  // In that case the user runs a script that runs impl_1, and then turns around
+  // and runs impl_1 -to_step write_bitstream. That second run takes place in
+  // the same directory, which means we may hit some of the same files, and in
+  // particular, we will open the runme.log file. Even though this script closes
+  // the file (now), we see cases where a subsequent attempt to open the file
+  // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+  // play? In any case, we try to work around this by first waiting if the file
+  // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+  // and try to open the file 10 times with a one second delay after each attempt.
+  // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+  // If there is an unrecognized exception when trying to open the file, we output
+  // an error message and write details to an exception.log file.
+  var ISEFullPath = ISERunDir + "/" + ISEFilename;
+  if (ISEFileSys.FileExists(ISEFullPath)) {
+    // File is already there. This could be a problem. Wait in case it is still in use.
+    WScript.Sleep(5000);
+  }
+  var i;
+  for (i = 0; i < 10; ++i) {
+    try {
+      return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+    } catch (exception) {
+      var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+      if (error_code == 52) { // 52 is bad file name or number.
+        // Wait a second and try again.
+        WScript.Sleep(1000);
+        continue;
+      } else {
+        WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+        var exceptionFilePath = ISERunDir + "/exception.log";
+        if (!ISEFileSys.FileExists(exceptionFilePath)) {
+          WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+          var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+          exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+          exceptionFile.WriteLine("\tException name: " + exception.name);
+          exceptionFile.WriteLine("\tException error code: " + error_code);
+          exceptionFile.WriteLine("\tException message: " + exception.message);
+          exceptionFile.Close();
+        }
+        throw exception;
+      }
+    }
+  }
+  // If we reached this point, we failed to open the file after 10 attempts.
+  // We need to error out.
+  WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+  WScript.Quit(1);
+}
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/ISEWrap.sh b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/ISEWrap.sh
new file mode 100755
index 000000000..05d538137
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,85 @@
+#!/bin/sh
+
+#
+#  Vivado(TM)
+#  ISEWrap.sh: Vivado Runs Script for UNIX
+#  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. 
+#  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. 
+#
+
+cmd_exists()
+{
+  command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo ""                                        >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo ""                                        >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo ""                      >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo "    with args $@"      >> $HD_LOG
+echo ""                      >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ] 
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST     #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>"                                                                     >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">"                                                   >> $ISE_BEGINFILE
+echo "    <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo "    </Process>"                                                                              >> $ISE_BEGINFILE
+echo "</ProcessHandle>"                                                                            >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+    /bin/touch .$ISE_STEP.end.rst
+else
+    /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/__synthesis_is_complete__ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 000000000..e69de29bb
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.dcp b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.dcp
new file mode 100644
index 000000000..beacf0206
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.dcp differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.tcl b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.tcl
new file mode 100644
index 000000000..e3581901e
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.tcl
@@ -0,0 +1,174 @@
+# 
+# Synthesis run script generated by Vivado
+# 
+
+set TIME_start [clock seconds] 
+namespace eval ::optrace {
+  variable script "/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.tcl"
+  variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+  namespace eval ::dispatch {
+    variable connected false
+    if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+      set result "true"
+      if {[catch {
+        if {[lsearch -exact [package names] DispatchTcl] < 0} {
+          set result [load librdi_cd_clienttcl[info sharedlibextension]] 
+        }
+        if {$result eq "false"} {
+          puts "WARNING: Could not load dispatch client library"
+        }
+        set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+        if { $connect_id eq "" } {
+          puts "WARNING: Could not initialize dispatch client"
+        } else {
+          puts "INFO: Dispatch client connection id - $connect_id"
+          set connected true
+        }
+      } catch_res]} {
+        puts "WARNING: failed to connect to dispatch server - $catch_res"
+      }
+    }
+  }
+}
+if {$::dispatch::connected} {
+  # Remove the dummy proc if it exists.
+  if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+    rename ::OPTRACE ""
+  }
+  proc ::OPTRACE { task action {tags {} } } {
+    ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+  }
+  # dispatch is generic. We specifically want to attach logging.
+  ::vitis_log::connect_client
+} else {
+  # Add dummy proc if it doesn't exist.
+  if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+    proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+        # Do nothing
+    }
+  }
+}
+
+proc create_report { reportName command } {
+  set status "."
+  append status $reportName ".fail"
+  if { [file exists $status] } {
+    eval file delete [glob $status]
+  }
+  send_msg_id runtcl-4 info "Executing : $command"
+  set retval [eval catch { $command } msg]
+  if { $retval != 0 } {
+    set fp [open $status w]
+    close $fp
+    send_msg_id runtcl-5 warning "$msg"
+  }
+}
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a200tfbg484-2
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_property webtalk.parent_dir /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.cache/wt [current_project]
+set_property parent.project_path /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.xpr [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language Verilog [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_verilog -library xil_defaultlib {
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/arbiter.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_cache.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_rx.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/iddr.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_rx.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_tx.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/oddr.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/rgmii_phy_if.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ssio_ddr_in.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/sync_reset.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_complete.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_rx.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_tx.v
+  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga.v
+}
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+  set_property used_in_implementation false $dcp
+}
+read_xdc /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc
+set_property used_in_implementation false [get_files /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]
+
+read_xdc /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc
+set_property used_in_implementation false [get_files /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc]
+
+read_xdc -unmanaged /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl
+set_property used_in_implementation false [get_files /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]
+
+read_xdc -unmanaged /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl
+set_property used_in_implementation false [get_files /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]
+
+read_xdc -unmanaged /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl
+set_property used_in_implementation false [get_files /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
+
+read_xdc -unmanaged /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
+set_property used_in_implementation false [get_files /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
+
+read_xdc -unmanaged /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl
+set_property used_in_implementation false [get_files /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
+
+set_param ips.enableIPCacheLiteLoad 1
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top fpga -part xc7a200tfbg484-2
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef fpga.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+create_report "synth_1_synth_report_utilization_0" "report_utilization -file fpga_utilization_synth.rpt -pb fpga_utilization_synth.pb"
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.vds b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.vds
new file mode 100644
index 000000000..a108c93a5
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.vds
@@ -0,0 +1,1403 @@
+#-----------------------------------------------------------
+# Vivado v2023.1 (64-bit)
+# SW Build 3865809 on Sun May  7 15:04:56 MDT 2023
+# IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
+# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
+# Start of session at: Wed Jan  8 11:22:41 2025
+# Process ID: 256309
+# Current directory: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1
+# Command line: vivado -log fpga.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fpga.tcl
+# Log file: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.vds
+# Journal file: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/vivado.jou
+# Running On: kavya-Precision-Tower-5810, OS: Linux, CPU Frequency: 2249.015 MHz, CPU Physical cores: 12, Host memory: 67345 MB
+#-----------------------------------------------------------
+source fpga.tcl -notrace
+create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1335.785 ; gain = 0.023 ; free physical = 51138 ; free virtual = 56143
+Command: synth_design -top fpga -part xc7a200tfbg484-2
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tfbg484-2
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 256359
+WARNING: [Synth 8-11065] parameter 'BYTE_LANES' becomes localparam in 'arp_eth_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:89]
+WARNING: [Synth 8-11065] parameter 'HDR_SIZE' becomes localparam in 'arp_eth_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:91]
+WARNING: [Synth 8-11065] parameter 'CYCLE_COUNT' becomes localparam in 'arp_eth_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:93]
+WARNING: [Synth 8-11065] parameter 'PTR_WIDTH' becomes localparam in 'arp_eth_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:95]
+WARNING: [Synth 8-11065] parameter 'OFFSET' becomes localparam in 'arp_eth_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:97]
+WARNING: [Synth 8-11065] parameter 'BYTE_LANES' becomes localparam in 'arp_eth_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:85]
+WARNING: [Synth 8-11065] parameter 'HDR_SIZE' becomes localparam in 'arp_eth_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:87]
+WARNING: [Synth 8-11065] parameter 'CYCLE_COUNT' becomes localparam in 'arp_eth_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:89]
+WARNING: [Synth 8-11065] parameter 'PTR_WIDTH' becomes localparam in 'arp_eth_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:91]
+WARNING: [Synth 8-11065] parameter 'OFFSET' becomes localparam in 'arp_eth_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:93]
+WARNING: [Synth 8-11065] parameter 'ADDR_WIDTH' becomes localparam in 'axis_async_fifo' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:145]
+WARNING: [Synth 8-11065] parameter 'OUTPUT_FIFO_ADDR_WIDTH' becomes localparam in 'axis_async_fifo' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:147]
+WARNING: [Synth 8-11065] parameter 'ADDR_WIDTH' becomes localparam in 'axis_fifo' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:137]
+WARNING: [Synth 8-11065] parameter 'OUTPUT_FIFO_ADDR_WIDTH' becomes localparam in 'axis_fifo' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:139]
+WARNING: [Synth 8-11065] parameter 'MIN_LEN_WIDTH' becomes localparam in 'axis_gmii_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:93]
+WARNING: [Synth 8-11065] parameter 'CL_S_COUNT' becomes localparam in 'eth_arb_mux' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:90]
+WARNING: [Synth 8-11065] parameter 'BYTE_LANES' becomes localparam in 'eth_axis_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:80]
+WARNING: [Synth 8-11065] parameter 'HDR_SIZE' becomes localparam in 'eth_axis_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:82]
+WARNING: [Synth 8-11065] parameter 'CYCLE_COUNT' becomes localparam in 'eth_axis_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:84]
+WARNING: [Synth 8-11065] parameter 'PTR_WIDTH' becomes localparam in 'eth_axis_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:86]
+WARNING: [Synth 8-11065] parameter 'OFFSET' becomes localparam in 'eth_axis_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:88]
+WARNING: [Synth 8-11065] parameter 'BYTE_LANES' becomes localparam in 'eth_axis_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:79]
+WARNING: [Synth 8-11065] parameter 'HDR_SIZE' becomes localparam in 'eth_axis_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:81]
+WARNING: [Synth 8-11065] parameter 'CYCLE_COUNT' becomes localparam in 'eth_axis_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:83]
+WARNING: [Synth 8-11065] parameter 'PTR_WIDTH' becomes localparam in 'eth_axis_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:85]
+WARNING: [Synth 8-11065] parameter 'OFFSET' becomes localparam in 'eth_axis_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:87]
+WARNING: [Synth 8-11065] parameter 'MAC_CTRL_ENABLE' becomes localparam in 'eth_mac_1g' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g.v:191]
+WARNING: [Synth 8-11065] parameter 'TX_USER_WIDTH_INT' becomes localparam in 'eth_mac_1g' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g.v:192]
+WARNING: [Synth 8-11065] parameter 'CL_S_COUNT' becomes localparam in 'ip_arb_mux' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:116]
+WARNING: [Synth 8-11065] parameter 'STYLE_INT' becomes localparam in 'lfsr' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v:355]
+WARNING: [Synth 8-11065] parameter 'LEVELS' becomes localparam in 'priority_encoder' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:47]
+WARNING: [Synth 8-11065] parameter 'W' becomes localparam in 'priority_encoder' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:48]
+WARNING: [Synth 8-11065] parameter 'HEADER_FIFO_ADDR_WIDTH' becomes localparam in 'udp_checksum_gen' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:143]
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2071.398 ; gain = 377.801 ; free physical = 50143 ; free virtual = 55148
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'fpga' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga.v:10]
+INFO: [Synth 8-6157] synthesizing module 'IBUFGDS' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:72266]
+INFO: [Synth 8-6155] done synthesizing module 'IBUFGDS' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:72266]
+INFO: [Synth 8-6157] synthesizing module 'MMCME2_BASE' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:80431]
+	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
+	Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: double 
+	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double 
+	Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double 
+	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer 
+	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT1_PHASE bound to: 90.000000 - type: double 
+	Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer 
+	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string 
+	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double 
+	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
+	Parameter REF_JITTER1 bound to: 0.010000 - type: double 
+	Parameter STARTUP_WAIT bound to: FALSE - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'MMCME2_BASE' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:80431]
+INFO: [Synth 8-6157] synthesizing module 'BUFG' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1519]
+INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1519]
+INFO: [Synth 8-6157] synthesizing module 'sync_reset' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/sync_reset.v:35]
+	Parameter N bound to: 4 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'sync_reset' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/sync_reset.v:35]
+WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga.v:146]
+INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73864]
+INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73864]
+INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73877]
+	Parameter IDELAY_TYPE bound to: FIXED - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73877]
+INFO: [Synth 8-6157] synthesizing module 'fpga_core' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+INFO: [Synth 8-6157] synthesizing module 'eth_mac_1g_rgmii_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string 
+	Parameter USE_CLK90 bound to: TRUE - type: string 
+	Parameter ENABLE_PADDING bound to: 1 - type: integer 
+	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer 
+	Parameter TX_FIFO_DEPTH bound to: 4096 - type: integer 
+	Parameter TX_FRAME_FIFO bound to: 1 - type: integer 
+	Parameter RX_FIFO_DEPTH bound to: 4096 - type: integer 
+	Parameter RX_FRAME_FIFO bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'eth_mac_1g_rgmii' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string 
+	Parameter USE_CLK90 bound to: TRUE - type: string 
+	Parameter ENABLE_PADDING bound to: 1 - type: integer 
+	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'rgmii_phy_if' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/rgmii_phy_if.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string 
+	Parameter USE_CLK90 bound to: TRUE - type: string 
+INFO: [Synth 8-6157] synthesizing module 'ssio_ddr_in' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ssio_ddr_in.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string 
+	Parameter WIDTH bound to: 5 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1791]
+INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1791]
+INFO: [Synth 8-6157] synthesizing module 'BUFR' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1857]
+	Parameter BUFR_DIVIDE bound to: BYPASS - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'BUFR' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1857]
+INFO: [Synth 8-6157] synthesizing module 'iddr' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/iddr.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter WIDTH bound to: 5 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'IDDR' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73742]
+	Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string 
+	Parameter SRTYPE bound to: ASYNC - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'IDDR' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73742]
+INFO: [Synth 8-6155] done synthesizing module 'iddr' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/iddr.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'ssio_ddr_in' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ssio_ddr_in.v:34]
+INFO: [Synth 8-6157] synthesizing module 'oddr' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/oddr.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'ODDR' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:94765]
+	Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string 
+	Parameter SRTYPE bound to: ASYNC - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'ODDR' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:94765]
+INFO: [Synth 8-6155] done synthesizing module 'oddr' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/oddr.v:34]
+INFO: [Synth 8-6157] synthesizing module 'oddr__parameterized0' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/oddr.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter WIDTH bound to: 5 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'oddr__parameterized0' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/oddr.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'rgmii_phy_if' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/rgmii_phy_if.v:34]
+INFO: [Synth 8-6157] synthesizing module 'eth_mac_1g' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g.v:34]
+	Parameter ENABLE_PADDING bound to: 1 - type: integer 
+	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'axis_gmii_rx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_rx.v:34]
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter PTP_TS_ENABLE bound to: 0 - type: integer 
+	Parameter PTP_TS_WIDTH bound to: 96 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'lfsr' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v:34]
+	Parameter LFSR_WIDTH bound to: 32 - type: integer 
+	Parameter LFSR_POLY bound to: 79764919 - type: integer 
+	Parameter LFSR_CONFIG bound to: GALOIS - type: string 
+	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer 
+	Parameter REVERSE bound to: 1 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter STYLE bound to: AUTO - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'lfsr' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_rx.v:189]
+INFO: [Synth 8-6155] done synthesizing module 'axis_gmii_rx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_rx.v:34]
+INFO: [Synth 8-6157] synthesizing module 'axis_gmii_tx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:34]
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter ENABLE_PADDING bound to: 1 - type: integer 
+	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer 
+	Parameter PTP_TS_ENABLE bound to: 0 - type: integer 
+	Parameter PTP_TS_WIDTH bound to: 96 - type: integer 
+	Parameter PTP_TS_CTRL_IN_TUSER bound to: 0 - type: integer 
+	Parameter PTP_TAG_ENABLE bound to: 0 - type: integer 
+	Parameter PTP_TAG_WIDTH bound to: 16 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:367]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:241]
+INFO: [Synth 8-6155] done synthesizing module 'axis_gmii_tx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'eth_mac_1g' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g.v:34]
+WARNING: [Synth 8-7071] port 'tx_ptp_ts' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_ptp_ts' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_axis_ptp_ts' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_axis_ptp_ts_tag' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_axis_ptp_ts_valid' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_lfc_req' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_lfc_resend' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_lfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_lfc_req' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_lfc_ack' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_pfc_req' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_pfc_resend' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_pfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_pfc_req' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_pfc_ack' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_lfc_pause_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_pause_req' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_pause_ack' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_start_packet' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_start_packet' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_mcf' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_mcf' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_lfc_pkt' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_lfc_xon' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_lfc_xoff' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_lfc_paused' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_pfc_pkt' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_pfc_xon' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_pfc_xoff' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_pfc_paused' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_lfc_pkt' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_lfc_xon' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_lfc_xoff' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_lfc_paused' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_pfc_pkt' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_pfc_xon' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_pfc_xoff' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_pfc_paused' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_eth_dst_mcast' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_check_eth_dst_mcast' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_eth_dst_ucast' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_check_eth_dst_ucast' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_eth_src' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_check_eth_src' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_eth_type' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_opcode_lfc' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_check_opcode_lfc' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_opcode_pfc' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_check_opcode_pfc' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_forward' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_enable' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_eth_dst' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_eth_src' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_eth_type' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_opcode' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_quanta' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_refresh' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_eth_dst' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_eth_src' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_eth_type' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_opcode' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_quanta' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_refresh' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_rx_lfc_opcode' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_rx_lfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_rx_pfc_opcode' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_rx_pfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7023] instance 'eth_mac_1g_inst' of module 'eth_mac_1g' has 98 connections declared, but only 29 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+INFO: [Synth 8-6155] done synthesizing module 'eth_mac_1g_rgmii' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:34]
+INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo_adapter' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
+	Parameter DEPTH bound to: 4096 - type: integer 
+	Parameter S_DATA_WIDTH bound to: 8 - type: integer 
+	Parameter S_KEEP_ENABLE bound to: 1'b0 
+	Parameter S_KEEP_WIDTH bound to: 1 - type: integer 
+	Parameter M_DATA_WIDTH bound to: 8 - type: integer 
+	Parameter M_KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter RAM_PIPELINE bound to: 1 - type: integer 
+	Parameter FRAME_FIFO bound to: 1 - type: integer 
+	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1 
+	Parameter USER_BAD_FRAME_MASK bound to: 1'b1 
+	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer 
+	Parameter DROP_BAD_FRAME bound to: 1 - type: integer 
+	Parameter DROP_WHEN_FULL bound to: 0 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
+	Parameter DEPTH bound to: 4096 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter KEEP_WIDTH bound to: 1 - type: integer 
+	Parameter LAST_ENABLE bound to: 1 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter ID_WIDTH bound to: 8 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_WIDTH bound to: 8 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter RAM_PIPELINE bound to: 1 - type: integer 
+	Parameter OUTPUT_FIFO_ENABLE bound to: 0 - type: integer 
+	Parameter FRAME_FIFO bound to: 1 - type: integer 
+	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1 
+	Parameter USER_BAD_FRAME_MASK bound to: 1'b1 
+	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer 
+	Parameter DROP_BAD_FRAME bound to: 1 - type: integer 
+	Parameter DROP_WHEN_FULL bound to: 0 - type: integer 
+	Parameter MARK_WHEN_FULL bound to: 0 - type: integer 
+	Parameter PAUSE_ENABLE bound to: 0 - type: integer 
+	Parameter FRAME_PAUSE bound to: 1 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo_adapter' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
+WARNING: [Synth 8-7071] port 's_pause_req' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 's_pause_ack' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 'm_pause_req' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 'm_pause_ack' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 's_status_depth' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 's_status_depth_commit' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 'm_status_depth' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 'm_status_depth_commit' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7023] instance 'tx_fifo' of module 'axis_async_fifo_adapter' has 34 connections declared, but only 26 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo_adapter__parameterized0' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
+	Parameter DEPTH bound to: 4096 - type: integer 
+	Parameter S_DATA_WIDTH bound to: 8 - type: integer 
+	Parameter S_KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter M_DATA_WIDTH bound to: 8 - type: integer 
+	Parameter M_KEEP_ENABLE bound to: 1'b0 
+	Parameter M_KEEP_WIDTH bound to: 1 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter RAM_PIPELINE bound to: 1 - type: integer 
+	Parameter FRAME_FIFO bound to: 1 - type: integer 
+	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1 
+	Parameter USER_BAD_FRAME_MASK bound to: 1'b1 
+	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer 
+	Parameter DROP_BAD_FRAME bound to: 1 - type: integer 
+	Parameter DROP_WHEN_FULL bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo__parameterized0' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
+	Parameter DEPTH bound to: 4096 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter KEEP_WIDTH bound to: 1 - type: integer 
+	Parameter LAST_ENABLE bound to: 1 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter ID_WIDTH bound to: 8 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_WIDTH bound to: 8 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter RAM_PIPELINE bound to: 1 - type: integer 
+	Parameter OUTPUT_FIFO_ENABLE bound to: 0 - type: integer 
+	Parameter FRAME_FIFO bound to: 1 - type: integer 
+	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1 
+	Parameter USER_BAD_FRAME_MASK bound to: 1'b1 
+	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer 
+	Parameter DROP_BAD_FRAME bound to: 1 - type: integer 
+	Parameter DROP_WHEN_FULL bound to: 1 - type: integer 
+	Parameter MARK_WHEN_FULL bound to: 0 - type: integer 
+	Parameter PAUSE_ENABLE bound to: 0 - type: integer 
+	Parameter FRAME_PAUSE bound to: 1 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo__parameterized0' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo_adapter__parameterized0' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
+WARNING: [Synth 8-7071] port 's_pause_req' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 's_pause_ack' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 'm_pause_req' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 'm_pause_ack' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 's_status_depth' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 's_status_depth_commit' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 'm_status_depth' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 'm_status_depth_commit' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7023] instance 'rx_fifo' of module 'axis_async_fifo_adapter' has 34 connections declared, but only 26 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+INFO: [Synth 8-6155] done synthesizing module 'eth_mac_1g_rgmii_fifo' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:34]
+WARNING: [Synth 8-7071] port 'tx_axis_tkeep' of module 'eth_mac_1g_rgmii_fifo' is unconnected for instance 'eth_mac_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:283]
+WARNING: [Synth 8-7071] port 'rx_axis_tkeep' of module 'eth_mac_1g_rgmii_fifo' is unconnected for instance 'eth_mac_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:283]
+WARNING: [Synth 8-7071] port 'tx_error_underflow' of module 'eth_mac_1g_rgmii_fifo' is unconnected for instance 'eth_mac_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:283]
+WARNING: [Synth 8-7023] instance 'eth_mac_inst' of module 'eth_mac_1g_rgmii_fifo' has 36 connections declared, but only 33 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:283]
+INFO: [Synth 8-6157] synthesizing module 'eth_axis_rx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'eth_axis_rx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:34]
+WARNING: [Synth 8-7071] port 's_axis_tkeep' of module 'eth_axis_rx' is unconnected for instance 'eth_axis_rx_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:325]
+WARNING: [Synth 8-7071] port 'm_eth_payload_axis_tkeep' of module 'eth_axis_rx' is unconnected for instance 'eth_axis_rx_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:325]
+WARNING: [Synth 8-7023] instance 'eth_axis_rx_inst' of module 'eth_axis_rx' has 21 connections declared, but only 19 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:325]
+INFO: [Synth 8-6157] synthesizing module 'eth_axis_tx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'eth_axis_tx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:34]
+WARNING: [Synth 8-7071] port 's_eth_payload_axis_tkeep' of module 'eth_axis_tx' is unconnected for instance 'eth_axis_tx_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:351]
+WARNING: [Synth 8-7071] port 'm_axis_tkeep' of module 'eth_axis_tx' is unconnected for instance 'eth_axis_tx_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:351]
+WARNING: [Synth 8-7023] instance 'eth_axis_tx_inst' of module 'eth_axis_tx' has 20 connections declared, but only 18 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:351]
+INFO: [Synth 8-6157] synthesizing module 'udp_complete' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_complete.v:34]
+INFO: [Synth 8-6157] synthesizing module 'ip_arb_mux' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:34]
+	Parameter S_COUNT bound to: 2 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer 
+	Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'arbiter' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/arbiter.v:34]
+	Parameter PORTS bound to: 2 - type: integer 
+	Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer 
+	Parameter ARB_BLOCK bound to: 1 - type: integer 
+	Parameter ARB_BLOCK_ACK bound to: 1 - type: integer 
+	Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'priority_encoder' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:34]
+	Parameter WIDTH bound to: 2 - type: integer 
+	Parameter LSB_HIGH_PRIORITY bound to: 1 - type: integer 
+WARNING: [Synth 8-693] zero replication count - replication ignored [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:51]
+INFO: [Synth 8-6155] done synthesizing module 'priority_encoder' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'arbiter' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/arbiter.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'ip_arb_mux' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:34]
+INFO: [Synth 8-6157] synthesizing module 'ip_complete' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v:34]
+	Parameter ARP_CACHE_ADDR_WIDTH bound to: 9 - type: integer 
+	Parameter ARP_REQUEST_RETRY_COUNT bound to: 4 - type: integer 
+	Parameter ARP_REQUEST_RETRY_INTERVAL bound to: 250000000 - type: integer 
+	Parameter ARP_REQUEST_TIMEOUT bound to: -544967296 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'eth_arb_mux' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:34]
+	Parameter S_COUNT bound to: 2 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer 
+	Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'eth_arb_mux' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:34]
+INFO: [Synth 8-6157] synthesizing module 'ip' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip.v:34]
+INFO: [Synth 8-6157] synthesizing module 'ip_eth_rx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_rx.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_rx.v:311]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_rx.v:279]
+INFO: [Synth 8-6155] done synthesizing module 'ip_eth_rx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_rx.v:34]
+INFO: [Synth 8-6157] synthesizing module 'ip_eth_tx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_tx.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_tx.v:237]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_tx.v:209]
+INFO: [Synth 8-6155] done synthesizing module 'ip_eth_tx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_tx.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip.v:274]
+INFO: [Synth 8-6155] done synthesizing module 'ip' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip.v:34]
+INFO: [Synth 8-6157] synthesizing module 'arp' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp.v:34]
+	Parameter CACHE_ADDR_WIDTH bound to: 9 - type: integer 
+	Parameter REQUEST_RETRY_COUNT bound to: 4 - type: integer 
+	Parameter REQUEST_RETRY_INTERVAL bound to: 250000000 - type: integer 
+	Parameter REQUEST_TIMEOUT bound to: -544967296 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'arp_eth_rx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:34]
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 1'b0 
+	Parameter KEEP_WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'arp_eth_rx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:34]
+INFO: [Synth 8-6157] synthesizing module 'arp_eth_tx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:34]
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 1'b0 
+	Parameter KEEP_WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'arp_eth_tx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:34]
+INFO: [Synth 8-6157] synthesizing module 'arp_cache' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_cache.v:34]
+	Parameter CACHE_ADDR_WIDTH bound to: 9 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized0' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v:34]
+	Parameter LFSR_WIDTH bound to: 32 - type: integer 
+	Parameter LFSR_POLY bound to: 79764919 - type: integer 
+	Parameter LFSR_CONFIG bound to: GALOIS - type: string 
+	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer 
+	Parameter REVERSE bound to: 1 - type: integer 
+	Parameter DATA_WIDTH bound to: 32 - type: integer 
+	Parameter STYLE bound to: AUTO - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized0' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'arp_cache' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_cache.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'arp' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp.v:34]
+WARNING: [Synth 8-7071] port 's_eth_payload_axis_tkeep' of module 'arp' is unconnected for instance 'arp_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v:401]
+WARNING: [Synth 8-7071] port 'm_eth_payload_axis_tkeep' of module 'arp' is unconnected for instance 'arp_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v:401]
+WARNING: [Synth 8-7023] instance 'arp_inst' of module 'arp' has 36 connections declared, but only 34 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v:401]
+INFO: [Synth 8-6155] done synthesizing module 'ip_complete' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v:34]
+INFO: [Synth 8-6157] synthesizing module 'udp' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp.v:34]
+	Parameter CHECKSUM_GEN_ENABLE bound to: 1 - type: integer 
+	Parameter CHECKSUM_PAYLOAD_FIFO_DEPTH bound to: 2048 - type: integer 
+	Parameter CHECKSUM_HEADER_FIFO_DEPTH bound to: 8 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'udp_checksum_gen' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:34]
+	Parameter PAYLOAD_FIFO_DEPTH bound to: 2048 - type: integer 
+	Parameter HEADER_FIFO_DEPTH bound to: 8 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'axis_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
+	Parameter DEPTH bound to: 2048 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter LAST_ENABLE bound to: 1 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter FRAME_FIFO bound to: 0 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'axis_fifo' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
+WARNING: [Synth 8-7071] port 'pause_req' of module 'axis_fifo' is unconnected for instance 'payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:214]
+WARNING: [Synth 8-7071] port 'pause_ack' of module 'axis_fifo' is unconnected for instance 'payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:214]
+WARNING: [Synth 8-7071] port 'status_depth' of module 'axis_fifo' is unconnected for instance 'payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:214]
+WARNING: [Synth 8-7071] port 'status_depth_commit' of module 'axis_fifo' is unconnected for instance 'payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:214]
+WARNING: [Synth 8-7023] instance 'payload_fifo' of module 'axis_fifo' has 25 connections declared, but only 21 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:214]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:450]
+INFO: [Synth 8-6155] done synthesizing module 'udp_checksum_gen' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:34]
+INFO: [Synth 8-6157] synthesizing module 'udp_ip_rx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_rx.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_rx.v:265]
+INFO: [Synth 8-6155] done synthesizing module 'udp_ip_rx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_rx.v:34]
+INFO: [Synth 8-6157] synthesizing module 'udp_ip_tx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_tx.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_tx.v:240]
+INFO: [Synth 8-6155] done synthesizing module 'udp_ip_tx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_tx.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'udp' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'udp_complete' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_complete.v:34]
+INFO: [Synth 8-6157] synthesizing module 'axis_fifo__parameterized0' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
+	Parameter DEPTH bound to: 8192 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter FRAME_FIFO bound to: 0 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'axis_fifo__parameterized0' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
+WARNING: [Synth 8-7071] port 'pause_req' of module 'axis_fifo' is unconnected for instance 'udp_payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:517]
+WARNING: [Synth 8-7071] port 'pause_ack' of module 'axis_fifo' is unconnected for instance 'udp_payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:517]
+INFO: [Common 17-14] Message 'Synth 8-7071' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+WARNING: [Synth 8-7023] instance 'udp_payload_fifo' of module 'axis_fifo' has 25 connections declared, but only 21 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:517]
+INFO: [Synth 8-6155] done synthesizing module 'fpga_core' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'fpga' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga.v:10]
+WARNING: [Synth 8-6014] Unused sequential element ptp_ts_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_rx.v:259]
+WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:413]
+WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_tag_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:414]
+WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_valid_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:415]
+WARNING: [Synth 8-6014] Unused sequential element wr_ptr_temp_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:423]
+WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:436]
+WARNING: [Synth 8-6014] Unused sequential element rd_ptr_temp_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:670]
+WARNING: [Synth 8-6014] Unused sequential element wr_ptr_temp_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:423]
+WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:436]
+WARNING: [Synth 8-6014] Unused sequential element rd_ptr_temp_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:670]
+WARNING: [Synth 8-6014] Unused sequential element save_axis_tdata_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:290]
+WARNING: [Synth 8-6014] Unused sequential element save_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:291]
+WARNING: [Synth 8-6014] Unused sequential element save_axis_tuser_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:292]
+WARNING: [Synth 8-6014] Unused sequential element save_axis_tlast_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:296]
+WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:379]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:384]
+WARNING: [Synth 8-6014] Unused sequential element save_eth_payload_axis_tdata_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:297]
+WARNING: [Synth 8-6014] Unused sequential element save_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:298]
+WARNING: [Synth 8-6014] Unused sequential element save_eth_payload_axis_tuser_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:299]
+WARNING: [Synth 8-6014] Unused sequential element save_eth_payload_axis_tlast_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:303]
+WARNING: [Synth 8-6014] Unused sequential element m_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:383]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:388]
+WARNING: [Synth 8-6014] Unused sequential element m_ip_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:374]
+WARNING: [Synth 8-6014] Unused sequential element m_ip_payload_axis_tid_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:376]
+WARNING: [Synth 8-6014] Unused sequential element m_ip_payload_axis_tdest_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:377]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_ip_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:381]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_ip_payload_axis_tid_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:383]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_ip_payload_axis_tdest_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:384]
+WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:283]
+WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tid_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:285]
+WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tdest_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:286]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:290]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tid_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:292]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tdest_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:293]
+WARNING: [Synth 8-6014] Unused sequential element busy_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:176]
+WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:342]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:347]
+WARNING: [Synth 8-6014] Unused sequential element busy_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:165]
+WARNING: [Synth 8-6014] Unused sequential element s_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:267]
+WARNING: [Synth 8-6014] Unused sequential element drop_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:311]
+WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:358]
+WARNING: [Synth 8-6014] Unused sequential element bad_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:256]
+WARNING: [Synth 8-6014] Unused sequential element good_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:257]
+WARNING: [Synth 8-6014] Unused sequential element s_udp_payload_axis_tready_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:521]
+WARNING: [Synth 8-6014] Unused sequential element s_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:267]
+WARNING: [Synth 8-6014] Unused sequential element drop_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:311]
+WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:358]
+WARNING: [Synth 8-6014] Unused sequential element bad_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:256]
+WARNING: [Synth 8-6014] Unused sequential element good_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:257]
+WARNING: [Synth 8-7129] Port s_axis_tkeep[0] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[7] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[6] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[5] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[4] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[3] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[2] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[1] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[0] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[7] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[6] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[5] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[4] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[3] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[2] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[1] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[0] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port pause_req in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tkeep[0] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[7] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[6] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[5] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[4] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[3] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[2] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[1] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[0] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[7] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[6] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[5] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[4] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[3] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[2] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[1] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[0] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port pause_req in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[15] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[14] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[13] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[12] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[11] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[10] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[9] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[8] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[7] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[6] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[5] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[4] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[3] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[2] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[1] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[0] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[15] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[14] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[13] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[12] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[11] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[10] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[9] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[8] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[7] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[6] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[5] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[4] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[3] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[2] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[1] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[0] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_eth_payload_axis_tkeep[0] in module arp_eth_rx is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[31] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[30] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[29] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[28] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[27] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[26] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[25] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[24] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[23] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[22] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[21] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[20] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[19] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[18] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[17] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[16] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[15] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[14] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[13] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[12] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[11] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[10] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[9] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[8] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[7] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[6] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[5] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[4] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[3] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[2] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[1] in module ip is either unconnected or has no load
+INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 2375.047 ; gain = 681.449 ; free physical = 49829 ; free virtual = 54836
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2380.984 ; gain = 687.387 ; free physical = 49829 ; free virtual = 54836
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2380.984 ; gain = 687.387 ; free physical = 49829 ; free virtual = 54836
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2383.953 ; gain = 0.000 ; free physical = 49829 ; free virtual = 54836
+INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+Finished Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc]
+Finished Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]
+Inserting timing constraints for rgmii_phy_if instance core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst
+INFO: [Timing 38-2] Deriving generated clocks [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl:23]
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]
+Inserting timing constraints for eth_mac_1g_rgmii instance core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
+Inserting timing constraints for ethernet MAC with FIFO instance core_inst/eth_mac_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
+Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_inst/rx_fifo/fifo_inst
+Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_inst/tx_fifo/fifo_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
+Inserting timing constraints for sync_reset instance sync_reset_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2525.734 ; gain = 0.000 ; free physical = 49827 ; free virtual = 54834
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 2 instances were transformed.
+  IBUFGDS => IBUFDS: 1 instance 
+  MMCME2_BASE => MMCME2_ADV: 1 instance 
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2525.734 ; gain = 0.000 ; free physical = 49827 ; free virtual = 54834
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49804 ; free virtual = 54811
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tfbg484-2
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49804 ; free virtual = 54811
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/\oddr[0].oddr_inst . (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/tx_mii_select_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/tx_mii_select_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_1_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_1_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_2_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_2_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_3_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_3_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_4_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_4_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/\tx_sync_reg_1_reg[0] . (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/\tx_sync_reg_2_reg[0] . (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/\tx_sync_reg_3_reg[0] . (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/\tx_sync_reg_4_reg[0] . (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_rst_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_rst_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_ack_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_ack_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/overflow_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/overflow_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/overflow_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/bad_frame_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/bad_frame_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/bad_frame_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/good_frame_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/good_frame_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/good_frame_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/m_rst_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/m_rst_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_update_ack_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_update_ack_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_update_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_update_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_update_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/overflow_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/overflow_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/overflow_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/bad_frame_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/bad_frame_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/bad_frame_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/good_frame_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/good_frame_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/good_frame_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for sync_reset_inst/sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl, line 23).
+Applied set_property ASYNC_REG = true for sync_reset_inst/sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl, line 23).
+Applied set_property ASYNC_REG = true for sync_reset_inst/sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl, line 23).
+Applied set_property ASYNC_REG = true for sync_reset_inst/sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl, line 23).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49804 ; free virtual = 54811
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'axis_gmii_rx'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'axis_gmii_tx'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'ip_eth_rx'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'ip_eth_tx'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'ip'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'udp_ip_rx'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'udp_ip_tx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                              001 |                              000
+           STATE_PAYLOAD |                              010 |                              001
+         STATE_WAIT_LAST |                              100 |                              010
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'one-hot' in module 'axis_gmii_rx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                              000 |                              000
+          STATE_PREAMBLE |                              001 |                              001
+           STATE_PAYLOAD |                              010 |                              010
+              STATE_LAST |                              011 |                              011
+               STATE_PAD |                              100 |                              100
+               STATE_FCS |                              101 |                              101
+               STATE_IFG |                              110 |                              110
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'axis_gmii_tx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                              000 |                              000
+       STATE_READ_HEADER |                              001 |                              001
+         STATE_WAIT_LAST |                              010 |                              100
+      STATE_READ_PAYLOAD |                              011 |                              010
+ STATE_READ_PAYLOAD_LAST |                              100 |                              011
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'ip_eth_rx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                             0001 |                              000
+      STATE_WRITE_HEADER |                             0010 |                              001
+     STATE_WRITE_PAYLOAD |                             0100 |                              010
+STATE_WRITE_PAYLOAD_LAST |                             1000 |                              011
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'one-hot' in module 'ip_eth_tx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                               00 |                               00
+         STATE_ARP_QUERY |                               01 |                               01
+       STATE_WAIT_PACKET |                               10 |                               10
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'ip'
+WARNING: [Synth 8-6430] The Block RAM "arp_cache:/ip_addr_mem_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision 
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                               00 |                              000
+       STATE_READ_HEADER |                               01 |                              001
+      STATE_READ_PAYLOAD |                               10 |                              010
+ STATE_READ_PAYLOAD_LAST |                               11 |                              011
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'udp_ip_rx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                               00 |                              000
+      STATE_WRITE_HEADER |                               01 |                              001
+     STATE_WRITE_PAYLOAD |                               10 |                              010
+STATE_WRITE_PAYLOAD_LAST |                               11 |                              011
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'udp_ip_tx'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49818 ; free virtual = 54827
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input   36 Bit       Adders := 1     
+	   2 Input   32 Bit       Adders := 1     
+	   3 Input   32 Bit       Adders := 3     
+	   2 Input   17 Bit       Adders := 12    
+	   2 Input   16 Bit       Adders := 13    
+	   3 Input   14 Bit       Adders := 1     
+	   2 Input   14 Bit       Adders := 1     
+	   2 Input   13 Bit       Adders := 4     
+	   3 Input   13 Bit       Adders := 8     
+	   3 Input   12 Bit       Adders := 1     
+	   2 Input   12 Bit       Adders := 1     
+	   2 Input    9 Bit       Adders := 1     
+	   2 Input    8 Bit       Adders := 1     
+	   2 Input    7 Bit       Adders := 1     
+	   2 Input    6 Bit       Adders := 5     
+	   2 Input    5 Bit       Adders := 2     
+	   2 Input    4 Bit       Adders := 4     
+	   2 Input    3 Bit       Adders := 3     
+	   2 Input    2 Bit       Adders := 1     
++---XORs : 
+	   2 Input     32 Bit         XORs := 1     
+	   2 Input     14 Bit         XORs := 1     
+	   2 Input     13 Bit         XORs := 10    
+	   2 Input     12 Bit         XORs := 1     
+	   2 Input      2 Bit         XORs := 1     
+	   2 Input      1 Bit         XORs := 167   
+	   3 Input      1 Bit         XORs := 44    
+	   4 Input      1 Bit         XORs := 20    
+	   5 Input      1 Bit         XORs := 20    
+	   6 Input      1 Bit         XORs := 20    
+	   8 Input      1 Bit         XORs := 14    
+	   7 Input      1 Bit         XORs := 12    
+	   9 Input      1 Bit         XORs := 10    
+	  10 Input      1 Bit         XORs := 6     
+	  12 Input      1 Bit         XORs := 6     
+	  14 Input      1 Bit         XORs := 4     
+	  17 Input      1 Bit         XORs := 8     
+	  13 Input      1 Bit         XORs := 4     
+	  16 Input      1 Bit         XORs := 12    
+	  20 Input      1 Bit         XORs := 8     
+	  21 Input      1 Bit         XORs := 2     
+	  15 Input      1 Bit         XORs := 10    
+	  19 Input      1 Bit         XORs := 2     
+	  11 Input      1 Bit         XORs := 4     
+	  24 Input      1 Bit         XORs := 2     
+	  22 Input      1 Bit         XORs := 4     
+	  23 Input      1 Bit         XORs := 2     
+	  18 Input      1 Bit         XORs := 4     
++---XORs : 
+	               13 Bit    Wide XORs := 48    
++---Registers : 
+	               48 Bit    Registers := 32    
+	               36 Bit    Registers := 1     
+	               32 Bit    Registers := 22    
+	               16 Bit    Registers := 52    
+	               14 Bit    Registers := 1     
+	               13 Bit    Registers := 36    
+	               12 Bit    Registers := 1     
+	               10 Bit    Registers := 8     
+	                9 Bit    Registers := 2     
+	                8 Bit    Registers := 44    
+	                7 Bit    Registers := 1     
+	                6 Bit    Registers := 11    
+	                5 Bit    Registers := 2     
+	                4 Bit    Registers := 18    
+	                3 Bit    Registers := 11    
+	                2 Bit    Registers := 26    
+	                1 Bit    Registers := 256   
++---RAMs : 
+	              80K Bit	(8192 X 10 bit)          RAMs := 1     
+	              40K Bit	(4096 X 10 bit)          RAMs := 2     
+	              24K Bit	(512 X 48 bit)          RAMs := 1     
+	              20K Bit	(2048 X 10 bit)          RAMs := 1     
+	              16K Bit	(512 X 32 bit)          RAMs := 1     
+	              512 Bit	(512 X 1 bit)          RAMs := 1     
+	              384 Bit	(8 X 48 bit)          RAMs := 2     
+	              256 Bit	(8 X 32 bit)          RAMs := 2     
+	              128 Bit	(8 X 16 bit)          RAMs := 7     
+	              104 Bit	(8 X 13 bit)          RAMs := 1     
+	               64 Bit	(8 X 8 bit)          RAMs := 1     
+	               48 Bit	(8 X 6 bit)          RAMs := 1     
+	               32 Bit	(8 X 4 bit)          RAMs := 2     
+	               24 Bit	(8 X 3 bit)          RAMs := 1     
+	               16 Bit	(8 X 2 bit)          RAMs := 1     
++---Muxes : 
+	   2 Input   48 Bit        Muxes := 21    
+	   6 Input   36 Bit        Muxes := 1     
+	   3 Input   36 Bit        Muxes := 1     
+	   2 Input   36 Bit        Muxes := 1     
+	   2 Input   32 Bit        Muxes := 14    
+	   7 Input   32 Bit        Muxes := 1     
+	   5 Input   28 Bit        Muxes := 1     
+	   2 Input   16 Bit        Muxes := 14    
+	   5 Input   16 Bit        Muxes := 2     
+	  21 Input   16 Bit        Muxes := 1     
+	   4 Input   16 Bit        Muxes := 3     
+	   7 Input   16 Bit        Muxes := 3     
+	   2 Input   13 Bit        Muxes := 25    
+	   2 Input    9 Bit        Muxes := 1     
+	   2 Input    8 Bit        Muxes := 76    
+	   3 Input    8 Bit        Muxes := 1     
+	   4 Input    8 Bit        Muxes := 4     
+	   7 Input    8 Bit        Muxes := 3     
+	   5 Input    8 Bit        Muxes := 1     
+	   3 Input    7 Bit        Muxes := 1     
+	   2 Input    6 Bit        Muxes := 6     
+	   7 Input    6 Bit        Muxes := 1     
+	   5 Input    6 Bit        Muxes := 1     
+	   4 Input    6 Bit        Muxes := 1     
+	   6 Input    6 Bit        Muxes := 1     
+	   2 Input    5 Bit        Muxes := 4     
+	   2 Input    4 Bit        Muxes := 18    
+	   4 Input    4 Bit        Muxes := 1     
+	  21 Input    4 Bit        Muxes := 1     
+	   3 Input    3 Bit        Muxes := 8     
+	   2 Input    3 Bit        Muxes := 14    
+	   7 Input    3 Bit        Muxes := 3     
+	  21 Input    3 Bit        Muxes := 1     
+	   5 Input    3 Bit        Muxes := 1     
+	  38 Input    3 Bit        Muxes := 1     
+	   4 Input    3 Bit        Muxes := 5     
+	   3 Input    2 Bit        Muxes := 6     
+	   2 Input    2 Bit        Muxes := 46    
+	   4 Input    2 Bit        Muxes := 6     
+	  22 Input    2 Bit        Muxes := 1     
+	  10 Input    2 Bit        Muxes := 1     
+	   8 Input    2 Bit        Muxes := 3     
+	   2 Input    1 Bit        Muxes := 389   
+	   3 Input    1 Bit        Muxes := 16    
+	   7 Input    1 Bit        Muxes := 22    
+	  21 Input    1 Bit        Muxes := 25    
+	   5 Input    1 Bit        Muxes := 34    
+	   4 Input    1 Bit        Muxes := 43    
+	   8 Input    1 Bit        Muxes := 11    
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance. 
+RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance. 
+WARNING: [Synth 8-6430] The Block RAM "\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst/ip_addr_mem_reg " may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision 
+RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance. 
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:02 ; elapsed = 00:01:03 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49776 ; free virtual = 54797
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+
+ROM: Preliminary Mapping Report
++------------+-------------------------------------+---------------+----------------+
+|Module Name | RTL Object                          | Depth x Width | Implemented As | 
++------------+-------------------------------------+---------------+----------------+
+|ip_complete | ip_inst/ip_eth_tx_inst/hdr_sum_next | 32x1          | LUT            | 
++------------+-------------------------------------+---------------+----------------+
+
+
+Block RAM: Preliminary Mapping Report (see note below)
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+|Module Name                                                              | RTL Object                                       | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+|fpga                                                                     | core_inst/eth_mac_inst/tx_fifo/fifo_inst/mem_reg | 4 K x 10(READ_FIRST)   | W |   | 4 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      | 
+|fpga                                                                     | core_inst/eth_mac_inst/rx_fifo/fifo_inst/mem_reg | 4 K x 10(NO_CHANGE)    | W |   | 4 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      | 
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | ip_addr_mem_reg                                  | 512 x 32(READ_FIRST)   | W |   | 512 x 32(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      | 
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | mac_addr_mem_reg                                 | 512 x 48(READ_FIRST)   | W |   | 512 x 48(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/payload_fifo/mem_reg       | 2 K x 10(READ_FIRST)   | W |   | 2 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
+|fpga                                                                     | core_inst/udp_payload_fifo/mem_reg               | 8 K x 10(READ_FIRST)   | W |   | 8 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 2      | 
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+
+Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 
+
+Distributed RAM: Preliminary Mapping Report (see note below)
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+|Module Name                                                              | RTL Object                                    | Inference | Size (Depth x Width) | Primitives     | 
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | valid_mem_reg                                 | Implied   | 512 x 1              | RAM128X1D x 4  | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_length_mem_reg      | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_ttl_mem_reg          | Implied   | 8 x 8                | RAM32M x 2     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_source_ip_mem_reg    | Implied   | 8 x 32               | RAM32M x 6     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_dest_ip_mem_reg      | Implied   | 8 x 32               | RAM32M x 6     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_source_port_mem_reg | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_dest_port_mem_reg   | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_checksum_mem_reg    | Implied   | 8 x 16               | RAM32M x 3     | 
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+
+Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl. [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
+WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl. [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:10 ; elapsed = 00:01:11 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49746 ; free virtual = 54767
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:01:14 ; elapsed = 00:01:15 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49703 ; free virtual = 54724
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+
+Block RAM: Final Mapping Report
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+|Module Name                                                              | RTL Object                                       | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+|fpga                                                                     | core_inst/eth_mac_inst/tx_fifo/fifo_inst/mem_reg | 4 K x 10(READ_FIRST)   | W |   | 4 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      | 
+|fpga                                                                     | core_inst/eth_mac_inst/rx_fifo/fifo_inst/mem_reg | 4 K x 10(NO_CHANGE)    | W |   | 4 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      | 
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | ip_addr_mem_reg                                  | 512 x 32(READ_FIRST)   | W |   | 512 x 32(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      | 
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | mac_addr_mem_reg                                 | 512 x 48(READ_FIRST)   | W |   | 512 x 48(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/payload_fifo/mem_reg       | 2 K x 10(READ_FIRST)   | W |   | 2 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
+|fpga                                                                     | core_inst/udp_payload_fifo/mem_reg               | 8 K x 10(READ_FIRST)   | W |   | 8 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 2      | 
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+
+
+Distributed RAM: Final Mapping Report
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+|Module Name                                                              | RTL Object                                    | Inference | Size (Depth x Width) | Primitives     | 
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | valid_mem_reg                                 | Implied   | 512 x 1              | RAM128X1D x 4  | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_length_mem_reg      | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_ttl_mem_reg          | Implied   | 8 x 8                | RAM32M x 2     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_source_ip_mem_reg    | Implied   | 8 x 32               | RAM32M x 6     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_dest_ip_mem_reg      | Implied   | 8 x 32               | RAM32M x 6     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_source_port_mem_reg | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_dest_port_mem_reg   | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_checksum_mem_reg    | Implied   | 8 x 16               | RAM32M x 3     | 
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+INFO: [Synth 8-7052] The timing for the instance core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/ip_addr_mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
+INFO: [Synth 8-7052] The timing for the instance core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/mac_addr_mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49717 ; free virtual = 54738
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:01:22 ; elapsed = 00:01:23 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:01:22 ; elapsed = 00:01:23 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+------------+------+
+|      |Cell        |Count |
++------+------------+------+
+|1     |BUFG        |     3|
+|2     |BUFIO       |     1|
+|3     |BUFR        |     1|
+|4     |CARRY4      |   200|
+|5     |IDDR        |     5|
+|6     |IDELAYCTRL  |     1|
+|7     |IDELAYE2    |     5|
+|8     |LUT1        |   173|
+|9     |LUT2        |   265|
+|10    |LUT3        |   403|
+|11    |LUT4        |   241|
+|12    |LUT5        |   351|
+|13    |LUT6        |   648|
+|14    |MMCME2_BASE |     1|
+|15    |MUXF7       |     9|
+|16    |ODDR        |     6|
+|17    |RAM128X1D   |     4|
+|18    |RAM32M      |    19|
+|19    |RAMB18E1    |     4|
+|23    |RAMB36E1    |     6|
+|28    |FDPE        |    14|
+|29    |FDRE        |  2581|
+|30    |FDSE        |   166|
+|31    |IBUF        |     7|
+|32    |IBUFGDS     |     1|
+|33    |OBUF        |     7|
++------+------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 110 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 2525.734 ; gain = 687.387 ; free physical = 49754 ; free virtual = 54775
+Synthesis Optimization Complete : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2525.734 ; gain = 0.000 ; free physical = 50047 ; free virtual = 55068
+INFO: [Netlist 29-17] Analyzing 261 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2525.734 ; gain = 0.000 ; free physical = 50051 ; free virtual = 55072
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 25 instances were transformed.
+  IBUFGDS => IBUFDS: 1 instance 
+  MMCME2_BASE => MMCME2_ADV: 1 instance 
+  RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 4 instances
+  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 19 instances
+
+Synth Design complete | Checksum: e689d0a8
+INFO: [Common 17-83] Releasing license: Synthesis
+152 Infos, 298 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:01:34 ; elapsed = 00:01:31 . Memory (MB): peak = 2525.734 ; gain = 1189.949 ; free physical = 50051 ; free virtual = 55072
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2021.381; main = 1692.642; forked = 352.937
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3471.828; main = 2525.738; forked = 978.105
+INFO: [Common 17-1381] The checkpoint '/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file fpga_utilization_synth.rpt -pb fpga_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Jan  8 11:24:30 2025...
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga_utilization_synth.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga_utilization_synth.pb
new file mode 100644
index 000000000..f0d9c84c1
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga_utilization_synth.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga_utilization_synth.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga_utilization_synth.rpt
new file mode 100644
index 000000000..9b84e8f39
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga_utilization_synth.rpt
@@ -0,0 +1,207 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:24:30 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_utilization -file fpga_utilization_synth.rpt -pb fpga_utilization_synth.pb
+| Design       : fpga
+| Device       : xc7a200tfbg484-2
+| Speed File   : -2
+| Design State : Synthesized
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++----------------------------+------+-------+------------+-----------+-------+
+|          Site Type         | Used | Fixed | Prohibited | Available | Util% |
++----------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs*                | 1858 |     0 |          0 |    134600 |  1.38 |
+|   LUT as Logic             | 1766 |     0 |          0 |    134600 |  1.31 |
+|   LUT as Memory            |   92 |     0 |          0 |     46200 |  0.20 |
+|     LUT as Distributed RAM |   92 |     0 |            |           |       |
+|     LUT as Shift Register  |    0 |     0 |            |           |       |
+| Slice Registers            | 2761 |     0 |          0 |    269200 |  1.03 |
+|   Register as Flip Flop    | 2761 |     0 |          0 |    269200 |  1.03 |
+|   Register as Latch        |    0 |     0 |          0 |    269200 |  0.00 |
+| F7 Muxes                   |   17 |     0 |          0 |     67300 |  0.03 |
+| F8 Muxes                   |    0 |     0 |          0 |     33650 |  0.00 |
++----------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 14    |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 166   |          Yes |         Set |            - |
+| 2581  |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++-------------------+------+-------+------------+-----------+-------+
+|     Site Type     | Used | Fixed | Prohibited | Available | Util% |
++-------------------+------+-------+------------+-----------+-------+
+| Block RAM Tile    |    8 |     0 |          0 |       365 |  2.19 |
+|   RAMB36/FIFO*    |    6 |     0 |          0 |       365 |  1.64 |
+|     RAMB36E1 only |    6 |       |            |           |       |
+|   RAMB18          |    4 |     0 |          0 |       730 |  0.55 |
+|     RAMB18E1 only |    4 |       |            |           |       |
++-------------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |       740 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |   16 |     0 |          0 |       285 |  5.61 |
+| Bonded IPADs                |    0 |     0 |          0 |        14 |  0.00 |
+| Bonded OPADs                |    0 |     0 |          0 |         8 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |        10 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |        10 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |        40 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |        40 |  0.00 |
+| IDELAYCTRL                  |    1 |     0 |          0 |        10 | 10.00 |
+| IBUFDS                      |    1 |     0 |          0 |       274 |  0.36 |
+| GTPE2_CHANNEL               |    0 |     0 |          0 |         4 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |        40 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |        40 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    5 |     0 |          0 |       500 |  1.00 |
+|   IDELAYE2 only             |    5 |     0 |            |           |       |
+| IBUFDS_GTE2                 |    0 |     0 |          0 |         2 |  0.00 |
+| ILOGIC                      |    5 |     0 |          0 |       285 |  1.75 |
+|   IDDR                      |    5 |       |            |           |       |
+| OLOGIC                      |    6 |     0 |          0 |       285 |  2.11 |
+|   ODDR                      |    6 |       |            |           |       |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++--------------+------+-------+------------+-----------+-------+
+|   Site Type  | Used | Fixed | Prohibited | Available | Util% |
++--------------+------+-------+------------+-----------+-------+
+| BUFGCTRL     |    3 |     0 |          0 |        32 |  9.38 |
+| BUFIO        |    1 |     0 |          0 |        40 |  2.50 |
+|   BUFIO only |    1 |     0 |            |           |       |
+| MMCME2_ADV   |    1 |     0 |          0 |        10 | 10.00 |
+| PLLE2_ADV    |    0 |     0 |          0 |        10 |  0.00 |
+| BUFMRCE      |    0 |     0 |          0 |        20 |  0.00 |
+| BUFHCE       |    0 |     0 |          0 |       120 |  0.00 |
+| BUFR         |    1 |     0 |          0 |        40 |  2.50 |
++--------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |          0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++------------+------+---------------------+
+|  Ref Name  | Used | Functional Category |
++------------+------+---------------------+
+| FDRE       | 2581 |        Flop & Latch |
+| LUT6       |  648 |                 LUT |
+| LUT3       |  403 |                 LUT |
+| LUT5       |  351 |                 LUT |
+| LUT2       |  265 |                 LUT |
+| LUT4       |  241 |                 LUT |
+| CARRY4     |  200 |          CarryLogic |
+| LUT1       |  173 |                 LUT |
+| FDSE       |  166 |        Flop & Latch |
+| RAMD32     |  114 |  Distributed Memory |
+| RAMS32     |   38 |  Distributed Memory |
+| MUXF7      |   17 |               MuxFx |
+| RAMD64E    |   16 |  Distributed Memory |
+| FDPE       |   14 |        Flop & Latch |
+| OBUF       |    7 |                  IO |
+| IBUF       |    7 |                  IO |
+| RAMB36E1   |    6 |        Block Memory |
+| ODDR       |    6 |                  IO |
+| IDELAYE2   |    5 |                  IO |
+| IDDR       |    5 |                  IO |
+| RAMB18E1   |    4 |        Block Memory |
+| BUFG       |    3 |               Clock |
+| MMCME2_ADV |    1 |               Clock |
+| IDELAYCTRL |    1 |                  IO |
+| IBUFDS     |    1 |                  IO |
+| BUFR       |    1 |               Clock |
+| BUFIO      |    1 |               Clock |
++------------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/gen_run.xml b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/gen_run.xml
new file mode 100644
index 000000000..df3bf5bbc
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/gen_run.xml
@@ -0,0 +1,348 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a200tfbg484-2" LaunchTime="1736315556">
+  <File Type="RDS-DCP" Name="fpga.dcp"/>
+  <File Type="RDS-UTIL-PB" Name="fpga_utilization_synth.pb"/>
+  <File Type="PA-TCL" Name="fpga.tcl"/>
+  <File Type="RDS-UTIL" Name="fpga_utilization_synth.rpt"/>
+  <File Type="REPORTS-TCL" Name="fpga_reports.tcl"/>
+  <File Type="RDS-RDS" Name="fpga.vds"/>
+  <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+    <Filter Type="Srcs"/>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/arbiter.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/arp.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/arp_cache.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/arp_eth_rx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/arp_eth_tx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/axis_async_fifo.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/axis_fifo.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/axis_gmii_rx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/axis_gmii_tx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_arb_mux.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_axis_rx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_axis_tx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_mac_1g.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_mac_1g_rgmii.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/eth_mac_1g_rgmii_fifo.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../rtl/fpga_core.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/iddr.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ip.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ip_arb_mux.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ip_complete.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ip_eth_rx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ip_eth_tx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/lfsr.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/oddr.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/priority_encoder.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/rgmii_phy_if.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ssio_ddr_in.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/sync_reset.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/udp.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/udp_checksum_gen.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/udp_complete.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/udp_ip_rx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/udp_ip_tx.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../rtl/fpga.v">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/defines.v">
+      <FileInfo>
+        <Attr Name="AutoDisabled" Val="1"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../rtl/sync_signal.v">
+      <FileInfo>
+        <Attr Name="AutoDisabled" Val="1"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/rtl/ssio_ddr_out.v">
+      <FileInfo>
+        <Attr Name="AutoDisabled" Val="1"/>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="DesignMode" Val="RTL"/>
+      <Option Name="TopModule" Val="fpga"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+    <Filter Type="Constrs"/>
+    <File Path="$PPRDIR/../fpga.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../eth.xdc">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/syn/vivado/rgmii_phy_if.tcl">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/syn/vivado/eth_mac_fifo.tcl">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <File Path="$PPRDIR/../lib/eth/lib/axis/syn/vivado/sync_reset.tcl">
+      <FileInfo>
+        <Attr Name="UsedIn" Val="synthesis"/>
+        <Attr Name="UsedIn" Val="implementation"/>
+        <Attr Name="UsedIn" Val="simulation"/>
+      </FileInfo>
+    </File>
+    <Config>
+      <Option Name="ConstrsType" Val="XDC"/>
+    </Config>
+  </FileSet>
+  <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+    <Filter Type="Utils"/>
+    <Config>
+      <Option Name="TopAutoSet" Val="TRUE"/>
+    </Config>
+  </FileSet>
+  <Strategy Version="1" Minor="2">
+    <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
+    <Step Id="synth_design"/>
+  </Strategy>
+</GenRun>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/htr.txt b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/htr.txt
new file mode 100644
index 000000000..391535f84
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/htr.txt
@@ -0,0 +1,10 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+#          the basic steps of a run.  Note that runme.bat/sh needs
+#          to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+
+vivado -log fpga.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fpga.tcl
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/project.wdf b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/project.wdf
new file mode 100644
index 000000000..6e3eea8e5
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/project.wdf
@@ -0,0 +1,31 @@
+version:1
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:3338:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:37:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c696d706c72756e73:31:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f72655f636f6e7461696e6572:66616c7365:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73696d756c61746f725f6c616e6775616765:4d69786564:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f6c616e6775616765:566572696c6f67:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64656661756c745f6c696272617279:78696c5f64656661756c746c6962:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:7461726765745f73696d756c61746f72:5853696d:00:00
+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6c61756e63685f73696d756c6174696f6e5f7873696d:30:00:00
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diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/rundef.js b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/rundef.js
new file mode 100644
index 000000000..6119c5aa4
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/rundef.js
@@ -0,0 +1,41 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+  PathVal = "/home/kavya/Downloads/Downloads/Vivado/2023.1/ids_lite/ISE/bin/lin64;/home/kavya/Downloads/Downloads/Vivado/2023.1/bin;";
+} else {
+  PathVal = "/home/kavya/Downloads/Downloads/Vivado/2023.1/ids_lite/ISE/bin/lin64;/home/kavya/Downloads/Downloads/Vivado/2023.1/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+         "-log fpga.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fpga.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+  var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+  var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+  var EAIFContents = EAInclFile.ReadAll();
+  EAInclFile.Close();
+  return EAIFContents;
+}
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/runme.bat b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/runme.bat
new file mode 100644
index 000000000..3a5f85351
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/runme.bat
@@ -0,0 +1,12 @@
+@echo off
+
+rem  Vivado (TM)
+rem  runme.bat: a Vivado-generated Script
+rem  Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+rem  Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/runme.log b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/runme.log
new file mode 100644
index 000000000..327c20475
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/runme.log
@@ -0,0 +1,1402 @@
+
+*** Running vivado
+    with args -log fpga.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fpga.tcl
+
+
+****** Vivado v2023.1 (64-bit)
+  **** SW Build 3865809 on Sun May  7 15:04:56 MDT 2023
+  **** IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
+  **** SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
+    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+
+source fpga.tcl -notrace
+create_project: Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1335.785 ; gain = 0.023 ; free physical = 51138 ; free virtual = 56143
+Command: synth_design -top fpga -part xc7a200tfbg484-2
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a200t'
+INFO: [Device 21-403] Loading part xc7a200tfbg484-2
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 256359
+WARNING: [Synth 8-11065] parameter 'BYTE_LANES' becomes localparam in 'arp_eth_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:89]
+WARNING: [Synth 8-11065] parameter 'HDR_SIZE' becomes localparam in 'arp_eth_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:91]
+WARNING: [Synth 8-11065] parameter 'CYCLE_COUNT' becomes localparam in 'arp_eth_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:93]
+WARNING: [Synth 8-11065] parameter 'PTR_WIDTH' becomes localparam in 'arp_eth_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:95]
+WARNING: [Synth 8-11065] parameter 'OFFSET' becomes localparam in 'arp_eth_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:97]
+WARNING: [Synth 8-11065] parameter 'BYTE_LANES' becomes localparam in 'arp_eth_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:85]
+WARNING: [Synth 8-11065] parameter 'HDR_SIZE' becomes localparam in 'arp_eth_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:87]
+WARNING: [Synth 8-11065] parameter 'CYCLE_COUNT' becomes localparam in 'arp_eth_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:89]
+WARNING: [Synth 8-11065] parameter 'PTR_WIDTH' becomes localparam in 'arp_eth_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:91]
+WARNING: [Synth 8-11065] parameter 'OFFSET' becomes localparam in 'arp_eth_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:93]
+WARNING: [Synth 8-11065] parameter 'ADDR_WIDTH' becomes localparam in 'axis_async_fifo' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:145]
+WARNING: [Synth 8-11065] parameter 'OUTPUT_FIFO_ADDR_WIDTH' becomes localparam in 'axis_async_fifo' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:147]
+WARNING: [Synth 8-11065] parameter 'ADDR_WIDTH' becomes localparam in 'axis_fifo' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:137]
+WARNING: [Synth 8-11065] parameter 'OUTPUT_FIFO_ADDR_WIDTH' becomes localparam in 'axis_fifo' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:139]
+WARNING: [Synth 8-11065] parameter 'MIN_LEN_WIDTH' becomes localparam in 'axis_gmii_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:93]
+WARNING: [Synth 8-11065] parameter 'CL_S_COUNT' becomes localparam in 'eth_arb_mux' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:90]
+WARNING: [Synth 8-11065] parameter 'BYTE_LANES' becomes localparam in 'eth_axis_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:80]
+WARNING: [Synth 8-11065] parameter 'HDR_SIZE' becomes localparam in 'eth_axis_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:82]
+WARNING: [Synth 8-11065] parameter 'CYCLE_COUNT' becomes localparam in 'eth_axis_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:84]
+WARNING: [Synth 8-11065] parameter 'PTR_WIDTH' becomes localparam in 'eth_axis_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:86]
+WARNING: [Synth 8-11065] parameter 'OFFSET' becomes localparam in 'eth_axis_rx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:88]
+WARNING: [Synth 8-11065] parameter 'BYTE_LANES' becomes localparam in 'eth_axis_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:79]
+WARNING: [Synth 8-11065] parameter 'HDR_SIZE' becomes localparam in 'eth_axis_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:81]
+WARNING: [Synth 8-11065] parameter 'CYCLE_COUNT' becomes localparam in 'eth_axis_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:83]
+WARNING: [Synth 8-11065] parameter 'PTR_WIDTH' becomes localparam in 'eth_axis_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:85]
+WARNING: [Synth 8-11065] parameter 'OFFSET' becomes localparam in 'eth_axis_tx' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:87]
+WARNING: [Synth 8-11065] parameter 'MAC_CTRL_ENABLE' becomes localparam in 'eth_mac_1g' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g.v:191]
+WARNING: [Synth 8-11065] parameter 'TX_USER_WIDTH_INT' becomes localparam in 'eth_mac_1g' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g.v:192]
+WARNING: [Synth 8-11065] parameter 'CL_S_COUNT' becomes localparam in 'ip_arb_mux' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:116]
+WARNING: [Synth 8-11065] parameter 'STYLE_INT' becomes localparam in 'lfsr' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v:355]
+WARNING: [Synth 8-11065] parameter 'LEVELS' becomes localparam in 'priority_encoder' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:47]
+WARNING: [Synth 8-11065] parameter 'W' becomes localparam in 'priority_encoder' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:48]
+WARNING: [Synth 8-11065] parameter 'HEADER_FIFO_ADDR_WIDTH' becomes localparam in 'udp_checksum_gen' with formal parameter declaration list [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:143]
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2071.398 ; gain = 377.801 ; free physical = 50143 ; free virtual = 55148
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'fpga' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga.v:10]
+INFO: [Synth 8-6157] synthesizing module 'IBUFGDS' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:72266]
+INFO: [Synth 8-6155] done synthesizing module 'IBUFGDS' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:72266]
+INFO: [Synth 8-6157] synthesizing module 'MMCME2_BASE' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:80431]
+	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
+	Parameter CLKFBOUT_MULT_F bound to: 5.000000 - type: double 
+	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKIN1_PERIOD bound to: 5.000000 - type: double 
+	Parameter CLKOUT0_DIVIDE_F bound to: 8.000000 - type: double 
+	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKOUT1_DIVIDE bound to: 8 - type: integer 
+	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT1_PHASE bound to: 90.000000 - type: double 
+	Parameter CLKOUT2_DIVIDE bound to: 5 - type: integer 
+	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKOUT4_CASCADE bound to: FALSE - type: string 
+	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: double 
+	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
+	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: double 
+	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: double 
+	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
+	Parameter REF_JITTER1 bound to: 0.010000 - type: double 
+	Parameter STARTUP_WAIT bound to: FALSE - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'MMCME2_BASE' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:80431]
+INFO: [Synth 8-6157] synthesizing module 'BUFG' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1519]
+INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1519]
+INFO: [Synth 8-6157] synthesizing module 'sync_reset' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/sync_reset.v:35]
+	Parameter N bound to: 4 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'sync_reset' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/sync_reset.v:35]
+WARNING: [Synth 8-4446] all outputs are unconnected for this instance and logic may be removed [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga.v:146]
+INFO: [Synth 8-6157] synthesizing module 'IDELAYCTRL' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73864]
+INFO: [Synth 8-6155] done synthesizing module 'IDELAYCTRL' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73864]
+INFO: [Synth 8-6157] synthesizing module 'IDELAYE2' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73877]
+	Parameter IDELAY_TYPE bound to: FIXED - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'IDELAYE2' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73877]
+INFO: [Synth 8-6157] synthesizing module 'fpga_core' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+INFO: [Synth 8-6157] synthesizing module 'eth_mac_1g_rgmii_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string 
+	Parameter USE_CLK90 bound to: TRUE - type: string 
+	Parameter ENABLE_PADDING bound to: 1 - type: integer 
+	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer 
+	Parameter TX_FIFO_DEPTH bound to: 4096 - type: integer 
+	Parameter TX_FRAME_FIFO bound to: 1 - type: integer 
+	Parameter RX_FIFO_DEPTH bound to: 4096 - type: integer 
+	Parameter RX_FRAME_FIFO bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'eth_mac_1g_rgmii' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string 
+	Parameter USE_CLK90 bound to: TRUE - type: string 
+	Parameter ENABLE_PADDING bound to: 1 - type: integer 
+	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'rgmii_phy_if' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/rgmii_phy_if.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string 
+	Parameter USE_CLK90 bound to: TRUE - type: string 
+INFO: [Synth 8-6157] synthesizing module 'ssio_ddr_in' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ssio_ddr_in.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter CLOCK_INPUT_STYLE bound to: BUFR - type: string 
+	Parameter WIDTH bound to: 5 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'BUFIO' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1791]
+INFO: [Synth 8-6155] done synthesizing module 'BUFIO' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1791]
+INFO: [Synth 8-6157] synthesizing module 'BUFR' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1857]
+	Parameter BUFR_DIVIDE bound to: BYPASS - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'BUFR' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:1857]
+INFO: [Synth 8-6157] synthesizing module 'iddr' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/iddr.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter WIDTH bound to: 5 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'IDDR' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73742]
+	Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string 
+	Parameter SRTYPE bound to: ASYNC - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'IDDR' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:73742]
+INFO: [Synth 8-6155] done synthesizing module 'iddr' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/iddr.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'ssio_ddr_in' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ssio_ddr_in.v:34]
+INFO: [Synth 8-6157] synthesizing module 'oddr' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/oddr.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'ODDR' [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:94765]
+	Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string 
+	Parameter SRTYPE bound to: ASYNC - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'ODDR' (0#1) [/home/kavya/Downloads/Downloads/Vivado/2023.1/scripts/rt/data/unisim_comp.v:94765]
+INFO: [Synth 8-6155] done synthesizing module 'oddr' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/oddr.v:34]
+INFO: [Synth 8-6157] synthesizing module 'oddr__parameterized0' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/oddr.v:34]
+	Parameter TARGET bound to: XILINX - type: string 
+	Parameter IODDR_STYLE bound to: IODDR - type: string 
+	Parameter WIDTH bound to: 5 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'oddr__parameterized0' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/oddr.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'rgmii_phy_if' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/rgmii_phy_if.v:34]
+INFO: [Synth 8-6157] synthesizing module 'eth_mac_1g' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g.v:34]
+	Parameter ENABLE_PADDING bound to: 1 - type: integer 
+	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'axis_gmii_rx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_rx.v:34]
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter PTP_TS_ENABLE bound to: 0 - type: integer 
+	Parameter PTP_TS_WIDTH bound to: 96 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'lfsr' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v:34]
+	Parameter LFSR_WIDTH bound to: 32 - type: integer 
+	Parameter LFSR_POLY bound to: 79764919 - type: integer 
+	Parameter LFSR_CONFIG bound to: GALOIS - type: string 
+	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer 
+	Parameter REVERSE bound to: 1 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter STYLE bound to: AUTO - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'lfsr' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_rx.v:189]
+INFO: [Synth 8-6155] done synthesizing module 'axis_gmii_rx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_rx.v:34]
+INFO: [Synth 8-6157] synthesizing module 'axis_gmii_tx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:34]
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter ENABLE_PADDING bound to: 1 - type: integer 
+	Parameter MIN_FRAME_LENGTH bound to: 64 - type: integer 
+	Parameter PTP_TS_ENABLE bound to: 0 - type: integer 
+	Parameter PTP_TS_WIDTH bound to: 96 - type: integer 
+	Parameter PTP_TS_CTRL_IN_TUSER bound to: 0 - type: integer 
+	Parameter PTP_TAG_ENABLE bound to: 0 - type: integer 
+	Parameter PTP_TAG_WIDTH bound to: 16 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:367]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:241]
+INFO: [Synth 8-6155] done synthesizing module 'axis_gmii_tx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'eth_mac_1g' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g.v:34]
+WARNING: [Synth 8-7071] port 'tx_ptp_ts' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_ptp_ts' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_axis_ptp_ts' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_axis_ptp_ts_tag' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_axis_ptp_ts_valid' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_lfc_req' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_lfc_resend' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_lfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_lfc_req' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_lfc_ack' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_pfc_req' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_pfc_resend' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_pfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_pfc_req' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_pfc_ack' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_lfc_pause_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_pause_req' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_pause_ack' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'tx_start_packet' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'rx_start_packet' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_mcf' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_mcf' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_lfc_pkt' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_lfc_xon' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_lfc_xoff' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_lfc_paused' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_pfc_pkt' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_pfc_xon' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_pfc_xoff' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_tx_pfc_paused' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_lfc_pkt' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_lfc_xon' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_lfc_xoff' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_lfc_paused' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_pfc_pkt' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_pfc_xon' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_pfc_xoff' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'stat_rx_pfc_paused' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_eth_dst_mcast' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_check_eth_dst_mcast' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_eth_dst_ucast' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_check_eth_dst_ucast' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_eth_src' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_check_eth_src' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_eth_type' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_opcode_lfc' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_check_opcode_lfc' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_opcode_pfc' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_check_opcode_pfc' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_forward' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_mcf_rx_enable' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_eth_dst' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_eth_src' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_eth_type' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_opcode' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_quanta' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_lfc_refresh' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_eth_dst' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_eth_src' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_eth_type' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_opcode' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_quanta' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_tx_pfc_refresh' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_rx_lfc_opcode' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_rx_lfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_rx_pfc_opcode' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7071] port 'cfg_rx_pfc_en' of module 'eth_mac_1g' is unconnected for instance 'eth_mac_1g_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+WARNING: [Synth 8-7023] instance 'eth_mac_1g_inst' of module 'eth_mac_1g' has 98 connections declared, but only 29 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:222]
+INFO: [Synth 8-6155] done synthesizing module 'eth_mac_1g_rgmii' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii.v:34]
+INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo_adapter' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
+	Parameter DEPTH bound to: 4096 - type: integer 
+	Parameter S_DATA_WIDTH bound to: 8 - type: integer 
+	Parameter S_KEEP_ENABLE bound to: 1'b0 
+	Parameter S_KEEP_WIDTH bound to: 1 - type: integer 
+	Parameter M_DATA_WIDTH bound to: 8 - type: integer 
+	Parameter M_KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter RAM_PIPELINE bound to: 1 - type: integer 
+	Parameter FRAME_FIFO bound to: 1 - type: integer 
+	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1 
+	Parameter USER_BAD_FRAME_MASK bound to: 1'b1 
+	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer 
+	Parameter DROP_BAD_FRAME bound to: 1 - type: integer 
+	Parameter DROP_WHEN_FULL bound to: 0 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
+	Parameter DEPTH bound to: 4096 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter KEEP_WIDTH bound to: 1 - type: integer 
+	Parameter LAST_ENABLE bound to: 1 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter ID_WIDTH bound to: 8 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_WIDTH bound to: 8 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter RAM_PIPELINE bound to: 1 - type: integer 
+	Parameter OUTPUT_FIFO_ENABLE bound to: 0 - type: integer 
+	Parameter FRAME_FIFO bound to: 1 - type: integer 
+	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1 
+	Parameter USER_BAD_FRAME_MASK bound to: 1'b1 
+	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer 
+	Parameter DROP_BAD_FRAME bound to: 1 - type: integer 
+	Parameter DROP_WHEN_FULL bound to: 0 - type: integer 
+	Parameter MARK_WHEN_FULL bound to: 0 - type: integer 
+	Parameter PAUSE_ENABLE bound to: 0 - type: integer 
+	Parameter FRAME_PAUSE bound to: 1 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo_adapter' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
+WARNING: [Synth 8-7071] port 's_pause_req' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 's_pause_ack' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 'm_pause_req' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 'm_pause_ack' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 's_status_depth' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 's_status_depth_commit' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 'm_status_depth' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7071] port 'm_status_depth_commit' of module 'axis_async_fifo_adapter' is unconnected for instance 'tx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+WARNING: [Synth 8-7023] instance 'tx_fifo' of module 'axis_async_fifo_adapter' has 34 connections declared, but only 26 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:273]
+INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo_adapter__parameterized0' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
+	Parameter DEPTH bound to: 4096 - type: integer 
+	Parameter S_DATA_WIDTH bound to: 8 - type: integer 
+	Parameter S_KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter M_DATA_WIDTH bound to: 8 - type: integer 
+	Parameter M_KEEP_ENABLE bound to: 1'b0 
+	Parameter M_KEEP_WIDTH bound to: 1 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter RAM_PIPELINE bound to: 1 - type: integer 
+	Parameter FRAME_FIFO bound to: 1 - type: integer 
+	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1 
+	Parameter USER_BAD_FRAME_MASK bound to: 1'b1 
+	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer 
+	Parameter DROP_BAD_FRAME bound to: 1 - type: integer 
+	Parameter DROP_WHEN_FULL bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'axis_async_fifo__parameterized0' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
+	Parameter DEPTH bound to: 4096 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter KEEP_WIDTH bound to: 1 - type: integer 
+	Parameter LAST_ENABLE bound to: 1 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter ID_WIDTH bound to: 8 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_WIDTH bound to: 8 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter RAM_PIPELINE bound to: 1 - type: integer 
+	Parameter OUTPUT_FIFO_ENABLE bound to: 0 - type: integer 
+	Parameter FRAME_FIFO bound to: 1 - type: integer 
+	Parameter USER_BAD_FRAME_VALUE bound to: 1'b1 
+	Parameter USER_BAD_FRAME_MASK bound to: 1'b1 
+	Parameter DROP_OVERSIZE_FRAME bound to: 1 - type: integer 
+	Parameter DROP_BAD_FRAME bound to: 1 - type: integer 
+	Parameter DROP_WHEN_FULL bound to: 1 - type: integer 
+	Parameter MARK_WHEN_FULL bound to: 0 - type: integer 
+	Parameter PAUSE_ENABLE bound to: 0 - type: integer 
+	Parameter FRAME_PAUSE bound to: 1 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo__parameterized0' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'axis_async_fifo_adapter__parameterized0' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v:34]
+WARNING: [Synth 8-7071] port 's_pause_req' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 's_pause_ack' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 'm_pause_req' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 'm_pause_ack' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 's_status_depth' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 's_status_depth_commit' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 'm_status_depth' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7071] port 'm_status_depth_commit' of module 'axis_async_fifo_adapter' is unconnected for instance 'rx_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+WARNING: [Synth 8-7023] instance 'rx_fifo' of module 'axis_async_fifo_adapter' has 34 connections declared, but only 26 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:324]
+INFO: [Synth 8-6155] done synthesizing module 'eth_mac_1g_rgmii_fifo' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_mac_1g_rgmii_fifo.v:34]
+WARNING: [Synth 8-7071] port 'tx_axis_tkeep' of module 'eth_mac_1g_rgmii_fifo' is unconnected for instance 'eth_mac_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:283]
+WARNING: [Synth 8-7071] port 'rx_axis_tkeep' of module 'eth_mac_1g_rgmii_fifo' is unconnected for instance 'eth_mac_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:283]
+WARNING: [Synth 8-7071] port 'tx_error_underflow' of module 'eth_mac_1g_rgmii_fifo' is unconnected for instance 'eth_mac_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:283]
+WARNING: [Synth 8-7023] instance 'eth_mac_inst' of module 'eth_mac_1g_rgmii_fifo' has 36 connections declared, but only 33 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:283]
+INFO: [Synth 8-6157] synthesizing module 'eth_axis_rx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'eth_axis_rx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:34]
+WARNING: [Synth 8-7071] port 's_axis_tkeep' of module 'eth_axis_rx' is unconnected for instance 'eth_axis_rx_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:325]
+WARNING: [Synth 8-7071] port 'm_eth_payload_axis_tkeep' of module 'eth_axis_rx' is unconnected for instance 'eth_axis_rx_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:325]
+WARNING: [Synth 8-7023] instance 'eth_axis_rx_inst' of module 'eth_axis_rx' has 21 connections declared, but only 19 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:325]
+INFO: [Synth 8-6157] synthesizing module 'eth_axis_tx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'eth_axis_tx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:34]
+WARNING: [Synth 8-7071] port 's_eth_payload_axis_tkeep' of module 'eth_axis_tx' is unconnected for instance 'eth_axis_tx_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:351]
+WARNING: [Synth 8-7071] port 'm_axis_tkeep' of module 'eth_axis_tx' is unconnected for instance 'eth_axis_tx_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:351]
+WARNING: [Synth 8-7023] instance 'eth_axis_tx_inst' of module 'eth_axis_tx' has 20 connections declared, but only 18 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:351]
+INFO: [Synth 8-6157] synthesizing module 'udp_complete' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_complete.v:34]
+INFO: [Synth 8-6157] synthesizing module 'ip_arb_mux' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:34]
+	Parameter S_COUNT bound to: 2 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer 
+	Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'arbiter' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/arbiter.v:34]
+	Parameter PORTS bound to: 2 - type: integer 
+	Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer 
+	Parameter ARB_BLOCK bound to: 1 - type: integer 
+	Parameter ARB_BLOCK_ACK bound to: 1 - type: integer 
+	Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'priority_encoder' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:34]
+	Parameter WIDTH bound to: 2 - type: integer 
+	Parameter LSB_HIGH_PRIORITY bound to: 1 - type: integer 
+WARNING: [Synth 8-693] zero replication count - replication ignored [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:51]
+INFO: [Synth 8-6155] done synthesizing module 'priority_encoder' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/priority_encoder.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'arbiter' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/arbiter.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'ip_arb_mux' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:34]
+INFO: [Synth 8-6157] synthesizing module 'ip_complete' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v:34]
+	Parameter ARP_CACHE_ADDR_WIDTH bound to: 9 - type: integer 
+	Parameter ARP_REQUEST_RETRY_COUNT bound to: 4 - type: integer 
+	Parameter ARP_REQUEST_RETRY_INTERVAL bound to: 250000000 - type: integer 
+	Parameter ARP_REQUEST_TIMEOUT bound to: -544967296 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'eth_arb_mux' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:34]
+	Parameter S_COUNT bound to: 2 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter ARB_TYPE_ROUND_ROBIN bound to: 0 - type: integer 
+	Parameter ARB_LSB_HIGH_PRIORITY bound to: 1 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'eth_arb_mux' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:34]
+INFO: [Synth 8-6157] synthesizing module 'ip' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip.v:34]
+INFO: [Synth 8-6157] synthesizing module 'ip_eth_rx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_rx.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_rx.v:311]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_rx.v:279]
+INFO: [Synth 8-6155] done synthesizing module 'ip_eth_rx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_rx.v:34]
+INFO: [Synth 8-6157] synthesizing module 'ip_eth_tx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_tx.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_tx.v:237]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_tx.v:209]
+INFO: [Synth 8-6155] done synthesizing module 'ip_eth_tx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_eth_tx.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip.v:274]
+INFO: [Synth 8-6155] done synthesizing module 'ip' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip.v:34]
+INFO: [Synth 8-6157] synthesizing module 'arp' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp.v:34]
+	Parameter CACHE_ADDR_WIDTH bound to: 9 - type: integer 
+	Parameter REQUEST_RETRY_COUNT bound to: 4 - type: integer 
+	Parameter REQUEST_RETRY_INTERVAL bound to: 250000000 - type: integer 
+	Parameter REQUEST_TIMEOUT bound to: -544967296 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'arp_eth_rx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:34]
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 1'b0 
+	Parameter KEEP_WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'arp_eth_rx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:34]
+INFO: [Synth 8-6157] synthesizing module 'arp_eth_tx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:34]
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 1'b0 
+	Parameter KEEP_WIDTH bound to: 1 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'arp_eth_tx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:34]
+INFO: [Synth 8-6157] synthesizing module 'arp_cache' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_cache.v:34]
+	Parameter CACHE_ADDR_WIDTH bound to: 9 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'lfsr__parameterized0' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v:34]
+	Parameter LFSR_WIDTH bound to: 32 - type: integer 
+	Parameter LFSR_POLY bound to: 79764919 - type: integer 
+	Parameter LFSR_CONFIG bound to: GALOIS - type: string 
+	Parameter LFSR_FEED_FORWARD bound to: 0 - type: integer 
+	Parameter REVERSE bound to: 1 - type: integer 
+	Parameter DATA_WIDTH bound to: 32 - type: integer 
+	Parameter STYLE bound to: AUTO - type: string 
+INFO: [Synth 8-6155] done synthesizing module 'lfsr__parameterized0' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/lfsr.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'arp_cache' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_cache.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'arp' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp.v:34]
+WARNING: [Synth 8-7071] port 's_eth_payload_axis_tkeep' of module 'arp' is unconnected for instance 'arp_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v:401]
+WARNING: [Synth 8-7071] port 'm_eth_payload_axis_tkeep' of module 'arp' is unconnected for instance 'arp_inst' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v:401]
+WARNING: [Synth 8-7023] instance 'arp_inst' of module 'arp' has 36 connections declared, but only 34 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v:401]
+INFO: [Synth 8-6155] done synthesizing module 'ip_complete' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_complete.v:34]
+INFO: [Synth 8-6157] synthesizing module 'udp' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp.v:34]
+	Parameter CHECKSUM_GEN_ENABLE bound to: 1 - type: integer 
+	Parameter CHECKSUM_PAYLOAD_FIFO_DEPTH bound to: 2048 - type: integer 
+	Parameter CHECKSUM_HEADER_FIFO_DEPTH bound to: 8 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'udp_checksum_gen' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:34]
+	Parameter PAYLOAD_FIFO_DEPTH bound to: 2048 - type: integer 
+	Parameter HEADER_FIFO_DEPTH bound to: 8 - type: integer 
+INFO: [Synth 8-6157] synthesizing module 'axis_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
+	Parameter DEPTH bound to: 2048 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter LAST_ENABLE bound to: 1 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter FRAME_FIFO bound to: 0 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'axis_fifo' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
+WARNING: [Synth 8-7071] port 'pause_req' of module 'axis_fifo' is unconnected for instance 'payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:214]
+WARNING: [Synth 8-7071] port 'pause_ack' of module 'axis_fifo' is unconnected for instance 'payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:214]
+WARNING: [Synth 8-7071] port 'status_depth' of module 'axis_fifo' is unconnected for instance 'payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:214]
+WARNING: [Synth 8-7071] port 'status_depth_commit' of module 'axis_fifo' is unconnected for instance 'payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:214]
+WARNING: [Synth 8-7023] instance 'payload_fifo' of module 'axis_fifo' has 25 connections declared, but only 21 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:214]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:450]
+INFO: [Synth 8-6155] done synthesizing module 'udp_checksum_gen' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:34]
+INFO: [Synth 8-6157] synthesizing module 'udp_ip_rx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_rx.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_rx.v:265]
+INFO: [Synth 8-6155] done synthesizing module 'udp_ip_rx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_rx.v:34]
+INFO: [Synth 8-6157] synthesizing module 'udp_ip_tx' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_tx.v:34]
+INFO: [Synth 8-155] case statement is not full and has no default [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_tx.v:240]
+INFO: [Synth 8-6155] done synthesizing module 'udp_ip_tx' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_ip_tx.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'udp' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'udp_complete' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_complete.v:34]
+INFO: [Synth 8-6157] synthesizing module 'axis_fifo__parameterized0' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
+	Parameter DEPTH bound to: 8192 - type: integer 
+	Parameter DATA_WIDTH bound to: 8 - type: integer 
+	Parameter KEEP_ENABLE bound to: 0 - type: integer 
+	Parameter ID_ENABLE bound to: 0 - type: integer 
+	Parameter DEST_ENABLE bound to: 0 - type: integer 
+	Parameter USER_ENABLE bound to: 1 - type: integer 
+	Parameter USER_WIDTH bound to: 1 - type: integer 
+	Parameter FRAME_FIFO bound to: 0 - type: integer 
+INFO: [Synth 8-6155] done synthesizing module 'axis_fifo__parameterized0' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:34]
+WARNING: [Synth 8-7071] port 'pause_req' of module 'axis_fifo' is unconnected for instance 'udp_payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:517]
+WARNING: [Synth 8-7071] port 'pause_ack' of module 'axis_fifo' is unconnected for instance 'udp_payload_fifo' [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:517]
+INFO: [Common 17-14] Message 'Synth 8-7071' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+WARNING: [Synth 8-7023] instance 'udp_payload_fifo' of module 'axis_fifo' has 25 connections declared, but only 21 given [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:517]
+INFO: [Synth 8-6155] done synthesizing module 'fpga_core' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v:34]
+INFO: [Synth 8-6155] done synthesizing module 'fpga' (0#1) [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/rtl/fpga.v:10]
+WARNING: [Synth 8-6014] Unused sequential element ptp_ts_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_rx.v:259]
+WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:413]
+WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_tag_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:414]
+WARNING: [Synth 8-6014] Unused sequential element m_axis_ptp_ts_valid_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/axis_gmii_tx.v:415]
+WARNING: [Synth 8-6014] Unused sequential element wr_ptr_temp_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:423]
+WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:436]
+WARNING: [Synth 8-6014] Unused sequential element rd_ptr_temp_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:670]
+WARNING: [Synth 8-6014] Unused sequential element wr_ptr_temp_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:423]
+WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:436]
+WARNING: [Synth 8-6014] Unused sequential element rd_ptr_temp_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_async_fifo.v:670]
+WARNING: [Synth 8-6014] Unused sequential element save_axis_tdata_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:290]
+WARNING: [Synth 8-6014] Unused sequential element save_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:291]
+WARNING: [Synth 8-6014] Unused sequential element save_axis_tuser_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:292]
+WARNING: [Synth 8-6014] Unused sequential element save_axis_tlast_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:296]
+WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:379]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_rx.v:384]
+WARNING: [Synth 8-6014] Unused sequential element save_eth_payload_axis_tdata_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:297]
+WARNING: [Synth 8-6014] Unused sequential element save_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:298]
+WARNING: [Synth 8-6014] Unused sequential element save_eth_payload_axis_tuser_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:299]
+WARNING: [Synth 8-6014] Unused sequential element save_eth_payload_axis_tlast_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:303]
+WARNING: [Synth 8-6014] Unused sequential element m_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:383]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_axis_tx.v:388]
+WARNING: [Synth 8-6014] Unused sequential element m_ip_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:374]
+WARNING: [Synth 8-6014] Unused sequential element m_ip_payload_axis_tid_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:376]
+WARNING: [Synth 8-6014] Unused sequential element m_ip_payload_axis_tdest_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:377]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_ip_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:381]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_ip_payload_axis_tid_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:383]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_ip_payload_axis_tdest_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/ip_arb_mux.v:384]
+WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:283]
+WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tid_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:285]
+WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tdest_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:286]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:290]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tid_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:292]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tdest_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/eth_arb_mux.v:293]
+WARNING: [Synth 8-6014] Unused sequential element busy_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_rx.v:176]
+WARNING: [Synth 8-6014] Unused sequential element m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:342]
+WARNING: [Synth 8-6014] Unused sequential element temp_m_eth_payload_axis_tkeep_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:347]
+WARNING: [Synth 8-6014] Unused sequential element busy_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/arp_eth_tx.v:165]
+WARNING: [Synth 8-6014] Unused sequential element s_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:267]
+WARNING: [Synth 8-6014] Unused sequential element drop_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:311]
+WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:358]
+WARNING: [Synth 8-6014] Unused sequential element bad_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:256]
+WARNING: [Synth 8-6014] Unused sequential element good_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:257]
+WARNING: [Synth 8-6014] Unused sequential element s_udp_payload_axis_tready_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/rtl/udp_checksum_gen.v:521]
+WARNING: [Synth 8-6014] Unused sequential element s_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:267]
+WARNING: [Synth 8-6014] Unused sequential element drop_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:311]
+WARNING: [Synth 8-6014] Unused sequential element send_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:358]
+WARNING: [Synth 8-6014] Unused sequential element bad_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:256]
+WARNING: [Synth 8-6014] Unused sequential element good_frame_reg_reg was removed.  [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/rtl/axis_fifo.v:257]
+WARNING: [Synth 8-7129] Port s_axis_tkeep[0] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[7] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[6] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[5] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[4] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[3] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[2] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[1] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[0] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[7] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[6] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[5] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[4] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[3] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[2] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[1] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[0] in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port pause_req in module axis_fifo__parameterized0 is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tkeep[0] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[7] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[6] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[5] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[4] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[3] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[2] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[1] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tid[0] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[7] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[6] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[5] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[4] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[3] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[2] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[1] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_axis_tdest[0] in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port pause_req in module axis_fifo is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[15] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[14] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[13] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[12] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[11] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[10] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[9] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[8] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[7] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[6] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[5] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[4] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[3] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[2] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[1] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_length[0] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[15] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[14] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[13] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[12] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[11] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[10] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[9] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[8] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[7] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[6] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[5] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[4] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[3] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[2] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[1] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_udp_checksum[0] in module udp is either unconnected or has no load
+WARNING: [Synth 8-7129] Port s_eth_payload_axis_tkeep[0] in module arp_eth_rx is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[31] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[30] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[29] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[28] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[27] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[26] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[25] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[24] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[23] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[22] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[21] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[20] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[19] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[18] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[17] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[16] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[15] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[14] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[13] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[12] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[11] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[10] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[9] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[8] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[7] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[6] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[5] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[4] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[3] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[2] in module ip is either unconnected or has no load
+WARNING: [Synth 8-7129] Port local_ip[1] in module ip is either unconnected or has no load
+INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:28 ; elapsed = 00:00:28 . Memory (MB): peak = 2375.047 ; gain = 681.449 ; free physical = 49829 ; free virtual = 54836
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2380.984 ; gain = 687.387 ; free physical = 49829 ; free virtual = 54836
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:28 ; elapsed = 00:00:29 . Memory (MB): peak = 2380.984 ; gain = 687.387 ; free physical = 49829 ; free virtual = 54836
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2383.953 ; gain = 0.000 ; free physical = 49829 ; free virtual = 54836
+INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]
+INFO: [Constraints 18-632] set_input_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:18]
+INFO: [Constraints 18-632] set_output_delay: No clock object specified, the clocks will be automatically identified [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc:50]
+Finished Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc]
+Finished Parsing XDC File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/eth.xdc]
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]
+Inserting timing constraints for rgmii_phy_if instance core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst
+INFO: [Timing 38-2] Deriving generated clocks [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl:23]
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]
+Inserting timing constraints for eth_mac_1g_rgmii instance core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
+Inserting timing constraints for ethernet MAC with FIFO instance core_inst/eth_mac_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
+Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_inst/rx_fifo/fifo_inst
+Inserting timing constraints for axis_async_fifo instance core_inst/eth_mac_inst/tx_fifo/fifo_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
+Inserting timing constraints for sync_reset instance sync_reset_inst
+Finished Sourcing Tcl File [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2525.734 ; gain = 0.000 ; free physical = 49827 ; free virtual = 54834
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 2 instances were transformed.
+  IBUFGDS => IBUFDS: 1 instance 
+  MMCME2_BASE => MMCME2_ADV: 1 instance 
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2525.734 ; gain = 0.000 ; free physical = 49827 ; free virtual = 54834
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49804 ; free virtual = 54811
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a200tfbg484-2
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:41 ; elapsed = 00:00:42 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49804 ; free virtual = 54811
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/tx_rst_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/clk_oddr_inst/\oddr[0].oddr_inst . (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/rgmii_phy_if.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/tx_mii_select_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/tx_mii_select_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_mii_select_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rx_prescale_sync_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_1_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_1_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_2_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_2_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_3_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_3_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_4_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_sync_reg_4_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/\tx_sync_reg_1_reg[0] . (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/\tx_sync_reg_2_reg[0] . (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/\tx_sync_reg_3_reg[0] . (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/\tx_sync_reg_4_reg[0] . (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_rst_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/s_rst_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/m_rst_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_ack_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_ack_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/wr_ptr_update_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/overflow_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/overflow_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/overflow_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/bad_frame_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/bad_frame_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/bad_frame_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/good_frame_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/good_frame_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/rx_fifo/fifo_inst/good_frame_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/s_rst_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/m_rst_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/m_rst_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/rd_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_gray_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_commit_sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_update_ack_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_update_ack_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_update_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_update_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/wr_ptr_update_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/overflow_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/overflow_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/overflow_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/bad_frame_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/bad_frame_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/bad_frame_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/good_frame_sync1_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/good_frame_sync2_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for core_inst/eth_mac_inst/tx_fifo/fifo_inst/good_frame_sync3_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl, line 23).
+Applied set_property ASYNC_REG = true for sync_reset_inst/sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl, line 23).
+Applied set_property ASYNC_REG = true for sync_reset_inst/sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl, line 23).
+Applied set_property ASYNC_REG = true for sync_reset_inst/sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl, line 23).
+Applied set_property ASYNC_REG = true for sync_reset_inst/sync_reg_reg. (constraint file  /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl, line 23).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:42 ; elapsed = 00:00:42 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49804 ; free virtual = 54811
+---------------------------------------------------------------------------------
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'axis_gmii_rx'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'axis_gmii_tx'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'ip_eth_rx'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'ip_eth_tx'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'ip'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'udp_ip_rx'
+INFO: [Synth 8-802] inferred FSM for state register 'state_reg_reg' in module 'udp_ip_tx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                              001 |                              000
+           STATE_PAYLOAD |                              010 |                              001
+         STATE_WAIT_LAST |                              100 |                              010
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'one-hot' in module 'axis_gmii_rx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                              000 |                              000
+          STATE_PREAMBLE |                              001 |                              001
+           STATE_PAYLOAD |                              010 |                              010
+              STATE_LAST |                              011 |                              011
+               STATE_PAD |                              100 |                              100
+               STATE_FCS |                              101 |                              101
+               STATE_IFG |                              110 |                              110
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'axis_gmii_tx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                              000 |                              000
+       STATE_READ_HEADER |                              001 |                              001
+         STATE_WAIT_LAST |                              010 |                              100
+      STATE_READ_PAYLOAD |                              011 |                              010
+ STATE_READ_PAYLOAD_LAST |                              100 |                              011
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'ip_eth_rx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                             0001 |                              000
+      STATE_WRITE_HEADER |                             0010 |                              001
+     STATE_WRITE_PAYLOAD |                             0100 |                              010
+STATE_WRITE_PAYLOAD_LAST |                             1000 |                              011
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'one-hot' in module 'ip_eth_tx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                               00 |                               00
+         STATE_ARP_QUERY |                               01 |                               01
+       STATE_WAIT_PACKET |                               10 |                               10
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'ip'
+WARNING: [Synth 8-6430] The Block RAM "arp_cache:/ip_addr_mem_reg" may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision 
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                               00 |                              000
+       STATE_READ_HEADER |                               01 |                              001
+      STATE_READ_PAYLOAD |                               10 |                              010
+ STATE_READ_PAYLOAD_LAST |                               11 |                              011
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'udp_ip_rx'
+---------------------------------------------------------------------------------------------------
+                   State |                     New Encoding |                Previous Encoding 
+---------------------------------------------------------------------------------------------------
+              STATE_IDLE |                               00 |                              000
+      STATE_WRITE_HEADER |                               01 |                              001
+     STATE_WRITE_PAYLOAD |                               10 |                              010
+STATE_WRITE_PAYLOAD_LAST |                               11 |                              011
+---------------------------------------------------------------------------------------------------
+INFO: [Synth 8-3354] encoded FSM with state register 'state_reg_reg' using encoding 'sequential' in module 'udp_ip_tx'
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:46 ; elapsed = 00:00:47 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49818 ; free virtual = 54827
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics 
+---------------------------------------------------------------------------------
+Detailed RTL Component Info : 
++---Adders : 
+	   2 Input   36 Bit       Adders := 1     
+	   2 Input   32 Bit       Adders := 1     
+	   3 Input   32 Bit       Adders := 3     
+	   2 Input   17 Bit       Adders := 12    
+	   2 Input   16 Bit       Adders := 13    
+	   3 Input   14 Bit       Adders := 1     
+	   2 Input   14 Bit       Adders := 1     
+	   2 Input   13 Bit       Adders := 4     
+	   3 Input   13 Bit       Adders := 8     
+	   3 Input   12 Bit       Adders := 1     
+	   2 Input   12 Bit       Adders := 1     
+	   2 Input    9 Bit       Adders := 1     
+	   2 Input    8 Bit       Adders := 1     
+	   2 Input    7 Bit       Adders := 1     
+	   2 Input    6 Bit       Adders := 5     
+	   2 Input    5 Bit       Adders := 2     
+	   2 Input    4 Bit       Adders := 4     
+	   2 Input    3 Bit       Adders := 3     
+	   2 Input    2 Bit       Adders := 1     
++---XORs : 
+	   2 Input     32 Bit         XORs := 1     
+	   2 Input     14 Bit         XORs := 1     
+	   2 Input     13 Bit         XORs := 10    
+	   2 Input     12 Bit         XORs := 1     
+	   2 Input      2 Bit         XORs := 1     
+	   2 Input      1 Bit         XORs := 167   
+	   3 Input      1 Bit         XORs := 44    
+	   4 Input      1 Bit         XORs := 20    
+	   5 Input      1 Bit         XORs := 20    
+	   6 Input      1 Bit         XORs := 20    
+	   8 Input      1 Bit         XORs := 14    
+	   7 Input      1 Bit         XORs := 12    
+	   9 Input      1 Bit         XORs := 10    
+	  10 Input      1 Bit         XORs := 6     
+	  12 Input      1 Bit         XORs := 6     
+	  14 Input      1 Bit         XORs := 4     
+	  17 Input      1 Bit         XORs := 8     
+	  13 Input      1 Bit         XORs := 4     
+	  16 Input      1 Bit         XORs := 12    
+	  20 Input      1 Bit         XORs := 8     
+	  21 Input      1 Bit         XORs := 2     
+	  15 Input      1 Bit         XORs := 10    
+	  19 Input      1 Bit         XORs := 2     
+	  11 Input      1 Bit         XORs := 4     
+	  24 Input      1 Bit         XORs := 2     
+	  22 Input      1 Bit         XORs := 4     
+	  23 Input      1 Bit         XORs := 2     
+	  18 Input      1 Bit         XORs := 4     
++---XORs : 
+	               13 Bit    Wide XORs := 48    
++---Registers : 
+	               48 Bit    Registers := 32    
+	               36 Bit    Registers := 1     
+	               32 Bit    Registers := 22    
+	               16 Bit    Registers := 52    
+	               14 Bit    Registers := 1     
+	               13 Bit    Registers := 36    
+	               12 Bit    Registers := 1     
+	               10 Bit    Registers := 8     
+	                9 Bit    Registers := 2     
+	                8 Bit    Registers := 44    
+	                7 Bit    Registers := 1     
+	                6 Bit    Registers := 11    
+	                5 Bit    Registers := 2     
+	                4 Bit    Registers := 18    
+	                3 Bit    Registers := 11    
+	                2 Bit    Registers := 26    
+	                1 Bit    Registers := 256   
++---RAMs : 
+	              80K Bit	(8192 X 10 bit)          RAMs := 1     
+	              40K Bit	(4096 X 10 bit)          RAMs := 2     
+	              24K Bit	(512 X 48 bit)          RAMs := 1     
+	              20K Bit	(2048 X 10 bit)          RAMs := 1     
+	              16K Bit	(512 X 32 bit)          RAMs := 1     
+	              512 Bit	(512 X 1 bit)          RAMs := 1     
+	              384 Bit	(8 X 48 bit)          RAMs := 2     
+	              256 Bit	(8 X 32 bit)          RAMs := 2     
+	              128 Bit	(8 X 16 bit)          RAMs := 7     
+	              104 Bit	(8 X 13 bit)          RAMs := 1     
+	               64 Bit	(8 X 8 bit)          RAMs := 1     
+	               48 Bit	(8 X 6 bit)          RAMs := 1     
+	               32 Bit	(8 X 4 bit)          RAMs := 2     
+	               24 Bit	(8 X 3 bit)          RAMs := 1     
+	               16 Bit	(8 X 2 bit)          RAMs := 1     
++---Muxes : 
+	   2 Input   48 Bit        Muxes := 21    
+	   6 Input   36 Bit        Muxes := 1     
+	   3 Input   36 Bit        Muxes := 1     
+	   2 Input   36 Bit        Muxes := 1     
+	   2 Input   32 Bit        Muxes := 14    
+	   7 Input   32 Bit        Muxes := 1     
+	   5 Input   28 Bit        Muxes := 1     
+	   2 Input   16 Bit        Muxes := 14    
+	   5 Input   16 Bit        Muxes := 2     
+	  21 Input   16 Bit        Muxes := 1     
+	   4 Input   16 Bit        Muxes := 3     
+	   7 Input   16 Bit        Muxes := 3     
+	   2 Input   13 Bit        Muxes := 25    
+	   2 Input    9 Bit        Muxes := 1     
+	   2 Input    8 Bit        Muxes := 76    
+	   3 Input    8 Bit        Muxes := 1     
+	   4 Input    8 Bit        Muxes := 4     
+	   7 Input    8 Bit        Muxes := 3     
+	   5 Input    8 Bit        Muxes := 1     
+	   3 Input    7 Bit        Muxes := 1     
+	   2 Input    6 Bit        Muxes := 6     
+	   7 Input    6 Bit        Muxes := 1     
+	   5 Input    6 Bit        Muxes := 1     
+	   4 Input    6 Bit        Muxes := 1     
+	   6 Input    6 Bit        Muxes := 1     
+	   2 Input    5 Bit        Muxes := 4     
+	   2 Input    4 Bit        Muxes := 18    
+	   4 Input    4 Bit        Muxes := 1     
+	  21 Input    4 Bit        Muxes := 1     
+	   3 Input    3 Bit        Muxes := 8     
+	   2 Input    3 Bit        Muxes := 14    
+	   7 Input    3 Bit        Muxes := 3     
+	  21 Input    3 Bit        Muxes := 1     
+	   5 Input    3 Bit        Muxes := 1     
+	  38 Input    3 Bit        Muxes := 1     
+	   4 Input    3 Bit        Muxes := 5     
+	   3 Input    2 Bit        Muxes := 6     
+	   2 Input    2 Bit        Muxes := 46    
+	   4 Input    2 Bit        Muxes := 6     
+	  22 Input    2 Bit        Muxes := 1     
+	  10 Input    2 Bit        Muxes := 1     
+	   8 Input    2 Bit        Muxes := 3     
+	   2 Input    1 Bit        Muxes := 389   
+	   3 Input    1 Bit        Muxes := 16    
+	   7 Input    1 Bit        Muxes := 22    
+	  21 Input    1 Bit        Muxes := 25    
+	   5 Input    1 Bit        Muxes := 34    
+	   4 Input    1 Bit        Muxes := 43    
+	   8 Input    1 Bit        Muxes := 11    
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics 
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 740 (col length:100)
+BRAMs: 730 (col length: RAMB18 100 RAMB36 50)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance. 
+RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance. 
+WARNING: [Synth 8-6430] The Block RAM "\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst/ip_addr_mem_reg " may get memory collision error if read and write address collide. Use attribute (* rw_addr_collision= "yes" *) to avoid collision 
+RAM Pipeline Warning: Read Address Register Found For RAM ip_addr_mem_reg. We will not be able to pipeline it. This may degrade performance. 
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:02 ; elapsed = 00:01:03 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49776 ; free virtual = 54797
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+
+ROM: Preliminary Mapping Report
++------------+-------------------------------------+---------------+----------------+
+|Module Name | RTL Object                          | Depth x Width | Implemented As | 
++------------+-------------------------------------+---------------+----------------+
+|ip_complete | ip_inst/ip_eth_tx_inst/hdr_sum_next | 32x1          | LUT            | 
++------------+-------------------------------------+---------------+----------------+
+
+
+Block RAM: Preliminary Mapping Report (see note below)
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+|Module Name                                                              | RTL Object                                       | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+|fpga                                                                     | core_inst/eth_mac_inst/tx_fifo/fifo_inst/mem_reg | 4 K x 10(READ_FIRST)   | W |   | 4 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      | 
+|fpga                                                                     | core_inst/eth_mac_inst/rx_fifo/fifo_inst/mem_reg | 4 K x 10(NO_CHANGE)    | W |   | 4 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      | 
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | ip_addr_mem_reg                                  | 512 x 32(READ_FIRST)   | W |   | 512 x 32(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      | 
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | mac_addr_mem_reg                                 | 512 x 48(READ_FIRST)   | W |   | 512 x 48(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/payload_fifo/mem_reg       | 2 K x 10(READ_FIRST)   | W |   | 2 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
+|fpga                                                                     | core_inst/udp_payload_fifo/mem_reg               | 8 K x 10(READ_FIRST)   | W |   | 8 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 2      | 
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+
+Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 
+
+Distributed RAM: Preliminary Mapping Report (see note below)
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+|Module Name                                                              | RTL Object                                    | Inference | Size (Depth x Width) | Primitives     | 
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | valid_mem_reg                                 | Implied   | 512 x 1              | RAM128X1D x 4  | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_length_mem_reg      | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_ttl_mem_reg          | Implied   | 8 x 8                | RAM32M x 2     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_source_ip_mem_reg    | Implied   | 8 x 32               | RAM32M x 6     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_dest_ip_mem_reg      | Implied   | 8 x 32               | RAM32M x 6     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_source_port_mem_reg | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_dest_port_mem_reg   | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_checksum_mem_reg    | Implied   | 8 x 16               | RAM32M x 3     | 
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+
+Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl. [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
+WARNING: [Synth 8-3321] set_false_path : Empty to list for constraint at line 23 of /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl. [/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl:23]
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:10 ; elapsed = 00:01:11 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49746 ; free virtual = 54767
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:01:14 ; elapsed = 00:01:15 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49703 ; free virtual = 54724
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+
+Block RAM: Final Mapping Report
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+|Module Name                                                              | RTL Object                                       | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+|fpga                                                                     | core_inst/eth_mac_inst/tx_fifo/fifo_inst/mem_reg | 4 K x 10(READ_FIRST)   | W |   | 4 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      | 
+|fpga                                                                     | core_inst/eth_mac_inst/rx_fifo/fifo_inst/mem_reg | 4 K x 10(NO_CHANGE)    | W |   | 4 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 1      | 
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | ip_addr_mem_reg                                  | 512 x 32(READ_FIRST)   | W |   | 512 x 32(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      | 
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | mac_addr_mem_reg                                 | 512 x 48(READ_FIRST)   | W |   | 512 x 48(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/payload_fifo/mem_reg       | 2 K x 10(READ_FIRST)   | W |   | 2 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 0      | 1      | 
+|fpga                                                                     | core_inst/udp_payload_fifo/mem_reg               | 8 K x 10(READ_FIRST)   | W |   | 8 K x 10(WRITE_FIRST)  |   | R | Port A and B     | 1      | 2      | 
++-------------------------------------------------------------------------+--------------------------------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
+
+
+Distributed RAM: Final Mapping Report
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+|Module Name                                                              | RTL Object                                    | Inference | Size (Depth x Width) | Primitives     | 
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+|\core_inst/udp_complete_inst /ip_complete_inst/\arp_inst/arp_cache_inst  | valid_mem_reg                                 | Implied   | 512 x 1              | RAM128X1D x 4  | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_length_mem_reg      | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_ttl_mem_reg          | Implied   | 8 x 8                | RAM32M x 2     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_source_ip_mem_reg    | Implied   | 8 x 32               | RAM32M x 6     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/ip_dest_ip_mem_reg      | Implied   | 8 x 32               | RAM32M x 6     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_source_port_mem_reg | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_dest_port_mem_reg   | Implied   | 8 x 16               | RAM32M x 3     | 
+|\core_inst/udp_complete_inst /udp_inst                                   | udp_checksum_gen_inst/udp_checksum_mem_reg    | Implied   | 8 x 16               | RAM32M x 3     | 
++-------------------------------------------------------------------------+-----------------------------------------------+-----------+----------------------+----------------+
+
+---------------------------------------------------------------------------------
+Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+INFO: [Synth 8-7052] The timing for the instance core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/ip_addr_mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
+INFO: [Synth 8-7052] The timing for the instance core_inst/udp_complete_inst/ip_complete_inst/arp_inst/arp_cache_inst/mac_addr_mem_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49717 ; free virtual = 54738
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:01:22 ; elapsed = 00:01:23 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:01:22 ; elapsed = 00:01:23 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes: 
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage: 
++------+------------+------+
+|      |Cell        |Count |
++------+------------+------+
+|1     |BUFG        |     3|
+|2     |BUFIO       |     1|
+|3     |BUFR        |     1|
+|4     |CARRY4      |   200|
+|5     |IDDR        |     5|
+|6     |IDELAYCTRL  |     1|
+|7     |IDELAYE2    |     5|
+|8     |LUT1        |   173|
+|9     |LUT2        |   265|
+|10    |LUT3        |   403|
+|11    |LUT4        |   241|
+|12    |LUT5        |   351|
+|13    |LUT6        |   648|
+|14    |MMCME2_BASE |     1|
+|15    |MUXF7       |     9|
+|16    |ODDR        |     6|
+|17    |RAM128X1D   |     4|
+|18    |RAM32M      |    19|
+|19    |RAMB18E1    |     4|
+|23    |RAMB36E1    |     6|
+|28    |FDPE        |    14|
+|29    |FDRE        |  2581|
+|30    |FDSE        |   166|
+|31    |IBUF        |     7|
+|32    |IBUFGDS     |     1|
+|33    |OBUF        |     7|
++------+------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 110 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:01:17 ; elapsed = 00:01:18 . Memory (MB): peak = 2525.734 ; gain = 687.387 ; free physical = 49754 ; free virtual = 54775
+Synthesis Optimization Complete : Time (s): cpu = 00:01:23 ; elapsed = 00:01:24 . Memory (MB): peak = 2525.734 ; gain = 832.137 ; free physical = 49754 ; free virtual = 54775
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2525.734 ; gain = 0.000 ; free physical = 50047 ; free virtual = 55068
+INFO: [Netlist 29-17] Analyzing 261 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2525.734 ; gain = 0.000 ; free physical = 50051 ; free virtual = 55072
+INFO: [Project 1-111] Unisim Transformation Summary:
+  A total of 25 instances were transformed.
+  IBUFGDS => IBUFDS: 1 instance 
+  MMCME2_BASE => MMCME2_ADV: 1 instance 
+  RAM128X1D => RAM128X1D (MUXF7(x2), RAMD64E(x4)): 4 instances
+  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 19 instances
+
+Synth Design complete | Checksum: e689d0a8
+INFO: [Common 17-83] Releasing license: Synthesis
+152 Infos, 298 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:01:34 ; elapsed = 00:01:31 . Memory (MB): peak = 2525.734 ; gain = 1189.949 ; free physical = 50051 ; free virtual = 55072
+INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2021.381; main = 1692.642; forked = 352.937
+INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3471.828; main = 2525.738; forked = 978.105
+INFO: [Common 17-1381] The checkpoint '/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file fpga_utilization_synth.rpt -pb fpga_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Wed Jan  8 11:24:30 2025...
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/runme.sh b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/runme.sh
new file mode 100755
index 000000000..eb25ae86e
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/runme.sh
@@ -0,0 +1,40 @@
+#!/bin/sh
+
+# 
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+# 
+
+if [ -z "$PATH" ]; then
+  PATH=/home/kavya/Downloads/Downloads/Vivado/2023.1/ids_lite/ISE/bin/lin64:/home/kavya/Downloads/Downloads/Vivado/2023.1/bin
+else
+  PATH=/home/kavya/Downloads/Downloads/Vivado/2023.1/ids_lite/ISE/bin/lin64:/home/kavya/Downloads/Downloads/Vivado/2023.1/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+  LD_LIBRARY_PATH=
+else
+  LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+     $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+     if [ $? -ne 0 ]
+     then
+         exit
+     fi
+}
+
+EAStep vivado -log fpga.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source fpga.tcl
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/vivado.jou b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/vivado.jou
new file mode 100644
index 000000000..890268a0e
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/vivado.jou
@@ -0,0 +1,14 @@
+#-----------------------------------------------------------
+# Vivado v2023.1 (64-bit)
+# SW Build 3865809 on Sun May  7 15:04:56 MDT 2023
+# IP Build 3864474 on Sun May  7 20:36:21 MDT 2023
+# SharedData Build 3865790 on Sun May 07 13:33:03 MDT 2023
+# Start of session at: Wed Jan  8 11:22:41 2025
+# Process ID: 256309
+# Current directory: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1
+# Command line: vivado -log fpga.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source fpga.tcl
+# Log file: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/fpga.vds
+# Journal file: /home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/vivado.jou
+# Running On: kavya-Precision-Tower-5810, OS: Linux, CPU Frequency: 2249.015 MHz, CPU Physical cores: 12, Host memory: 67345 MB
+#-----------------------------------------------------------
+source fpga.tcl -notrace
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/vivado.pb b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/vivado.pb
new file mode 100644
index 000000000..e0baf051d
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/fpga.runs/synth_1/vivado.pb differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga.xpr b/example/AX7203_ARTIX7/fpga/fpga/fpga.xpr
new file mode 100644
index 000000000..31a526b8d
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga.xpr
@@ -0,0 +1,522 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2023.1 (64-bit)                              -->
+<!--                                                                         -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
+<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.   -->
+
+<Project Product="Vivado" Version="7" Minor="63" Path="/home/kavya/Desktop/git_kavya/verilog-ethernet/example/AX7203_ARTIX7/fpga/fpga/fpga.xpr">
+  <DefaultLaunch Dir="$PRUNDIR"/>
+  <Configuration>
+    <Option Name="Id" Val="65ca61cd27154554a547382399855c32"/>
+    <Option Name="Part" Val="xc7a200tfbg484-2"/>
+    <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+    <Option Name="CompiledLibDirXSim" Val=""/>
+    <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+    <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+    <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+    <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+    <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+    <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+    <Option Name="SimulatorInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorInstallDirVCS" Val=""/>
+    <Option Name="SimulatorInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+    <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+    <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+    <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+    <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+    <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+    <Option Name="SimulatorVersionXsim" Val="2023.1"/>
+    <Option Name="SimulatorVersionModelSim" Val="2022.3"/>
+    <Option Name="SimulatorVersionQuesta" Val="2022.3"/>
+    <Option Name="SimulatorVersionXcelium" Val="22.09.001"/>
+    <Option Name="SimulatorVersionVCS" Val="T-2022.06-SP1"/>
+    <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+    <Option Name="SimulatorVersionActiveHdl" Val="13.1"/>
+    <Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+    <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+    <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+    <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+    <Option Name="BoardPart" Val=""/>
+    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="DefaultLib" Val="xil_defaultlib"/>
+    <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+    <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+    <Option Name="IPCachePermission" Val="read"/>
+    <Option Name="IPCachePermission" Val="write"/>
+    <Option Name="EnableCoreContainer" Val="FALSE"/>
+    <Option Name="EnableResourceEstimation" Val="FALSE"/>
+    <Option Name="SimCompileState" Val="TRUE"/>
+    <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+    <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+    <Option Name="EnableBDX" Val="FALSE"/>
+    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTModelSimLaunchSim" Val="0"/>
+    <Option Name="WTQuestaLaunchSim" Val="0"/>
+    <Option Name="WTIesLaunchSim" Val="0"/>
+    <Option Name="WTVcsLaunchSim" Val="0"/>
+    <Option Name="WTRivieraLaunchSim" Val="0"/>
+    <Option Name="WTActivehdlLaunchSim" Val="0"/>
+    <Option Name="WTXSimExportSim" Val="0"/>
+    <Option Name="WTModelSimExportSim" Val="0"/>
+    <Option Name="WTQuestaExportSim" Val="0"/>
+    <Option Name="WTIesExportSim" Val="0"/>
+    <Option Name="WTVcsExportSim" Val="0"/>
+    <Option Name="WTRivieraExportSim" Val="0"/>
+    <Option Name="WTActivehdlExportSim" Val="0"/>
+    <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+    <Option Name="XSimRadix" Val="hex"/>
+    <Option Name="XSimTimeUnit" Val="ns"/>
+    <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+    <Option Name="XSimTraceLimit" Val="65536"/>
+    <Option Name="SimTypes" Val="rtl"/>
+    <Option Name="SimTypes" Val="bfm"/>
+    <Option Name="SimTypes" Val="tlm"/>
+    <Option Name="SimTypes" Val="tlm_dpi"/>
+    <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+    <Option Name="DcpsUptoDate" Val="TRUE"/>
+    <Option Name="ClassicSocBoot" Val="FALSE"/>
+    <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+  </Configuration>
+  <FileSets Version="1" Minor="31">
+    <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/arbiter.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/arp.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/arp_cache.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/arp_eth_rx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/arp_eth_tx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/axis_async_fifo.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/axis_fifo.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/axis_gmii_rx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/axis_gmii_tx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/eth_arb_mux.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/eth_axis_rx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/eth_axis_tx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/eth_mac_1g.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/eth_mac_1g_rgmii.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/eth_mac_1g_rgmii_fifo.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rtl/fpga_core.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/iddr.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/ip.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/ip_arb_mux.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/ip_complete.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/ip_eth_rx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/ip_eth_tx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/lfsr.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/oddr.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/priority_encoder.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/rgmii_phy_if.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/ssio_ddr_in.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/lib/axis/rtl/sync_reset.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/udp.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/udp_checksum_gen.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/udp_complete.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/udp_ip_rx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/udp_ip_tx.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rtl/fpga.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/defines.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../rtl/sync_signal.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/rtl/ssio_ddr_out.v">
+        <FileInfo>
+          <Attr Name="AutoDisabled" Val="1"/>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="fpga"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+      <Filter Type="Constrs"/>
+      <File Path="$PPRDIR/../fpga.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../eth.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/syn/vivado/rgmii_phy_if.tcl">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/syn/vivado/eth_mac_1g_rgmii.tcl">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/syn/vivado/eth_mac_fifo.tcl">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/../lib/eth/lib/axis/syn/vivado/sync_reset.tcl">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="ConstrsType" Val="XDC"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+      </Config>
+    </FileSet>
+    <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+      <Filter Type="Utils"/>
+      <Config>
+        <Option Name="TopAutoSet" Val="TRUE"/>
+      </Config>
+    </FileSet>
+  </FileSets>
+  <Simulators>
+    <Simulator Name="XSim">
+      <Option Name="Description" Val="Vivado Simulator"/>
+      <Option Name="CompiledLib" Val="0"/>
+    </Simulator>
+    <Simulator Name="ModelSim">
+      <Option Name="Description" Val="ModelSim Simulator"/>
+    </Simulator>
+    <Simulator Name="Questa">
+      <Option Name="Description" Val="Questa Advanced Simulator"/>
+    </Simulator>
+    <Simulator Name="Xcelium">
+      <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+    </Simulator>
+    <Simulator Name="VCS">
+      <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+    </Simulator>
+    <Simulator Name="Riviera">
+      <Option Name="Description" Val="Riviera-PRO Simulator"/>
+    </Simulator>
+  </Simulators>
+  <Runs Version="1" Minor="20">
+    <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg484-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
+        <Step Id="synth_design"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+    <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg484-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 4 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+      <Strategy Version="1" Minor="2">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
+        <Step Id="init_design"/>
+        <Step Id="opt_design"/>
+        <Step Id="power_opt_design"/>
+        <Step Id="place_design"/>
+        <Step Id="post_place_power_opt_design"/>
+        <Step Id="phys_opt_design"/>
+        <Step Id="route_design"/>
+        <Step Id="post_route_phys_opt_design"/>
+        <Step Id="write_bitstream"/>
+      </Strategy>
+      <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+      <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
+      <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+      <RQSFiles/>
+    </Run>
+  </Runs>
+  <Board/>
+  <DashboardSummary Version="1" Minor="0">
+    <Dashboards>
+      <Dashboard Name="default_dashboard">
+        <Gadgets>
+          <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+          </Gadget>
+          <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+          </Gadget>
+          <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+          </Gadget>
+          <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+          </Gadget>
+          <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+            <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+            <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+          </Gadget>
+          <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+            <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+          </Gadget>
+        </Gadgets>
+      </Dashboard>
+      <CurrentDashboard>default_dashboard</CurrentDashboard>
+    </Dashboards>
+  </DashboardSummary>
+</Project>
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga_utilization.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga_utilization.rpt
new file mode 100644
index 000000000..ae11ac27f
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga_utilization.rpt
@@ -0,0 +1,238 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:28:09 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_utilization -file fpga_utilization.rpt
+| Design       : fpga
+| Device       : xc7a200tfbg484-2
+| Speed File   : -2
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++----------------------------+------+-------+------------+-----------+-------+
+|          Site Type         | Used | Fixed | Prohibited | Available | Util% |
++----------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs                 | 1817 |     0 |          0 |    134600 |  1.35 |
+|   LUT as Logic             | 1725 |     0 |          0 |    134600 |  1.28 |
+|   LUT as Memory            |   92 |     0 |          0 |     46200 |  0.20 |
+|     LUT as Distributed RAM |   92 |     0 |            |           |       |
+|     LUT as Shift Register  |    0 |     0 |            |           |       |
+| Slice Registers            | 2761 |     0 |          0 |    269200 |  1.03 |
+|   Register as Flip Flop    | 2761 |     0 |          0 |    269200 |  1.03 |
+|   Register as Latch        |    0 |     0 |          0 |    269200 |  0.00 |
+| F7 Muxes                   |   17 |     0 |          0 |     67300 |  0.03 |
+| F8 Muxes                   |    0 |     0 |          0 |     33650 |  0.00 |
++----------------------------+------+-------+------------+-----------+-------+
+* Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0     |            _ |           - |            - |
+| 0     |            _ |           - |          Set |
+| 0     |            _ |           - |        Reset |
+| 0     |            _ |         Set |            - |
+| 0     |            _ |       Reset |            - |
+| 0     |          Yes |           - |            - |
+| 14    |          Yes |           - |          Set |
+| 0     |          Yes |           - |        Reset |
+| 166   |          Yes |         Set |            - |
+| 2581  |          Yes |       Reset |            - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+------+-------+------------+-----------+-------+
+|                  Site Type                 | Used | Fixed | Prohibited | Available | Util% |
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Slice                                      |  955 |     0 |          0 |     33650 |  2.84 |
+|   SLICEL                                   |  582 |     0 |            |           |       |
+|   SLICEM                                   |  373 |     0 |            |           |       |
+| LUT as Logic                               | 1725 |     0 |          0 |    134600 |  1.28 |
+|   using O5 output only                     |    0 |       |            |           |       |
+|   using O6 output only                     | 1364 |       |            |           |       |
+|   using O5 and O6                          |  361 |       |            |           |       |
+| LUT as Memory                              |   92 |     0 |          0 |     46200 |  0.20 |
+|   LUT as Distributed RAM                   |   92 |     0 |            |           |       |
+|     using O5 output only                   |    0 |       |            |           |       |
+|     using O6 output only                   |   16 |       |            |           |       |
+|     using O5 and O6                        |   76 |       |            |           |       |
+|   LUT as Shift Register                    |    0 |     0 |            |           |       |
+| Slice Registers                            | 2761 |     0 |          0 |    269200 |  1.03 |
+|   Register driven from within the Slice    | 1125 |       |            |           |       |
+|   Register driven from outside the Slice   | 1636 |       |            |           |       |
+|     LUT in front of the register is unused | 1237 |       |            |           |       |
+|     LUT in front of the register is used   |  399 |       |            |           |       |
+| Unique Control Sets                        |  151 |       |          0 |     33650 |  0.45 |
++--------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++-------------------+------+-------+------------+-----------+-------+
+|     Site Type     | Used | Fixed | Prohibited | Available | Util% |
++-------------------+------+-------+------------+-----------+-------+
+| Block RAM Tile    |    8 |     0 |          0 |       365 |  2.19 |
+|   RAMB36/FIFO*    |    6 |     0 |          0 |       365 |  1.64 |
+|     RAMB36E1 only |    6 |       |            |           |       |
+|   RAMB18          |    4 |     0 |          0 |       730 |  0.55 |
+|     RAMB18E1 only |    4 |       |            |           |       |
++-------------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs      |    0 |     0 |          0 |       740 |  0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+|          Site Type          | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB                  |   16 |    16 |          0 |       285 |  5.61 |
+|   IOB Master Pads           |    7 |       |            |           |       |
+|   IOB Slave Pads            |    9 |       |            |           |       |
+| Bonded IPADs                |    0 |     0 |          0 |        14 |  0.00 |
+| Bonded OPADs                |    0 |     0 |          0 |         8 |  0.00 |
+| PHY_CONTROL                 |    0 |     0 |          0 |        10 |  0.00 |
+| PHASER_REF                  |    0 |     0 |          0 |        10 |  0.00 |
+| OUT_FIFO                    |    0 |     0 |          0 |        40 |  0.00 |
+| IN_FIFO                     |    0 |     0 |          0 |        40 |  0.00 |
+| IDELAYCTRL                  |    1 |     0 |          0 |        10 | 10.00 |
+| IBUFDS                      |    1 |     1 |          0 |       274 |  0.36 |
+| GTPE2_CHANNEL               |    0 |     0 |          0 |         4 |  0.00 |
+| PHASER_OUT/PHASER_OUT_PHY   |    0 |     0 |          0 |        40 |  0.00 |
+| PHASER_IN/PHASER_IN_PHY     |    0 |     0 |          0 |        40 |  0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY |    5 |     5 |          0 |       500 |  1.00 |
+|   IDELAYE2 only             |    5 |     5 |            |           |       |
+| IBUFDS_GTE2                 |    0 |     0 |          0 |         2 |  0.00 |
+| ILOGIC                      |    5 |     5 |          0 |       285 |  1.75 |
+|   IFF_IDDR_Register         |    5 |     5 |            |           |       |
+| OLOGIC                      |    6 |     6 |          0 |       285 |  2.11 |
+|   OUTFF_ODDR_Register       |    6 |     6 |            |           |       |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++--------------+------+-------+------------+-----------+-------+
+|   Site Type  | Used | Fixed | Prohibited | Available | Util% |
++--------------+------+-------+------------+-----------+-------+
+| BUFGCTRL     |    3 |     0 |          0 |        32 |  9.38 |
+| BUFIO        |    1 |     1 |          0 |        40 |  2.50 |
+|   BUFIO only |    1 |     1 |            |           |       |
+| MMCME2_ADV   |    1 |     0 |          0 |        10 | 10.00 |
+| PLLE2_ADV    |    0 |     0 |          0 |        10 |  0.00 |
+| BUFMRCE      |    0 |     0 |          0 |        20 |  0.00 |
+| BUFHCE       |    0 |     0 |          0 |       120 |  0.00 |
+| BUFR         |    1 |     0 |          0 |        40 |  2.50 |
++--------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+|  Site Type  | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2     |    0 |     0 |          0 |         4 |  0.00 |
+| CAPTUREE2   |    0 |     0 |          0 |         1 |  0.00 |
+| DNA_PORT    |    0 |     0 |          0 |         1 |  0.00 |
+| EFUSE_USR   |    0 |     0 |          0 |         1 |  0.00 |
+| FRAME_ECCE2 |    0 |     0 |          0 |         1 |  0.00 |
+| ICAPE2      |    0 |     0 |          0 |         2 |  0.00 |
+| PCIE_2_1    |    0 |     0 |          0 |         1 |  0.00 |
+| STARTUPE2   |    0 |     0 |          0 |         1 |  0.00 |
+| XADC        |    0 |     0 |          0 |         1 |  0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++------------+------+---------------------+
+|  Ref Name  | Used | Functional Category |
++------------+------+---------------------+
+| FDRE       | 2581 |        Flop & Latch |
+| LUT6       |  649 |                 LUT |
+| LUT3       |  403 |                 LUT |
+| LUT5       |  355 |                 LUT |
+| LUT2       |  264 |                 LUT |
+| LUT4       |  246 |                 LUT |
+| CARRY4     |  200 |          CarryLogic |
+| LUT1       |  169 |                 LUT |
+| FDSE       |  166 |        Flop & Latch |
+| RAMD32     |  114 |  Distributed Memory |
+| RAMS32     |   38 |  Distributed Memory |
+| MUXF7      |   17 |               MuxFx |
+| RAMD64E    |   16 |  Distributed Memory |
+| FDPE       |   14 |        Flop & Latch |
+| OBUF       |    7 |                  IO |
+| IBUF       |    7 |                  IO |
+| RAMB36E1   |    6 |        Block Memory |
+| ODDR       |    6 |                  IO |
+| IDELAYE2   |    5 |                  IO |
+| IDDR       |    5 |                  IO |
+| RAMB18E1   |    4 |        Block Memory |
+| BUFG       |    3 |               Clock |
+| MMCME2_ADV |    1 |               Clock |
+| IDELAYCTRL |    1 |                  IO |
+| IBUFDS     |    1 |                  IO |
+| BUFR       |    1 |               Clock |
+| BUFIO      |    1 |               Clock |
++------------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/fpga_utilization_hierarchical.rpt b/example/AX7203_ARTIX7/fpga/fpga/fpga_utilization_hierarchical.rpt
new file mode 100644
index 000000000..b8964d999
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/fpga_utilization_hierarchical.rpt
@@ -0,0 +1,82 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2023.1 (lin64) Build 3865809 Sun May  7 15:04:56 MDT 2023
+| Date         : Wed Jan  8 11:28:09 2025
+| Host         : kavya-Precision-Tower-5810 running 64-bit Ubuntu 22.04.5 LTS
+| Command      : report_utilization -hierarchical -file fpga_utilization_hierarchical.rpt
+| Design       : fpga
+| Device       : xc7a200tfbg484-2
+| Speed File   : -2
+| Design State : Routed
+---------------------------------------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Utilization by Hierarchy
+
+1. Utilization by Hierarchy
+---------------------------
+
++-----------------------------------+-----------------------------------------+------------+------------+---------+------+------+--------+--------+------------+
+|              Instance             |                  Module                 | Total LUTs | Logic LUTs | LUTRAMs | SRLs |  FFs | RAMB36 | RAMB18 | DSP Blocks |
++-----------------------------------+-----------------------------------------+------------+------------+---------+------+------+--------+--------+------------+
+| fpga                              |                                   (top) |       1817 |       1725 |      92 |    0 | 2761 |      6 |      4 |          0 |
+|   (fpga)                          |                                   (top) |          0 |          0 |       0 |    0 |    9 |      0 |      0 |          0 |
+|   core_inst                       |                               fpga_core |       1814 |       1722 |      92 |    0 | 2748 |      6 |      4 |          0 |
+|     (core_inst)                   |                               fpga_core |          2 |          2 |       0 |    0 |    2 |      0 |      0 |          0 |
+|     eth_axis_rx_inst              |                             eth_axis_rx |         39 |         39 |       0 |    0 |   95 |      0 |      0 |          0 |
+|     eth_axis_tx_inst              |                             eth_axis_tx |         51 |         51 |       0 |    0 |   81 |      0 |      0 |          0 |
+|     eth_mac_inst                  |                   eth_mac_1g_rgmii_fifo |        366 |        366 |       0 |    0 |  506 |      2 |      2 |          0 |
+|       eth_mac_1g_rgmii_inst       |                        eth_mac_1g_rgmii |        212 |        212 |       0 |    0 |  212 |      0 |      0 |          0 |
+|         (eth_mac_1g_rgmii_inst)   |                        eth_mac_1g_rgmii |         13 |         13 |       0 |    0 |   22 |      0 |      0 |          0 |
+|         eth_mac_1g_inst           |                              eth_mac_1g |        177 |        177 |       0 |    0 |  173 |      0 |      0 |          0 |
+|           axis_gmii_rx_inst       |                            axis_gmii_rx |         75 |         75 |       0 |    0 |   98 |      0 |      0 |          0 |
+|             (axis_gmii_rx_inst)   |                            axis_gmii_rx |         42 |         42 |       0 |    0 |   98 |      0 |      0 |          0 |
+|             eth_crc_8             |                                  lfsr_1 |         33 |         33 |       0 |    0 |    0 |      0 |      0 |          0 |
+|           axis_gmii_tx_inst       |                            axis_gmii_tx |        102 |        102 |       0 |    0 |   75 |      0 |      0 |          0 |
+|             (axis_gmii_tx_inst)   |                            axis_gmii_tx |         69 |         69 |       0 |    0 |   75 |      0 |      0 |          0 |
+|             eth_crc_8             |                                    lfsr |         33 |         33 |       0 |    0 |    0 |      0 |      0 |          0 |
+|         rgmii_phy_if_inst         |                            rgmii_phy_if |         23 |         23 |       0 |    0 |   17 |      0 |      0 |          0 |
+|           (rgmii_phy_if_inst)     |                            rgmii_phy_if |         17 |         17 |       0 |    0 |   17 |      0 |      0 |          0 |
+|           clk_oddr_inst           |                                    oddr |          0 |          0 |       0 |    0 |    0 |      0 |      0 |          0 |
+|           data_oddr_inst          |                    oddr__parameterized0 |          0 |          0 |       0 |    0 |    0 |      0 |      0 |          0 |
+|           rx_ssio_ddr_inst        |                             ssio_ddr_in |          6 |          6 |       0 |    0 |    0 |      0 |      0 |          0 |
+|             (rx_ssio_ddr_inst)    |                             ssio_ddr_in |          0 |          0 |       0 |    0 |    0 |      0 |      0 |          0 |
+|             data_iddr_inst        |                                    iddr |          6 |          6 |       0 |    0 |    0 |      0 |      0 |          0 |
+|       rx_fifo                     | axis_async_fifo_adapter__parameterized0 |         68 |         68 |       0 |    0 |  147 |      1 |      1 |          0 |
+|         fifo_inst                 |         axis_async_fifo__parameterized0 |         68 |         68 |       0 |    0 |  147 |      1 |      1 |          0 |
+|       tx_fifo                     |                 axis_async_fifo_adapter |         88 |         88 |       0 |    0 |  147 |      1 |      1 |          0 |
+|         fifo_inst                 |                         axis_async_fifo |         88 |         88 |       0 |    0 |  147 |      1 |      1 |          0 |
+|     udp_complete_inst             |                            udp_complete |       1337 |       1245 |      92 |    0 | 2021 |      2 |      1 |          0 |
+|       (udp_complete_inst)         |                            udp_complete |          0 |          0 |       0 |    0 |    2 |      0 |      0 |          0 |
+|       ip_arb_mux_inst             |                              ip_arb_mux |         34 |         34 |       0 |    0 |   90 |      0 |      0 |          0 |
+|         (ip_arb_mux_inst)         |                              ip_arb_mux |         27 |         27 |       0 |    0 |   89 |      0 |      0 |          0 |
+|         arb_inst                  |                               arbiter_0 |          7 |          7 |       0 |    0 |    1 |      0 |      0 |          0 |
+|       ip_complete_inst            |                             ip_complete |        839 |        823 |      16 |    0 | 1339 |      1 |      1 |          0 |
+|         (ip_complete_inst)        |                             ip_complete |          0 |          0 |       0 |    0 |    3 |      0 |      0 |          0 |
+|         arp_inst                  |                                     arp |        385 |        369 |      16 |    0 |  874 |      1 |      1 |          0 |
+|           (arp_inst)              |                                     arp |         71 |         71 |       0 |    0 |  317 |      0 |      0 |          0 |
+|           arp_cache_inst          |                               arp_cache |        159 |        143 |      16 |    0 |  113 |      1 |      1 |          0 |
+|           arp_eth_rx_inst         |                              arp_eth_rx |         98 |         98 |       0 |    0 |  283 |      0 |      0 |          0 |
+|           arp_eth_tx_inst         |                              arp_eth_tx |         58 |         58 |       0 |    0 |  161 |      0 |      0 |          0 |
+|         eth_arb_mux_inst          |                             eth_arb_mux |         31 |         31 |       0 |    0 |   80 |      0 |      0 |          0 |
+|           (eth_arb_mux_inst)      |                             eth_arb_mux |          4 |          4 |       0 |    0 |   77 |      0 |      0 |          0 |
+|           arb_inst                |                                 arbiter |         27 |         27 |       0 |    0 |    3 |      0 |      0 |          0 |
+|         ip_inst                   |                                      ip |        423 |        423 |       0 |    0 |  382 |      0 |      0 |          0 |
+|           (ip_inst)               |                                      ip |          4 |          4 |       0 |    0 |   55 |      0 |      0 |          0 |
+|           ip_eth_rx_inst          |                               ip_eth_rx |        148 |        148 |       0 |    0 |  139 |      0 |      0 |          0 |
+|           ip_eth_tx_inst          |                               ip_eth_tx |        271 |        271 |       0 |    0 |  188 |      0 |      0 |          0 |
+|       udp_inst                    |                                     udp |        465 |        389 |      76 |    0 |  590 |      1 |      0 |          0 |
+|         udp_checksum_gen_inst     |                        udp_checksum_gen |        255 |        179 |      76 |    0 |  274 |      1 |      0 |          0 |
+|           (udp_checksum_gen_inst) |                        udp_checksum_gen |        233 |        157 |      76 |    0 |  237 |      0 |      0 |          0 |
+|           payload_fifo            |                               axis_fifo |         22 |         22 |       0 |    0 |   37 |      1 |      0 |          0 |
+|         udp_ip_rx_inst            |                               udp_ip_rx |         95 |         95 |       0 |    0 |  135 |      0 |      0 |          0 |
+|         udp_ip_tx_inst            |                               udp_ip_tx |        116 |        116 |       0 |    0 |  181 |      0 |      0 |          0 |
+|     udp_payload_fifo              |               axis_fifo__parameterized0 |         27 |         27 |       0 |    0 |   43 |      2 |      1 |          0 |
+|   sync_reset_inst                 |                              sync_reset |          3 |          3 |       0 |    0 |    4 |      0 |      0 |          0 |
++-----------------------------------+-----------------------------------------+------------+------------+---------+------+------+--------+--------+------------+
+* Note: The sum of lower-level cells may be larger than their parent cells total, due to cross-hierarchy LUT combining
+
+
diff --git a/example/AX7203_ARTIX7/fpga/fpga/generate_bit.tcl b/example/AX7203_ARTIX7/fpga/fpga/generate_bit.tcl
new file mode 100644
index 000000000..a903eabc7
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/generate_bit.tcl
@@ -0,0 +1,4 @@
+open_project fpga.xpr
+open_run impl_1
+write_bitstream -force fpga.runs/impl_1/fpga.bit
+write_debug_probes -force fpga.runs/impl_1/fpga.ltx
diff --git a/example/AX7203_ARTIX7/fpga/fpga/generate_bit_iodelay.tcl b/example/AX7203_ARTIX7/fpga/fpga/generate_bit_iodelay.tcl
new file mode 100644
index 000000000..d97f96678
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/generate_bit_iodelay.tcl
@@ -0,0 +1,6 @@
+open_project fpga.xpr
+open_run impl_1
+set_property IDELAY_VALUE 0 [get_cells {phy_rx_ctl_idelay phy_rxd_idelay_*}]
+set_property CLKOUT1_PHASE 90 [get_cells clk_mmcm_inst]
+write_bitstream -force fpga.bit
+exit
diff --git a/example/AX7203_ARTIX7/fpga/fpga/rev/fpga_rev100.bit b/example/AX7203_ARTIX7/fpga/fpga/rev/fpga_rev100.bit
new file mode 100644
index 000000000..7fd84efaf
Binary files /dev/null and b/example/AX7203_ARTIX7/fpga/fpga/rev/fpga_rev100.bit differ
diff --git a/example/AX7203_ARTIX7/fpga/fpga/run_impl.tcl b/example/AX7203_ARTIX7/fpga/fpga/run_impl.tcl
new file mode 100644
index 000000000..b8aa5510b
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/run_impl.tcl
@@ -0,0 +1,7 @@
+open_project fpga.xpr
+reset_run impl_1
+launch_runs -jobs 4 impl_1
+wait_on_run impl_1
+open_run impl_1
+report_utilization -file fpga_utilization.rpt
+report_utilization -hierarchical -file fpga_utilization_hierarchical.rpt
diff --git a/example/AX7203_ARTIX7/fpga/fpga/run_synth.tcl b/example/AX7203_ARTIX7/fpga/fpga/run_synth.tcl
new file mode 100644
index 000000000..c1597cbd9
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/run_synth.tcl
@@ -0,0 +1,4 @@
+open_project fpga.xpr
+reset_run synth_1
+launch_runs -jobs 4 synth_1
+wait_on_run synth_1
diff --git a/example/AX7203_ARTIX7/fpga/fpga/update_config.tcl b/example/AX7203_ARTIX7/fpga/fpga/update_config.tcl
new file mode 100644
index 000000000..b1fa9b94c
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/fpga/update_config.tcl
@@ -0,0 +1 @@
+open_project -quiet fpga.xpr
diff --git a/example/AX7203_ARTIX7/fpga/lib/eth b/example/AX7203_ARTIX7/fpga/lib/eth
new file mode 120000
index 000000000..11a54ed36
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/lib/eth
@@ -0,0 +1 @@
+../../../../
\ No newline at end of file
diff --git a/example/AX7203_ARTIX7/fpga/rtl/fpga.v b/example/AX7203_ARTIX7/fpga/rtl/fpga.v
new file mode 100644
index 000000000..4322c29fc
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/rtl/fpga.v
@@ -0,0 +1,275 @@
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga (
+    /*
+     * Clock: 100MHz
+     * Reset: Push button, active low
+     */
+    input  wire       clk_p,
+    input   wire      clk_n,
+    input  wire       reset_n,
+
+
+    /*
+     * Ethernet: 1000BASE-T RGMII
+     */
+    input  wire       phy_rx_clk,
+    input  wire [3:0] phy_rxd,
+    input  wire       phy_rx_ctl,
+    output wire       phy_tx_clk,
+    output wire [3:0] phy_txd,
+    output wire       phy_tx_ctl,
+    output wire       phy_reset_n 
+);
+
+wire clk_ibufg;
+// Clock and reset
+IBUFGDS
+clk_200mhz_ibufgds_inst(
+    .I(clk_p),
+    .IB(clk_n),
+    .O(clk_ibufg)
+);
+
+// Internal 125 MHz clock
+wire clk_mmcm_out;
+wire clk_int;
+wire rst_int;   
+
+wire mmcm_rst = ~reset_n;
+wire mmcm_locked;
+wire mmcm_clkfb;
+wire clk90_mmcm_out;
+wire clk90_int;
+
+wire clk_200_mmcm_out;
+wire clk_200_int;
+
+// MMCM instance
+// 200 MHz in, 125 MHz out
+// PFD range: 10 MHz to 500 MHz
+// VCO range: 600 MHz to 1440 MHz
+// M = 5, D = 1 sets Fvco = 1000 MHz (in range)
+// Divide by 8 to get output frequency of 125 MHz
+// Need two 125 MHz outputs with 90 degree offset
+// Also need 200 MHz out for IODELAY
+// 1000 / 5 = 200 MHz
+MMCME2_BASE #(
+    .BANDWIDTH("OPTIMIZED"),
+    .CLKOUT0_DIVIDE_F(8),
+    .CLKOUT0_DUTY_CYCLE(0.5),
+    .CLKOUT0_PHASE(0),
+    .CLKOUT1_DIVIDE(8),
+    .CLKOUT1_DUTY_CYCLE(0.5),
+    .CLKOUT1_PHASE(90),
+    .CLKOUT2_DIVIDE(5),
+    .CLKOUT2_DUTY_CYCLE(0.5),
+    .CLKOUT2_PHASE(0),
+    .CLKOUT3_DIVIDE(1),
+    .CLKOUT3_DUTY_CYCLE(0.5),
+    .CLKOUT3_PHASE(0),
+    .CLKOUT4_DIVIDE(1),
+    .CLKOUT4_DUTY_CYCLE(0.5),
+    .CLKOUT4_PHASE(0),
+    .CLKOUT5_DIVIDE(1),
+    .CLKOUT5_DUTY_CYCLE(0.5),
+    .CLKOUT5_PHASE(0),
+    .CLKOUT6_DIVIDE(1),
+    .CLKOUT6_DUTY_CYCLE(0.5),
+    .CLKOUT6_PHASE(0),
+    .CLKFBOUT_MULT_F(5),
+    .CLKFBOUT_PHASE(0),
+    .DIVCLK_DIVIDE(1),
+    .REF_JITTER1(0.010),
+    .CLKIN1_PERIOD(5.0),
+    .STARTUP_WAIT("FALSE"),
+    .CLKOUT4_CASCADE("FALSE")
+)
+clk_mmcm_inst (
+    .CLKIN1(clk_ibufg),
+    .CLKFBIN(mmcm_clkfb),
+    .RST(mmcm_rst),
+    .PWRDWN(1'b0),
+    .CLKOUT0(clk_mmcm_out),
+    .CLKOUT0B(),
+    .CLKOUT1(clk90_mmcm_out),
+    .CLKOUT1B(),
+    .CLKOUT2(clk_200_mmcm_out),
+    .CLKOUT2B(),
+    .CLKOUT3(),
+    .CLKOUT3B(),
+    .CLKOUT4(),
+    .CLKOUT5(),
+    .CLKOUT6(),
+    .CLKFBOUT(mmcm_clkfb),
+    .CLKFBOUTB(),
+    .LOCKED(mmcm_locked)
+);
+BUFG
+clk_bufg_inst (
+    .I(clk_mmcm_out),
+    .O(clk_int)
+);
+
+BUFG
+clk90_bufg_inst (
+    .I(clk90_mmcm_out),
+    .O(clk90_int)
+);
+
+BUFG
+clk_200_bufg_inst (
+    .I(clk_200_mmcm_out),
+    .O(clk_200_int)
+);
+sync_reset #(
+    .N(4)
+)
+sync_reset_inst (
+    .clk(clk_int),
+    .rst(~mmcm_locked),
+    .out(rst_int)
+);
+
+// IODELAY elements for RGMII interface to PHY
+wire [3:0] phy_rxd_delay;
+wire       phy_rx_ctl_delay;
+
+IDELAYCTRL
+idelayctrl_inst
+(
+    .REFCLK(clk_200_int),
+    .RST(rst_int),
+    .RDY()
+);
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rxd_idelay_0
+(
+    .IDATAIN(phy_rxd[0]),
+    .DATAOUT(phy_rxd_delay[0]),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rxd_idelay_1
+(
+    .IDATAIN(phy_rxd[1]),
+    .DATAOUT(phy_rxd_delay[1]),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rxd_idelay_2
+(
+    .IDATAIN(phy_rxd[2]),
+    .DATAOUT(phy_rxd_delay[2]),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rxd_idelay_3
+(
+    .IDATAIN(phy_rxd[3]),
+    .DATAOUT(phy_rxd_delay[3]),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+IDELAYE2 #(
+    .IDELAY_TYPE("FIXED")
+)
+phy_rx_ctl_idelay
+(
+    .IDATAIN(phy_rx_ctl),
+    .DATAOUT(phy_rx_ctl_delay),
+    .DATAIN(1'b0),
+    .C(1'b0),
+    .CE(1'b0),
+    .INC(1'b0),
+    .CINVCTRL(1'b0),
+    .CNTVALUEIN(5'd0),
+    .CNTVALUEOUT(),
+    .LD(1'b0),
+    .LDPIPEEN(1'b0),
+    .REGRST(1'b0)
+);
+
+fpga_core #(
+    .TARGET("XILINX")
+)
+core_inst (
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    .clk(clk_int),
+    .clk90(clk90_int),
+    .rst(rst_int),
+
+    /*
+     * Ethernet: 1000BASE-T RGMII
+     */
+    .phy_rx_clk(phy_rx_clk),
+    .phy_rxd(phy_rxd_delay),
+    .phy_rx_ctl(phy_rx_ctl_delay),
+    .phy_tx_clk(phy_tx_clk),
+    .phy_txd(phy_txd),
+    .phy_tx_ctl(phy_tx_ctl),
+    .phy_reset_n(phy_reset_n) 
+
+);
+
+endmodule
+
+`resetall
\ No newline at end of file
diff --git a/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v b/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v
new file mode 100644
index 000000000..3fc9318a1
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/rtl/fpga_core.v
@@ -0,0 +1,549 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    parameter TARGET = "GENERIC"
+)
+(
+    /*
+     * Clock: 125MHz
+     * Synchronous reset
+     */
+    input  wire       clk,
+    input  wire       clk90,
+    input  wire       rst,
+
+    /*
+     * Ethernet: 1000BASE-T RGMII
+     */
+    input  wire       phy_rx_clk,
+    input  wire [3:0] phy_rxd,
+    input  wire       phy_rx_ctl,
+    output wire       phy_tx_clk,
+    output wire [3:0] phy_txd,
+    output wire       phy_tx_ctl,
+    output wire       phy_reset_n
+);
+
+// AXI between MAC and Ethernet modules
+wire [7:0] rx_axis_tdata ;
+wire rx_axis_tvalid;
+wire rx_axis_tready;
+wire rx_axis_tlast;
+wire rx_axis_tuser;
+
+wire [7:0] tx_axis_tdata;
+wire tx_axis_tvalid;
+wire tx_axis_tready;
+wire tx_axis_tlast;
+wire tx_axis_tuser;
+
+// Ethernet frame between Ethernet modules and UDP stack
+wire rx_eth_hdr_ready;
+wire rx_eth_hdr_valid;
+wire [47:0] rx_eth_dest_mac;
+wire [47:0] rx_eth_src_mac;
+wire [15:0] rx_eth_type;
+wire [7:0] rx_eth_payload_axis_tdata;
+wire rx_eth_payload_axis_tvalid;
+wire rx_eth_payload_axis_tready;
+wire rx_eth_payload_axis_tlast;
+wire rx_eth_payload_axis_tuser;
+
+wire tx_eth_hdr_ready;
+wire tx_eth_hdr_valid;
+wire [47:0] tx_eth_dest_mac;
+wire [47:0] tx_eth_src_mac;
+wire [15:0] tx_eth_type;
+wire [7:0] tx_eth_payload_axis_tdata;
+wire tx_eth_payload_axis_tvalid;
+wire tx_eth_payload_axis_tready;
+wire tx_eth_payload_axis_tlast;
+wire tx_eth_payload_axis_tuser;
+
+// IP frame connections
+wire rx_ip_hdr_valid;
+wire rx_ip_hdr_ready;
+wire [47:0] rx_ip_eth_dest_mac;
+wire [47:0] rx_ip_eth_src_mac;
+wire [15:0] rx_ip_eth_type;
+wire [3:0] rx_ip_version;
+wire [3:0] rx_ip_ihl;
+wire [5:0] rx_ip_dscp;
+wire [1:0] rx_ip_ecn;
+wire [15:0] rx_ip_length;
+wire [15:0] rx_ip_identification;
+wire [2:0] rx_ip_flags;
+wire [12:0] rx_ip_fragment_offset;
+wire [7:0] rx_ip_ttl;
+wire [7:0] rx_ip_protocol;
+wire [15:0] rx_ip_header_checksum;
+wire [31:0] rx_ip_source_ip;
+wire [31:0] rx_ip_dest_ip;
+wire [7:0] rx_ip_payload_axis_tdata;
+wire rx_ip_payload_axis_tvalid;
+wire rx_ip_payload_axis_tready;
+wire rx_ip_payload_axis_tlast;
+wire rx_ip_payload_axis_tuser;
+
+wire tx_ip_hdr_valid;
+wire tx_ip_hdr_ready;
+wire [5:0] tx_ip_dscp;
+wire [1:0] tx_ip_ecn;
+wire [15:0] tx_ip_length;
+wire [7:0] tx_ip_ttl;
+wire [7:0] tx_ip_protocol;
+wire [31:0] tx_ip_source_ip;
+wire [31:0] tx_ip_dest_ip;
+wire [7:0] tx_ip_payload_axis_tdata;
+wire tx_ip_payload_axis_tvalid;
+wire tx_ip_payload_axis_tready;
+wire tx_ip_payload_axis_tlast;
+wire tx_ip_payload_axis_tuser;
+
+// UDP frame connections
+wire rx_udp_hdr_valid;
+wire rx_udp_hdr_ready;
+wire [47:0] rx_udp_eth_dest_mac;
+wire [47:0] rx_udp_eth_src_mac;
+wire [15:0] rx_udp_eth_type;
+wire [3:0] rx_udp_ip_version;
+wire [3:0] rx_udp_ip_ihl;
+wire [5:0] rx_udp_ip_dscp;
+wire [1:0] rx_udp_ip_ecn;
+wire [15:0] rx_udp_ip_length;
+wire [15:0] rx_udp_ip_identification;
+wire [2:0] rx_udp_ip_flags;
+wire [12:0] rx_udp_ip_fragment_offset;
+wire [7:0] rx_udp_ip_ttl;
+wire [7:0] rx_udp_ip_protocol;
+wire [15:0] rx_udp_ip_header_checksum;
+wire [31:0] rx_udp_ip_source_ip;
+wire [31:0] rx_udp_ip_dest_ip;
+wire [15:0] rx_udp_source_port;
+wire [15:0] rx_udp_dest_port;
+wire [15:0] rx_udp_length;
+wire [15:0] rx_udp_checksum;
+wire [7:0] rx_udp_payload_axis_tdata;
+wire rx_udp_payload_axis_tvalid;
+wire rx_udp_payload_axis_tready;
+wire rx_udp_payload_axis_tlast;
+wire rx_udp_payload_axis_tuser;
+
+wire tx_udp_hdr_valid;
+wire tx_udp_hdr_ready;
+wire [5:0] tx_udp_ip_dscp;
+wire [1:0] tx_udp_ip_ecn;
+wire [7:0] tx_udp_ip_ttl;
+wire [31:0] tx_udp_ip_source_ip;
+wire [31:0] tx_udp_ip_dest_ip;
+wire [15:0] tx_udp_source_port;
+wire [15:0] tx_udp_dest_port;
+wire [15:0] tx_udp_length;
+wire [15:0] tx_udp_checksum;
+wire [7:0] tx_udp_payload_axis_tdata;
+wire tx_udp_payload_axis_tvalid;
+wire tx_udp_payload_axis_tready;
+wire tx_udp_payload_axis_tlast;
+wire tx_udp_payload_axis_tuser;
+
+wire [7:0] rx_fifo_udp_payload_axis_tdata;
+wire rx_fifo_udp_payload_axis_tvalid;
+wire rx_fifo_udp_payload_axis_tready;
+wire rx_fifo_udp_payload_axis_tlast;
+wire rx_fifo_udp_payload_axis_tuser;
+
+wire [7:0] tx_fifo_udp_payload_axis_tdata;
+wire tx_fifo_udp_payload_axis_tvalid;
+wire tx_fifo_udp_payload_axis_tready;
+wire tx_fifo_udp_payload_axis_tlast;
+wire tx_fifo_udp_payload_axis_tuser;
+
+// Configuration
+wire [47:0] local_mac   = 48'h02_00_00_00_00_00;
+wire [31:0] local_ip    = {8'd192, 8'd168, 8'd1,   8'd128};
+wire [31:0] gateway_ip  = {8'd192, 8'd168, 8'd1,   8'd1};
+wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
+
+// IP ports not used
+assign rx_ip_hdr_ready = 1;
+assign rx_ip_payload_axis_tready = 1;
+
+assign tx_ip_hdr_valid = 0;
+assign tx_ip_dscp = 0;
+assign tx_ip_ecn = 0;
+assign tx_ip_length = 0;
+assign tx_ip_ttl = 0;
+assign tx_ip_protocol = 0;
+assign tx_ip_source_ip = 0;
+assign tx_ip_dest_ip = 0;
+assign tx_ip_payload_axis_tdata = 0;
+assign tx_ip_payload_axis_tvalid = 0;
+assign tx_ip_payload_axis_tlast = 0;
+assign tx_ip_payload_axis_tuser = 0;
+
+// Loop back UDP
+wire match_cond = rx_udp_dest_port == 1234;
+wire no_match = !match_cond;
+
+reg match_cond_reg = 0;
+reg no_match_reg = 0;
+
+always @(posedge clk) begin
+    if (rst) begin
+        match_cond_reg <= 0;
+        no_match_reg <= 0;
+    end else begin
+        if (rx_udp_payload_axis_tvalid) begin
+            if ((!match_cond_reg && !no_match_reg) ||
+                (rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
+                match_cond_reg <= match_cond;
+                no_match_reg <= no_match;
+            end
+        end else begin
+            match_cond_reg <= 0;
+            no_match_reg <= 0;
+        end
+    end
+end
+
+assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
+assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
+assign tx_udp_ip_dscp = 0;
+assign tx_udp_ip_ecn = 0;
+assign tx_udp_ip_ttl = 64;
+assign tx_udp_ip_source_ip = local_ip;
+assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
+assign tx_udp_source_port = rx_udp_dest_port;
+assign tx_udp_dest_port = rx_udp_source_port;
+assign tx_udp_length = rx_udp_length;
+assign tx_udp_checksum = 0;
+
+assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
+assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
+assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
+assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
+assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
+
+assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
+assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
+assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
+assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
+assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
+
+
+
+
+assign phy_reset_n = !rst;
+
+
+eth_mac_1g_rgmii_fifo #(
+    .TARGET(TARGET),
+    .IODDR_STYLE("IODDR"),
+    .CLOCK_INPUT_STYLE("BUFR"),
+    .USE_CLK90("TRUE"),
+    .ENABLE_PADDING(1),
+    .MIN_FRAME_LENGTH(64),
+    .TX_FIFO_DEPTH(4096),
+    .TX_FRAME_FIFO(1),
+    .RX_FIFO_DEPTH(4096),
+    .RX_FRAME_FIFO(1)
+)
+eth_mac_inst (
+    .gtx_clk(clk),
+    .gtx_clk90(clk90),
+    .gtx_rst(rst),
+    .logic_clk(clk),
+    .logic_rst(rst),
+
+    .tx_axis_tdata(tx_axis_tdata),
+    .tx_axis_tvalid(tx_axis_tvalid),
+    .tx_axis_tready(tx_axis_tready),
+    .tx_axis_tlast(tx_axis_tlast),
+    .tx_axis_tuser(tx_axis_tuser),
+
+    .rx_axis_tdata(rx_axis_tdata),
+    .rx_axis_tvalid(rx_axis_tvalid),
+    .rx_axis_tready(rx_axis_tready),
+    .rx_axis_tlast(rx_axis_tlast),
+    .rx_axis_tuser(rx_axis_tuser),
+
+    .rgmii_rx_clk(phy_rx_clk),
+    .rgmii_rxd(phy_rxd),
+    .rgmii_rx_ctl(phy_rx_ctl),
+    .rgmii_tx_clk(phy_tx_clk),
+    .rgmii_txd(phy_txd),
+    .rgmii_tx_ctl(phy_tx_ctl),
+
+    .tx_fifo_overflow(),
+    .tx_fifo_bad_frame(),
+    .tx_fifo_good_frame(),
+    .rx_error_bad_frame(),
+    .rx_error_bad_fcs(),
+    .rx_fifo_overflow(),
+    .rx_fifo_bad_frame(),
+    .rx_fifo_good_frame(),
+    .speed(),
+
+    .cfg_ifg(8'd12),
+    .cfg_tx_enable(1'b1),
+    .cfg_rx_enable(1'b1)
+);
+
+eth_axis_rx
+eth_axis_rx_inst (
+    .clk(clk),
+    .rst(rst),
+    // AXI input
+    .s_axis_tdata(rx_axis_tdata),
+    .s_axis_tvalid(rx_axis_tvalid),
+    .s_axis_tready(rx_axis_tready),
+    .s_axis_tlast(rx_axis_tlast),
+    .s_axis_tuser(rx_axis_tuser),
+    // Ethernet frame output
+    .m_eth_hdr_valid(rx_eth_hdr_valid),
+    .m_eth_hdr_ready(rx_eth_hdr_ready),
+    .m_eth_dest_mac(rx_eth_dest_mac),
+    .m_eth_src_mac(rx_eth_src_mac),
+    .m_eth_type(rx_eth_type),
+    .m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
+    .m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
+    .m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
+    .m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
+    .m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
+    // Status signals
+    .busy(),
+    .error_header_early_termination()
+);
+
+eth_axis_tx
+eth_axis_tx_inst (
+    .clk(clk),
+    .rst(rst),
+    // Ethernet frame input
+    .s_eth_hdr_valid(tx_eth_hdr_valid),
+    .s_eth_hdr_ready(tx_eth_hdr_ready),
+    .s_eth_dest_mac(tx_eth_dest_mac),
+    .s_eth_src_mac(tx_eth_src_mac),
+    .s_eth_type(tx_eth_type),
+    .s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
+    .s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
+    .s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
+    .s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
+    .s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
+    // AXI output
+    .m_axis_tdata(tx_axis_tdata),
+    .m_axis_tvalid(tx_axis_tvalid),
+    .m_axis_tready(tx_axis_tready),
+    .m_axis_tlast(tx_axis_tlast),
+    .m_axis_tuser(tx_axis_tuser),
+    // Status signals
+    .busy()
+);
+
+udp_complete
+udp_complete_inst (
+    .clk(clk),
+    .rst(rst),
+    // Ethernet frame input
+    .s_eth_hdr_valid(rx_eth_hdr_valid),
+    .s_eth_hdr_ready(rx_eth_hdr_ready),
+    .s_eth_dest_mac(rx_eth_dest_mac),
+    .s_eth_src_mac(rx_eth_src_mac),
+    .s_eth_type(rx_eth_type),
+    .s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
+    .s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
+    .s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
+    .s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
+    .s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
+    // Ethernet frame output
+    .m_eth_hdr_valid(tx_eth_hdr_valid),
+    .m_eth_hdr_ready(tx_eth_hdr_ready),
+    .m_eth_dest_mac(tx_eth_dest_mac),
+    .m_eth_src_mac(tx_eth_src_mac),
+    .m_eth_type(tx_eth_type),
+    .m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
+    .m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
+    .m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
+    .m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
+    .m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
+    // IP frame input
+    .s_ip_hdr_valid(tx_ip_hdr_valid),
+    .s_ip_hdr_ready(tx_ip_hdr_ready),
+    .s_ip_dscp(tx_ip_dscp),
+    .s_ip_ecn(tx_ip_ecn),
+    .s_ip_length(tx_ip_length),
+    .s_ip_ttl(tx_ip_ttl),
+    .s_ip_protocol(tx_ip_protocol),
+    .s_ip_source_ip(tx_ip_source_ip),
+    .s_ip_dest_ip(tx_ip_dest_ip),
+    .s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
+    .s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
+    .s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
+    .s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
+    .s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
+    // IP frame output
+    .m_ip_hdr_valid(rx_ip_hdr_valid),
+    .m_ip_hdr_ready(rx_ip_hdr_ready),
+    .m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
+    .m_ip_eth_src_mac(rx_ip_eth_src_mac),
+    .m_ip_eth_type(rx_ip_eth_type),
+    .m_ip_version(rx_ip_version),
+    .m_ip_ihl(rx_ip_ihl),
+    .m_ip_dscp(rx_ip_dscp),
+    .m_ip_ecn(rx_ip_ecn),
+    .m_ip_length(rx_ip_length),
+    .m_ip_identification(rx_ip_identification),
+    .m_ip_flags(rx_ip_flags),
+    .m_ip_fragment_offset(rx_ip_fragment_offset),
+    .m_ip_ttl(rx_ip_ttl),
+    .m_ip_protocol(rx_ip_protocol),
+    .m_ip_header_checksum(rx_ip_header_checksum),
+    .m_ip_source_ip(rx_ip_source_ip),
+    .m_ip_dest_ip(rx_ip_dest_ip),
+    .m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
+    .m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
+    .m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
+    .m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
+    .m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
+    // UDP frame input
+    .s_udp_hdr_valid(tx_udp_hdr_valid),
+    .s_udp_hdr_ready(tx_udp_hdr_ready),
+    .s_udp_ip_dscp(tx_udp_ip_dscp),
+    .s_udp_ip_ecn(tx_udp_ip_ecn),
+    .s_udp_ip_ttl(tx_udp_ip_ttl),
+    .s_udp_ip_source_ip(tx_udp_ip_source_ip),
+    .s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
+    .s_udp_source_port(tx_udp_source_port),
+    .s_udp_dest_port(tx_udp_dest_port),
+    .s_udp_length(tx_udp_length),
+    .s_udp_checksum(tx_udp_checksum),
+    .s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
+    .s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
+    .s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
+    .s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
+    .s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
+    // UDP frame output
+    .m_udp_hdr_valid(rx_udp_hdr_valid),
+    .m_udp_hdr_ready(rx_udp_hdr_ready),
+    .m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
+    .m_udp_eth_src_mac(rx_udp_eth_src_mac),
+    .m_udp_eth_type(rx_udp_eth_type),
+    .m_udp_ip_version(rx_udp_ip_version),
+    .m_udp_ip_ihl(rx_udp_ip_ihl),
+    .m_udp_ip_dscp(rx_udp_ip_dscp),
+    .m_udp_ip_ecn(rx_udp_ip_ecn),
+    .m_udp_ip_length(rx_udp_ip_length),
+    .m_udp_ip_identification(rx_udp_ip_identification),
+    .m_udp_ip_flags(rx_udp_ip_flags),
+    .m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
+    .m_udp_ip_ttl(rx_udp_ip_ttl),
+    .m_udp_ip_protocol(rx_udp_ip_protocol),
+    .m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
+    .m_udp_ip_source_ip(rx_udp_ip_source_ip),
+    .m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
+    .m_udp_source_port(rx_udp_source_port),
+    .m_udp_dest_port(rx_udp_dest_port),
+    .m_udp_length(rx_udp_length),
+    .m_udp_checksum(rx_udp_checksum),
+    .m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
+    .m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
+    .m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
+    .m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
+    .m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
+    // Status signals
+    .ip_rx_busy(),
+    .ip_tx_busy(),
+    .udp_rx_busy(),
+    .udp_tx_busy(),
+    .ip_rx_error_header_early_termination(),
+    .ip_rx_error_payload_early_termination(),
+    .ip_rx_error_invalid_header(),
+    .ip_rx_error_invalid_checksum(),
+    .ip_tx_error_payload_early_termination(),
+    .ip_tx_error_arp_failed(),
+    .udp_rx_error_header_early_termination(),
+    .udp_rx_error_payload_early_termination(),
+    .udp_tx_error_payload_early_termination(),
+    // Configuration
+    .local_mac(local_mac),
+    .local_ip(local_ip),
+    .gateway_ip(gateway_ip),
+    .subnet_mask(subnet_mask),
+    .clear_arp_cache(0)
+);
+
+axis_fifo #(
+    .DEPTH(8192),
+    .DATA_WIDTH(8),
+    .KEEP_ENABLE(0),
+    .ID_ENABLE(0),
+    .DEST_ENABLE(0),
+    .USER_ENABLE(1),
+    .USER_WIDTH(1),
+    .FRAME_FIFO(0)
+)
+udp_payload_fifo (
+    .clk(clk),
+    .rst(rst),
+
+    // AXI input
+    .s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
+    .s_axis_tkeep(0),
+    .s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
+    .s_axis_tready(rx_fifo_udp_payload_axis_tready),
+    .s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
+    .s_axis_tid(0),
+    .s_axis_tdest(0),
+    .s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
+
+    // AXI output
+    .m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
+    .m_axis_tkeep(),
+    .m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
+    .m_axis_tready(tx_fifo_udp_payload_axis_tready),
+    .m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
+    .m_axis_tid(),
+    .m_axis_tdest(),
+    .m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
+
+    // Status
+    .status_overflow(),
+    .status_bad_frame(),
+    .status_good_frame()
+);
+
+endmodule
+
+`resetall
diff --git a/example/AX7203_ARTIX7/fpga/rtl/sync_signal.v b/example/AX7203_ARTIX7/fpga/rtl/sync_signal.v
new file mode 100644
index 000000000..74b855fa1
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/rtl/sync_signal.v
@@ -0,0 +1,62 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes an asyncronous signal to a given clock by using a pipeline of
+ * two registers.
+ */
+module sync_signal #(
+    parameter WIDTH=1, // width of the input and output signals
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire [WIDTH-1:0] in,
+    output wire [WIDTH-1:0] out
+);
+
+reg [WIDTH-1:0] sync_reg[N-1:0];
+
+/*
+ * The synchronized output is the last register in the pipeline.
+ */
+assign out = sync_reg[N-1];
+
+integer k;
+
+always @(posedge clk) begin
+    sync_reg[0] <= in;
+    for (k = 1; k < N; k = k + 1) begin
+        sync_reg[k] <= sync_reg[k-1];
+    end
+end
+
+endmodule
+
+`resetall
diff --git a/example/AX7203_ARTIX7/fpga/tb/fpga_core/Makefile b/example/AX7203_ARTIX7/fpga/tb/fpga_core/Makefile
new file mode 100644
index 000000000..2c0f29ce3
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/tb/fpga_core/Makefile
@@ -0,0 +1,100 @@
+# Copyright (c) 2020 Alex Forencich
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= icarus
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = fpga_core
+TOPLEVEL = $(DUT)
+MODULE   = test_$(DUT)
+VERILOG_SOURCES += ../../rtl/$(DUT).v
+VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_1g_rgmii_fifo.v
+VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_1g_rgmii.v
+VERILOG_SOURCES += ../../lib/eth/rtl/iddr.v
+VERILOG_SOURCES += ../../lib/eth/rtl/oddr.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ssio_ddr_in.v
+VERILOG_SOURCES += ../../lib/eth/rtl/rgmii_phy_if.v
+VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_1g.v
+VERILOG_SOURCES += ../../lib/eth/rtl/axis_gmii_rx.v
+VERILOG_SOURCES += ../../lib/eth/rtl/axis_gmii_tx.v
+VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
+VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_rx.v
+VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_tx.v
+VERILOG_SOURCES += ../../lib/eth/rtl/udp_complete.v
+VERILOG_SOURCES += ../../lib/eth/rtl/udp_checksum_gen.v
+VERILOG_SOURCES += ../../lib/eth/rtl/udp.v
+VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_rx.v
+VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_tx.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ip_complete.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ip.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_rx.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_tx.v
+VERILOG_SOURCES += ../../lib/eth/rtl/ip_arb_mux.v
+VERILOG_SOURCES += ../../lib/eth/rtl/arp.v
+VERILOG_SOURCES += ../../lib/eth/rtl/arp_cache.v
+VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_rx.v
+VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_tx.v
+VERILOG_SOURCES += ../../lib/eth/rtl/eth_arb_mux.v
+VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/arbiter.v
+VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/priority_encoder.v
+VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_fifo.v
+VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
+VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
+
+# module parameters
+#export PARAM_A := value
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+#	COMPILE_ARGS += -P $(TOPLEVEL).A=$(PARAM_A)
+
+	ifeq ($(WAVES), 1)
+		VERILOG_SOURCES += iverilog_dump.v
+		COMPILE_ARGS += -s iverilog_dump
+	endif
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
+
+#	COMPILE_ARGS += -GA=$(PARAM_A)
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+iverilog_dump.v:
+	echo 'module iverilog_dump();' > $@
+	echo 'initial begin' >> $@
+	echo '    $$dumpfile("$(TOPLEVEL).fst");' >> $@
+	echo '    $$dumpvars(0, $(TOPLEVEL));' >> $@
+	echo 'end' >> $@
+	echo 'endmodule' >> $@
+
+clean::
+	@rm -rf iverilog_dump.v
+	@rm -rf dump.fst $(TOPLEVEL).fst
diff --git a/example/AX7203_ARTIX7/fpga/tb/fpga_core/results.xml b/example/AX7203_ARTIX7/fpga/tb/fpga_core/results.xml
new file mode 100644
index 000000000..c617575a5
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/tb/fpga_core/results.xml
@@ -0,0 +1,6 @@
+<testsuites name="results">
+  <testsuite name="all" package="all">
+    <property name="random_seed" value="1735972827" />
+    <testcase name="run_test" classname="test_fpga_core" file="/home/kavya/Desktop/open_src_mac/verilog-ethernet-baac5f8d811d43853d59d69957975ead8bbed088/example/AX7203_ARTIX7/fpga/tb/fpga_core/test_fpga_core.py" lineno="84" time="1.9256463050842285" sim_time_ns="12440.001" ratio_time="6460.169225862" />
+  </testsuite>
+</testsuites>
diff --git a/example/AX7203_ARTIX7/fpga/tb/fpga_core/sim_build/cmds.f b/example/AX7203_ARTIX7/fpga/tb/fpga_core/sim_build/cmds.f
new file mode 100644
index 000000000..3e26e00a8
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/tb/fpga_core/sim_build/cmds.f
@@ -0,0 +1 @@
++timescale+1ns/1ps
diff --git a/example/AX7203_ARTIX7/fpga/tb/fpga_core/test_fpga_core.py b/example/AX7203_ARTIX7/fpga/tb/fpga_core/test_fpga_core.py
new file mode 100644
index 000000000..ea0788e87
--- /dev/null
+++ b/example/AX7203_ARTIX7/fpga/tb/fpga_core/test_fpga_core.py
@@ -0,0 +1,226 @@
+"""
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+import logging
+import os
+
+from scapy.layers.l2 import Ether, ARP
+from scapy.layers.inet import IP, UDP
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.log import SimLog
+from cocotb.triggers import RisingEdge, Timer
+
+from cocotbext.eth import GmiiFrame, RgmiiPhy
+
+
+class TB:
+    def __init__(self, dut, speed=1000e6):
+        self.dut = dut
+
+        self.log = SimLog("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        self.rgmii_phy = RgmiiPhy(dut.phy_txd, dut.phy_tx_ctl, dut.phy_tx_clk,
+            dut.phy_rxd, dut.phy_rx_ctl, dut.phy_rx_clk, speed=speed)
+
+    
+
+        dut.clk.setimmediatevalue(0)
+        dut.clk90.setimmediatevalue(0)
+
+        cocotb.start_soon(self._run_clk())
+
+    async def init(self):
+
+        self.dut.rst.setimmediatevalue(0)
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk)
+
+        self.dut.rst.value = 1
+
+        for k in range(10):
+            await RisingEdge(self.dut.clk)
+
+        self.dut.rst.value = 0
+
+    async def _run_clk(self):
+        t = Timer(2, 'ns')
+        while True:
+            self.dut.clk.value = 1
+            await t
+            self.dut.clk90.value = 1
+            await t
+            self.dut.clk.value = 0
+            await t
+            self.dut.clk90.value = 0
+            await t
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    tb.log.info("test UDP RX packet")
+
+    payload = bytes([x % 256 for x in range(256)])
+    eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00')
+    ip = IP(src='192.168.1.100', dst='192.168.1.128')
+    udp = UDP(sport=5678, dport=1234)
+    test_pkt = eth / ip / udp / payload
+
+    test_frame = GmiiFrame.from_payload(test_pkt.build())
+    
+    await tb.rgmii_phy.rx.send(test_frame)
+
+    tb.log.info("receive ARP request")
+
+    rx_frame = await tb.rgmii_phy.tx.recv()
+    
+    rx_pkt = Ether(bytes(rx_frame.get_payload()))
+
+    tb.log.info("RX packet: %s", repr(rx_pkt))
+
+    assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff'
+    assert rx_pkt.src == test_pkt.dst
+    assert rx_pkt[ARP].hwtype == 1
+    assert rx_pkt[ARP].ptype == 0x0800
+    assert rx_pkt[ARP].hwlen == 6
+    assert rx_pkt[ARP].plen == 4
+    assert rx_pkt[ARP].op == 1
+    assert rx_pkt[ARP].hwsrc == test_pkt.dst
+    assert rx_pkt[ARP].psrc == test_pkt[IP].dst
+    assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00'
+    assert rx_pkt[ARP].pdst == test_pkt[IP].src
+
+    tb.log.info("send ARP response")
+
+    eth = Ether(src=test_pkt.src, dst=test_pkt.dst)
+    arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2,
+        hwsrc=test_pkt.src, psrc=test_pkt[IP].src,
+        hwdst=test_pkt.dst, pdst=test_pkt[IP].dst)
+    resp_pkt = eth / arp
+
+    resp_frame = GmiiFrame.from_payload(resp_pkt.build())
+
+    await tb.rgmii_phy.rx.send(resp_frame)
+
+    tb.log.info("receive UDP packet")
+
+    rx_frame = await tb.rgmii_phy.tx.recv()
+
+    rx_pkt = Ether(bytes(rx_frame.get_payload()))
+    print("\n")
+    print("\n")
+    print(rx_frame)
+    print("\n")
+    print("\n")
+    tb.log.info("RX packet: %s", repr(rx_pkt))
+
+    assert rx_pkt.dst == test_pkt.src
+    assert rx_pkt.src == test_pkt.dst
+    assert rx_pkt[IP].dst == test_pkt[IP].src
+    assert rx_pkt[IP].src == test_pkt[IP].dst
+    assert rx_pkt[UDP].dport == test_pkt[UDP].sport
+    assert rx_pkt[UDP].sport == test_pkt[UDP].dport
+    assert rx_pkt[UDP].payload == test_pkt[UDP].payload
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+# cocotb-test
+
+tests_dir = os.path.abspath(os.path.dirname(__file__))
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
+axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl'))
+eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
+
+
+def test_fpga_core(request):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.v"),
+        os.path.join(eth_rtl_dir, "eth_mac_1g_rgmii_fifo.v"),
+        os.path.join(eth_rtl_dir, "eth_mac_1g_rgmii.v"),
+        os.path.join(eth_rtl_dir, "iddr.v"),
+        os.path.join(eth_rtl_dir, "oddr.v"),
+        os.path.join(eth_rtl_dir, "ssio_ddr_in.v"),
+        os.path.join(eth_rtl_dir, "rgmii_phy_if.v"),
+        os.path.join(eth_rtl_dir, "eth_mac_1g.v"),
+        os.path.join(eth_rtl_dir, "axis_gmii_rx.v"),
+        os.path.join(eth_rtl_dir, "axis_gmii_tx.v"),
+        os.path.join(eth_rtl_dir, "lfsr.v"),
+        os.path.join(eth_rtl_dir, "eth_axis_rx.v"),
+        os.path.join(eth_rtl_dir, "eth_axis_tx.v"),
+        os.path.join(eth_rtl_dir, "udp_complete.v"),
+        os.path.join(eth_rtl_dir, "udp_checksum_gen.v"),
+        os.path.join(eth_rtl_dir, "udp.v"),
+        os.path.join(eth_rtl_dir, "udp_ip_rx.v"),
+        os.path.join(eth_rtl_dir, "udp_ip_tx.v"),
+        os.path.join(eth_rtl_dir, "ip_complete.v"),
+        os.path.join(eth_rtl_dir, "ip.v"),
+        os.path.join(eth_rtl_dir, "ip_eth_rx.v"),
+        os.path.join(eth_rtl_dir, "ip_eth_tx.v"),
+        os.path.join(eth_rtl_dir, "ip_arb_mux.v"),
+        os.path.join(eth_rtl_dir, "arp.v"),
+        os.path.join(eth_rtl_dir, "arp_cache.v"),
+        os.path.join(eth_rtl_dir, "arp_eth_rx.v"),
+        os.path.join(eth_rtl_dir, "arp_eth_tx.v"),
+        os.path.join(eth_rtl_dir, "eth_arb_mux.v"),
+        os.path.join(axis_rtl_dir, "arbiter.v"),
+        os.path.join(axis_rtl_dir, "priority_encoder.v"),
+        os.path.join(axis_rtl_dir, "axis_fifo.v"),
+        os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
+        os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
+    ]
+
+    parameters = {}
+
+    # parameters['A'] = val
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )