chore: Rework improper formatting of some code examples inside docstrings

Author: ecoussoux-ansys

src/pyedb/generic/design_types.py

@@ -152,17 +152,10 @@ def Edb(
         4. Simulation Setup
 
         # Create SIwave SYZ setup
-    >>> syz_setup = edb.create_siwave_syz_setup(
-    >>> name = ("GHz_Setup",)
-    >>> start_freq = ("1GHz",)
-    >>> stop_freq = "10GHz"
-    >>> )
+    >>> syz_setup = edb.create_siwave_syz_setup(name="GHz_Setup", start_freq="1GHz", stop_freq="10GHz")
 
         # Create SIwave DC setup
-    >>> dc_setup = edb.create_siwave_dc_setup(
-    >>> name = ("DC_Analysis",)
-    >>> use_dc_point = True
-    >>> )
+    >>> dc_setup = edb.create_siwave_dc_setup(name="DC_Analysis", use_dc_point=True)
 
         # Solve with SIwave
     >>> edb.solve_siwave()
@@ -193,17 +186,10 @@ def Edb(
         7. Port Creation
 
         # Create wave port between two pins
-    >>> wave_port = edb.source_excitation.create_port(
-    >>> positive_terminal = (pin1,)
-    >>> negative_terminal = (pin2,)
-    >>> port_type = "Wave"
-    >>> )
+    >>> wave_port = edb.source_excitation.create_port(positive_terminal=pin1, negative_terminal=pin2, port_type="Wave")
 
         # Create lumped port
-    >>> lumped_port = edb.source_excitation.create_port(
-    >>> positive_terminal = (via_terminal,)
-    >>> port_type = "Lumped"
-    >>> )
+    >>> lumped_port = edb.source_excitation.create_port(positive_terminal=via_terminal, port_type="Lumped")
 
         8. Component Management
 
@@ -216,12 +202,7 @@ def Edb(
         9. Parametrization
 
         # Auto-parametrize design elements
-    >>> params = edb.auto_parametrize_design(
-    >>> traces = (True,)
-    >>> pads = (True,)
-    >>> antipads = (True,)
-    >>> use_relative_variables = True
-    >>> )
+    >>> params = edb.auto_parametrize_design(traces=True, pads=True, antipads=True, use_relative_variables=True)
     >>> print("Created parameters:", params)
 
         10. Design Statistics
@@ -240,11 +221,7 @@ def Edb(
         12. Differential Pairs
 
         # Create differential pair
-    >>> edb.differential_pairs.create(
-    >>> positive_net = ("USB_P",)
-    >>> negative_net = ("USB_N",)
-    >>> name = "USB_DP"
-    >>> )
+    >>> edb.differential_pairs.create(positive_net="USB_P", negative_net="USB_N", name="USB_DP")
 
         13. Workflow Automation
 

src/pyedb/grpc/database/control_file.py

@@ -58,40 +58,26 @@ def convert_technology_file(tech_file, edbversion=None, control_file=None):
         -------
         # Example 1: Converting a technology file to control file
     >>> converted_file = convert_technology_file(
-    >>> tech_file = ("/path/to/tech.t",)
-    >>> edbversion = ("2025.2",)
-    >>> control_file = "/path/to/output.xml"
-    >>> )
+    ...     tech_file="/path/to/tech.t", edbversion="2025.2", control_file="/path/to/output.xml"
+    ... )
     >>> if converted_file:
     >>> print(f"Converted to: {converted_file}")
 
         # Example 2: Creating a material
     >>> from pyedb import ControlFileMaterial
-    >>> material = ControlFileMaterial(
-    >>> ("Copper",)
-    >>> {"Permittivity": 1.0, "Conductivity": 5.8e7}
-    >>> )
+    >>> material = ControlFileMaterial("Copper", {"Permittivity": 1.0, "Conductivity": 5.8e7})
 
         # Example 3: Creating a dielectric layer
     >>> from pyedb import ControlFileDielectric
-    >>> dielectric = ControlFileDielectric(
-    >>> ("Core",)
-    >>> {"Thickness": "0.2mm", "Material": "FR4"}
-    >>> )
+    >>> dielectric = ControlFileDielectric("Core", {"Thickness": "0.2mm", "Material": "FR4"})
 
         # Example 4: Creating a signal layer
     >>> from pyedb import ControlFileLayer
-    >>> signal_layer = ControlFileLayer(
-    >>> ("TopLayer",)
-    >>> {"Type": "signal", "Material": "Copper", "Thickness": "0.035mm"}
-    >>> )
+    >>> signal_layer = ControlFileLayer("TopLayer", {"Type": "signal", "Material": "Copper", "Thickness": "0.035mm"})
 
         # Example 5: Creating a via layer
     >>> from pyedb import ControlFileVia
-    >>> via_layer = ControlFileVia(
-    >>> ("Via1",)
-    >>> {"StartLayer": "TopLayer", "StopLayer": "BottomLayer"}
-    >>> )
+    >>> via_layer = ControlFileVia("Via1", {"StartLayer": "TopLayer", "StopLayer": "BottomLayer"})
     >>> via_layer.create_via_group = True
     >>> via_layer.tolerance = "0.1mm"
 
@@ -111,11 +97,7 @@ def convert_technology_file(tech_file, edbversion=None, control_file=None):
 
         # Example 8: Setting up simulation extents
     >>> from pyedb import ControlExtent
-    >>> extent = ControlExtent(
-    >>> type = ("Conforming",)
-    >>> diel_hactor = (0.3,)
-    >>> airbox_hfactor = 0.5
-    >>> )
+    >>> extent = ControlExtent(type="Conforming", diel_hactor=0.3, airbox_hfactor=0.5)
 
         # Example 9: Creating circuit ports
     >>> from pyedb import ControlCircuitPt
@@ -142,26 +124,11 @@ def convert_technology_file(tech_file, edbversion=None, control_file=None):
 
         # Example 13: Frequency sweep configuration
     >>> from pyedb import ControlFileSweep
-    >>> sweep = ControlFileSweep(
-    >>> (
-    ...     "Sweep1",
-    ...     "1GHz",
-    ...     "10GHz",
-    ...     "0.1GHz",
-    ... )
-    >>> "Interpolating", "LinearStep", True
-    >>> )
+    >>> sweep = ControlFileSweep("Sweep1", "1GHz", "10GHz", "0.1GHz", "Interpolating", "LinearStep", True)
 
         # Example 14: Mesh operation setup
     >>> from pyedb import ControlFileMeshOp
-    >>> mesh_op = ControlFileMeshOp(
-    >>> (
-    ...     "FineMesh",
-    ...     "Region1",
-    ...     "MeshOperationSkinDepth",
-    ... )
-    >>> {"Net1": "TopLayer"}
-    >>> )
+    >>> mesh_op = ControlFileMeshOp("FineMesh", "Region1", "MeshOperationSkinDepth", {"Net1": "TopLayer"})
     >>> mesh_op.skin_depth = "1um"
 
         # Example 15: Simulation setup configuration

src/pyedb/grpc/database/nets.py

@@ -95,34 +95,21 @@ class Nets(CommonNets):
     >>> print("Eligible power nets:", [net.name for net in eligible_pwr])
 
     >>> # Generate extended nets (deprecated)
-    >>> nets.generate_extended_nets(
-    >>> resistor_below = (5,)
-    >>>inductor_below=0.5,
-    >>> capacitor_above = 0.1
-    >>> )
+    >>> nets.generate_extended_nets(resistor_below=5, inductor_below=0.5, capacitor_above=0.1)
 
     >>> # Classify nets
-    >>> nets.classify_nets(
-    >>> power_nets = (["VDD_CPU", "VDD_MEM"],)
-    >>> signal_nets = ["PCIe_TX", "ETH_RX"]
-    >>> )
+    >>> nets.classify_nets(power_nets=["VDD_CPU", "VDD_MEM"], signal_nets=["PCIe_TX", "ETH_RX"])
 
     >>> # Check power/ground status
     >>> is_power = nets.is_power_gound_net(["VDD_CPU", "PCIe_TX"])
     >>> print("Is power net:", is_power)
 
     >>> # Get DC-connected nets
-    >>> dc_connected = nets.get_dcconnected_net_list(
-    >>> ground_nets = (["GND"],)
-    >>> res_value = 0.002
-    >>> )
+    >>> dc_connected = nets.get_dcconnected_net_list(ground_nets=["GND"], res_value=0.002)
         print("DC-connected nets:", dc_connected)
 
     >>> # Get power tree
-    >>> comp_list, columns, net_group = nets.get_powertree(
-    >>> power_net_name = ("VDD_CPU",)
-    >>> ground_nets = ["GND"]
-    >>> )
+    >>> comp_list, columns, net_group = nets.get_powertree(power_net_name="VDD_CPU", ground_nets=["GND"])
     >>> print("Power tree components:", comp_list)
 
     >>> # Find net by name
@@ -142,10 +129,7 @@ class Nets(CommonNets):
     >>> print("Net in component:", in_component)
 
     >>> # Find and fix disjoint nets (deprecated)
-    >>> fixed_nets = nets.find_and_fix_disjoint_nets(
-    >>> net_list = (["PCIe_TX"],)
-    >>> clean_disjoints_less_than = 1e-6
-    >>> )
+    >>> fixed_nets = nets.find_and_fix_disjoint_nets(net_list=["PCIe_TX"], clean_disjoints_less_than=1e-6)
     >>> print("Fixed nets:", fixed_nets)
 
     >>> # Merge net polygons

src/pyedb/grpc/database/source_excitations.py

@@ -65,14 +65,14 @@ class SourceExcitation:
     >>> # Create voltage source on component pins
     >>> from pyedb.grpc.database.utility.sources import Source, SourceType
     >>> source = Source(
-    >>> source_type = (SourceType.Vsource,)
-    >>> name = ("V1",)
-    >>> positive_node = (("U1", "VCC"),)
-    >>> negative_node = (("U1", "GND"),)
-    >>> amplitude = ("1V",)
-    >>> phase = ("0deg",)
-    >>> impedance = "50ohm"
-    >>> )
+    ...     source_type=SourceType.Vsource,
+    ...     name="V1",
+    ...     positive_node=("U1", "VCC"),
+    ...     negative_node=("U1", "GND"),
+    ...     amplitude="1V",
+    ...     phase="0deg",
+    ...     impedance="50ohm",
+    ... )
     >>> source_excitations.create_source_on_component([source])
 
     >>> # 2. create_port
@@ -84,21 +84,14 @@ class SourceExcitation:
     >>> # 3. create_port_on_pins
     >>> # Create circuit port between component pins
     >>> port_term = source_excitations.create_port_on_pins(
-    >>> refdes = ("U1",)
-    >>> pins = ("Pin1",)
-    >>> reference_pins = (["GND_Pin1", "GND_Pin2"],)
-    >>> impedance = (50,)
-    >>> port_name = "Port1"
-    >>> )
+    ...     refdes="U1", pins="Pin1", reference_pins=["GND_Pin1", "GND_Pin2"], impedance=50, port_name="Port1"
+    ... )
 
     >>> # 4. create_port_on_component
     >>> # Create coaxial ports on component nets
     >>> source_excitations.create_port_on_component(
-    >>>  component="U1",
-    >>> net_list = (["PCIe_RX0", "PCIe_RX1"],)
-    >>> port_type = (SourceType.CoaxPort,)
-    >>> reference_net = "GND"
-    >>> )
+    ...     component="U1", net_list=["PCIe_RX0", "PCIe_RX1"], port_type=SourceType.CoaxPort, reference_net="GND"
+    ... )
 
     >>> # 5. add_port_on_rlc_component
     >>> # Replace RLC component with circuit port
@@ -152,44 +145,26 @@ class SourceExcitation:
     >>> # 16. create_coax_port_on_component
     >>> # Create coaxial ports on component
     >>> ports = source_excitations.create_coax_port_on_component(
-    >>> (["U1", "U2"],)
-    >>> (["PCIe_RX0", "PCIe_TX0"],)
-    >>> delete_existing_terminal = True
-    >>> )
+    ...     ["U1", "U2"], ["PCIe_RX0", "PCIe_TX0"], delete_existing_terminal=True
+    ... )
 
     >>> # 17. create_differential_wave_port
     >>> # Create differential wave port
     >>> pos_prim = edb.modeler.primitives[0]
     >>> neg_prim = edb.modeler.primitives[1]
     >>> port_name, diff_port = source_excitations.create_differential_wave_port(
-    >>> (
-    ...     pos_prim.id,
-    ...     [0, 0],
+    ...     pos_prim.id, [0, 0], neg_prim.id, [0, 0.2], "DiffPort"
     ... )
-    >>> (
-    ...     neg_prim.id,
-    ...     [0, 0.2],
-    ... )
-    >>> "DiffPort"
-    >>> )
 
     >>> # 18. create_wave_port
     >>> # Create wave port
-    >>> port_name, wave_port = source_excitations.create_wave_port(
-    >>> (
-    ...     pos_prim.id,
-    ...     [0, 0],
-    ... )
-    >>> "WavePort"
-    >>> )
+    >>> port_name, wave_port = source_excitations.create_wave_port(pos_prim.id, [0, 0], "WavePort")
 
     >>> # 19. create_bundle_wave_port
     >>> # Create bundle wave port
     >>> port_name, bundle_port = source_excitations.create_bundle_wave_port(
-    >>> ([pos_prim.id, neg_prim.id],)
-    >>> ([[0, 0], [0, 0.2]],)
-    >>> "BundlePort"
-    >>> )
+    ...     [pos_prim.id, neg_prim.id], [[0, 0], [0, 0.2]], "BundlePort"
+    ... )
 
     >>> # 20. create_dc_terminal
     >>> # Create DC terminal
@@ -202,14 +177,8 @@ class SourceExcitation:
     >>> # 22. place_voltage_probe
     >>> # Place voltage probe between points
     >>> source_excitations.place_voltage_probe(
-    >>> ("Probe1",)
-    >>> (
-    ...     "SignalNet",
-    ...     [0, 0],
-    ...     "TopLayer",
+    ...     "Probe1", "SignalNet", [0, 0], "TopLayer", "GND", [0.1, 0.1], "BottomLayer"
     ... )
-    >>> "GND", [0.1, 0.1], "BottomLayer"
-    >>> )
 
     >>> # Save and close EDB
     >>> edb.save()

src/pyedb/grpc/edb.py

@@ -3765,7 +3765,7 @@ def create_model_for_arbitrary_wave_ports(
 
         if not void_padstacks:
             self.logger.error(
-                "No padstack instances found inside evaluated voids during model creation for arbitrarywaveports"
+                "No padstack instances found inside evaluated voids during model creation for arbitrary waveports"
             )
             return False
         cloned_edb = Edb(edbpath=output_edb, edbversion=self.edbversion, restart_rpc_server=True)