From 894373b5a3efeaa2aeb8051c961da84a180327b7 Mon Sep 17 00:00:00 2001
From: Maleehaakbar <maleehaashley@gmail.com>
Date: Tue, 3 Dec 2024 22:51:02 +0500
Subject: [PATCH] add support for mtvt CSR

---
 arch/riscv/cpu_registers.c | 2 ++
 arch/riscv/cpu_registers.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/arch/riscv/cpu_registers.c b/arch/riscv/cpu_registers.c
index ef8d342b2..4a5c68e16 100644
--- a/arch/riscv/cpu_registers.c
+++ b/arch/riscv/cpu_registers.c
@@ -127,6 +127,8 @@ uint32_t *get_reg_pointer_32(int reg)
         return &(cpu->mip);
     case SPTBR_32:     // same index as SATP_32
         return (cpu->privilege_architecture >= RISCV_PRIV1_10) ? &(cpu->satp) : &(cpu->sptbr);
+    case MTVT_32:
+        return &(cpu->mtvt);
     case MSTATUS_32:
         return &(cpu->mstatus);
     case MISA_32:
diff --git a/arch/riscv/cpu_registers.h b/arch/riscv/cpu_registers.h
index 44bdd0d24..a6b57ba08 100644
--- a/arch/riscv/cpu_registers.h
+++ b/arch/riscv/cpu_registers.h
@@ -210,6 +210,7 @@ typedef enum {
     SIP_32      = 0x185,
     SATP_32     = 0x1C1,
     SPTBR_32    = 0x1C1,
+    MTVT_32     = 0x307,
     MSTATUS_32  = 0x341,
     MISA_32     = 0x342,
     MEDELEG_32  = 0x343,