KeeloqBruteforce.src.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity KeeloqBruteforce is
	port(
		reset_n		: in std_logic;
		clk			: in std_logic;
		blk_cipher	: in std_logic_vector(31 downto 0);
		blk_plain	: in std_logic_vector(31 downto 0);
		key_out		: out std_logic_vector(63 downto 0);
		found			: out std_logic
	);
end entity;


architecture behavioral of KeeloqBruteforce is
	component KeeloqDecryptUnrolled is
		port(
			blk_in	: in std_logic_vector(31 downto 0);
			key_in	: in std_logic_vector(63 downto 0);
			blk_out	: out std_logic_vector(31 downto 0)
		);
	end component;
	signal key		: std_logic_vector(63 downto 0);
	signal blk_tst	: std_logic_vector(31 downto 0);
begin

	kd1	: KeeloqDecryptUnrolled port map(blk_in=>blk_cipher, blk_out=>blk_tst, key_in=>key);
	process(reset_n, clk)
	begin
		if reset_n = '0' then
			key <= (others=>'0');
			found <= '0';
		elsif(rising_edge(clk)) then
			if blk_tst = blk_plain then
				key_out <= key;
				found <= '1';
			else
				key <= std_logic_vector(unsigned(key) + 1);
			end if;
		end if;
	end process;
end behavioral;