diff --git a/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-kaluga-1/index.rst b/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-kaluga-1/index.rst index 8c2a4bef11a83..00f373e7ec082 100644 --- a/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-kaluga-1/index.rst +++ b/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-kaluga-1/index.rst @@ -297,6 +297,22 @@ After successfully built and flashed, run on the boards' terminal:: nxlooper> loopback 2 8 44100 +rtc +--- + +This configuration demonstrates the use of the RTC driver through alarms. +You can set an alarm, check its progress and receive a notification after it expires:: + + nsh> alarm 10 + alarm_daemon started + alarm_daemon: Running + Opening /dev/rtc0 + Alarm 0 set in 10 seconds + nsh> alarm -r + Opening /dev/rtc0 + Alarm 0 is active with 10 seconds to expiration + nsh> alarm_daemon: alarm 0 received + twai ---- diff --git a/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index.rst b/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index.rst index 6c7ba49bbe67f..aa6404f6712e5 100644 --- a/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index.rst +++ b/Documentation/platforms/xtensa/esp32s2/boards/esp32s2-saola-1/index.rst @@ -335,6 +335,22 @@ To test it, just run ``rand`` to get 32 randomly generated bytes:: 0000 98 b9 66 a2 a2 c0 a2 ae 09 70 93 d1 b5 91 86 c8 ..f......p...... 0010 8f 0e 0b 04 29 64 21 72 01 92 7c a2 27 60 6f 90 ....)d!r..|.'`o. +rtc +--- + +This configuration demonstrates the use of the RTC driver through alarms. +You can set an alarm, check its progress and receive a notification after it expires:: + + nsh> alarm 10 + alarm_daemon started + alarm_daemon: Running + Opening /dev/rtc0 + Alarm 0 set in 10 seconds + nsh> alarm -r + Opening /dev/rtc0 + Alarm 0 is active with 10 seconds to expiration + nsh> alarm_daemon: alarm 0 received + timer ----- diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig index 3e56c2c8bf6ae..bdda62eb025d9 100644 --- a/arch/xtensa/src/esp32s2/Kconfig +++ b/arch/xtensa/src/esp32s2/Kconfig @@ -420,6 +420,10 @@ config ESP32S2_RWDT to have the RTC module reset, please, use the Timers' Module WDTs. They will only reset Main System. +config ESP32S2_RTC + bool "Real Time Clock (RTC)" + default y + config ESP32S2_UART0 bool "UART 0" default n @@ -1020,6 +1024,49 @@ config ESP32S2_SPIRAM_IGNORE_NOTFOUND endmenu # SPI RAM Configuration +menu "RTC Configuration" + depends on ESP32S2_RTC + +choice ESP32S2_RTC_CLK_SRC + prompt "RTC clock source" + default ESP32S2_RTC_CLK_INT_RC + ---help--- + Choose which clock is used as RTC clock source. + + - "Internal 90KHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32KHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32KHz oscillator" allows using 32KHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8.5MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 90KHz oscillator. It does not require external components. + +config ESP32S2_RTC_CLK_INT_RC + bool "Internal 90KHz RC oscillator" + +config ESP32S2_RTC_CLK_EXT_XTAL + bool "External 32KHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config ESP32S2_RTC_CLK_EXT_OSC + bool "External 32KHz oscillator at 32K_XN pin" + select ESP_SYSTEM_RTC_EXT_XTAL + +config ESP32S2_RTC_CLK_INT_8MD256 + bool "Internal 8.5MHz oscillator, divided by 256 (~33kHz)" + +endchoice +endmenu # "RTC Configuration" + menu "Real-Time Timer Configuration" depends on ESP32S2_RT_TIMER diff --git a/arch/xtensa/src/esp32s2/Make.defs b/arch/xtensa/src/esp32s2/Make.defs index 4a2fceb1577c6..4621feaefbff9 100644 --- a/arch/xtensa/src/esp32s2/Make.defs +++ b/arch/xtensa/src/esp32s2/Make.defs @@ -137,6 +137,12 @@ CHIP_CSRCS += esp32s2_spiram.c CHIP_CSRCS += esp32s2_psram.c endif +CHIP_CSRCS += esp32s2_rtc.c + +ifeq ($(CONFIG_RTC_DRIVER),y) +CHIP_CSRCS += esp32s2_rtc_lowerhalf.c +endif + ############################################################################# # Espressif HAL for 3rd Party Platforms ############################################################################# diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc.c b/arch/xtensa/src/esp32s2/esp32s2_rtc.c new file mode 100644 index 0000000000000..35851ea357c41 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc.c @@ -0,0 +1,2691 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_rtc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include + +#include +#include + +#include "clock/clock.h" + +#include "esp32s2_clockconfig.h" +#include "esp32s2_rt_timer.h" + +#include "hardware/esp32s2_rtccntl.h" +#include "hardware/esp32s2_rtc_io.h" +#include "hardware/esp32s2_system.h" +#include "hardware/esp32s2_i2s.h" + +#include "hardware/esp32s2_rtccntl.h" +#include "hardware/esp32s2_rtc_io.h" +#include "hardware/esp32s2_system.h" +#include "hardware/esp32s2_tim.h" +#include "hardware/regi2c_ctrl.h" +#include "hardware/esp32s2_spi_mem_reg.h" +#include "hardware/esp32s2_extmem.h" +#include "hardware/esp32s2_syscon.h" +#include "hardware/regi2c_bbpll.h" +#include "hardware/regi2c_lp_bias.h" + +#include "xtensa.h" +#include "xtensa_attr.h" + +#include "esp32s2_rtc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Various delays to be programmed into power control state machines */ + +#define RTC_CNTL_XTL_BUF_WAIT_SLP 2 +#define RTC_CNTL_CK8M_WAIT_SLP 4 +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP +#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT + +#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP +#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT + +#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP +#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT + +#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP +#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT + +#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP +#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT + +#define RTC_CNTL_PLL_BUF_WAIT_SLP 2 + +#define DELAY_FAST_CLK_SWITCH 3 + +#define XTAL_32K_DAC_VAL 1 +#define XTAL_32K_DRES_VAL 3 +#define XTAL_32K_DBIAS_VAL 0 + +#define XTAL_32K_EXT_DAC_VAL 2 +#define XTAL_32K_EXT_DRES_VAL 3 +#define XTAL_32K_EXT_DBIAS_VAL 1 + +#define DELAY_SLOW_CLK_SWITCH 300 + +#define DELAY_8M_ENABLE 50 + +#define RETRY_CAL_EXT 1 + +/* Lower threshold for a reasonably-looking calibration value + * for a 32KHz XTAL. The ideal value (assuming 32768 Hz frequency) + * is 1000000/32768*(2**19) = 16*10^6. + */ + +#define MIN_32K_XTAL_CAL_VAL 15000000L + +/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP + * setting + */ + +#define RTC_FAST_CLK_FREQ_8M 8500000 +#define RTC_SLOW_CLK_FREQ_90K 90000 +#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256) +#define RTC_SLOW_CLK_FREQ_32K 32768 + +/* Number of fractional bits in values returned by rtc_clk_cal */ + +#define RTC_CLK_CAL_FRACT 19 + +/* With the default value of CK8M_DFREQ, + * 8M clock frequency is 8.5 MHz +/- 7% + */ + +#define RTC_FAST_CLK_FREQ_APPROX 8500000 +#define RCT_FAST_D256_FREQ_APPROX (RTC_FAST_CLK_FREQ_APPROX / 256) +#define RTC_SLOW_CLK_FREQ_APPROX 32768 + +/* Disable logging from the ROM code. */ + +#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) + +#define RTC_SLEEP_PD_DIG BIT(0) /* Deep sleep (power down digital domain) */ +#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) /* Power down RTC peripherals */ +#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) /* Power down RTC SLOW memory */ +#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) /* Power down RTC FAST memory */ +#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) /* RTC FAST and SLOW memories are automatically powered up and down along with the CPU */ +#define RTC_SLEEP_PD_VDDSDIO BIT(5) /* Power down VDDSDIO regulator */ +#define RTC_SLEEP_PD_WIFI BIT(6) /* Power down WIFI */ +#define RTC_SLEEP_PD_INT_8M BIT(7) /* Power down Internal 8M oscillator */ +#define RTC_SLEEP_PD_XTAL BIT(8) /* Power down main XTAL */ + +/* These flags are not power domains, but will affect some sleep parameters */ + +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) /* Avoid using ultra low power in deep sleep, + * in which RTCIO cannot be used as input, + * and RTCMEM can't work under high temperature */ + +#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) + +/* set sleep_init default param. */ + +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6 +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_BIASSLP_SLEEP_ON 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_SLEEP_ON 0 + +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1 +#define RTC_CNTL_BIASSLP_MONITOR_ON 0 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_ON 0 + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ + +#define RTC_CNTL_DBIAS_0V90 0 /* sleep dig_dbias & rtc_dbias */ +#define RTC_CNTL_DBIAS_0V95 1 /* digital voltage */ +#define RTC_CNTL_DBIAS_1V00 2 +#define RTC_CNTL_DBIAS_1V05 3 +#define RTC_CNTL_DBIAS_1V10 4 +#define RTC_CNTL_DBIAS_1V15 5 +#define RTC_CNTL_DBIAS_1V20 6 +#define RTC_CNTL_DBIAS_1V25 7 /* voltage is about 1.34v in fact */ + +/* Default initializer for esp32s2_rtc_sleep_config_t + * This initializer sets all fields to "reasonable" values + * (e.g. suggested for production use) based on a combination + * of RTC_SLEEP_PD_x flags. + */ + +#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ + .lslp_mem_inf_fpu = 0, \ + .rtc_mem_inf_follow_cpu = ((sleep_flags) & \ + RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ + .wifi_pd_en = (sleep_flags & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ + .int_8m_pd_en = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ + .wdt_flashboot_mod_en = 0, \ + .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ + : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? \ + RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP, \ + .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ + : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? \ + RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP, \ + .bias_sleep_monitor = 0, \ + .dbg_atten_slp = 0, \ + .pd_cur_monitor = 0, \ + .pd_cur_slp = 0, \ + .rtc_regulator_fpu = 0, \ + .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ + .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ + .deep_slp_reject = 1, \ + .light_slp_reject = 1, \ +} + +#define X32K_CONFIG_DEFAULT() { \ + .dac = 3, \ + .dres = 3, \ + .dgm = 3, \ + .dbuf = 1, \ +} + +/* Initializer for rtc_sleep_pd_config_t which + * sets all flags to the same value + */ + +#define RTC_SLEEP_PD_CONFIG_ALL(val) { \ + .dig_fpu = (val), \ + .rtc_fpu = (val), \ + .cpu_fpu = (val), \ + .i2s_fpu = (val), \ + .bb_fpu = (val), \ + .nrx_fpu = (val), \ + .fe_fpu = (val), \ +} + +/* Default initializer of struct esp32s2_rtc_config_s. + * This initializer sets all fields to "reasonable" values + * (e.g. suggested for production use). + */ + +#define RTC_CONFIG_DEFAULT() { \ + .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ + .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ + .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ + .clkctl_init = 1, \ + .pwrctl_init = 1, \ + .rtc_dboost_fpd = 1, \ + .xtal_fpu = 0, \ + .bbpll_fpu = 0, \ + .cpu_waiti_clk_gate = 1, \ + .cali_ocode = 0 \ +} + +/* The magic data for the struct esp32s2_rtc_backup_s that is in RTC slow + * memory. + */ + +#define MAGIC_RTC_SAVE UINT64_C(0x11223344556677) + +/* RTC Memory & Store Register usage */ + +#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG /* RTC_SLOW_CLK calibration value */ +#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG /* Boot time, low word */ +#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG /* Boot time, high word */ +#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG /* External XTAL frequency */ +#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG /* APB bus frequency */ +#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG /* FAST_RTC_MEMORY_ENTRY */ +#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG +#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG /* FAST_RTC_MEMORY_CRC */ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* RTC power and clock control initialization settings */ + +struct esp32s2_rtc_priv_s +{ + uint32_t ck8m_wait : 8; /* Number of rtc_fast_clk cycles to wait for 8M clock to be ready */ + uint32_t xtal_wait : 8; /* Number of rtc_fast_clk cycles to wait for XTAL clock to be ready */ + uint32_t pll_wait : 8; /* Number of rtc_fast_clk cycles to wait for PLL to be ready */ + uint32_t clkctl_init : 1; /* Perform clock control related initialization */ + uint32_t pwrctl_init : 1; /* Perform power control related initialization */ + uint32_t rtc_dboost_fpd : 1; /* Force power down RTC_DBOOST */ + uint32_t xtal_fpu : 1; + uint32_t bbpll_fpu : 1; + uint32_t cpu_waiti_clk_gate : 1; + uint32_t cali_ocode : 1; /* Calibrate Ocode to make bangap voltage more precise. */ +}; + +/* sleep configuration for rtc_sleep_init function */ + +struct esp32s2_rtc_sleep_config_s +{ + uint32_t lslp_mem_inf_fpu : 1; /* force normal voltage in sleep mode (digital domain memory) */ + uint32_t rtc_mem_inf_follow_cpu : 1; /* keep low voltage in sleep mode (even if ULP/touch is used) */ + uint32_t rtc_fastmem_pd_en : 1; /* power down RTC fast memory */ + uint32_t rtc_slowmem_pd_en : 1; /* power down RTC slow memory */ + uint32_t rtc_peri_pd_en : 1; /* power down RTC peripherals */ + uint32_t wifi_pd_en : 1; /* power down WiFi */ + uint32_t int_8m_pd_en : 1; /* Power down Internal 8M oscillator */ + uint32_t deep_slp : 1; /* power down digital domain */ + uint32_t wdt_flashboot_mod_en : 1; /* enable WDT flashboot mode */ + uint32_t dig_dbias_wak : 3; /* set bias for digital domain, in active mode */ + uint32_t dig_dbias_slp : 3; /* set bias for digital domain, in sleep mode */ + uint32_t rtc_dbias_wak : 3; /* set bias for RTC domain, in active mode */ + uint32_t rtc_dbias_slp : 3; /* set bias for RTC domain, in sleep mode */ + uint32_t bias_sleep_monitor : 1; /* circuit control parameter, in monitor mode */ + uint32_t dbg_atten_slp : 4; /* voltage parameter, in sleep mode */ + uint32_t bias_sleep_slp : 1; /* circuit control parameter, in sleep mode */ + uint32_t pd_cur_monitor : 1; /* circuit control parameter, in monitor mode */ + uint32_t pd_cur_slp : 1; /* circuit control parameter, in sleep mode */ + uint32_t vddsdio_pd_en : 1; /* power down VDDSDIO regulator */ + uint32_t xtal_fpu : 1; /* keep main XTAL powered up in sleep */ + uint32_t rtc_regulator_fpu : 1; /* keep rtc regulator powered up in sleep */ + uint32_t deep_slp_reject : 1; /* enable deep sleep reject */ + uint32_t light_slp_reject : 1; /* enable light sleep reject */ +}; + +/* Power down flags for rtc_sleep_pd function */ + +struct esp32s2_rtc_sleep_pd_config_s +{ + uint32_t dig_fpu : 1; /* Set to 1 to power down digital part in sleep */ + uint32_t rtc_fpu : 1; /* Set to 1 to power down RTC memories in sleep */ + uint32_t cpu_fpu : 1; /* Set to 1 to power down digital memories and CPU in sleep */ + uint32_t i2s_fpu : 1; /* Set to 1 to power down I2S in sleep */ + uint32_t bb_fpu : 1; /* Set to 1 to power down Wi-Fi in sleep */ + uint32_t nrx_fpu : 1; /* Set to 1 to power down Wi-Fi in sleep */ + uint32_t fe_fpu : 1; /* Set to 1 to power down Wi-Fi in sleep */ +}; + +#ifdef CONFIG_RTC_ALARM +struct alm_cbinfo_s +{ + struct rt_timer_s *alarm_hdl; /* Timer id point to here */ + volatile alm_callback_t ac_cb; /* Client callback function */ + volatile void *ac_arg; /* Argument to pass with the callback function */ + uint64_t deadline_us; + uint8_t index; +}; +#endif + +/* crystal configuration */ + +struct esp32s2_rtc_x32k_config_s +{ + uint32_t dac : 6; + uint32_t dres : 3; + uint32_t dgm : 3; + uint32_t dbuf: 1; +}; + +struct esp32s2_rtc_backup_s +{ + uint64_t magic; + int64_t offset; /* Offset time from RTC HW value */ + int64_t reserved0; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* APB Frequency */ + +static uint32_t g_apb_freq; + +/* Callback to use when the alarm expires */ + +#ifdef CONFIG_RTC_ALARM +static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; +#endif + +static RTC_DATA_ATTR struct esp32s2_rtc_backup_s rtc_saved_data; + +/* Saved data for persistent RTC time */ + +static struct esp32s2_rtc_backup_s *g_rtc_save; +static bool g_rt_timer_enabled = false; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rtc_sleep_pd( + struct esp32s2_rtc_sleep_pd_config_s cfg); +static inline bool esp32s2_clk_val_is_valid(uint32_t val); +static void IRAM_ATTR esp32s2_rtc_clk_fast_freq_set( + enum esp32s2_rtc_fast_freq_e fast_freq); +static uint32_t IRAM_ATTR esp32s2_rtc_clk_cal_internal( + enum esp32s2_rtc_cal_sel_e cal_clk, + uint32_t slowclk_cycles); +static int IRAM_ATTR esp32s2_rtc_clk_slow_freq_get(void); +static void IRAM_ATTR esp32s2_rtc_clk_slow_freq_set( + enum esp32s2_rtc_slow_freq_e slow_freq); +static void esp32s2_select_rtc_slow_clk(enum esp32s2_slow_clk_sel_e + slow_clk); +static void esp32s2_rtc_clk_32k_enable(bool enable); +static void IRAM_ATTR esp32s2_rtc_clk_8m_enable(bool clk_8m_en, + bool d256_en); +static void esp32s2_rtc_calibrate_ocode(void); +static void IRAM_ATTR esp32s2_rtc_clk_bbpll_disable(void); +static void IRAM_ATTR esp32s2_rtc_bbpll_configure( + enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq); +static void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_to_8m(void); +static void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz); + +void IRAM_ATTR esp32s2_rtc_bbpll_disable(void); +void esp32s2_rtc_clk_apb_freq_update(uint32_t apb_freq); +void IRAM_ATTR esp32s2_rtc_update_to_xtal(int freq, int div); +static void esp32s2_wait_dig_dbias_valid(uint64_t rtc_cycles); +uint32_t esp32s2_rtc_clk_apb_freq_get(void); + +#ifdef CONFIG_RTC_ALARM +static void IRAM_ATTR esp32s2_rt_cb_handler(void *arg); +#endif +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile bool g_rtc_enabled = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Set the real CPU ticks per us to the ets, so that ets_delay_us + * will be accurate. Call this function when CPU frequency is changed. + */ + +extern void ets_update_cpu_frequency(uint32_t ticks_per_us); + +/**************************************************************************** + * Name: esp32s2_rtc_sleep_pd + * + * Description: + * Configure whether certain peripherals are powered up in deep sleep. + * + * Input Parameters: + * cfg - power down flags as rtc_sleep_pu_config_t structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR + esp32s2_rtc_sleep_pd(struct esp32s2_rtc_sleep_pd_config_s cfg) +{ + REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, + RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); + REG_SET_FIELD(RTC_CNTL_PWC_REG, + RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); + REG_SET_FIELD(RTC_CNTL_PWC_REG, + RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu); + REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, + SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, + SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, + SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); + REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu); + REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu); + REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu); + REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu); + REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu); + REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu); +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_fast_freq_set + * + * Description: + * Select source for RTC_FAST_CLK. + * + * Input Parameters: + * fast_freq - Clock source (one of enum esp32s2_rtc_fast_freq_e values) + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rtc_clk_fast_freq_set( + enum esp32s2_rtc_fast_freq_e fast_freq) +{ + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, + fast_freq); + up_udelay(DELAY_FAST_CLK_SWITCH); +} + +/**************************************************************************** + * Name: esp32s2_clk_val_is_valid + * + * Description: + * Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are + * stored as two copies in lower and upper 16-bit halves. + * These are the routines to work with such a representation. + * + * Input Parameters: + * val - register value + * + * Returned Value: + * true: Valid register value. + * false: Invalid register value. + * + ****************************************************************************/ + +static inline bool esp32s2_clk_val_is_valid(uint32_t val) +{ + return (val & 0xffff) == ((val >> 16) & 0xffff) + && val != 0 && val != UINT32_MAX; +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_cal_internal + * + * Description: + * Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio + * + * Input Parameters: + * cal_clk - which clock to calibrate + * slowclk_cycles - number of slow clock cycles to count. + * + * Returned Value: + * Number of XTAL clock cycles within the given number of slow clock + * cycles. + * In case of error, return 0 cycle. + * + ****************************************************************************/ + +static uint32_t IRAM_ATTR esp32s2_rtc_clk_cal_internal( + enum esp32s2_rtc_cal_sel_e cal_clk, uint32_t slowclk_cycles) +{ + uint32_t expected_freq; + uint32_t us_time_estimate; + uint32_t clks_state; + uint32_t clks_mask; + uint32_t cal_val; + enum esp32s2_rtc_slow_freq_e slow_freq; + + /* Get the current state */ + + clks_mask = (RTC_CNTL_DIG_XTAL32K_EN_M | RTC_CNTL_DIG_CLK8M_D256_EN_M); + clks_state = getreg32(RTC_CNTL_CLK_CONF_REG); + clks_state &= clks_mask; + + /* On ESP32S2, choosing RTC_CAL_RTC_MUX results in calibration of + * the 150k RTC clock regardless of the currenlty selected SLOW_CLK. + * The following code emulates ESP32 behavior + */ + + if (cal_clk == RTC_CAL_RTC_MUX) + { + slow_freq = esp32s2_rtc_clk_slow_freq_get(); + if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) + { + cal_clk = RTC_CAL_32K_XTAL; + } + else if (slow_freq == RTC_SLOW_FREQ_8MD256) + { + cal_clk = RTC_CAL_8MD256; + } + } + else if (cal_clk == RTC_CAL_INTERNAL_OSC) + { + cal_clk = RTC_CAL_RTC_MUX; + } + + /* Enable requested clock (150k clock is always on) */ + + if (cal_clk == RTC_CAL_32K_XTAL && !(clks_state & RTC_CNTL_DIG_XTAL32K_EN)) + { + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1); + } + else if (cal_clk == RTC_CAL_8MD256 && + !(clks_state & RTC_CNTL_DIG_CLK8M_D256_EN)) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_DIG_CLK8M_D256_EN); + } + + /* Prepare calibration */ + + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); + modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING, 0); + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); + + /* Figure out how long to wait for calibration to finish */ + + slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, + RTC_CNTL_ANA_CLK_RTC_SEL); + + if (cal_clk == RTC_CAL_32K_XTAL || slow_freq == RTC_SLOW_FREQ_32K_XTAL) + { + expected_freq = 32768; /* standard 32KHz XTAL */ + } + else if (cal_clk == RTC_CAL_8MD256 || slow_freq == RTC_SLOW_FREQ_8MD256) + { + expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256; + } + else + { + expected_freq = 150000; /* 150k internal oscillator */ + } + + us_time_estimate = (uint32_t) (((uint64_t)slowclk_cycles) * + MHZ / expected_freq); + + /* Start calibration */ + + modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START, 0); + modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); + + /* Wait the expected time calibration should take */ + + up_udelay(us_time_estimate); + + /* Wait for calibration to finish up to another us_time_estimate */ + + while (true) + { + if (getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY) + { + cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), + TIMG_RTC_CALI_VALUE); + break; + } + + if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) + { + cal_val = 0; + break; + } + } + + CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); + + /* Restore the previous clocks states */ + + modifyreg32(RTC_CNTL_CLK_CONF_REG, clks_mask, clks_state); + + return cal_val; +} + +static void esp32s2_wait_dig_dbias_valid(uint64_t rtc_cycles) +{ + int slow_clk_freq = esp32s2_rtc_clk_slow_freq_get(); + int cal_clk = RTC_CAL_RTC_MUX; + + if (slow_clk_freq == RTC_SLOW_FREQ_32K_XTAL) + { + cal_clk = RTC_CAL_32K_XTAL; + } + else if (slow_clk_freq == RTC_SLOW_FREQ_8MD256) + { + cal_clk = RTC_CAL_8MD256; + } + + esp32s2_rtc_clk_cal(cal_clk, rtc_cycles); +} + +/**************************************************************************** + * Name: esp32s2_rtc_update_to_xtal + * + * Description: + * Switch to XTAL frequency, does not disable the PLL + * + * Input Parameters: + * freq - XTAL frequency + * div - REF_TICK divider + * + * Returned Value: + * none + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_update_to_xtal(int freq, int div) +{ + ets_update_cpu_frequency(freq); + esp32s2_wait_dig_dbias_valid(2); + + /* Set divider from XTAL to APB clock. + * Need to set divider to 1 (reg. value 0) first. + */ + + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1); + + /* No need to adjust the REF_TICK. + * Switch clock source. + */ + + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_XTAL); + + esp32s2_rtc_clk_apb_freq_update(freq * MHZ); +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_slow_freq_set + * + * Description: + * Select source for RTC_SLOW_CLK + * + * Input Parameters: + * slow_freq - Select source for RTC_SLOW_CLK + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rtc_clk_slow_freq_set( + enum esp32s2_rtc_slow_freq_e slow_freq) +{ + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, + slow_freq); + + REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, + (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); + + up_udelay(DELAY_SLOW_CLK_SWITCH); +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_32k_enable + * + * Description: + * Enable 32 KHz XTAL oscillator + * + * Input Parameters: + * enable - boolean Enable/Disable + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rtc_clk_32k_enable(bool enable) +{ + if (enable) + { + struct esp32s2_rtc_x32k_config_s cfg = X32K_CONFIG_DEFAULT(); + + modifyreg32(RTCIO_XTAL_32P_PAD_REG, 0, RTCIO_X32P_MUX_SEL); + modifyreg32(RTCIO_XTAL_32N_PAD_REG, 0, RTCIO_X32N_MUX_SEL); + + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, + RTC_CNTL_DAC_XTAL_32K, cfg.dac); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, + RTC_CNTL_DRES_XTAL_32K, cfg.dres); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, + RTC_CNTL_DGM_XTAL_32K, cfg.dgm); + REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, + RTC_CNTL_DBUF_XTAL_32K, cfg.dbuf); + modifyreg32(RTC_CNTL_EXT_XTL_CONF_REG, 0, + RTC_CNTL_XPD_XTAL_32K); + } + else + { + modifyreg32(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K, + RTC_CNTL_XTAL32K_XPD_FORCE); + } +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_8m_enable + * + * Description: + * Enable or disable 8 MHz internal oscillator + * + * Input Parameters: + * clk_8m_en - true to enable 8MHz generator, false to disable + * d256_en - true to enable /256 divider, false to disable + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) +{ + if (clk_8m_en) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M, 0); + + /* no need to wait once enabled by software */ + + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1); + if (d256_en) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV, 0); + } + else + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M_DIV); + } + + up_udelay(DELAY_8M_ENABLE); + } + else + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, + RTC_CNTL_CK8M_WAIT_DEFAULT); + } +} + +/**************************************************************************** + * Name: esp32s2_select_rtc_slow_clk + * + * Description: + * Selects an clock source for RTC. + * + * Input Parameters: + * slow_clk - RTC SLOW_CLK frequency values + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32s2_select_rtc_slow_clk(enum esp32s2_slow_clk_sel_e slow_clk) +{ + /* Number of times to repeat 32KHz XTAL calibration before giving up and + * switching to the internal RC. + */ + + int retry_32k_xtal = 0; + uint32_t cal_val = 0; + uint64_t cal_dividend; + enum esp32s2_rtc_slow_freq_e rtc_slow_freq = slow_clk & + RTC_CNTL_ANA_CLK_RTC_SEL_V; + + do + { + if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) + { + /* 32KHz XTAL oscillator needs to be enabled and running before + * it can be used. Hardware doesn't have a direct way of checking + * if the oscillator is running. Here we use rtc_clk_cal function + * to count the number of main XTAL cycles in the given number of + * 32KHz XTAL oscillator cycles. If the 32KHz XTAL has not + * started up, calibration will time out, returning 0. + */ + + rtcinfo("Waiting for 32KHz oscillator to start up\n"); + if (slow_clk == SLOW_CLK_32K_XTAL || + slow_clk == SLOW_CLK_32K_EXT_OSC) + { + esp32s2_rtc_clk_32k_enable(true); + } + + if (SLOW_CLK_CAL_CYCLES > 0) + { + cal_val = esp32s2_rtc_clk_cal(RTC_CAL_32K_XTAL, + SLOW_CLK_CAL_CYCLES); + if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) + { + if (retry_32k_xtal-- > 0) + { + continue; + } + + rtc_slow_freq = RTC_SLOW_FREQ_RTC; + } + } + } + else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) + { + esp32s2_rtc_clk_8m_enable(true, true); + } + + esp32s2_rtc_clk_slow_freq_set(rtc_slow_freq); + if (SLOW_CLK_CAL_CYCLES > 0) + { + /* 32KHz XTAL oscillator has some frequency drift at startup. + * Improve calibration routine to wait until + * the frequency is stable. + */ + + cal_val = esp32s2_rtc_clk_cal(RTC_CAL_RTC_MUX, + SLOW_CLK_CAL_CYCLES); + } + else + { + cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; + cal_val = (uint32_t)(cal_dividend / + esp32s2_rtc_clk_slow_freq_get_hz()); + } + + retry_32k_xtal++; + } + while (cal_val == 0 && retry_32k_xtal < RETRY_CAL_EXT); + rtcinfo("RTC_SLOW_CLK calibration value: %d\n", cal_val); + putreg32((uint32_t)cal_val, RTC_SLOW_CLK_CAL_REG); +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_cpu_freq_to_8m + * + * Description: + * Switch CPU frequency to 8 Mhz. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_to_8m(void) +{ + int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL); + int origin_div_cnt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_PRE_DIV_CNT); + ets_update_cpu_frequency(8); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); + + esp32s2_wait_dig_dbias_valid(2); + + if ((DPORT_SOC_CLK_SEL_XTAL == origin_soc_clk) + && (origin_div_cnt > 4)) + { + esp32s2_wait_dig_dbias_valid(2); + } + + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, + DPORT_SOC_CLK_SEL_8M); + esp32s2_rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_APPROX); +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_cpu_freq_to_pll_mhz + * + * Description: + * Switch to one of PLL-based frequencies. + * + * Input Parameters: + * cpu_freq_mhz - CPU frequency + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) +{ + int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL); + int origin_cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, + SYSTEM_CPUPERIOD_SEL); + int dbias = DIG_DBIAS_80M_160M; + int per_conf = DPORT_CPUPERIOD_SEL_80; + if (cpu_freq_mhz == 80) + { + /* Nothing to do */ + } + else if (cpu_freq_mhz == 160) + { + dbias = DIG_DBIAS_80M_160M; + per_conf = DPORT_CPUPERIOD_SEL_160; + } + else if (cpu_freq_mhz == 240) + { + dbias = DIG_DBIAS_240M; + per_conf = DPORT_CPUPERIOD_SEL_240; + } + else + { + rtcerr("Invalid frequency\n"); + } + + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, dbias); + + if ((origin_soc_clk == DPORT_SOC_CLK_SEL_XTAL) + || (origin_soc_clk == DPORT_SOC_CLK_SEL_8M) + || (((origin_soc_clk == DPORT_SOC_CLK_SEL_PLL) + && (0 == origin_cpuperiod_sel)))) + { + esp32s2_wait_dig_dbias_valid(2); + } + + REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf); + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); + REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, + DPORT_SOC_CLK_SEL_PLL); + esp32s2_rtc_clk_apb_freq_update(80 * MHZ); + ets_update_cpu_frequency(cpu_freq_mhz); +} + +#ifdef CONFIG_RTC_ALARM + +/**************************************************************************** + * Name: esp32s2_rt_cb_handler + * + * Description: + * RT-Timer service routine + * + * Input Parameters: + * arg - Information about the RT-Timer configuration. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rt_cb_handler(void *arg) +{ + struct alm_cbinfo_s *cbinfo = (struct alm_cbinfo_s *)arg; + alm_callback_t cb; + void *cb_arg; + int alminfo_id; + + DEBUGASSERT(cbinfo != NULL); + alminfo_id = cbinfo->index; + DEBUGASSERT((RTC_ALARM0 <= alminfo_id) && + (alminfo_id < RTC_ALARM_LAST)); + + if (cbinfo->ac_cb != NULL) + { + /* Alarm callback */ + + cb = cbinfo->ac_cb; + cb_arg = (void *)cbinfo->ac_arg; + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + cbinfo->deadline_us = 0; + cb(cb_arg, alminfo_id); + } +} + +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: esp32s2_rtc_calibrate_ocode + * + * Description: + * Calibrate o-code by software + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void esp32s2_rtc_calibrate_ocode(void) +{ + uint64_t cycle0; + uint64_t timeout_cycle; + uint32_t slow_clk_period; + uint64_t max_delay_cycle; + bool odone_flag = 0; + bool bg_odone_flag = 0; + uint64_t cycle1 = 0; + uint64_t max_delay_time_us = 10000; + struct esp32s2_cpu_freq_config_s freq_config; + + /* Bandgap output voltage is not precise when calibrate o-code by hardware + * sometimes, so need software o-code calibration (must turn off PLL). + * Method: + * 1. read current cpu config, save in old_config + * 2. switch cpu to xtal because PLL will be closed when o-code calibration + * 3. begin o-code calibration + * 4. wait o-code calibration done flag or timeout + * 5. set cpu to old-config + */ + + enum esp32s2_rtc_slow_freq_e slow_clk_freq = + esp32s2_rtc_clk_slow_freq_get(); + enum esp32s2_rtc_slow_freq_e rtc_slow_freq_x32k = + RTC_SLOW_FREQ_32K_XTAL; + enum esp32s2_rtc_slow_freq_e rtc_slow_freq_8md256 = + RTC_SLOW_FREQ_8MD256; + enum esp32s2_rtc_cal_sel_e cal_clk = RTC_CAL_RTC_MUX; + if (slow_clk_freq == rtc_slow_freq_x32k) + { + cal_clk = RTC_CAL_32K_XTAL; + } + else if (slow_clk_freq == rtc_slow_freq_8md256) + { + cal_clk = RTC_CAL_8MD256; + } + + slow_clk_period = esp32s2_rtc_clk_cal(cal_clk, 100); + max_delay_cycle = esp32s2_rtc_time_us_to_slowclk(max_delay_time_us, + slow_clk_period); + cycle0 = esp32s2_rtc_time_get(); + timeout_cycle = cycle0 + max_delay_cycle; + + esp32s2_rtc_clk_cpu_freq_get_config(&freq_config); + esp32s2_rtc_cpu_freq_set_xtal(); + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); + REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); + while (1) + { + odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG); + bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG); + cycle1 = esp32s2_rtc_time_get(); + if (odone_flag && bg_odone_flag) + { + break; + } + + if (cycle1 >= timeout_cycle) + { + break; + } + } + + esp32s2_rtc_clk_cpu_freq_set_config(&freq_config); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +static int IRAM_ATTR esp32s2_rtc_clk_slow_freq_get(void) +{ + return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_slow_freq_get_hz + * + * Description: + * Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * Input Parameters: + * None + * + * Returned Value: + * RTC_SLOW_CLK frequency, in Hz + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32s2_rtc_clk_slow_freq_get_hz(void) +{ + enum esp32s2_rtc_slow_freq_e slow_clk_freq = + REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, + RTC_CNTL_ANA_CLK_RTC_SEL); + switch (slow_clk_freq) + { + case RTC_SLOW_FREQ_RTC: + return RTC_SLOW_CLK_FREQ_APPROX; + + case RTC_SLOW_FREQ_32K_XTAL: + return RTC_SLOW_CLK_FREQ_APPROX; + + case RTC_SLOW_FREQ_8MD256: + return RCT_FAST_D256_FREQ_APPROX; + } + + return OK; +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_fast_freq_get_hz + * + * Description: + * Get fast_clk_rtc source in Hz. + * + * Input Parameters: + * None + * + * Returned Value: + * The clock source in Hz. + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32s2_rtc_clk_fast_freq_get_hz(void) +{ + return RTC_FAST_CLK_FREQ_APPROX; +} + +/**************************************************************************** + * Name: esp32s2_rtc_get_slow_clk_rtc + * + * Description: + * Get slow_clk_rtc source. + * + * Input Parameters: + * None + * + * Returned Value: + * The clock source: + * - SLOW_CK + * - CK_XTAL_32K + * - CK8M_D256_OUT + * + ****************************************************************************/ + +enum esp32s2_rtc_slow_freq_e IRAM_ATTR esp32s2_rtc_get_slow_clk(void) +{ + enum esp32s2_rtc_slow_freq_e slow_freq; + + /* Get the clock source for slow_clk_rtc */ + + slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, + RTC_CNTL_ANA_CLK_RTC_SEL); + + return slow_freq; +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_cal + * + * Description: + * Measure RTC slow clock's period, based on main XTAL frequency + * + * Input Parameters: + * cal_clk - clock to be measured + * slowclk_cycles - number of slow clock cycles to average + * + * Returned Value: + * Average slow clock period in microseconds, Q13.19 fixed point format + * or 0 if calibration has timed out + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32s2_rtc_clk_cal(enum esp32s2_rtc_cal_sel_e cal_clk, + uint32_t slowclk_cycles) +{ + enum esp32s2_rtc_xtal_freq_e xtal_freq; + uint64_t xtal_cycles; + uint64_t divider; + uint64_t period_64; + uint32_t period; + + xtal_freq = esp32s2_rtc_clk_xtal_freq_get(); + xtal_cycles = esp32s2_rtc_clk_cal_internal(cal_clk, slowclk_cycles); + divider = ((uint64_t)xtal_freq) * slowclk_cycles; + period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) + / divider; + period = (uint32_t)(period_64 & UINT32_MAX); + + return period; +} + +enum esp32s2_rtc_xtal_freq_e rtc_get_xtal(void) + __attribute__((alias("esp32s2_rtc_clk_xtal_freq_get"))); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_xtal_freq_get + * + * Description: + * Get main XTAL frequency + * + * Input Parameters: + * None + * + * Returned Value: + * XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values) + * + ****************************************************************************/ + +enum esp32s2_rtc_xtal_freq_e IRAM_ATTR esp32s2_rtc_clk_xtal_freq_get(void) +{ + /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */ + + uint32_t xtal_freq_reg = getreg32(RTC_XTAL_FREQ_REG); + + if (!esp32s2_clk_val_is_valid(xtal_freq_reg)) + { + return RTC_XTAL_FREQ_40M; + } + + return (xtal_freq_reg & ~RTC_DISABLE_ROM_LOG) & UINT16_MAX; +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_bbpll_disable + * + * Description: + * disable BBPLL. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rtc_clk_bbpll_disable(void) +{ + modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_BB_I2C_FORCE_PD | + RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); +} + +/**************************************************************************** + * Name: esp32s2_rtc_bbpll_configure + * + * Description: + * Configure main XTAL frequency values according to pll_freq. + * + * Input Parameters: + * xtal_freq - XTAL frequency values + * pll_freq - PLL frequency values + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void IRAM_ATTR esp32s2_rtc_bbpll_configure( + enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq) +{ + static uint8_t div_ref = 0; + static uint8_t div7_0 = 0; + static uint8_t dr1 = 0 ; + static uint8_t dr3 = 0 ; + static uint8_t dchgp = 0; + static uint8_t dcur = 0; + uint8_t i2c_bbpll_lref = 0; + uint8_t i2c_bbpll_div_7_0 = 0; + uint8_t i2c_bbpll_dcur = 0; + + if (pll_freq == RTC_PLL_FREQ_480M) + { + /* Set this register to let the digital part know 480M PLL is used */ + + modifyreg32(SYSTEM_CPU_PER_CONF_REG, 0, SYSTEM_PLL_FREQ_SEL); + + /* Configure 480M PLL */ + + div_ref = 0; + div7_0 = 8; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 4; + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b); + } + else + { + /* Clear this register to let the digital part know 320M PLL is used */ + + modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL, 0); + + /* Configure 320M PLL */ + + div_ref = 0; + div7_0 = 4; + dr1 = 0; + dr3 = 0; + dchgp = 5; + dcur = 5; + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69); + } + + i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref); + i2c_bbpll_div_7_0 = div7_0; + i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | + (2 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; + + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); + REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2); + REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1); +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_set + * + * Description: + * Set RTC CLK frequency. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_clk_set(void) +{ + enum esp32s2_rtc_fast_freq_e fast_freq = RTC_FAST_FREQ_8M; + enum esp32s2_slow_clk_sel_e slow_clk = SLOW_CLK_90K; + +#if defined(CONFIG_ESP32S2_RTC_CLK_EXT_XTAL) + slow_clk = SLOW_CLK_32K_XTAL; +#elif defined(CONFIG_ESP32S2_RTC_CLK_EXT_OSC) + slow_clk = SLOW_CLK_32K_EXT_OSC; +#elif defined(CONFIG_ESP32S2_RTC_CLK_INT_8MD256) + slow_clk = SLOW_CLK_8MD256; +#endif + + esp32s2_rtc_clk_fast_freq_set(fast_freq); + esp32s2_select_rtc_slow_clk(slow_clk); +} + +/**************************************************************************** + * Name: esp32s2_rtc_init + * + * Description: + * Initialize RTC clock and power control related functions. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_init(void) +{ + struct esp32s2_rtc_priv_s cfg = RTC_CONFIG_DEFAULT(); + + modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU, 0); + + modifyreg32(RTC_CNTL_TIMER1_REG, 0, + cfg.pll_wait ? RTC_CNTL_PLL_BUF_WAIT : 0); + + modifyreg32(RTC_CNTL_TIMER1_REG, 0, + cfg.ck8m_wait ? RTC_CNTL_CK8M_WAIT : 0); + + /* Moved from rtc sleep to rtc init to save sleep function running time */ + + /* set shortest possible sleep time limit */ + + REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, + RTC_CNTL_MIN_SLP_VAL_MIN); + + /* set wifi timer */ + + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, 1); + REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, 1); + + if (cfg.cali_ocode) + { + /* TODO: Use calibration from efuse if configured */ + + esp32s2_rtc_calibrate_ocode(); + } + + if (cfg.clkctl_init) + { + /* clear CMMU clock force on */ + + modifyreg32(EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG, + EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON, 0); + + /* clear rom clock force on */ + + REG_SET_FIELD(SYSTEM_ROM_CTRL_0_REG, SYSTEM_ROM_FO, 0); + + /* clear tag clock force on */ + + REG_SET_FIELD(SYSTEM_SRAM_CTRL_0_REG, SYSTEM_SRAM_FO, 0); + + /* clear tag clock force on */ + + modifyreg32(EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG, + EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON, 0); + modifyreg32(EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG, + EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON, 0); + + /* clear register clock force on */ + + modifyreg32(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN, 0); + modifyreg32(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN, 0); + } + + if (cfg.pwrctl_init) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, 0); + + /* Cancel xtal force pu if no need to force power up + * Cannot cancel xtal force pu if pll is force power on + */ + + if (!(cfg.xtal_fpu || cfg.bbpll_fpu)) + { + modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, 0); + } + else + { + modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_XTL_FORCE_PU); + } + + /* CLEAR APLL close */ + + CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); + SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); + + /* Cancel bbpll force pu if setting no force power up */ + + if (!cfg.bbpll_fpu) + { + modifyreg32(RTC_CNTL_OPTIONS0_REG, + RTC_CNTL_BBPLL_FORCE_PU | + RTC_CNTL_BBPLL_I2C_FORCE_PU | + RTC_CNTL_BB_I2C_FORCE_PU, 0); + } + else + { + modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, + RTC_CNTL_BBPLL_FORCE_PU | + RTC_CNTL_BBPLL_I2C_FORCE_PU | + RTC_CNTL_BB_I2C_FORCE_PU); + } + + /* Cancel RTC REG force PU */ + + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_PU, 0); + modifyreg32(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU | + RTC_CNTL_DBOOST_FORCE_PU, 0); + + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU | + RTC_CNTL_FASTMEM_FORCE_PU | + RTC_CNTL_SLOWMEM_FORCE_NOISO | + RTC_CNTL_FASTMEM_FORCE_NOISO, 0); + + if (cfg.rtc_dboost_fpd) + { + modifyreg32(RTC_CNTL_REG, 0, RTC_CNTL_DBOOST_FORCE_PD); + } + else + { + modifyreg32(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD, 0); + } + + /* cancel digital pu force */ + + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU | + RTC_CNTL_FASTMEM_FORCE_PU, 0); + + /* If this mask is enabled, all soc mem cannot enter power down mode + * We should control soc memory power down mode from RTC, so we will + * not touch this register any more + */ + + modifyreg32(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK, 0); + + /* If this pd_cfg is set to 1, all memory won't enter low power mode + * during light sleep. + * If this pd_cfg is set to 0, all memory will enter low power mode + * during light sleep. + */ + + struct esp32s2_rtc_sleep_pd_config_s + pu_cfg = RTC_SLEEP_PD_CONFIG_ALL(0); + esp32s2_rtc_sleep_pd(pu_cfg); + + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU, 0); + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_WIFI_FORCE_PU, 0); + modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO | + RTC_CNTL_DG_WRAP_FORCE_ISO, 0); + + modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | + RTC_CNTL_DG_WRAP_FORCE_NOISO, 0); + + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO, 0); + + /* cancel digital PADS force no iso */ + + if (cfg.cpu_waiti_clk_gate) + { + modifyreg32(SYSTEM_CPU_PER_CONF_REG, + SYSTEM_CPU_WAIT_MODE_FORCE_ON, 0); + } + else + { + modifyreg32(SYSTEM_CPU_PER_CONF_REG, 0, + SYSTEM_CPU_WAIT_MODE_FORCE_ON); + } + + /* If SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0, the cpu clk will be closed + * when cpu enter WAITI mode + */ + + modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD | + RTC_CNTL_DG_PAD_FORCE_NOISO, 0); + } +} + +/**************************************************************************** + * Name: esp32s2_rtc_time_get + * + * Description: + * Get current value of RTC counter. + * + * Input Parameters: + * None + * + * Returned Value: + * Current value of RTC counter + * + ****************************************************************************/ + +uint64_t IRAM_ATTR esp32s2_rtc_time_get(void) +{ + uint64_t rtc_time; + + modifyreg32(RTC_CNTL_TIME_UPDATE_REG, 0, RTC_CNTL_TIME_UPDATE); + + rtc_time = getreg32(RTC_CNTL_TIME0_REG); + rtc_time |= ((uint64_t) getreg32(RTC_CNTL_TIME1_REG)) << 32; + + return rtc_time; +} + +/**************************************************************************** + * Name: esp32s2_rtc_time_us_to_slowclk + * + * Description: + * Convert time interval from microseconds to RTC_SLOW_CLK cycles. + * + * Input Parameters: + * time_in_us - Time interval in microseconds + * period - Period of slow clock in microseconds + * + * Returned Value: + * Number of slow clock cycles + * + ****************************************************************************/ + +uint64_t IRAM_ATTR esp32s2_rtc_time_us_to_slowclk(uint64_t time_in_us, + uint32_t period) +{ + uint64_t slow_clk_cycles = 0; + uint64_t max_time_in_us = (UINT64_C(1) << 45) - 1; + + /* Handle overflow that would happen if time_in_us >= 2^45 */ + + while (time_in_us > max_time_in_us) + { + time_in_us -= max_time_in_us; + slow_clk_cycles += ((max_time_in_us << RTC_CLK_CAL_FRACT) / period); + } + + slow_clk_cycles += ((time_in_us << RTC_CLK_CAL_FRACT) / period); + + return slow_clk_cycles; +} + +/**************************************************************************** + * Name: esp32s2_rtc_time_slowclk_to_us + * + * Description: + * Convert time interval from RTC_SLOW_CLK to microseconds + * + * Input Parameters: + * rtc_cycles - Time interval in RTC_SLOW_CLK cycles + * period - Period of slow clock in microseconds + * + * Returned Value: + * Time interval in microseconds + * + ****************************************************************************/ + +uint64_t IRAM_ATTR esp32s2_rtc_time_slowclk_to_us(uint64_t rtc_cycles, + uint32_t period) +{ + return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT; +} + +/**************************************************************************** + * Name: esp32s2_clk_slowclk_cal_get + * + * Description: + * Get the calibration value of RTC slow clock. + * + * Input Parameters: + * None + * + * Returned Value: + * The calibration value obtained using rtc_clk_cal + * + ****************************************************************************/ + +uint32_t IRAM_ATTR esp32s2_clk_slowclk_cal_get(void) +{ + return getreg32(RTC_SLOW_CLK_CAL_REG); +} + +/**************************************************************************** + * Name: esp32s2_rtc_sleep_set_wakeup_time + * + * Description: + * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. + * + * Input Parameters: + * t - value of RTC counter at which wakeup from sleep will happen. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_sleep_set_wakeup_time(uint64_t t) +{ + putreg32(t & UINT32_MAX, RTC_CNTL_SLP_TIMER0_REG); + putreg32((uint32_t)(t >> 32), RTC_CNTL_SLP_TIMER1_REG); +} + +/**************************************************************************** + * Name: esp32s2_rtc_wait_for_slow_cycle + * + * Description: + * Busy loop until next RTC_SLOW_CLK cycle. + * + * Input Parameters: + * None + * + * Returned Value: + * none + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_wait_for_slow_cycle(void) +{ + modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | + TIMG_RTC_CALI_START, 0); + modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY, 0); + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, + RTC_CAL_RTC_MUX); + + /* Request to run calibration for 0 slow clock cycles. + * RDY bit will be set on the nearest slow clock cycle. + */ + + REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0); + modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); + + /* RDY needs some time to go low */ + + up_udelay(1); + + while (!(getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY)) + { + up_udelay(1); + } +} + +void esp32s2_rtc_clk_apb_freq_update(uint32_t apb_freq) +{ + g_apb_freq = apb_freq; +} + +uint32_t esp32s2_rtc_clk_apb_freq_get(void) +{ + return g_apb_freq; +} + +/**************************************************************************** + * Name: esp32s2_rtc_cpu_freq_set_xtal + * + * Description: + * Switch CPU clock source to XTAL + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_cpu_freq_set_xtal(void) +{ + int freq_mhz = (int) esp32s2_rtc_clk_xtal_freq_get(); + esp32s2_rtc_update_to_xtal(freq_mhz, 1); + esp32s2_rtc_wait_for_slow_cycle(); +} + +/**************************************************************************** + * Name: esp_rtc_clk_get_cpu_freq + * + * Description: + * Get the currently used CPU frequency configuration. + * + * Input Parameters: + * None + * + * Returned Value: + * CPU frequency + * + ****************************************************************************/ + +int IRAM_ATTR esp_rtc_clk_get_cpu_freq(void) +{ + uint32_t source_freq_mhz; + uint32_t div; + uint32_t soc_clk_sel; + uint32_t cpuperiod_sel; + int freq_mhz = 0; + + soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); + switch (soc_clk_sel) + { + case DPORT_SOC_CLK_SEL_XTAL: + { + div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_PRE_DIV_CNT) + 1; + source_freq_mhz = (uint32_t) esp32s2_rtc_clk_xtal_freq_get(); + freq_mhz = source_freq_mhz / div; + } + break; + + case DPORT_SOC_CLK_SEL_PLL: + { + cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, + SYSTEM_CPUPERIOD_SEL); + uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, + SYSTEM_PLL_FREQ_SEL); + source_freq_mhz = (pllfreq_sel) ? RTC_PLL_FREQ_480M : + RTC_PLL_FREQ_320M; + if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) + { + div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4; + freq_mhz = 480 / div; + } + else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) + { + div = 3; + freq_mhz = 480 / div; + } + else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) + { + div = 2; + freq_mhz = 480 / div; + } + else + { + rtcerr("unsupported frequency configuration"); + return -ENODEV; + } + } + break; + + case DPORT_SOC_CLK_SEL_8M: + { + source_freq_mhz = 8; + div = 1; + freq_mhz = source_freq_mhz / div; + } + break; + + default: + { + rtcerr("unsupported frequency configuration"); + return -ENODEV; + } + } + + return freq_mhz; +} + +/**************************************************************************** + * Name: esp32s2_rtc_sleep_init + * + * Description: + * Prepare the chip to enter sleep mode + * + * Input Parameters: + * flags - sleep mode configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_sleep_init(uint32_t flags) +{ + struct esp32s2_rtc_sleep_config_s cfg = RTC_SLEEP_CONFIG_DEFAULT(flags); + + /* Starts here */ + + if (cfg.lslp_mem_inf_fpu) + { + struct esp32s2_rtc_sleep_pd_config_s + pu_cfg = RTC_SLEEP_PD_CONFIG_ALL(1); + esp32s2_rtc_sleep_pd(pu_cfg); + } + + if (cfg.rtc_mem_inf_follow_cpu) + { + modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_SLOWMEM_FOLW_CPU | + RTC_CNTL_FASTMEM_FOLW_CPU); + } + else + { + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FOLW_CPU | + RTC_CNTL_FASTMEM_FOLW_CPU, 0); + } + + if (cfg.rtc_fastmem_pd_en) + { + modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_FASTMEM_PD_EN); + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU, 0); + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO, 0); + } + else + { + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN, 0); + modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_FASTMEM_FORCE_PU); + modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_FASTMEM_FORCE_NOISO); + } + + if (cfg.rtc_slowmem_pd_en) + { + modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_SLOWMEM_PD_EN); + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU, 0); + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO, 0); + } + else + { + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN, 0); + modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_SLOWMEM_FORCE_PU); + modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_SLOWMEM_FORCE_NOISO); + } + + if (cfg.wifi_pd_en) + { + modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | + RTC_CNTL_WIFI_FORCE_ISO, 0); + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU, 0); + modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_WIFI_PD_EN); + } + else + { + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN, 0); + } + + if (cfg.rtc_peri_pd_en) + { + modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_PD_EN); + } + else + { + modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN, 0); + } + + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); + + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, + RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, + RTC_CNTL_BIASSLP_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, + (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_BIASSLP_SLEEP_ON : + RTC_CNTL_BIASSLP_SLEEP_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, + RTC_CNTL_PD_CUR_MONITOR_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, + (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_PD_CUR_SLEEP_ON : + RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, + cfg.dbg_atten_slp); + + if (cfg.deep_slp) + { + modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_ISO | + RTC_CNTL_DG_PAD_FORCE_NOISO, 0); + + /* Shut down parts of RTC which may have been left + * enabled by the wireless drivers. + */ + + modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | + RTC_CNTL_PLL_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | + RTC_CNTL_TXRF_I2C_PU, 0); + } + else + { + modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN, 0); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, + RTC_CNTL_DBG_ATTEN_DEEP_SLP, 0); + } + + REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, + cfg.xtal_fpu); + + if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL) == + RTC_SLOW_FREQ_8MD256) + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_CK8M_FORCE_PU); + } + else + { + modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, 0); + } + + /* Keep the RTC8M_CLK on in light_sleep mode if the + * ledc low-speed channel is clocked by RTC8M_CLK. + */ + + if (!cfg.deep_slp && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, + RTC_CNTL_DIG_CLK8M_EN_M)) + { + REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD); + REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); + } + + /* enable VDDSDIO control by state machine */ + + modifyreg32(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE, 0); + REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_REG_PD_EN, + cfg.vddsdio_pd_en); + + REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, + RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); + REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, + RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); + + REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, + cfg.xtal_fpu); +} + +/**************************************************************************** + * Name: esp32s2_rtc_sleep_start + * + * Description: + * Enter force sleep mode. + * + * Input Parameters: + * wakeup_opt - bit mask wake up reasons to enable + * reject_opt - bit mask of sleep reject reasons. + * + * Returned Value: + * Non-zero if sleep was rejected by hardware + * + ****************************************************************************/ + +int IRAM_ATTR esp32s2_rtc_sleep_start(uint32_t wakeup_opt, + uint32_t reject_opt) +{ + int reject; + REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, + RTC_CNTL_WAKEUP_ENA, wakeup_opt); + putreg32((uint32_t)reject_opt, RTC_CNTL_SLP_REJECT_CONF_REG); + + /* Start entry into sleep mode */ + + modifyreg32(RTC_CNTL_STATE0_REG, 0, RTC_CNTL_SLEEP_EN); + + while ((getreg32(RTC_CNTL_INT_RAW_RTC_REG) & + (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW)) == 0); + + /* In deep sleep mode, we never get here */ + + reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_RTC_REG, + RTC_CNTL_SLP_REJECT_INT_RAW); + + modifyreg32(RTC_CNTL_INT_CLR_RTC_REG, 0, + RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); + + /* restore DBG_ATTEN to the default value */ + + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, + RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT); + return reject; +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_cpu_freq_set_config + * + * Description: + * Set CPU frequency configuration. + * + * Input Parameters: + * config - CPU frequency configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_set_config( + const struct esp32s2_cpu_freq_config_s *config) +{ + uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL); + if (config->source == RTC_CPU_FREQ_SRC_XTAL) + { + esp32s2_rtc_update_to_xtal(config->freq_mhz, config->div); + if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) + { + esp32s2_rtc_clk_bbpll_disable(); + } + } + else if (config->source == RTC_CPU_FREQ_SRC_PLL) + { + if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) + { + modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | + RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD, + 0); + esp32s2_rtc_bbpll_configure(esp32s2_rtc_clk_xtal_freq_get(), + config->source_freq_mhz); + } + + esp32s2_rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); + } + else if (config->source == RTC_CPU_FREQ_SRC_8M) + { + esp32s2_rtc_clk_cpu_freq_to_8m(); + if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) + { + esp32s2_rtc_clk_bbpll_disable(); + } + } +} + +/**************************************************************************** + * Name: esp32s2_rtc_clk_cpu_freq_get_config + * + * Description: + * Get the currently used CPU frequency configuration. + * + * Input Parameters: + * out_config - CPU frequency configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_get_config( + struct esp32s2_cpu_freq_config_s *out_config) +{ + uint32_t div = 3; + uint32_t freq_mhz = 160; + uint32_t source_freq_mhz = RTC_PLL_FREQ_480M; + enum esp32s2_rtc_cpu_freq_src_e source = RTC_CPU_FREQ_SRC_PLL; + uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_SOC_CLK_SEL); + switch (soc_clk_sel) + { + case DPORT_SOC_CLK_SEL_XTAL: + { + source = RTC_CPU_FREQ_SRC_XTAL; + div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, + SYSTEM_PRE_DIV_CNT) + 1; + source_freq_mhz = (uint32_t) esp32s2_rtc_clk_xtal_freq_get(); + freq_mhz = source_freq_mhz / div; + } + break; + + case DPORT_SOC_CLK_SEL_PLL: + { + uint32_t cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, + SYSTEM_CPUPERIOD_SEL); + uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, + SYSTEM_PLL_FREQ_SEL); + source = RTC_CPU_FREQ_SRC_PLL; + source_freq_mhz = (pllfreq_sel) ? + RTC_PLL_FREQ_480M : RTC_PLL_FREQ_320M; + if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) + { + div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4; + freq_mhz = 80; + } + else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) + { + div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 3 : 2; + div = 3; + freq_mhz = 160; + } + else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) + { + div = 2; + freq_mhz = 240; + } + else + { + return; + } + } + break; + + case DPORT_SOC_CLK_SEL_8M: + { + source = RTC_CPU_FREQ_SRC_8M; + source_freq_mhz = 8; + div = 1; + freq_mhz = source_freq_mhz; + } + break; + + default: + PANIC(); + break; + } + + *out_config = (struct esp32s2_cpu_freq_config_s) + { + .source = source, + .source_freq_mhz = source_freq_mhz, + .div = div, + .freq_mhz = freq_mhz + }; +} + +/**************************************************************************** + * Name: esp32s2_rtc_get_time_us + * + * Description: + * Get current value of RTC counter in microseconds + * + * Input Parameters: + * None + * + * Returned Value: + * Current value of RTC counter in microseconds + * + ****************************************************************************/ + +uint64_t esp32s2_rtc_get_time_us(void) +{ + const uint32_t cal = getreg32(RTC_SLOW_CLK_CAL_REG); + const uint64_t rtc_this_ticks = esp32s2_rtc_time_get(); + + /* RTC counter result is up to 2^48, calibration factor is up to 2^24, + * for a 32KHz clock. We need to calculate (assuming no overflow): + * (ticks * cal) >> RTC_CLK_CAL_FRACT. An overflow in the (ticks * cal) + * multiplication would cause time to wrap around after approximately + * 13 days, which is probably not enough for some applications. + * Therefore multiplication is split into two terms, for the lower 32-bit + * and the upper 16-bit parts of "ticks", i.e.: + * ((ticks_low + 2^32 * ticks_high) * cal) >> RTC_CLK_CAL_FRACT + */ + + const uint64_t ticks_low = rtc_this_ticks & UINT32_MAX; + const uint64_t ticks_high = rtc_this_ticks >> 32; + const uint64_t delta_time_us = ((ticks_low * cal) >> RTC_CLK_CAL_FRACT) + + ((ticks_high * cal) << (32 - RTC_CLK_CAL_FRACT)); + + return delta_time_us; +} + +/**************************************************************************** + * Name: esp32_rtc_bbpll_disable + * + * Description: + * Disable BBPLL. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_bbpll_disable(void) +{ + modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_BB_I2C_FORCE_PD | + RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); +} + +/**************************************************************************** + * Name: esp32s2_rtc_set_boot_time + * + * Description: + * Set time to RTC register to replace the original boot time. + * + * Input Parameters: + * time_us - set time in microseconds. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void IRAM_ATTR esp32s2_rtc_set_boot_time(uint64_t time_us) +{ + putreg32((uint32_t)(time_us & UINT32_MAX), RTC_BOOT_TIME_LOW_REG); + putreg32((uint32_t)(time_us >> 32), RTC_BOOT_TIME_HIGH_REG); +} + +/**************************************************************************** + * Name: esp32s2_rtc_get_boot_time + * + * Description: + * Get time of RTC register to indicate the original boot time. + * + * Input Parameters: + * None + * + * Returned Value: + * Get time in microseconds. + * + ****************************************************************************/ + +uint64_t IRAM_ATTR esp32s2_rtc_get_boot_time(void) +{ + return ((uint64_t)getreg32(RTC_BOOT_TIME_LOW_REG)) + + (((uint64_t)getreg32(RTC_BOOT_TIME_HIGH_REG)) << 32); +} + +/**************************************************************************** + * Name: up_rtc_time + * + * Description: + * Get the current time in seconds. This is similar to the standard time() + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation is selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC is + * set but CONFIG_RTC_HIRES is not set. + * + * Input Parameters: + * None + * + * Returned Value: + * The current time in seconds + * + ****************************************************************************/ + +#ifndef CONFIG_RTC_HIRES +time_t up_rtc_time(void) +{ + uint64_t time_us; + irqstate_t flags; + + flags = spin_lock_irqsave(NULL); + + /* NOTE: RT-Timer starts to work after the board is initialized, and the + * RTC controller starts works after up_rtc_initialize is initialized. + * Since the system clock starts to work before the board is initialized, + * if CONFIG_RTC is enabled, the system time must be matched by the time + * of the RTC controller (up_rtc_initialize has already been initialized, + * and RT-Timer cannot work). + */ + + /* Determine if RT-Timer is started */ + + if (g_rt_timer_enabled == true) + { + /* Get the time from RT-Timer, the time interval between RTC + * controller and RT-Timer is stored in g_rtc_save->offset. + */ + + time_us = rt_timer_time_us() + g_rtc_save->offset + + esp32s2_rtc_get_boot_time(); + } + else + { + /* Get the time from RTC controller. */ + + time_us = esp32s2_rtc_get_time_us() + esp32s2_rtc_get_boot_time(); + } + + spin_unlock_irqrestore(NULL, flags); + + return (time_t)(time_us / USEC_PER_SEC); +} +#endif /* !CONFIG_RTC_HIRES */ + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be + * able to set their time based on a standard timespec. + * + * Input Parameters: + * ts - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(const struct timespec *ts) +{ + irqstate_t flags; + uint64_t now_us; + uint64_t rtc_offset_us; + + DEBUGASSERT(ts != NULL && ts->tv_nsec < NSEC_PER_SEC); + flags = spin_lock_irqsave(NULL); + + now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC + + ts->tv_nsec / NSEC_PER_USEC; + if (g_rt_timer_enabled == true) + { + /* Set based on RT-Timer offset value. */ + + rtc_offset_us = now_us - rt_timer_time_us(); + } + else + { + /* Set based on the offset value of the RT controller. */ + + rtc_offset_us = now_us - esp32s2_rtc_get_time_us(); + } + + g_rtc_save->offset = 0; + esp32s2_rtc_set_boot_time(rtc_offset_us); + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ + g_rtc_save = &rtc_saved_data; + + /* If saved data is invalid, clear offset information */ + + if (g_rtc_save->magic != MAGIC_RTC_SAVE) + { + g_rtc_save->magic = MAGIC_RTC_SAVE; + g_rtc_save->offset = 0; + esp32s2_rtc_set_boot_time(0); + } + +#ifdef CONFIG_RTC_HIRES + /* Synchronize the base time to the RTC time */ + + up_rtc_gettime(&g_basetime); +#endif + + g_rtc_enabled = true; + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_gettime + * + * Description: + * Get the current time from the high resolution RTC time or RT-Timer. This + * interface is only supported by the high-resolution RTC/counter hardware + * implementation. It is used to replace the system timer. + * + * Input Parameters: + * tp - The location to return the RTC time or RT-Timer value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_HIRES +int up_rtc_gettime(struct timespec *tp) +{ + irqstate_t flags; + uint64_t time_us; + + flags = spin_lock_irqsave(NULL); + + if (g_rt_timer_enabled == true) + { + time_us = rt_timer_time_us() + g_rtc_save->offset + + esp32s2_rtc_get_boot_time(); + } + else + { + time_us = esp32s2_rtc_get_time_us() + esp32s2_rtc_get_boot_time(); + } + + tp->tv_sec = time_us / USEC_PER_SEC; + tp->tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} +#endif /* CONFIG_RTC_HIRES */ + +#ifdef CONFIG_RTC_ALARM + +/**************************************************************************** + * Name: up_rtc_setalarm + * + * Description: + * Set up an alarm. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_setalarm(struct alm_setalarm_s *alminfo) +{ + struct rt_timer_args_s rt_timer_args; + struct alm_cbinfo_s *cbinfo; + irqstate_t flags; + int ret = -EBUSY; + int id; + + DEBUGASSERT(alminfo != NULL); + DEBUGASSERT((RTC_ALARM0 <= alminfo->as_id) && + (alminfo->as_id < RTC_ALARM_LAST)); + + /* Set the alarm in RT-Timer */ + + id = alminfo->as_id; + cbinfo = &g_alarmcb[id]; + + if (cbinfo->ac_cb == NULL) + { + /* Create the RT-Timer alarm */ + + flags = spin_lock_irqsave(NULL); + + if (cbinfo->alarm_hdl == NULL) + { + cbinfo->index = id; + rt_timer_args.arg = cbinfo; + rt_timer_args.callback = esp32s2_rt_cb_handler; + ret = rt_timer_create(&rt_timer_args, &cbinfo->alarm_hdl); + if (ret < 0) + { + rtcerr("ERROR: Failed to create rt_timer error=%d\n", ret); + spin_unlock_irqrestore(NULL, flags); + return ret; + } + } + + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; + cbinfo->deadline_us = alminfo->as_time.tv_sec * USEC_PER_SEC + + alminfo->as_time.tv_nsec / NSEC_PER_USEC; + + if (cbinfo->alarm_hdl == NULL) + { + rtcerr("ERROR: failed to create alarm timer\n"); + } + else + { + rtcinfo("Start RTC alarm.\n"); + rt_timer_start(cbinfo->alarm_hdl, cbinfo->deadline_us, false); + ret = OK; + } + + spin_unlock_irqrestore(NULL, flags); + } + + return ret; +} + +/**************************************************************************** + * Name: up_rtc_cancelalarm + * + * Description: + * Cancel an alarm. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_cancelalarm(enum alm_id_e alarmid) +{ + struct alm_cbinfo_s *cbinfo; + irqstate_t flags; + int ret = -ENODATA; + + DEBUGASSERT((RTC_ALARM0 <= alarmid) && + (alarmid < RTC_ALARM_LAST)); + + /* Set the alarm in hardware and enable interrupts */ + + cbinfo = &g_alarmcb[alarmid]; + + if (cbinfo->ac_cb != NULL) + { + flags = spin_lock_irqsave(NULL); + + /* Stop and delete the alarm */ + + rtcinfo("Cancel RTC alarm.\n"); + rt_timer_stop(cbinfo->alarm_hdl); + rt_timer_delete(cbinfo->alarm_hdl); + cbinfo->ac_cb = NULL; + cbinfo->deadline_us = 0; + cbinfo->alarm_hdl = NULL; + + spin_unlock_irqrestore(NULL, flags); + + ret = OK; + } + + return ret; +} + +/**************************************************************************** + * Name: up_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * tp - Location to return the timer match register. + * alarmid - Identifies the alarm to get. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid) +{ + irqstate_t flags; + struct alm_cbinfo_s *cbinfo; + DEBUGASSERT(tp != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarmid) && + (alarmid < RTC_ALARM_LAST)); + + flags = spin_lock_irqsave(NULL); + + /* Get the alarm according to the alarmid */ + + cbinfo = &g_alarmcb[alarmid]; + + tp->tv_sec = (rt_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us) / USEC_PER_SEC; + tp->tv_nsec = ((rt_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC; + + spin_unlock_irqrestore(NULL, flags); + + return OK; +} + +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: up_rtc_timer_init + * + * Description: + * Init RTC timer. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_timer_init(void) +{ + /* RT-Timer enabled */ + + g_rt_timer_enabled = true; + + /* Get the time difference between rt_timer and RTC timer */ + + g_rtc_save->offset = esp32s2_rtc_get_time_us() - + rt_timer_time_us(); + + return OK; +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc.h b/arch/xtensa/src/esp32s2/esp32s2_rtc.h new file mode 100644 index 0000000000000..aa2633594403b --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc.h @@ -0,0 +1,754 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_rtc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include "hardware/esp32s2_soc.h" + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Number of cycles to wait from the 32KHz XTAL oscillator to + * consider it running. Larger values increase startup delay. + * Smaller values may cause false positive detection + * (i.e. oscillator runs for a few cycles and then stops). + */ + +#define SLOW_CLK_CAL_CYCLES 1024 + +/* Indicates that 32KHz oscillator gets input from external oscillator + * instead of a crystal. + */ + +#define EXT_OSC_FLAG BIT(3) + +/* Number of fractional bits in values returned by rtc_clk_cal */ + +#define RTC_CLK_CAL_FRACT 19 + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* CPU clock source */ + +enum esp32s2_rtc_cpu_freq_src_e +{ + RTC_CPU_FREQ_SRC_XTAL, /* XTAL */ + RTC_CPU_FREQ_SRC_PLL, /* PLL (480M or 320M) */ + RTC_CPU_FREQ_SRC_8M, /* Internal 8M RTC oscillator */ +}; + +/* Possible main XTAL frequency values. + * Enum values should be equal to frequency in MHz. + */ + +enum esp32s2_rtc_xtal_freq_e +{ + RTC_XTAL_FREQ_40M = 40, /* 40 MHz XTAL */ +}; + +/* RTC SLOW_CLK frequency values */ + +enum esp32s2_rtc_slow_freq_e +{ + RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */ + RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */ + RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided by 256 */ +}; + +/* RTC FAST_CLK frequency values */ + +enum esp32s2_rtc_fast_freq_e +{ + RTC_FAST_FREQ_XTALD4 = 0, /* Main XTAL, divided by 4 */ + RTC_FAST_FREQ_8M = 1, /* Internal 8 MHz RC oscillator */ +}; + +/* This is almost the same as esp32s2_rtc_slow_freq_e, except that we define + * an extra enum member for the external 32KHz oscillator. For convenience, + * lower 2 bits should correspond to esp32s2_rtc_slow_freq_e values. + */ + +enum esp32s2_slow_clk_sel_e +{ + /* Internal 90 kHz RC oscillator */ + + SLOW_CLK_90K = RTC_SLOW_FREQ_RTC, + + /* External 32 kHz XTAL */ + + SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, + + /* Internal 8 MHz RC oscillator, divided by 256 */ + + SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, + + /* External 32KHz oscillator connected to 32K_XP pin */ + + SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG +}; + +/* Clock source to be calibrated using rtc_clk_cal function */ + +enum esp32s2_rtc_cal_sel_e +{ + RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */ + RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */ + RTC_CAL_32K_XTAL = 2, /* External 32 kHz XTAL */ + RTC_CAL_INTERNAL_OSC = 3 /* Internal 150 kHz oscillator */ +}; + +/* CPU clock configuration structure */ + +struct esp32s2_cpu_freq_config_s +{ + /* The clock from which CPU clock is derived */ + + enum esp32s2_rtc_cpu_freq_src_e source; + uint32_t source_freq_mhz; /* Source clock frequency */ + uint32_t div; /* Divider, freq_mhz = source_freq_mhz / div */ + uint32_t freq_mhz; /* CPU clock frequency */ +}; + +#ifdef CONFIG_RTC_ALARM + +/* The form of an alarm callback */ + +typedef void (*alm_callback_t)(void *arg, unsigned int alarmid); + +enum alm_id_e +{ + RTC_ALARM0 = 0, /* RTC ALARM 0 */ + RTC_ALARM1 = 1, /* RTC ALARM 1 */ + RTC_ALARM_LAST, +}; + +/* Structure used to pass parameters to set an alarm */ + +struct alm_setalarm_s +{ + int as_id; /* enum alm_id_e */ + struct timespec as_time; /* Alarm expiration time */ + alm_callback_t as_cb; /* Callback (if non-NULL) */ + void *as_arg; /* Argument for callback */ +}; + +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_rtc_clk_slow_freq_get_hz + * + * Description: + * Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * Input Parameters: + * None + * + * Returned Value: + * RTC_SLOW_CLK frequency, in Hz + * + ****************************************************************************/ + +uint32_t esp32s2_rtc_clk_slow_freq_get_hz(void); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_fast_freq_get_hz + * + * Description: + * Get fast_clk_rtc source in Hz. + * + * Input Parameters: + * None + * + * Returned Value: + * The clock source in Hz. + * + ****************************************************************************/ + +uint32_t esp32s2_rtc_clk_fast_freq_get_hz(void); + +/**************************************************************************** + * Name: esp32s2_rtc_get_slow_clk_rtc + * + * Description: + * Get slow_clk_rtc source. + * + * Input Parameters: + * None + * + * Returned Value: + * The clock source: + * - SLOW_CK + * - CK_XTAL_32K + * - CK8M_D256_OUT + * + ****************************************************************************/ + +enum esp32s2_rtc_slow_freq_e esp32s2_rtc_get_slow_clk(void); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_cal + * + * Description: + * Measure RTC slow clock's period, based on main XTAL frequency + * + * Input Parameters: + * cal_clk - clock to be measured + * slowclk_cycles - number of slow clock cycles to average + * + * Returned Value: + * Average slow clock period in microseconds, Q13.19 fixed point format + * or 0 if calibration has timed out + * + ****************************************************************************/ + +uint32_t esp32s2_rtc_clk_cal(enum esp32s2_rtc_cal_sel_e cal_clk, + uint32_t slowclk_cycles); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_xtal_freq_get + * + * Description: + * Get main XTAL frequency + * + * Input Parameters: + * None + * + * Returned Value: + * XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values) + * + ****************************************************************************/ + +enum esp32s2_rtc_xtal_freq_e esp32s2_rtc_clk_xtal_freq_get(void); + +/**************************************************************************** + * Name: esp32s2_rtc_update_to_xtal + * + * Description: + * Switch to XTAL frequency, does not disable the PLL + * + * Input Parameters: + * freq - XTAL frequency + * div - REF_TICK divider + * + * Returned Value: + * none + * + ****************************************************************************/ + +void esp32s2_rtc_update_to_xtal(int freq, int div); + +/**************************************************************************** + * Name: esp32s2_rtc_bbpll_enable + * + * Description: + * Reset BBPLL configuration. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_bbpll_enable(void); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_set + * + * Description: + * Set RTC CLK frequency. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_clk_set(void); + +/**************************************************************************** + * Name: esp32s2_rtc_init + * + * Description: + * Initialize RTC clock and power control related functions. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_init(void); + +/**************************************************************************** + * Name: esp32s2_rtc_time_get + * + * Description: + * Get current value of RTC counter. + * + * Input Parameters: + * None + * + * Returned Value: + * Current value of RTC counter + * + ****************************************************************************/ + +uint64_t esp32s2_rtc_time_get(void); + +/**************************************************************************** + * Name: esp32s2_rtc_time_us_to_slowclk + * + * Description: + * Convert time interval from microseconds to RTC_SLOW_CLK cycles. + * + * Input Parameters: + * time_in_us - Time interval in microseconds + * period - Period of slow clock in microseconds + * + * Returned Value: + * number of slow clock cycles + * + ****************************************************************************/ + +uint64_t esp32s2_rtc_time_us_to_slowclk(uint64_t time_in_us, + uint32_t period); + +/**************************************************************************** + * Name: esp32s2_rtc_time_slowclk_to_us + * + * Description: + * Convert time interval from RTC_SLOW_CLK to microseconds + * + * Input Parameters: + * rtc_cycles - Time interval in RTC_SLOW_CLK cycles + * period - Period of slow clock in microseconds + * + * Returned Value: + * Time interval in microseconds + * + ****************************************************************************/ + +uint64_t esp32s2_rtc_time_slowclk_to_us(uint64_t rtc_cycles, + uint32_t period); + +/**************************************************************************** + * Name: esp32s2_clk_slowclk_cal_get + * + * Description: + * Get the calibration value of RTC slow clock. + * + * Input Parameters: + * None + * + * Returned Value: + * The calibration value obtained using rtc_clk_cal + * + ****************************************************************************/ + +uint32_t esp32s2_clk_slowclk_cal_get(void); + +/**************************************************************************** + * Name: esp32s2_rtc_bbpll_disable + * + * Description: + * Disable BBPLL. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_bbpll_disable(void); + +/**************************************************************************** + * Name: esp32s2_rtc_sleep_set_wakeup_time + * + * Description: + * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. + * + * Input Parameters: + * t - value of RTC counter at which wakeup from sleep will happen. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_sleep_set_wakeup_time(uint64_t t); + +/**************************************************************************** + * Name: esp32s2_rtc_wait_for_slow_cycle + * + * Description: + * Busy loop until next RTC_SLOW_CLK cycle. + * + * Input Parameters: + * None + * + * Returned Value: + * none + * + ****************************************************************************/ + +void esp32s2_rtc_wait_for_slow_cycle(void); + +/**************************************************************************** + * Name: esp32s2_rtc_cpu_freq_set_xtal + * + * Description: + * Switch CPU clock source to XTAL + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_cpu_freq_set_xtal(void); + +/**************************************************************************** + * Name: esp_rtc_clk_get_cpu_freq + * + * Description: + * Get the currently used CPU frequency configuration. + * + * Input Parameters: + * None + * + * Returned Value: + * CPU frequency + * + ****************************************************************************/ + +int esp_rtc_clk_get_cpu_freq(void); + +/**************************************************************************** + * Name: esp32s2_rtc_sleep_init + * + * Description: + * Prepare the chip to enter sleep mode + * + * Input Parameters: + * flags - sleep mode configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_sleep_init(uint32_t flags); + +/**************************************************************************** + * Name: esp32s2_rtc_sleep_start + * + * Description: + * Enter force sleep mode. + * + * Input Parameters: + * wakeup_opt - bit mask wake up reasons to enable + * reject_opt - bit mask of sleep reject reasons. + * + * Returned Value: + * Non-zero if sleep was rejected by hardware + * + ****************************************************************************/ + +int esp32s2_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); + +/**************************************************************************** + * Name: esp32s2_rtc_get_time_us + * + * Description: + * Get current value of RTC counter in microseconds + * + * Input Parameters: + * None + * + * Returned Value: + * Current value of RTC counter in microseconds + * + ****************************************************************************/ + +uint64_t esp32s2_rtc_get_time_us(void); + +/**************************************************************************** + * Name: esp32s2_rtc_set_boot_time + * + * Description: + * Set time to RTC register to replace the original boot time. + * + * Input Parameters: + * time_us - set time in microseconds. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_set_boot_time(uint64_t time_us); + +/**************************************************************************** + * Name: esp32s2_rtc_get_boot_time + * + * Description: + * Get time of RTC register to indicate the original boot time. + * + * Input Parameters: + * None + * + * Returned Value: + * Get time in microseconds. + * + ****************************************************************************/ + +uint64_t esp32s2_rtc_get_boot_time(void); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_cpu_freq_set_config + * + * Description: + * Set CPU frequency configuration. + * + * Input Parameters: + * config - CPU frequency configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_clk_cpu_freq_set_config( + const struct esp32s2_cpu_freq_config_s *config); + +/**************************************************************************** + * Name: esp32s2_rtc_clk_cpu_freq_get_config + * + * Description: + * Get the currently used CPU frequency configuration. + * + * Input Parameters: + * out_config - CPU frequency configuration + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp32s2_rtc_clk_cpu_freq_get_config( + struct esp32s2_cpu_freq_config_s *out_config); + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Name: up_rtc_time + * + * Description: + * Get the current time in seconds. This is similar to the standard time() + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC is + * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. + * + * Input Parameters: + * None + * + * Returned Value: + * The current time in seconds + * + ****************************************************************************/ + +#ifndef CONFIG_RTC_HIRES +time_t up_rtc_time(void); +#endif + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be + * able to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(const struct timespec *ts); + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. + * This function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void); + +/**************************************************************************** + * Name: up_rtc_gettime + * + * Description: + * Get the current time from the high resolution RTC clock/counter. This + * interface is only supported by the high-resolution RTC/counter hardware + * implementation. It is used to replace the system timer. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_HIRES +int up_rtc_gettime(struct timespec *tp); +#endif + +#ifdef CONFIG_RTC_ALARM + +/**************************************************************************** + * Name: up_rtc_setalarm + * + * Description: + * Set up an alarm. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_setalarm(struct alm_setalarm_s *alminfo); + +/**************************************************************************** + * Name: up_rtc_cancelalarm + * + * Description: + * Cancel an alaram. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_cancelalarm(enum alm_id_e alarmid); + +/**************************************************************************** + * Name: up_rtc_rdalarm + * + * Description: + * Query an alarm configured in hardware. + * + * Input Parameters: + * tp - Location to return the timer match register. + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid); + +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: up_rtc_timer_init + * + * Description: + * Init RTC timer. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_timer_init(void); + +#endif /* CONFIG_RTC_DRIVER */ + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c b/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c new file mode 100644 index 0000000000000..4faf215408084 --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c @@ -0,0 +1,554 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "esp32s2_rtc.h" +#include "hardware/esp32s2_tim.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +struct esp32s2_cbinfo_s +{ + volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ + volatile void *priv; /* Private argument to accompany callback */ +}; +#endif + +/* This is the private type for the RTC state. It must be cast compatible + * with struct rtc_lowerhalf_s. + */ + +struct esp32s2_lowerhalf_s +{ + /* This is the contained reference to the read-only, lower-half + * operations vtable (which may lie in FLASH or ROM) + */ + + const struct rtc_ops_s *ops; +#ifdef CONFIG_RTC_ALARM + /* Alarm callback information */ + + struct esp32s2_cbinfo_s cbinfo[RTC_ALARM_LAST]; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Prototypes for static methods in struct rtc_ops_s */ + +static int rtc_lh_rdtime(struct rtc_lowerhalf_s *lower, + struct rtc_time *rtctime); +static int rtc_lh_settime(struct rtc_lowerhalf_s *lower, + const struct rtc_time *rtctime); +static bool rtc_lh_havesettime(struct rtc_lowerhalf_s *lower); + +#ifdef CONFIG_RTC_ALARM +static void rtc_lh_alarm_callback(void *arg, unsigned int alarmid); +static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, + const struct lower_setalarm_s *alarminfo); +static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, + const struct lower_setrelative_s *alarminfo); +static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); +static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, + struct lower_rdalarm_s *alarminfo); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* ESP32S2 RTC driver operations */ + +static const struct rtc_ops_s g_rtc_ops = +{ + .rdtime = rtc_lh_rdtime, + .settime = rtc_lh_settime, + .havesettime = rtc_lh_havesettime, +#ifdef CONFIG_RTC_ALARM + .setalarm = rtc_lh_setalarm, + .setrelative = rtc_lh_setrelative, + .cancelalarm = rtc_lh_cancelalarm, + .rdalarm = rtc_lh_rdalarm, +#endif +}; + +/* ESP32S2 RTC device state */ + +static struct esp32s2_lowerhalf_s g_rtc_lowerhalf = +{ + .ops = &g_rtc_ops, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rtc_lh_alarm_callback + * + * Description: + * This is the function that is called from the RTC driver when the alarm + * goes off. It just invokes the upper half drivers callback. + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static void rtc_lh_alarm_callback(void *arg, unsigned int alarmid) +{ + struct esp32s2_lowerhalf_s *lower; + struct esp32s2_cbinfo_s *cbinfo; + rtc_alarm_callback_t cb; + void *priv; + + DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); + + lower = (struct esp32s2_lowerhalf_s *)arg; + cbinfo = &lower->cbinfo[alarmid]; + + /* Sample and clear the callback information to minimize the window in + * time in which race conditions can occur. + */ + + cb = (rtc_alarm_callback_t)cbinfo->cb; + priv = (void *)cbinfo->priv; + + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(priv, alarmid); + } +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_rdtime + * + * Description: + * Returns the current RTC time. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The location in which to return the current RTC time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int rtc_lh_rdtime(struct rtc_lowerhalf_s *lower, + struct rtc_time *rtctime) +{ +#if defined(CONFIG_RTC_HIRES) + struct timespec ts; + int ret; + + /* Get the higher resolution time */ + + ret = up_rtc_gettime(&ts); + if (ret < 0) + { + goto errout; + } + + /* Convert the one second epoch time to a struct tm. This operation + * depends on the fact that struct rtc_time and struct tm are cast + * compatible. + */ + + if (!gmtime_r(&ts.tv_sec, (struct tm *)rtctime)) + { + ret = -get_errno(); + goto errout; + } + + return OK; + +errout: + rtcerr("ERROR: failed to get RTC time: %d\n", ret); + return ret; + +#else + time_t timer; + + /* The resolution of time is only 1 second */ + + timer = up_rtc_time(); + + /* Convert the one second epoch time to a struct tm */ + + if (gmtime_r(&timer, (struct tm *)rtctime) == 0) + { + int errcode = get_errno(); + DEBUGASSERT(errcode > 0); + + rtcerr("ERROR: gmtime_r failed: %d\n", errcode); + return -errcode; + } + + return OK; +#endif +} + +/**************************************************************************** + * Name: rtc_lh_settime + * + * Description: + * Implements the settime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The new time to set + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int rtc_lh_settime(struct rtc_lowerhalf_s *lower, + const struct rtc_time *rtctime) +{ + struct timespec ts; + + /* Convert the struct rtc_time to a time_t. Here we assume that struct + * rtc_time is cast compatible with struct tm. + */ + + ts.tv_sec = mktime((struct tm *)rtctime); + ts.tv_nsec = 0; + + /* Now set the time (with an accuracy of seconds) */ + + return up_rtc_settime(&ts); +} + +/**************************************************************************** + * Name: rtc_lh_havesettime + * + * Description: + * Implements the havesettime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * + * Returned Value: + * Returns true if RTC date-time has been previously set. + * + ****************************************************************************/ + +static bool rtc_lh_havesettime(struct rtc_lowerhalf_s *lower) +{ + if (esp32s2_rtc_get_boot_time() == 0) + { + return false; + } + + return true; +} + +/**************************************************************************** + * Name: rtc_lh_setalarm + * + * Description: + * Set a new alarm. This function implements the setalarm() method of the + * RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, + const struct lower_setalarm_s *alarminfo) +{ + struct esp32s2_lowerhalf_s *priv; + struct esp32s2_cbinfo_s *cbinfo; + struct alm_setalarm_s lowerinfo; + int ret; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && + (alarminfo->id < RTC_ALARM_LAST)); + + priv = (struct esp32s2_lowerhalf_s *)lower; + + /* Remember the callback information */ + + cbinfo = &priv->cbinfo[alarminfo->id]; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + + /* Set the alarm */ + + lowerinfo.as_id = alarminfo->id; + lowerinfo.as_cb = rtc_lh_alarm_callback; + lowerinfo.as_arg = priv; + + /* Convert the RTC time to a timespec (1 second accuracy) */ + + lowerinfo.as_time.tv_sec = mktime((struct tm *)&alarminfo->time); + lowerinfo.as_time.tv_nsec = 0; + + /* And set the alarm */ + + ret = up_rtc_setalarm(&lowerinfo); + if (ret < 0) + { + cbinfo->cb = NULL; + cbinfo->priv = NULL; + } + + return ret; +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_setrelative + * + * Description: + * Set a new alarm relative to the current time. This function implements + * the setrelative() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, + const struct lower_setrelative_s *alarminfo) +{ + struct lower_setalarm_s setalarm; + time_t seconds; + int ret = -EINVAL; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && + (alarminfo->id < RTC_ALARM_LAST)); + + if (alarminfo->reltime > 0) + { + flags = spin_lock_irqsave(NULL); + + seconds = alarminfo->reltime; + gmtime_r(&seconds, (struct tm *)&setalarm.time); + + /* The set the alarm using this absolute time */ + + setalarm.id = alarminfo->id; + setalarm.cb = alarminfo->cb; + setalarm.priv = alarminfo->priv; + ret = rtc_lh_setalarm(lower, &setalarm); + + spin_unlock_irqrestore(NULL, flags); + } + + return ret; +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_cancelalarm + * + * Description: + * Cancel the current alarm. This function implements the cancelalarm() + * method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarmid - the alarm id + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) +{ + struct esp32s2_lowerhalf_s *priv; + struct esp32s2_cbinfo_s *cbinfo; + + DEBUGASSERT(lower != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); + + priv = (struct esp32s2_lowerhalf_s *)lower; + + /* Nullify callback information to reduce window for race conditions */ + + cbinfo = &priv->cbinfo[alarmid]; + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Then cancel the alarm */ + + return up_rtc_cancelalarm((enum alm_id_e)alarmid); +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: rtc_lh_rdalarm + * + * Description: + * Query the RTC alarm. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to query the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, + struct lower_rdalarm_s *alarminfo) +{ + struct timespec ts; + int ret; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL); + DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && + (alarminfo->id < RTC_ALARM_LAST)); + + flags = spin_lock_irqsave(NULL); + + ret = up_rtc_rdalarm(&ts, alarminfo->id); + localtime_r((const time_t *)&ts.tv_sec, + (struct tm *)alarminfo->time); + + spin_unlock_irqrestore(NULL, flags); + + return ret; +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_rtc_lowerhalf + * + * Description: + * Instantiate the RTC lower half driver for the ESP32S2. + * + * Input Parameters: + * None + * + * Returned Value: + * On success, a non-NULL RTC lower interface is returned. NULL is + * returned on any failure. + * + ****************************************************************************/ + +struct rtc_lowerhalf_s *esp32s2_rtc_lowerhalf(void) +{ + return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; +} + +/**************************************************************************** + * Name: esp32s2_rtc_driverinit + * + * Description: + * Bind the configuration timer to a timer lower half instance and register + * the timer drivers at 'devpath' + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32s2_rtc_driverinit(void) +{ + int ret = ERROR; + struct rtc_lowerhalf_s *lower; + + /* Instantiate the ESP32S2 lower-half RTC driver */ + + lower = esp32s2_rtc_lowerhalf(); + if (lower == NULL) + { + return ret; + } + else + { + /* Bind the lower half driver and register the combined RTC driver + * as /dev/rtc0 + */ + + ret = rtc_initialize(0, lower); + } + + /* Init RTC timer */ + + up_rtc_timer_init(); + + return ret; +} diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h b/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h new file mode 100644 index 0000000000000..ecf80cace926b --- /dev/null +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_LOWERHALF_H +#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_LOWERHALF_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32s2_rtc_driverinit + * + * Description: + * Bind the configuration timer to a timer lower half instance and register + * the timer drivers at 'devpath' + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32s2_rtc_driverinit(void); + +#endif /* CONFIG_RTC_DRIVER */ + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_LOWERHALF_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_start.c b/arch/xtensa/src/esp32s2/esp32s2_start.c index 22a0b368eadd2..9d991bbaefc3d 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_start.c +++ b/arch/xtensa/src/esp32s2/esp32s2_start.c @@ -42,6 +42,7 @@ #include "esp32s2_start.h" #include "esp32s2_lowputc.h" #include "esp32s2_wdt.h" +#include "esp32s2_rtc.h" /**************************************************************************** * Pre-processor Definitions @@ -338,6 +339,11 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void) esp32s2_wdt_early_deinit(); + /* Initialize RTC parameters */ + + esp32s2_rtc_init(); + esp32s2_rtc_clk_set(); + /* Set CPU frequency configured in board.h */ esp32s2_clockconfig(); diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h index 8c461c13dfc75..bc11d21cc0107 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_extmem.h @@ -31,71 +31,2727 @@ * Pre-processor Definitions ****************************************************************************/ -#define EXTMEM_PRO_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x044) +/* EXTMEM_PRO_DCACHE_CTRL_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0) -/* EXTMEM_PRO_ICACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; - * description: The bit is used to disable ibus2 - * 0: enable 1: disable +/* EXTMEM_PRO_DCACHE_LOCK_DONE : RO; bitpos: [25]; default: 0; + * The bit is used to indicate lock operation is finished. */ -#define EXTMEM_PRO_ICACHE_MASK_BUS2 (BIT(2)) -#define EXTMEM_PRO_ICACHE_MASK_BUS2_M (BIT(2)) -#define EXTMEM_PRO_ICACHE_MASK_BUS2_V 0x1 -#define EXTMEM_PRO_ICACHE_MASK_BUS2_S 2 +#define EXTMEM_PRO_DCACHE_LOCK_DONE (BIT(25)) +#define EXTMEM_PRO_DCACHE_LOCK_DONE_M (EXTMEM_PRO_DCACHE_LOCK_DONE_V << EXTMEM_PRO_DCACHE_LOCK_DONE_S) +#define EXTMEM_PRO_DCACHE_LOCK_DONE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_LOCK_DONE_S 25 -/* EXTMEM_PRO_ICACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; - * description: The bit is used to disable ibus1 - * 0: enable 1: disable +/* EXTMEM_PRO_DCACHE_LOCK_ENA : R/W; bitpos: [24]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware + * after lock operation done. */ -#define EXTMEM_PRO_ICACHE_MASK_BUS1 (BIT(1)) -#define EXTMEM_PRO_ICACHE_MASK_BUS1_M (BIT(1)) -#define EXTMEM_PRO_ICACHE_MASK_BUS1_V 0x1 -#define EXTMEM_PRO_ICACHE_MASK_BUS1_S 1 +#define EXTMEM_PRO_DCACHE_LOCK_ENA (BIT(24)) +#define EXTMEM_PRO_DCACHE_LOCK_ENA_M (EXTMEM_PRO_DCACHE_LOCK_ENA_V << EXTMEM_PRO_DCACHE_LOCK_ENA_S) +#define EXTMEM_PRO_DCACHE_LOCK_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_LOCK_ENA_S 24 -/* EXTMEM_PRO_ICACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; - * description: The bit is used to disable ibus0 - * 0: enable 1: disable +/* EXTMEM_PRO_DCACHE_UNLOCK_DONE : RO; bitpos: [23]; default: 0; + * The bit is used to indicate unlock operation is finished. */ -#define EXTMEM_PRO_ICACHE_MASK_BUS0 (BIT(0)) -#define EXTMEM_PRO_ICACHE_MASK_BUS0_M (BIT(0)) -#define EXTMEM_PRO_ICACHE_MASK_BUS0_V 0x1 -#define EXTMEM_PRO_ICACHE_MASK_BUS0_S 0 -#define EXTMEM_PRO_ICACHE_MASK_IRAM0 EXTMEM_PRO_ICACHE_MASK_BUS0 -#define EXTMEM_PRO_ICACHE_MASK_IRAM1 EXTMEM_PRO_ICACHE_MASK_BUS1 -#define EXTMEM_PRO_ICACHE_MASK_DROM0 EXTMEM_PRO_ICACHE_MASK_BUS2 +#define EXTMEM_PRO_DCACHE_UNLOCK_DONE (BIT(23)) +#define EXTMEM_PRO_DCACHE_UNLOCK_DONE_M (EXTMEM_PRO_DCACHE_UNLOCK_DONE_V << EXTMEM_PRO_DCACHE_UNLOCK_DONE_S) +#define EXTMEM_PRO_DCACHE_UNLOCK_DONE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_UNLOCK_DONE_S 23 -#define EXTMEM_PRO_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) +/* EXTMEM_PRO_DCACHE_UNLOCK_ENA : R/W; bitpos: [22]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by + * hardware after unlock operation done. + */ -/* EXTMEM_PRO_DCACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +#define EXTMEM_PRO_DCACHE_UNLOCK_ENA (BIT(22)) +#define EXTMEM_PRO_DCACHE_UNLOCK_ENA_M (EXTMEM_PRO_DCACHE_UNLOCK_ENA_V << EXTMEM_PRO_DCACHE_UNLOCK_ENA_S) +#define EXTMEM_PRO_DCACHE_UNLOCK_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_UNLOCK_ENA_S 22 -/* Description: The bit is used to disable dbus2 0: enable 1: disable */ +/* EXTMEM_PRO_DCACHE_PRELOAD_DONE : RO; bitpos: [21]; default: 0; + * The bit is used to indicate preload operation is finished. + */ -#define EXTMEM_PRO_DCACHE_MASK_BUS2 (BIT(2)) -#define EXTMEM_PRO_DCACHE_MASK_BUS2_M (BIT(2)) -#define EXTMEM_PRO_DCACHE_MASK_BUS2_V 0x1 -#define EXTMEM_PRO_DCACHE_MASK_BUS2_S 2 +#define EXTMEM_PRO_DCACHE_PRELOAD_DONE (BIT(21)) +#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_M (EXTMEM_PRO_DCACHE_PRELOAD_DONE_V << EXTMEM_PRO_DCACHE_PRELOAD_DONE_S) +#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_PRELOAD_DONE_S 21 -/* EXTMEM_PRO_DCACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/* EXTMEM_PRO_DCACHE_PRELOAD_ENA : R/W; bitpos: [20]; default: 0; + * The bit is used to enable preload operation. It will be cleared by + * hardware after preload operation done. + */ -/* Description: The bit is used to disable dbus1 0: enable 1: disable */ +#define EXTMEM_PRO_DCACHE_PRELOAD_ENA (BIT(20)) +#define EXTMEM_PRO_DCACHE_PRELOAD_ENA_M (EXTMEM_PRO_DCACHE_PRELOAD_ENA_V << EXTMEM_PRO_DCACHE_PRELOAD_ENA_S) +#define EXTMEM_PRO_DCACHE_PRELOAD_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_PRELOAD_ENA_S 20 -#define EXTMEM_PRO_DCACHE_MASK_BUS1 (BIT(1)) -#define EXTMEM_PRO_DCACHE_MASK_BUS1_M (BIT(1)) -#define EXTMEM_PRO_DCACHE_MASK_BUS1_V 0x1 -#define EXTMEM_PRO_DCACHE_MASK_BUS1_S 1 +/* EXTMEM_PRO_DCACHE_AUTOLOAD_DONE : RO; bitpos: [19]; default: 0; + * The bit is used to indicate conditional-preload operation is finished. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE (BIT(19)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_M (EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_V << EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_DONE_S 19 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_ENA : R/W; bitpos: [18]; default: 0; + * The bit is used to enable and disable conditional-preload operation. It + * is combined with pre_dcache_autoload_done. 1: enable, 0: disable. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA (BIT(18)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_M (EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_V << EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ENA_S 18 + +/* EXTMEM_PRO_DCACHE_LOCK1_EN : R/W; bitpos: [15]; default: 0; + * The bit is used to enable pre-lock operation which is combined with + * PRO_DCACHE_LOCK1_ADDR_REG and PRO_DCACHE_LOCK1_SIZE_REG. + */ + +#define EXTMEM_PRO_DCACHE_LOCK1_EN (BIT(15)) +#define EXTMEM_PRO_DCACHE_LOCK1_EN_M (EXTMEM_PRO_DCACHE_LOCK1_EN_V << EXTMEM_PRO_DCACHE_LOCK1_EN_S) +#define EXTMEM_PRO_DCACHE_LOCK1_EN_V 0x00000001 +#define EXTMEM_PRO_DCACHE_LOCK1_EN_S 15 + +/* EXTMEM_PRO_DCACHE_LOCK0_EN : R/W; bitpos: [14]; default: 0; + * The bit is used to enable pre-lock operation which is combined with + * PRO_DCACHE_LOCK0_ADDR_REG and PRO_DCACHE_LOCK0_SIZE_REG. + */ + +#define EXTMEM_PRO_DCACHE_LOCK0_EN (BIT(14)) +#define EXTMEM_PRO_DCACHE_LOCK0_EN_M (EXTMEM_PRO_DCACHE_LOCK0_EN_V << EXTMEM_PRO_DCACHE_LOCK0_EN_S) +#define EXTMEM_PRO_DCACHE_LOCK0_EN_V 0x00000001 +#define EXTMEM_PRO_DCACHE_LOCK0_EN_S 14 + +/* EXTMEM_PRO_DCACHE_CLEAN_DONE : RO; bitpos: [13]; default: 0; + * The bit is used to indicate clean operation is finished. + */ + +#define EXTMEM_PRO_DCACHE_CLEAN_DONE (BIT(13)) +#define EXTMEM_PRO_DCACHE_CLEAN_DONE_M (EXTMEM_PRO_DCACHE_CLEAN_DONE_V << EXTMEM_PRO_DCACHE_CLEAN_DONE_S) +#define EXTMEM_PRO_DCACHE_CLEAN_DONE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_CLEAN_DONE_S 13 + +/* EXTMEM_PRO_DCACHE_CLEAN_ENA : R/W; bitpos: [12]; default: 0; + * The bit is used to enable clean operation. It will be cleared by hardware + * after clean operation done. + */ + +#define EXTMEM_PRO_DCACHE_CLEAN_ENA (BIT(12)) +#define EXTMEM_PRO_DCACHE_CLEAN_ENA_M (EXTMEM_PRO_DCACHE_CLEAN_ENA_V << EXTMEM_PRO_DCACHE_CLEAN_ENA_S) +#define EXTMEM_PRO_DCACHE_CLEAN_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_CLEAN_ENA_S 12 + +/* EXTMEM_PRO_DCACHE_FLUSH_DONE : RO; bitpos: [11]; default: 0; + * The bit is used to indicate flush operation is finished. + */ + +#define EXTMEM_PRO_DCACHE_FLUSH_DONE (BIT(11)) +#define EXTMEM_PRO_DCACHE_FLUSH_DONE_M (EXTMEM_PRO_DCACHE_FLUSH_DONE_V << EXTMEM_PRO_DCACHE_FLUSH_DONE_S) +#define EXTMEM_PRO_DCACHE_FLUSH_DONE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_FLUSH_DONE_S 11 + +/* EXTMEM_PRO_DCACHE_FLUSH_ENA : R/W; bitpos: [10]; default: 0; + * The bit is used to enable flush operation. It will be cleared by hardware + * after flush operation done. + */ + +#define EXTMEM_PRO_DCACHE_FLUSH_ENA (BIT(10)) +#define EXTMEM_PRO_DCACHE_FLUSH_ENA_M (EXTMEM_PRO_DCACHE_FLUSH_ENA_V << EXTMEM_PRO_DCACHE_FLUSH_ENA_S) +#define EXTMEM_PRO_DCACHE_FLUSH_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_FLUSH_ENA_S 10 + +/* EXTMEM_PRO_DCACHE_INVALIDATE_DONE : RO; bitpos: [9]; default: 0; + * The bit is used to indicate invalidate operation is finished. + */ -/* EXTMEM_PRO_DCACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE (BIT(9)) +#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_M (EXTMEM_PRO_DCACHE_INVALIDATE_DONE_V << EXTMEM_PRO_DCACHE_INVALIDATE_DONE_S) +#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_INVALIDATE_DONE_S 9 -/* description: The bit is used to disable dbus0 0: enable 1: disable */ +/* EXTMEM_PRO_DCACHE_INVALIDATE_ENA : R/W; bitpos: [8]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by + * hardware after invalidate operation done. + */ + +#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA (BIT(8)) +#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_M (EXTMEM_PRO_DCACHE_INVALIDATE_ENA_V << EXTMEM_PRO_DCACHE_INVALIDATE_ENA_S) +#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_INVALIDATE_ENA_S 8 + +/* EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE : R/W; bitpos: [3]; default: 0; + * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes + */ + +#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE (BIT(3)) +#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_M (EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_V << EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_S) +#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_BLOCKSIZE_MODE_S 3 + +/* EXTMEM_PRO_DCACHE_SETSIZE_MODE : R/W; bitpos: [2]; default: 0; + * The bit is used to configure cache memory size.0: 8KB, 1: 16KB + */ + +#define EXTMEM_PRO_DCACHE_SETSIZE_MODE (BIT(2)) +#define EXTMEM_PRO_DCACHE_SETSIZE_MODE_M (EXTMEM_PRO_DCACHE_SETSIZE_MODE_V << EXTMEM_PRO_DCACHE_SETSIZE_MODE_S) +#define EXTMEM_PRO_DCACHE_SETSIZE_MODE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_SETSIZE_MODE_S 2 + +/* EXTMEM_PRO_DCACHE_ENABLE : R/W; bitpos: [0]; default: 0; + * The bit is used to activate the data cache. 0: disable, 1: enable + */ + +#define EXTMEM_PRO_DCACHE_ENABLE (BIT(0)) +#define EXTMEM_PRO_DCACHE_ENABLE_M (EXTMEM_PRO_DCACHE_ENABLE_V << EXTMEM_PRO_DCACHE_ENABLE_S) +#define EXTMEM_PRO_DCACHE_ENABLE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_ENABLE_S 0 + +/* EXTMEM_PRO_DCACHE_CTRL1_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4) + +/* EXTMEM_PRO_DCACHE_MASK_BUS2 : R/W; bitpos: [2]; default: 1; + * The bit is used to disable dbus2, 0: enable, 1: disable + */ -#define EXTMEM_PRO_DCACHE_MASK_BUS0 (BIT(0)) -#define EXTMEM_PRO_DCACHE_MASK_BUS0_M (BIT(0)) -#define EXTMEM_PRO_DCACHE_MASK_BUS0_V 0x1 +#define EXTMEM_PRO_DCACHE_MASK_BUS2 (BIT(2)) +#define EXTMEM_PRO_DCACHE_MASK_BUS2_M (EXTMEM_PRO_DCACHE_MASK_BUS2_V << EXTMEM_PRO_DCACHE_MASK_BUS2_S) +#define EXTMEM_PRO_DCACHE_MASK_BUS2_V 0x00000001 +#define EXTMEM_PRO_DCACHE_MASK_BUS2_S 2 + +/* EXTMEM_PRO_DCACHE_MASK_BUS1 : R/W; bitpos: [1]; default: 1; + * The bit is used to disable dbus1, 0: enable, 1: disable + */ + +#define EXTMEM_PRO_DCACHE_MASK_BUS1 (BIT(1)) +#define EXTMEM_PRO_DCACHE_MASK_BUS1_M (EXTMEM_PRO_DCACHE_MASK_BUS1_V << EXTMEM_PRO_DCACHE_MASK_BUS1_S) +#define EXTMEM_PRO_DCACHE_MASK_BUS1_V 0x00000001 +#define EXTMEM_PRO_DCACHE_MASK_BUS1_S 1 + +/* EXTMEM_PRO_DCACHE_MASK_BUS0 : R/W; bitpos: [0]; default: 1; + * The bit is used to disable dbus0, 0: enable, 1: disable + */ + +#define EXTMEM_PRO_DCACHE_MASK_BUS0 (BIT(0)) +#define EXTMEM_PRO_DCACHE_MASK_BUS0_M (EXTMEM_PRO_DCACHE_MASK_BUS0_V << EXTMEM_PRO_DCACHE_MASK_BUS0_S) +#define EXTMEM_PRO_DCACHE_MASK_BUS0_V 0x00000001 #define EXTMEM_PRO_DCACHE_MASK_BUS0_S 0 -#define EXTMEM_PRO_DCACHE_MASK_DRAM0 EXTMEM_PRO_DCACHE_MASK_BUS0 -#define EXTMEM_PRO_DCACHE_MASK_DRAM1 EXTMEM_PRO_DCACHE_MASK_BUS1 -#define EXTMEM_PRO_DCACHE_MASK_DPORT EXTMEM_PRO_DCACHE_MASK_BUS2 + +/* EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8) + +/* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, + * 1: power up + */ + +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_M (EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_V << EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_S) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_V 0x00000001 +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PU_S 2 + +/* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd, + * 1: power down + */ + +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_M (EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_V << EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_S) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_V 0x00000001 +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_PD_S 1 + +/* EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; + * The bit is used to close clock gating of dcache tag memory. 1: close + * gating, 0: open clock gating. + */ + +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_M (EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_V << EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_S) +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_V 0x00000001 +#define EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON_S 0 + +/* EXTMEM_PRO_DCACHE_LOCK0_ADDR_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE + 0xc) + +/* EXTMEM_PRO_DCACHE_LOCK0_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the first start virtual address of data + * locking, which is combined with PRO_DCACHE_LOCK0_SIZE_REG + */ + +#define EXTMEM_PRO_DCACHE_LOCK0_ADDR 0xffffffff +#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_M (EXTMEM_PRO_DCACHE_LOCK0_ADDR_V << EXTMEM_PRO_DCACHE_LOCK0_ADDR_S) +#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_V 0xffffffff +#define EXTMEM_PRO_DCACHE_LOCK0_ADDR_S 0 + +/* EXTMEM_PRO_DCACHE_LOCK0_SIZE_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x10) + +/* EXTMEM_PRO_DCACHE_LOCK0_SIZE : R/W; bitpos: [15:0]; default: 0; + * The bits are used to configure the first length of data locking, which is + * combined with PRO_DCACHE_LOCK0_ADDR_REG + */ + +#define EXTMEM_PRO_DCACHE_LOCK0_SIZE 0x0000ffff +#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_M (EXTMEM_PRO_DCACHE_LOCK0_SIZE_V << EXTMEM_PRO_DCACHE_LOCK0_SIZE_S) +#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_V 0x0000ffff +#define EXTMEM_PRO_DCACHE_LOCK0_SIZE_S 0 + +/* EXTMEM_PRO_DCACHE_LOCK1_ADDR_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x14) + +/* EXTMEM_PRO_DCACHE_LOCK1_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the second start virtual address of data + * locking, which is combined with PRO_DCACHE_LOCK1_SIZE_REG + */ + +#define EXTMEM_PRO_DCACHE_LOCK1_ADDR 0xffffffff +#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_M (EXTMEM_PRO_DCACHE_LOCK1_ADDR_V << EXTMEM_PRO_DCACHE_LOCK1_ADDR_S) +#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_V 0xffffffff +#define EXTMEM_PRO_DCACHE_LOCK1_ADDR_S 0 + +/* EXTMEM_PRO_DCACHE_LOCK1_SIZE_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x18) + +/* EXTMEM_PRO_DCACHE_LOCK1_SIZE : R/W; bitpos: [15:0]; default: 0; + * The bits are used to configure the second length of data locking, which + * is combined with PRO_DCACHE_LOCK1_ADDR_REG + */ + +#define EXTMEM_PRO_DCACHE_LOCK1_SIZE 0x0000ffff +#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_M (EXTMEM_PRO_DCACHE_LOCK1_SIZE_V << EXTMEM_PRO_DCACHE_LOCK1_SIZE_S) +#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_V 0x0000ffff +#define EXTMEM_PRO_DCACHE_LOCK1_SIZE_S 0 + +/* EXTMEM_PRO_DCACHE_MEM_SYNC0_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_MEM_SYNC0_REG (DR_REG_EXTMEM_BASE + 0x1c) + +/* EXTMEM_PRO_DCACHE_MEMSYNC_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the start virtual address for invalidate, + * flush, clean, lock and unlock operations. The manual operations will be + * issued if the address is validate. The auto operations will be issued if + * the address is invalidate. It should be combined with + * PRO_DCACHE_MEM_SYNC1. + */ + +#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR 0xffffffff +#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_M (EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_V << EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_S) +#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_V 0xffffffff +#define EXTMEM_PRO_DCACHE_MEMSYNC_ADDR_S 0 + +/* EXTMEM_PRO_DCACHE_MEM_SYNC1_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_MEM_SYNC1_REG (DR_REG_EXTMEM_BASE + 0x20) + +/* EXTMEM_PRO_DCACHE_MEMSYNC_SIZE : R/W; bitpos: [18:0]; default: 0; + * The bits are used to configure the length for invalidate, flush, clean, + * lock and unlock operations. The manual operations will be issued if it is + * validate. The auto operations will be issued if it is invalidate. It + * should be combined with PRO_DCACHE_MEM_SYNC0. + */ + +#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE 0x0007ffff +#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_M (EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_V << EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_S) +#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_V 0x0007ffff +#define EXTMEM_PRO_DCACHE_MEMSYNC_SIZE_S 0 + +/* EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x24) + +/* EXTMEM_PRO_DCACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the start virtual address for manual + * pre-load operation. It should be combined with + * PRO_DCACHE_PRELOAD_SIZE_REG. + */ + +#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR 0xffffffff +#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_M (EXTMEM_PRO_DCACHE_PRELOAD_ADDR_V << EXTMEM_PRO_DCACHE_PRELOAD_ADDR_S) +#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_V 0xffffffff +#define EXTMEM_PRO_DCACHE_PRELOAD_ADDR_S 0 + +/* EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x28) + +/* EXTMEM_PRO_DCACHE_PRELOAD_ORDER : R/W; bitpos: [10]; default: 0; + * The bits are used to configure the direction of manual pre-load + * operation. 1: descending, 0: ascending. + */ + +#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER (BIT(10)) +#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_M (EXTMEM_PRO_DCACHE_PRELOAD_ORDER_V << EXTMEM_PRO_DCACHE_PRELOAD_ORDER_S) +#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_V 0x00000001 +#define EXTMEM_PRO_DCACHE_PRELOAD_ORDER_S 10 + +/* EXTMEM_PRO_DCACHE_PRELOAD_SIZE : R/W; bitpos: [9:0]; default: 512; + * The bits are used to configure the length for manual pre-load operation. + * It should be combined with PRO_DCACHE_PRELOAD_ADDR_REG.. + */ + +#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE 0x000003ff +#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_M (EXTMEM_PRO_DCACHE_PRELOAD_SIZE_V << EXTMEM_PRO_DCACHE_PRELOAD_SIZE_S) +#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_V 0x000003ff +#define EXTMEM_PRO_DCACHE_PRELOAD_SIZE_S 0 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_CFG_REG (DR_REG_EXTMEM_BASE + 0x2c) + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0; + * The bits are used to enable the first section for conditional pre-load + * operation. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ENA_S 9 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0; + * The bits are used to enable the second section for conditional pre-load + * operation. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ENA_S 8 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE : R/W; bitpos: [7:6]; default: 0; + * The bits are used to configure the numbers of the cache block for the + * issuing conditional pre-load operation. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE 0x00000003 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_V 0x00000003 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SIZE_S 6 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_RQST : R/W; bitpos: [5:4]; default: 0; + * The bits are used to configure trigger conditions for conditional + * pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST 0x00000003 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_M (EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_V << EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_V 0x00000003 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_RQST_S 4 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER : R/W; bitpos: [3]; default: 0; + * The bits are used to configure the direction of conditional pre-load + * operation. 1: descending, 0: ascending. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER (BIT(3)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_M (EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_V << EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_V 0x00000001 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_ORDER_S 3 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_STEP : R/W; bitpos: [2:1]; default: 0; + * Reserved. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP 0x00000003 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_M (EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_V << EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_V 0x00000003 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_STEP_S 1 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_MODE : R/W; bitpos: [0]; default: 0; + * Reserved. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE (BIT(0)) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_M (EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_V << EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_V 0x00000001 +#define EXTMEM_PRO_DCACHE_AUTOLOAD_MODE_S 0 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x30) + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the start virtual address of the first + * section for conditional pre-load operation. It should be combined with + * pro_dcache_autoload_sct0_ena. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR 0xffffffff +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xffffffff +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x34) + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [23:0]; default: + * 32768; + * The bits are used to configure the length of the first section for + * conditional pre-load operation. It should be combined with + * pro_dcache_autoload_sct0_ena. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE 0x00ffffff +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V 0x00ffffff +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x38) + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the start virtual address of the second + * section for conditional pre-load operation. It should be combined with + * pro_dcache_autoload_sct1_ena. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR 0xffffffff +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xffffffff +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x3c) + +/* EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [23:0]; default: + * 32768; + * The bits are used to configure the length of the second section for + * conditional pre-load operation. It should be combined with + * pro_dcache_autoload_sct1_ena. + */ + +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE 0x00ffffff +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_M (EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V << EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S) +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V 0x00ffffff +#define EXTMEM_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 + +/* EXTMEM_PRO_ICACHE_CTRL_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x40) + +/* EXTMEM_PRO_ICACHE_LOCK_DONE : RO; bitpos: [25]; default: 0; + * The bit is used to indicate lock operation is finished. + */ + +#define EXTMEM_PRO_ICACHE_LOCK_DONE (BIT(25)) +#define EXTMEM_PRO_ICACHE_LOCK_DONE_M (EXTMEM_PRO_ICACHE_LOCK_DONE_V << EXTMEM_PRO_ICACHE_LOCK_DONE_S) +#define EXTMEM_PRO_ICACHE_LOCK_DONE_V 0x00000001 +#define EXTMEM_PRO_ICACHE_LOCK_DONE_S 25 + +/* EXTMEM_PRO_ICACHE_LOCK_ENA : R/W; bitpos: [24]; default: 0; + * The bit is used to enable lock operation. It will be cleared by hardware + * after lock operation done. + */ + +#define EXTMEM_PRO_ICACHE_LOCK_ENA (BIT(24)) +#define EXTMEM_PRO_ICACHE_LOCK_ENA_M (EXTMEM_PRO_ICACHE_LOCK_ENA_V << EXTMEM_PRO_ICACHE_LOCK_ENA_S) +#define EXTMEM_PRO_ICACHE_LOCK_ENA_V 0x00000001 +#define EXTMEM_PRO_ICACHE_LOCK_ENA_S 24 + +/* EXTMEM_PRO_ICACHE_UNLOCK_DONE : RO; bitpos: [23]; default: 0; + * The bit is used to indicate unlock operation is finished. + */ + +#define EXTMEM_PRO_ICACHE_UNLOCK_DONE (BIT(23)) +#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_M (EXTMEM_PRO_ICACHE_UNLOCK_DONE_V << EXTMEM_PRO_ICACHE_UNLOCK_DONE_S) +#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_V 0x00000001 +#define EXTMEM_PRO_ICACHE_UNLOCK_DONE_S 23 + +/* EXTMEM_PRO_ICACHE_UNLOCK_ENA : R/W; bitpos: [22]; default: 0; + * The bit is used to enable unlock operation. It will be cleared by + * hardware after unlock operation done. + */ + +#define EXTMEM_PRO_ICACHE_UNLOCK_ENA (BIT(22)) +#define EXTMEM_PRO_ICACHE_UNLOCK_ENA_M (EXTMEM_PRO_ICACHE_UNLOCK_ENA_V << EXTMEM_PRO_ICACHE_UNLOCK_ENA_S) +#define EXTMEM_PRO_ICACHE_UNLOCK_ENA_V 0x00000001 +#define EXTMEM_PRO_ICACHE_UNLOCK_ENA_S 22 + +/* EXTMEM_PRO_ICACHE_PRELOAD_DONE : RO; bitpos: [21]; default: 0; + * The bit is used to indicate preload operation is finished. + */ + +#define EXTMEM_PRO_ICACHE_PRELOAD_DONE (BIT(21)) +#define EXTMEM_PRO_ICACHE_PRELOAD_DONE_M (EXTMEM_PRO_ICACHE_PRELOAD_DONE_V << EXTMEM_PRO_ICACHE_PRELOAD_DONE_S) +#define EXTMEM_PRO_ICACHE_PRELOAD_DONE_V 0x00000001 +#define EXTMEM_PRO_ICACHE_PRELOAD_DONE_S 21 + +/* EXTMEM_PRO_ICACHE_PRELOAD_ENA : R/W; bitpos: [20]; default: 0; + * The bit is used to enable preload operation. It will be cleared by + * hardware after preload operation done. + */ + +#define EXTMEM_PRO_ICACHE_PRELOAD_ENA (BIT(20)) +#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_M (EXTMEM_PRO_ICACHE_PRELOAD_ENA_V << EXTMEM_PRO_ICACHE_PRELOAD_ENA_S) +#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_V 0x00000001 +#define EXTMEM_PRO_ICACHE_PRELOAD_ENA_S 20 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_DONE : RO; bitpos: [19]; default: 0; + * The bit is used to indicate conditional-preload operation is finished. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE (BIT(19)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_M (EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_V << EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_V 0x00000001 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_DONE_S 19 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_ENA : R/W; bitpos: [18]; default: 0; + * The bit is used to enable and disable conditional-preload operation. It + * is combined with pre_dcache_autoload_done. 1: enable, 0: disable. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA (BIT(18)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_M (EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_V << EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_V 0x00000001 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ENA_S 18 + +/* EXTMEM_PRO_ICACHE_LOCK1_EN : R/W; bitpos: [15]; default: 0; + * The bit is used to enable pre-lock operation which is combined with + * PRO_ICACHE_LOCK1_ADDR_REG and PRO_ICACHE_LOCK1_SIZE_REG. + */ + +#define EXTMEM_PRO_ICACHE_LOCK1_EN (BIT(15)) +#define EXTMEM_PRO_ICACHE_LOCK1_EN_M (EXTMEM_PRO_ICACHE_LOCK1_EN_V << EXTMEM_PRO_ICACHE_LOCK1_EN_S) +#define EXTMEM_PRO_ICACHE_LOCK1_EN_V 0x00000001 +#define EXTMEM_PRO_ICACHE_LOCK1_EN_S 15 + +/* EXTMEM_PRO_ICACHE_LOCK0_EN : R/W; bitpos: [14]; default: 0; + * The bit is used to enable pre-lock operation which is combined with + * PRO_ICACHE_LOCK0_ADDR_REG and PRO_ICACHE_LOCK0_SIZE_REG. + */ + +#define EXTMEM_PRO_ICACHE_LOCK0_EN (BIT(14)) +#define EXTMEM_PRO_ICACHE_LOCK0_EN_M (EXTMEM_PRO_ICACHE_LOCK0_EN_V << EXTMEM_PRO_ICACHE_LOCK0_EN_S) +#define EXTMEM_PRO_ICACHE_LOCK0_EN_V 0x00000001 +#define EXTMEM_PRO_ICACHE_LOCK0_EN_S 14 + +/* EXTMEM_PRO_ICACHE_INVALIDATE_DONE : RO; bitpos: [9]; default: 0; + * The bit is used to indicate invalidate operation is finished. + */ + +#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE (BIT(9)) +#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_M (EXTMEM_PRO_ICACHE_INVALIDATE_DONE_V << EXTMEM_PRO_ICACHE_INVALIDATE_DONE_S) +#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_V 0x00000001 +#define EXTMEM_PRO_ICACHE_INVALIDATE_DONE_S 9 + +/* EXTMEM_PRO_ICACHE_INVALIDATE_ENA : R/W; bitpos: [8]; default: 1; + * The bit is used to enable invalidate operation. It will be cleared by + * hardware after invalidate operation done. + */ + +#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA (BIT(8)) +#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_M (EXTMEM_PRO_ICACHE_INVALIDATE_ENA_V << EXTMEM_PRO_ICACHE_INVALIDATE_ENA_S) +#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_V 0x00000001 +#define EXTMEM_PRO_ICACHE_INVALIDATE_ENA_S 8 + +/* EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE : R/W; bitpos: [3]; default: 0; + * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes + */ + +#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE (BIT(3)) +#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_M (EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_V << EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_S) +#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_V 0x00000001 +#define EXTMEM_PRO_ICACHE_BLOCKSIZE_MODE_S 3 + +/* EXTMEM_PRO_ICACHE_SETSIZE_MODE : R/W; bitpos: [2]; default: 0; + * The bit is used to configure cache memory size.0: 8KB, 1: 16KB + */ + +#define EXTMEM_PRO_ICACHE_SETSIZE_MODE (BIT(2)) +#define EXTMEM_PRO_ICACHE_SETSIZE_MODE_M (EXTMEM_PRO_ICACHE_SETSIZE_MODE_V << EXTMEM_PRO_ICACHE_SETSIZE_MODE_S) +#define EXTMEM_PRO_ICACHE_SETSIZE_MODE_V 0x00000001 +#define EXTMEM_PRO_ICACHE_SETSIZE_MODE_S 2 + +/* EXTMEM_PRO_ICACHE_ENABLE : R/W; bitpos: [0]; default: 0; + * The bit is used to activate the data cache. 0: disable, 1: enable + */ + +#define EXTMEM_PRO_ICACHE_ENABLE (BIT(0)) +#define EXTMEM_PRO_ICACHE_ENABLE_M (EXTMEM_PRO_ICACHE_ENABLE_V << EXTMEM_PRO_ICACHE_ENABLE_S) +#define EXTMEM_PRO_ICACHE_ENABLE_V 0x00000001 +#define EXTMEM_PRO_ICACHE_ENABLE_S 0 + +/* EXTMEM_PRO_ICACHE_CTRL1_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x44) + +/* EXTMEM_PRO_ICACHE_MASK_BUS2 : R/W; bitpos: [2]; default: 1; + * The bit is used to disable ibus2, 0: enable, 1: disable + */ + +#define EXTMEM_PRO_ICACHE_MASK_BUS2 (BIT(2)) +#define EXTMEM_PRO_ICACHE_MASK_BUS2_M (EXTMEM_PRO_ICACHE_MASK_BUS2_V << EXTMEM_PRO_ICACHE_MASK_BUS2_S) +#define EXTMEM_PRO_ICACHE_MASK_BUS2_V 0x00000001 +#define EXTMEM_PRO_ICACHE_MASK_BUS2_S 2 + +/* EXTMEM_PRO_ICACHE_MASK_BUS1 : R/W; bitpos: [1]; default: 1; + * The bit is used to disable ibus1, 0: enable, 1: disable + */ + +#define EXTMEM_PRO_ICACHE_MASK_BUS1 (BIT(1)) +#define EXTMEM_PRO_ICACHE_MASK_BUS1_M (EXTMEM_PRO_ICACHE_MASK_BUS1_V << EXTMEM_PRO_ICACHE_MASK_BUS1_S) +#define EXTMEM_PRO_ICACHE_MASK_BUS1_V 0x00000001 +#define EXTMEM_PRO_ICACHE_MASK_BUS1_S 1 + +/* EXTMEM_PRO_ICACHE_MASK_BUS0 : R/W; bitpos: [0]; default: 1; + * The bit is used to disable ibus0, 0: enable, 1: disable + */ + +#define EXTMEM_PRO_ICACHE_MASK_BUS0 (BIT(0)) +#define EXTMEM_PRO_ICACHE_MASK_BUS0_M (EXTMEM_PRO_ICACHE_MASK_BUS0_V << EXTMEM_PRO_ICACHE_MASK_BUS0_S) +#define EXTMEM_PRO_ICACHE_MASK_BUS0_V 0x00000001 +#define EXTMEM_PRO_ICACHE_MASK_BUS0_S 0 +#define EXTMEM_PRO_ICACHE_MASK_IRAM0 EXTMEM_PRO_ICACHE_MASK_BUS0 +#define EXTMEM_PRO_ICACHE_MASK_IRAM1 EXTMEM_PRO_ICACHE_MASK_BUS1 +#define EXTMEM_PRO_ICACHE_MASK_DROM0 EXTMEM_PRO_ICACHE_MASK_BUS2 + +/* EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x48) + +/* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: + * power up + */ + +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_M (EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_V << EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_S) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_V 0x00000001 +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PU_S 2 + +/* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: + * power down + */ + +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_M (EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_V << EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_S) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_V 0x00000001 +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_PD_S 1 + +/* EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; + * The bit is used to close clock gating of icache tag memory. 1: close + * gating, 0: open clock gating. + */ + +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_M (EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_V << EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_S) +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_V 0x00000001 +#define EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON_S 0 + +/* EXTMEM_PRO_ICACHE_LOCK0_ADDR_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x4c) + +/* EXTMEM_PRO_ICACHE_LOCK0_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the first start virtual address of data + * locking, which is combined with PRO_ICACHE_LOCK0_SIZE_REG + */ + +#define EXTMEM_PRO_ICACHE_LOCK0_ADDR 0xffffffff +#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_M (EXTMEM_PRO_ICACHE_LOCK0_ADDR_V << EXTMEM_PRO_ICACHE_LOCK0_ADDR_S) +#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_V 0xffffffff +#define EXTMEM_PRO_ICACHE_LOCK0_ADDR_S 0 + +/* EXTMEM_PRO_ICACHE_LOCK0_SIZE_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x50) + +/* EXTMEM_PRO_ICACHE_LOCK0_SIZE : R/W; bitpos: [15:0]; default: 0; + * The bits are used to configure the first length of data locking, which is + * combined with PRO_ICACHE_LOCK0_ADDR_REG + */ + +#define EXTMEM_PRO_ICACHE_LOCK0_SIZE 0x0000ffff +#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_M (EXTMEM_PRO_ICACHE_LOCK0_SIZE_V << EXTMEM_PRO_ICACHE_LOCK0_SIZE_S) +#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_V 0x0000ffff +#define EXTMEM_PRO_ICACHE_LOCK0_SIZE_S 0 + +/* EXTMEM_PRO_ICACHE_LOCK1_ADDR_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x54) + +/* EXTMEM_PRO_ICACHE_LOCK1_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the second start virtual address of data + * locking, which is combined with PRO_ICACHE_LOCK1_SIZE_REG + */ + +#define EXTMEM_PRO_ICACHE_LOCK1_ADDR 0xffffffff +#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_M (EXTMEM_PRO_ICACHE_LOCK1_ADDR_V << EXTMEM_PRO_ICACHE_LOCK1_ADDR_S) +#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_V 0xffffffff +#define EXTMEM_PRO_ICACHE_LOCK1_ADDR_S 0 + +/* EXTMEM_PRO_ICACHE_LOCK1_SIZE_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x58) + +/* EXTMEM_PRO_ICACHE_LOCK1_SIZE : R/W; bitpos: [15:0]; default: 0; + * The bits are used to configure the second length of data locking, which + * is combined with PRO_ICACHE_LOCK1_ADDR_REG + */ + +#define EXTMEM_PRO_ICACHE_LOCK1_SIZE 0x0000ffff +#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_M (EXTMEM_PRO_ICACHE_LOCK1_SIZE_V << EXTMEM_PRO_ICACHE_LOCK1_SIZE_S) +#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_V 0x0000ffff +#define EXTMEM_PRO_ICACHE_LOCK1_SIZE_S 0 + +/* EXTMEM_PRO_ICACHE_MEM_SYNC0_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_MEM_SYNC0_REG (DR_REG_EXTMEM_BASE + 0x5c) + +/* EXTMEM_PRO_ICACHE_MEMSYNC_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the start virtual address for invalidate, + * flush, clean, lock and unlock operations. The manual operations will be + * issued if the address is validate. The auto operations will be issued if + * the address is invalidate. It should be combined with + * PRO_ICACHE_MEM_SYNC1. + */ + +#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR 0xffffffff +#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_M (EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_V << EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_S) +#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_V 0xffffffff +#define EXTMEM_PRO_ICACHE_MEMSYNC_ADDR_S 0 + +/* EXTMEM_PRO_ICACHE_MEM_SYNC1_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_MEM_SYNC1_REG (DR_REG_EXTMEM_BASE + 0x60) + +/* EXTMEM_PRO_ICACHE_MEMSYNC_SIZE : R/W; bitpos: [18:0]; default: 0; + * The bits are used to configure the length for invalidate, flush, clean, + * lock and unlock operations. The manual operations will be issued if it is + * validate. The auto operations will be issued if it is invalidate. It + * should be combined with PRO_ICACHE_MEM_SYNC0. + */ + +#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE 0x0007ffff +#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_M (EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_V << EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_S) +#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_V 0x0007ffff +#define EXTMEM_PRO_ICACHE_MEMSYNC_SIZE_S 0 + +/* EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x64) + +/* EXTMEM_PRO_ICACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the start virtual address for manual + * pre-load operation. It should be combined with + * PRO_ICACHE_PRELOAD_SIZE_REG. + */ + +#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR 0xffffffff +#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_M (EXTMEM_PRO_ICACHE_PRELOAD_ADDR_V << EXTMEM_PRO_ICACHE_PRELOAD_ADDR_S) +#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_V 0xffffffff +#define EXTMEM_PRO_ICACHE_PRELOAD_ADDR_S 0 + +/* EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x68) + +/* EXTMEM_PRO_ICACHE_PRELOAD_ORDER : R/W; bitpos: [10]; default: 0; + * The bits are used to configure the direction of manual pre-load + * operation. 1: descending, 0: ascending. + */ + +#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER (BIT(10)) +#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_M (EXTMEM_PRO_ICACHE_PRELOAD_ORDER_V << EXTMEM_PRO_ICACHE_PRELOAD_ORDER_S) +#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_V 0x00000001 +#define EXTMEM_PRO_ICACHE_PRELOAD_ORDER_S 10 + +/* EXTMEM_PRO_ICACHE_PRELOAD_SIZE : R/W; bitpos: [9:0]; default: 512; + * The bits are used to configure the length for manual pre-load operation. + * It should be combined with PRO_ICACHE_PRELOAD_ADDR_REG.. + */ + +#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE 0x000003ff +#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_M (EXTMEM_PRO_ICACHE_PRELOAD_SIZE_V << EXTMEM_PRO_ICACHE_PRELOAD_SIZE_S) +#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_V 0x000003ff +#define EXTMEM_PRO_ICACHE_PRELOAD_SIZE_S 0 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_CFG_REG (DR_REG_EXTMEM_BASE + 0x6c) + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [9]; default: 0; + * The bits are used to enable the first section for conditional pre-load + * operation. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA (BIT(9)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_V 0x00000001 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ENA_S 9 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [8]; default: 0; + * The bits are used to enable the second section for conditional pre-load + * operation. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA (BIT(8)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_V 0x00000001 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ENA_S 8 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE : R/W; bitpos: [7:6]; default: 0; + * The bits are used to configure the numbers of the cache block for the + * issuing conditional pre-load operation. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE 0x00000003 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_V 0x00000003 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SIZE_S 6 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_RQST : R/W; bitpos: [5:4]; default: 0; + * The bits are used to configure trigger conditions for conditional + * pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST 0x00000003 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_M (EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_V << EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_V 0x00000003 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_RQST_S 4 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER : R/W; bitpos: [3]; default: 0; + * The bits are used to configure the direction of conditional pre-load + * operation. 1: descending, 0: ascending. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER (BIT(3)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_M (EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_V << EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_V 0x00000001 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_ORDER_S 3 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_STEP : R/W; bitpos: [2:1]; default: 0; + * Reserved. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP 0x00000003 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_M (EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_V << EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_V 0x00000003 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_STEP_S 1 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_MODE : R/W; bitpos: [0]; default: 0; + * Reserved. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE (BIT(0)) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_M (EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_V << EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_V 0x00000001 +#define EXTMEM_PRO_ICACHE_AUTOLOAD_MODE_S 0 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x70) + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the start virtual address of the first + * section for conditional pre-load operation. It should be combined with + * pro_icache_autoload_sct0_ena. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR 0xffffffff +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xffffffff +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x74) + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [23:0]; default: + * 32768; + * The bits are used to configure the length of the first section for + * conditional pre-load operation. It should be combined with + * pro_icache_autoload_sct0_ena. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE 0x00ffffff +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x00ffffff +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x78) + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0; + * The bits are used to configure the start virtual address of the second + * section for conditional pre-load operation. It should be combined with + * pro_icache_autoload_sct1_ena. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR 0xffffffff +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xffffffff +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x7c) + +/* EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [23:0]; default: + * 32768; + * The bits are used to configure the length of the second section for + * conditional pre-load operation. It should be combined with + * pro_icache_autoload_sct1_ena. + */ + +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE 0x00ffffff +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_M (EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V << EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S) +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x00ffffff +#define EXTMEM_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 + +/* EXTMEM_IC_PRELOAD_CNT_REG register + * register description + */ + +#define EXTMEM_IC_PRELOAD_CNT_REG (DR_REG_EXTMEM_BASE + 0x80) + +/* EXTMEM_IC_PRELOAD_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of issued pre-load which include + * manual pre-load and conditional pre-load. + */ + +#define EXTMEM_IC_PRELOAD_CNT 0x0000ffff +#define EXTMEM_IC_PRELOAD_CNT_M (EXTMEM_IC_PRELOAD_CNT_V << EXTMEM_IC_PRELOAD_CNT_S) +#define EXTMEM_IC_PRELOAD_CNT_V 0x0000ffff +#define EXTMEM_IC_PRELOAD_CNT_S 0 + +/* EXTMEM_IC_PRELOAD_MISS_CNT_REG register + * register description + */ + +#define EXTMEM_IC_PRELOAD_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x84) + +/* EXTMEM_IC_PRELOAD_MISS_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of missed pre-load which include + * manual pre-load and conditional pre-load. + */ + +#define EXTMEM_IC_PRELOAD_MISS_CNT 0x0000ffff +#define EXTMEM_IC_PRELOAD_MISS_CNT_M (EXTMEM_IC_PRELOAD_MISS_CNT_V << EXTMEM_IC_PRELOAD_MISS_CNT_S) +#define EXTMEM_IC_PRELOAD_MISS_CNT_V 0x0000ffff +#define EXTMEM_IC_PRELOAD_MISS_CNT_S 0 + +/* EXTMEM_IBUS2_ABANDON_CNT_REG register + * register description + */ + +#define EXTMEM_IBUS2_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x88) + +/* EXTMEM_IBUS2_ABANDON_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of the abandoned ibus2 access. + */ + +#define EXTMEM_IBUS2_ABANDON_CNT 0x0000ffff +#define EXTMEM_IBUS2_ABANDON_CNT_M (EXTMEM_IBUS2_ABANDON_CNT_V << EXTMEM_IBUS2_ABANDON_CNT_S) +#define EXTMEM_IBUS2_ABANDON_CNT_V 0x0000ffff +#define EXTMEM_IBUS2_ABANDON_CNT_S 0 + +/* EXTMEM_IBUS1_ABANDON_CNT_REG register + * register description + */ + +#define EXTMEM_IBUS1_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x8c) + +/* EXTMEM_IBUS1_ABANDON_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of the abandoned ibus1 access. + */ + +#define EXTMEM_IBUS1_ABANDON_CNT 0x0000ffff +#define EXTMEM_IBUS1_ABANDON_CNT_M (EXTMEM_IBUS1_ABANDON_CNT_V << EXTMEM_IBUS1_ABANDON_CNT_S) +#define EXTMEM_IBUS1_ABANDON_CNT_V 0x0000ffff +#define EXTMEM_IBUS1_ABANDON_CNT_S 0 + +/* EXTMEM_IBUS0_ABANDON_CNT_REG register + * register description + */ + +#define EXTMEM_IBUS0_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0x90) + +/* EXTMEM_IBUS0_ABANDON_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of the abandoned ibus0 access. + */ + +#define EXTMEM_IBUS0_ABANDON_CNT 0x0000ffff +#define EXTMEM_IBUS0_ABANDON_CNT_M (EXTMEM_IBUS0_ABANDON_CNT_V << EXTMEM_IBUS0_ABANDON_CNT_S) +#define EXTMEM_IBUS0_ABANDON_CNT_V 0x0000ffff +#define EXTMEM_IBUS0_ABANDON_CNT_S 0 + +/* EXTMEM_IBUS2_ACS_MISS_CNT_REG register + * register description + */ + +#define EXTMEM_IBUS2_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x94) + +/* EXTMEM_IBUS2_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of the cache miss caused by ibus2 + * access. + */ + +#define EXTMEM_IBUS2_ACS_MISS_CNT 0xffffffff +#define EXTMEM_IBUS2_ACS_MISS_CNT_M (EXTMEM_IBUS2_ACS_MISS_CNT_V << EXTMEM_IBUS2_ACS_MISS_CNT_S) +#define EXTMEM_IBUS2_ACS_MISS_CNT_V 0xffffffff +#define EXTMEM_IBUS2_ACS_MISS_CNT_S 0 + +/* EXTMEM_IBUS1_ACS_MISS_CNT_REG register + * register description + */ + +#define EXTMEM_IBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x98) + +/* EXTMEM_IBUS1_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of the cache miss caused by ibus1 + * access. + */ + +#define EXTMEM_IBUS1_ACS_MISS_CNT 0xffffffff +#define EXTMEM_IBUS1_ACS_MISS_CNT_M (EXTMEM_IBUS1_ACS_MISS_CNT_V << EXTMEM_IBUS1_ACS_MISS_CNT_S) +#define EXTMEM_IBUS1_ACS_MISS_CNT_V 0xffffffff +#define EXTMEM_IBUS1_ACS_MISS_CNT_S 0 + +/* EXTMEM_IBUS0_ACS_MISS_CNT_REG register + * register description + */ + +#define EXTMEM_IBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x9c) + +/* EXTMEM_IBUS0_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of the cache miss caused by ibus0 + * access. + */ + +#define EXTMEM_IBUS0_ACS_MISS_CNT 0xffffffff +#define EXTMEM_IBUS0_ACS_MISS_CNT_M (EXTMEM_IBUS0_ACS_MISS_CNT_V << EXTMEM_IBUS0_ACS_MISS_CNT_S) +#define EXTMEM_IBUS0_ACS_MISS_CNT_V 0xffffffff +#define EXTMEM_IBUS0_ACS_MISS_CNT_S 0 + +/* EXTMEM_IBUS2_ACS_CNT_REG register + * register description + */ + +#define EXTMEM_IBUS2_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xa0) + +/* EXTMEM_IBUS2_ACS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of ibus2 access icache. + */ + +#define EXTMEM_IBUS2_ACS_CNT 0xffffffff +#define EXTMEM_IBUS2_ACS_CNT_M (EXTMEM_IBUS2_ACS_CNT_V << EXTMEM_IBUS2_ACS_CNT_S) +#define EXTMEM_IBUS2_ACS_CNT_V 0xffffffff +#define EXTMEM_IBUS2_ACS_CNT_S 0 + +/* EXTMEM_IBUS1_ACS_CNT_REG register + * register description + */ + +#define EXTMEM_IBUS1_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xa4) + +/* EXTMEM_IBUS1_ACS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of ibus1 access icache. + */ + +#define EXTMEM_IBUS1_ACS_CNT 0xffffffff +#define EXTMEM_IBUS1_ACS_CNT_M (EXTMEM_IBUS1_ACS_CNT_V << EXTMEM_IBUS1_ACS_CNT_S) +#define EXTMEM_IBUS1_ACS_CNT_V 0xffffffff +#define EXTMEM_IBUS1_ACS_CNT_S 0 + +/* EXTMEM_IBUS0_ACS_CNT_REG register + * register description + */ + +#define EXTMEM_IBUS0_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xa8) + +/* EXTMEM_IBUS0_ACS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of ibus0 access icache. + */ + +#define EXTMEM_IBUS0_ACS_CNT 0xffffffff +#define EXTMEM_IBUS0_ACS_CNT_M (EXTMEM_IBUS0_ACS_CNT_V << EXTMEM_IBUS0_ACS_CNT_S) +#define EXTMEM_IBUS0_ACS_CNT_V 0xffffffff +#define EXTMEM_IBUS0_ACS_CNT_S 0 + +/* EXTMEM_DC_PRELOAD_CNT_REG register + * register description + */ + +#define EXTMEM_DC_PRELOAD_CNT_REG (DR_REG_EXTMEM_BASE + 0xac) + +/* EXTMEM_DC_PRELOAD_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of issued pre-load which include + * manual pre-load and conditional pre-load. + */ + +#define EXTMEM_DC_PRELOAD_CNT 0x0000ffff +#define EXTMEM_DC_PRELOAD_CNT_M (EXTMEM_DC_PRELOAD_CNT_V << EXTMEM_DC_PRELOAD_CNT_S) +#define EXTMEM_DC_PRELOAD_CNT_V 0x0000ffff +#define EXTMEM_DC_PRELOAD_CNT_S 0 + +/* EXTMEM_DC_PRELOAD_EVICT_CNT_REG register + * register description + */ + +#define EXTMEM_DC_PRELOAD_EVICT_CNT_REG (DR_REG_EXTMEM_BASE + 0xb0) + +/* EXTMEM_DC_PRELOAD_EVICT_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of cache evictions by pre-load + * which include manual pre-load and conditional pre-load. + */ + +#define EXTMEM_DC_PRELOAD_EVICT_CNT 0x0000ffff +#define EXTMEM_DC_PRELOAD_EVICT_CNT_M (EXTMEM_DC_PRELOAD_EVICT_CNT_V << EXTMEM_DC_PRELOAD_EVICT_CNT_S) +#define EXTMEM_DC_PRELOAD_EVICT_CNT_V 0x0000ffff +#define EXTMEM_DC_PRELOAD_EVICT_CNT_S 0 + +/* EXTMEM_DC_PRELOAD_MISS_CNT_REG register + * register description + */ + +#define EXTMEM_DC_PRELOAD_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xb4) + +/* EXTMEM_DC_PRELOAD_MISS_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of missed pre-load which include + * manual pre-load and conditional pre-load. + */ + +#define EXTMEM_DC_PRELOAD_MISS_CNT 0x0000ffff +#define EXTMEM_DC_PRELOAD_MISS_CNT_M (EXTMEM_DC_PRELOAD_MISS_CNT_V << EXTMEM_DC_PRELOAD_MISS_CNT_S) +#define EXTMEM_DC_PRELOAD_MISS_CNT_V 0x0000ffff +#define EXTMEM_DC_PRELOAD_MISS_CNT_S 0 + +/* EXTMEM_DBUS2_ABANDON_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS2_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0xb8) + +/* EXTMEM_DBUS2_ABANDON_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of the abandoned dbus2 access. + */ + +#define EXTMEM_DBUS2_ABANDON_CNT 0x0000ffff +#define EXTMEM_DBUS2_ABANDON_CNT_M (EXTMEM_DBUS2_ABANDON_CNT_V << EXTMEM_DBUS2_ABANDON_CNT_S) +#define EXTMEM_DBUS2_ABANDON_CNT_V 0x0000ffff +#define EXTMEM_DBUS2_ABANDON_CNT_S 0 + +/* EXTMEM_DBUS1_ABANDON_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS1_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0xbc) + +/* EXTMEM_DBUS1_ABANDON_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of the abandoned dbus1 access. + */ + +#define EXTMEM_DBUS1_ABANDON_CNT 0x0000ffff +#define EXTMEM_DBUS1_ABANDON_CNT_M (EXTMEM_DBUS1_ABANDON_CNT_V << EXTMEM_DBUS1_ABANDON_CNT_S) +#define EXTMEM_DBUS1_ABANDON_CNT_V 0x0000ffff +#define EXTMEM_DBUS1_ABANDON_CNT_S 0 + +/* EXTMEM_DBUS0_ABANDON_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS0_ABANDON_CNT_REG (DR_REG_EXTMEM_BASE + 0xc0) + +/* EXTMEM_DBUS0_ABANDON_CNT : RO; bitpos: [15:0]; default: 0; + * The bits are used to count the number of the abandoned dbus0 access. + */ + +#define EXTMEM_DBUS0_ABANDON_CNT 0x0000ffff +#define EXTMEM_DBUS0_ABANDON_CNT_M (EXTMEM_DBUS0_ABANDON_CNT_V << EXTMEM_DBUS0_ABANDON_CNT_S) +#define EXTMEM_DBUS0_ABANDON_CNT_V 0x0000ffff +#define EXTMEM_DBUS0_ABANDON_CNT_S 0 + +/* EXTMEM_DBUS2_ACS_WB_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS2_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0xc4) + +/* EXTMEM_DBUS2_ACS_WB_CNT : RO; bitpos: [19:0]; default: 0; + * The bits are used to count the number of cache evictions by dbus2 access + * cache. + */ + +#define EXTMEM_DBUS2_ACS_WB_CNT 0x000fffff +#define EXTMEM_DBUS2_ACS_WB_CNT_M (EXTMEM_DBUS2_ACS_WB_CNT_V << EXTMEM_DBUS2_ACS_WB_CNT_S) +#define EXTMEM_DBUS2_ACS_WB_CNT_V 0x000fffff +#define EXTMEM_DBUS2_ACS_WB_CNT_S 0 + +/* EXTMEM_DBUS1_ACS_WB_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS1_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0xc8) + +/* EXTMEM_DBUS1_ACS_WB_CNT : RO; bitpos: [19:0]; default: 0; + * The bits are used to count the number of cache evictions by dbus1 access + * cache. + */ + +#define EXTMEM_DBUS1_ACS_WB_CNT 0x000fffff +#define EXTMEM_DBUS1_ACS_WB_CNT_M (EXTMEM_DBUS1_ACS_WB_CNT_V << EXTMEM_DBUS1_ACS_WB_CNT_S) +#define EXTMEM_DBUS1_ACS_WB_CNT_V 0x000fffff +#define EXTMEM_DBUS1_ACS_WB_CNT_S 0 + +/* EXTMEM_DBUS0_ACS_WB_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS0_ACS_WB_CNT_REG (DR_REG_EXTMEM_BASE + 0xcc) + +/* EXTMEM_DBUS0_ACS_WB_CNT : RO; bitpos: [19:0]; default: 0; + * The bits are used to count the number of cache evictions by dbus0 access + * cache. + */ + +#define EXTMEM_DBUS0_ACS_WB_CNT 0x000fffff +#define EXTMEM_DBUS0_ACS_WB_CNT_M (EXTMEM_DBUS0_ACS_WB_CNT_V << EXTMEM_DBUS0_ACS_WB_CNT_S) +#define EXTMEM_DBUS0_ACS_WB_CNT_V 0x000fffff +#define EXTMEM_DBUS0_ACS_WB_CNT_S 0 + +/* EXTMEM_DBUS2_ACS_MISS_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS2_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd0) + +/* EXTMEM_DBUS2_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of the cache miss caused by dbus2 + * access. + */ + +#define EXTMEM_DBUS2_ACS_MISS_CNT 0xffffffff +#define EXTMEM_DBUS2_ACS_MISS_CNT_M (EXTMEM_DBUS2_ACS_MISS_CNT_V << EXTMEM_DBUS2_ACS_MISS_CNT_S) +#define EXTMEM_DBUS2_ACS_MISS_CNT_V 0xffffffff +#define EXTMEM_DBUS2_ACS_MISS_CNT_S 0 + +/* EXTMEM_DBUS1_ACS_MISS_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS1_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd4) + +/* EXTMEM_DBUS1_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of the cache miss caused by dbus1 + * access. + */ + +#define EXTMEM_DBUS1_ACS_MISS_CNT 0xffffffff +#define EXTMEM_DBUS1_ACS_MISS_CNT_M (EXTMEM_DBUS1_ACS_MISS_CNT_V << EXTMEM_DBUS1_ACS_MISS_CNT_S) +#define EXTMEM_DBUS1_ACS_MISS_CNT_V 0xffffffff +#define EXTMEM_DBUS1_ACS_MISS_CNT_S 0 + +/* EXTMEM_DBUS0_ACS_MISS_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS0_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd8) + +/* EXTMEM_DBUS0_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of the cache miss caused by dbus0 + * access. + */ + +#define EXTMEM_DBUS0_ACS_MISS_CNT 0xffffffff +#define EXTMEM_DBUS0_ACS_MISS_CNT_M (EXTMEM_DBUS0_ACS_MISS_CNT_V << EXTMEM_DBUS0_ACS_MISS_CNT_S) +#define EXTMEM_DBUS0_ACS_MISS_CNT_V 0xffffffff +#define EXTMEM_DBUS0_ACS_MISS_CNT_S 0 + +/* EXTMEM_DBUS2_ACS_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS2_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xdc) + +/* EXTMEM_DBUS2_ACS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of dbus2 access dcache. + */ + +#define EXTMEM_DBUS2_ACS_CNT 0xffffffff +#define EXTMEM_DBUS2_ACS_CNT_M (EXTMEM_DBUS2_ACS_CNT_V << EXTMEM_DBUS2_ACS_CNT_S) +#define EXTMEM_DBUS2_ACS_CNT_V 0xffffffff +#define EXTMEM_DBUS2_ACS_CNT_S 0 + +/* EXTMEM_DBUS1_ACS_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS1_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xe0) + +/* EXTMEM_DBUS1_ACS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of dbus1 access dcache. + */ + +#define EXTMEM_DBUS1_ACS_CNT 0xffffffff +#define EXTMEM_DBUS1_ACS_CNT_M (EXTMEM_DBUS1_ACS_CNT_V << EXTMEM_DBUS1_ACS_CNT_S) +#define EXTMEM_DBUS1_ACS_CNT_V 0xffffffff +#define EXTMEM_DBUS1_ACS_CNT_S 0 + +/* EXTMEM_DBUS0_ACS_CNT_REG register + * register description + */ + +#define EXTMEM_DBUS0_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xe4) + +/* EXTMEM_DBUS0_ACS_CNT : RO; bitpos: [31:0]; default: 0; + * The bits are used to count the number of dbus0 access dcache. + */ + +#define EXTMEM_DBUS0_ACS_CNT 0xffffffff +#define EXTMEM_DBUS0_ACS_CNT_M (EXTMEM_DBUS0_ACS_CNT_V << EXTMEM_DBUS0_ACS_CNT_S) +#define EXTMEM_DBUS0_ACS_CNT_V 0xffffffff +#define EXTMEM_DBUS0_ACS_CNT_S 0 + +/* EXTMEM_CACHE_DBG_INT_ENA_REG register + * register description + */ + +#define EXTMEM_CACHE_DBG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xe8) + +/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W; bitpos: [19]; default: 0; + * The bit is used to enable interrupt by mmu entry fault. + */ + +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(19)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V << EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S) +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x00000001 +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 19 + +/* EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA : R/W; bitpos: [18]; default: 0; + * The bit is used to enable interrupt by illegal writing lock registers of + * dcache while dcache is busy to issue lock,sync or pre-load operations. + */ + +#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA (BIT(18)) +#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_M (EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_V << EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_S) +#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_V 0x00000001 +#define EXTMEM_DCACHE_SET_LOCK_ILG_INT_ENA_S 18 + +/* EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA : R/W; bitpos: [17]; default: 0; + * The bit is used to enable interrupt by illegal writing sync registers of + * dcache while dcache is busy to issue lock,sync and pre-load operations. + */ + +#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA (BIT(17)) +#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_M (EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_V << EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_S) +#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_V 0x00000001 +#define EXTMEM_DCACHE_SET_SYNC_ILG_INT_ENA_S 17 + +/* EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA : R/W; bitpos: [16]; default: 0; + * The bit is used to enable interrupt by illegal writing preload registers + * of dcache while dcache is busy to issue lock,sync and pre-load operations. + */ + +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA (BIT(16)) +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_M (EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_V << EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_S) +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_V 0x00000001 +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_INT_ENA_S 16 + +/* EXTMEM_DCACHE_REJECT_INT_ENA : R/W; bitpos: [15]; default: 0; + * The bit is used to enable interrupt by authentication fail. + */ + +#define EXTMEM_DCACHE_REJECT_INT_ENA (BIT(15)) +#define EXTMEM_DCACHE_REJECT_INT_ENA_M (EXTMEM_DCACHE_REJECT_INT_ENA_V << EXTMEM_DCACHE_REJECT_INT_ENA_S) +#define EXTMEM_DCACHE_REJECT_INT_ENA_V 0x00000001 +#define EXTMEM_DCACHE_REJECT_INT_ENA_S 15 + +/* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W; bitpos: [14]; default: 0; + * The bit is used to enable interrupt by dcache trying to write flash. + */ + +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(14)) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V << EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x00000001 +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 14 + +/* EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA : R/W; bitpos: [13]; default: 0; + * The bit is used to enable interrupt by manual pre-load configurations + * fault. + */ + +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA (BIT(13)) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_M (EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_V << EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_S) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_V 0x00000001 +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_ENA_S 13 + +/* EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA : R/W; bitpos: [12]; default: 0; + * The bit is used to enable interrupt by manual sync configurations fault. + */ + +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA (BIT(12)) +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_M (EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_V << EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_S) +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_V 0x00000001 +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_ENA_S 12 + +/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W; bitpos: [11]; default: 0; + * The bit is used to enable interrupt by dbus counter overflow. + */ + +#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(11)) +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (EXTMEM_DBUS_CNT_OVF_INT_ENA_V << EXTMEM_DBUS_CNT_OVF_INT_ENA_S) +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x00000001 +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 11 + +/* EXTMEM_DBUS_ACS_MSK_DC_INT_ENA : R/W; bitpos: [10]; default: 0; + * The bit is used to enable interrupt by cpu access dcache while the + * corresponding dbus is disabled which include speculative access. + */ + +#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA (BIT(10)) +#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_M (EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_V << EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_S) +#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_V 0x00000001 +#define EXTMEM_DBUS_ACS_MSK_DC_INT_ENA_S 10 + +/* EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA : R/W; bitpos: [9]; default: 0; + * The bit is used to enable interrupt by illegal writing lock registers of + * icache while icache is busy to issue lock,sync or pre-load operations. + */ + +#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA (BIT(9)) +#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_M (EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_V << EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_S) +#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_V 0x00000001 +#define EXTMEM_ICACHE_SET_LOCK_ILG_INT_ENA_S 9 + +/* EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA : R/W; bitpos: [8]; default: 0; + * The bit is used to enable interrupt by illegal writing sync registers of + * icache while icache is busy to issue lock,sync and pre-load operations. + */ + +#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA (BIT(8)) +#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_M (EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_V << EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_S) +#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_V 0x00000001 +#define EXTMEM_ICACHE_SET_SYNC_ILG_INT_ENA_S 8 + +/* EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA : R/W; bitpos: [7]; default: 0; + * The bit is used to enable interrupt by illegal writing preload registers + * of icache while icache is busy to issue lock,sync and pre-load operations. + */ + +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA (BIT(7)) +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_M (EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_V << EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_S) +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_V 0x00000001 +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_INT_ENA_S 7 + +/* EXTMEM_ICACHE_REJECT_INT_ENA : R/W; bitpos: [6]; default: 0; + * The bit is used to enable interrupt by authentication fail. + */ + +#define EXTMEM_ICACHE_REJECT_INT_ENA (BIT(6)) +#define EXTMEM_ICACHE_REJECT_INT_ENA_M (EXTMEM_ICACHE_REJECT_INT_ENA_V << EXTMEM_ICACHE_REJECT_INT_ENA_S) +#define EXTMEM_ICACHE_REJECT_INT_ENA_V 0x00000001 +#define EXTMEM_ICACHE_REJECT_INT_ENA_S 6 + +/* EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA : R/W; bitpos: [5]; default: 0; + * The bit is used to enable interrupt by manual pre-load configurations + * fault. + */ + +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA (BIT(5)) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_M (EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_V << EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_S) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_V 0x00000001 +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_ENA_S 5 + +/* EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable interrupt by manual sync configurations fault. + */ + +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA (BIT(4)) +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_M (EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_V << EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_S) +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_V 0x00000001 +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_ENA_S 4 + +/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W; bitpos: [3]; default: 0; + * The bit is used to enable interrupt by ibus counter overflow. + */ + +#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(3)) +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (EXTMEM_IBUS_CNT_OVF_INT_ENA_V << EXTMEM_IBUS_CNT_OVF_INT_ENA_S) +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x00000001 +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 3 + +/* EXTMEM_IBUS_ACS_MSK_IC_INT_ENA : R/W; bitpos: [2]; default: 0; + * The bit is used to enable interrupt by cpu access icache while the + * corresponding ibus is disabled which include speculative access. + */ + +#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA (BIT(2)) +#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_M (EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_V << EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_S) +#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_V 0x00000001 +#define EXTMEM_IBUS_ACS_MSK_IC_INT_ENA_S 2 + +/* EXTMEM_CACHE_DBG_EN : R/W; bitpos: [0]; default: 1; + * The bit is used to activate the cache track function. 1: enable, 0: + * disable. + */ + +#define EXTMEM_CACHE_DBG_EN (BIT(0)) +#define EXTMEM_CACHE_DBG_EN_M (EXTMEM_CACHE_DBG_EN_V << EXTMEM_CACHE_DBG_EN_S) +#define EXTMEM_CACHE_DBG_EN_V 0x00000001 +#define EXTMEM_CACHE_DBG_EN_S 0 + +/* EXTMEM_CACHE_DBG_INT_CLR_REG register + * register description + */ + +#define EXTMEM_CACHE_DBG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xec) + +/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD; bitpos: [13]; default: 0; + * The bit is used to clear interrupt by mmu entry fault. + */ + +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(13)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V << EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S) +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x00000001 +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 13 + +/* EXTMEM_DCACHE_SET_ILG_INT_CLR : WOD; bitpos: [12]; default: 0; + * The bit is used to clear interrupt by illegal writing lock registers of + * dcache while dcache is busy to issue lock,sync or pre-load operations. + */ + +#define EXTMEM_DCACHE_SET_ILG_INT_CLR (BIT(12)) +#define EXTMEM_DCACHE_SET_ILG_INT_CLR_M (EXTMEM_DCACHE_SET_ILG_INT_CLR_V << EXTMEM_DCACHE_SET_ILG_INT_CLR_S) +#define EXTMEM_DCACHE_SET_ILG_INT_CLR_V 0x00000001 +#define EXTMEM_DCACHE_SET_ILG_INT_CLR_S 12 + +/* EXTMEM_DCACHE_REJECT_INT_CLR : WOD; bitpos: [11]; default: 0; + * The bit is used to clear interrupt by authentication fail. + */ + +#define EXTMEM_DCACHE_REJECT_INT_CLR (BIT(11)) +#define EXTMEM_DCACHE_REJECT_INT_CLR_M (EXTMEM_DCACHE_REJECT_INT_CLR_V << EXTMEM_DCACHE_REJECT_INT_CLR_S) +#define EXTMEM_DCACHE_REJECT_INT_CLR_V 0x00000001 +#define EXTMEM_DCACHE_REJECT_INT_CLR_S 11 + +/* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD; bitpos: [10]; default: 0; + * The bit is used to clear interrupt by dcache trying to write flash. + */ + +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(10)) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V << EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x00000001 +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 10 + +/* EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR : WOD; bitpos: [9]; default: 0; + * The bit is used to clear interrupt by manual pre-load configurations + * fault. + */ + +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR (BIT(9)) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_M (EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_V << EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_S) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_V 0x00000001 +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_INT_CLR_S 9 + +/* EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR : WOD; bitpos: [8]; default: 0; + * The bit is used to clear interrupt by manual sync configurations fault. + */ + +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR (BIT(8)) +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_M (EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_V << EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_S) +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_V 0x00000001 +#define EXTMEM_DC_SYNC_SIZE_FAULT_INT_CLR_S 8 + +/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD; bitpos: [7]; default: 0; + * The bit is used to clear interrupt by dbus counter overflow. + */ + +#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(7)) +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (EXTMEM_DBUS_CNT_OVF_INT_CLR_V << EXTMEM_DBUS_CNT_OVF_INT_CLR_S) +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x00000001 +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 7 + +/* EXTMEM_DBUS_ACS_MSK_DC_INT_CLR : WOD; bitpos: [6]; default: 0; + * The bit is used to clear interrupt by cpu access dcache while the + * corresponding dbus is disabled or dcache is disabled which include + * speculative access. + */ + +#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR (BIT(6)) +#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_M (EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_V << EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_S) +#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_V 0x00000001 +#define EXTMEM_DBUS_ACS_MSK_DC_INT_CLR_S 6 + +/* EXTMEM_ICACHE_SET_ILG_INT_CLR : WOD; bitpos: [5]; default: 0; + * The bit is used to clear interrupt by illegal writing lock registers of + * icache while icache is busy to issue lock,sync or pre-load operations. + */ + +#define EXTMEM_ICACHE_SET_ILG_INT_CLR (BIT(5)) +#define EXTMEM_ICACHE_SET_ILG_INT_CLR_M (EXTMEM_ICACHE_SET_ILG_INT_CLR_V << EXTMEM_ICACHE_SET_ILG_INT_CLR_S) +#define EXTMEM_ICACHE_SET_ILG_INT_CLR_V 0x00000001 +#define EXTMEM_ICACHE_SET_ILG_INT_CLR_S 5 + +/* EXTMEM_ICACHE_REJECT_INT_CLR : WOD; bitpos: [4]; default: 0; + * The bit is used to clear interrupt by authentication fail. + */ + +#define EXTMEM_ICACHE_REJECT_INT_CLR (BIT(4)) +#define EXTMEM_ICACHE_REJECT_INT_CLR_M (EXTMEM_ICACHE_REJECT_INT_CLR_V << EXTMEM_ICACHE_REJECT_INT_CLR_S) +#define EXTMEM_ICACHE_REJECT_INT_CLR_V 0x00000001 +#define EXTMEM_ICACHE_REJECT_INT_CLR_S 4 + +/* EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR : WOD; bitpos: [3]; default: 0; + * The bit is used to clear interrupt by manual pre-load configurations + * fault. + */ + +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR (BIT(3)) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_M (EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_V << EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_S) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_V 0x00000001 +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_INT_CLR_S 3 + +/* EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR : WOD; bitpos: [2]; default: 0; + * The bit is used to clear interrupt by manual sync configurations fault. + */ + +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR (BIT(2)) +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_M (EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_V << EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_S) +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_V 0x00000001 +#define EXTMEM_IC_SYNC_SIZE_FAULT_INT_CLR_S 2 + +/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD; bitpos: [1]; default: 0; + * The bit is used to clear interrupt by ibus counter overflow. + */ + +#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(1)) +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (EXTMEM_IBUS_CNT_OVF_INT_CLR_V << EXTMEM_IBUS_CNT_OVF_INT_CLR_S) +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x00000001 +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 1 + +/* EXTMEM_IBUS_ACS_MSK_IC_INT_CLR : WOD; bitpos: [0]; default: 0; + * The bit is used to clear interrupt by cpu access icache while the + * corresponding ibus is disabled or icache is disabled which include + * speculative access. + */ + +#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) +#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_M (EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_V << EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_S) +#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_V 0x00000001 +#define EXTMEM_IBUS_ACS_MSK_IC_INT_CLR_S 0 + +/* EXTMEM_CACHE_DBG_STATUS0_REG register + * register description + */ + +#define EXTMEM_CACHE_DBG_STATUS0_REG (DR_REG_EXTMEM_BASE + 0xf0) + +/* EXTMEM_ICACHE_SET_LOCK_ILG_ST : RO; bitpos: [24]; default: 0; + * The bit is used to indicate interrupt by illegal writing lock registers + * of icache while icache is busy to issue lock,sync or pre-load operations. + */ + +#define EXTMEM_ICACHE_SET_LOCK_ILG_ST (BIT(24)) +#define EXTMEM_ICACHE_SET_LOCK_ILG_ST_M (EXTMEM_ICACHE_SET_LOCK_ILG_ST_V << EXTMEM_ICACHE_SET_LOCK_ILG_ST_S) +#define EXTMEM_ICACHE_SET_LOCK_ILG_ST_V 0x00000001 +#define EXTMEM_ICACHE_SET_LOCK_ILG_ST_S 24 + +/* EXTMEM_ICACHE_SET_SYNC_ILG_ST : RO; bitpos: [23]; default: 0; + * The bit is used to indicate interrupt by illegal writing sync registers + * of icache while icache is busy to issue lock,sync and pre-load operations. + */ + +#define EXTMEM_ICACHE_SET_SYNC_ILG_ST (BIT(23)) +#define EXTMEM_ICACHE_SET_SYNC_ILG_ST_M (EXTMEM_ICACHE_SET_SYNC_ILG_ST_V << EXTMEM_ICACHE_SET_SYNC_ILG_ST_S) +#define EXTMEM_ICACHE_SET_SYNC_ILG_ST_V 0x00000001 +#define EXTMEM_ICACHE_SET_SYNC_ILG_ST_S 23 + +/* EXTMEM_ICACHE_SET_PRELOAD_ILG_ST : RO; bitpos: [22]; default: 0; + * The bit is used to indicate interrupt by illegal writing preload + * registers of icache while icache is busy to issue lock,sync and pre-load + * operations. + */ + +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST (BIT(22)) +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_M (EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_V << EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_S) +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_V 0x00000001 +#define EXTMEM_ICACHE_SET_PRELOAD_ILG_ST_S 22 + +/* EXTMEM_ICACHE_REJECT_ST : RO; bitpos: [21]; default: 0; + * The bit is used to indicate interrupt by authentication fail. + */ + +#define EXTMEM_ICACHE_REJECT_ST (BIT(21)) +#define EXTMEM_ICACHE_REJECT_ST_M (EXTMEM_ICACHE_REJECT_ST_V << EXTMEM_ICACHE_REJECT_ST_S) +#define EXTMEM_ICACHE_REJECT_ST_V 0x00000001 +#define EXTMEM_ICACHE_REJECT_ST_S 21 + +/* EXTMEM_IC_PRELOAD_SIZE_FAULT_ST : RO; bitpos: [20]; default: 0; + * The bit is used to indicate interrupt by manual pre-load configurations + * fault. + */ + +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST (BIT(20)) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_M (EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_V << EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_S) +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_V 0x00000001 +#define EXTMEM_IC_PRELOAD_SIZE_FAULT_ST_S 20 + +/* EXTMEM_IC_SYNC_SIZE_FAULT_ST : RO; bitpos: [19]; default: 0; + * The bit is used to indicate interrupt by manual sync configurations fault. + */ + +#define EXTMEM_IC_SYNC_SIZE_FAULT_ST (BIT(19)) +#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_M (EXTMEM_IC_SYNC_SIZE_FAULT_ST_V << EXTMEM_IC_SYNC_SIZE_FAULT_ST_S) +#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_V 0x00000001 +#define EXTMEM_IC_SYNC_SIZE_FAULT_ST_S 19 + +/* EXTMEM_IC_PRELOAD_CNT_OVF_ST : RO; bitpos: [18]; default: 0; + * The bit is used to indicate interrupt by pre-load counter overflow. + */ + +#define EXTMEM_IC_PRELOAD_CNT_OVF_ST (BIT(18)) +#define EXTMEM_IC_PRELOAD_CNT_OVF_ST_M (EXTMEM_IC_PRELOAD_CNT_OVF_ST_V << EXTMEM_IC_PRELOAD_CNT_OVF_ST_S) +#define EXTMEM_IC_PRELOAD_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IC_PRELOAD_CNT_OVF_ST_S 18 + +/* EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST : RO; bitpos: [16]; default: 0; + * The bit is used to indicate interrupt by pre-load miss counter overflow. + */ + +#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST (BIT(16)) +#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_M (EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_V << EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_S) +#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IC_PRELOAD_MISS_CNT_OVF_ST_S 16 + +/* EXTMEM_IBUS2_ABANDON_CNT_OVF_ST : RO; bitpos: [14]; default: 0; + * The bit is used to indicate interrupt by ibus2 abandon counter overflow. + */ + +#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST (BIT(14)) +#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_M (EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_V << EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_S) +#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IBUS2_ABANDON_CNT_OVF_ST_S 14 + +/* EXTMEM_IBUS1_ABANDON_CNT_OVF_ST : RO; bitpos: [13]; default: 0; + * The bit is used to indicate interrupt by ibus1 abandon counter overflow. + */ + +#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST (BIT(13)) +#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_M (EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_V << EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_S) +#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IBUS1_ABANDON_CNT_OVF_ST_S 13 + +/* EXTMEM_IBUS0_ABANDON_CNT_OVF_ST : RO; bitpos: [12]; default: 0; + * The bit is used to indicate interrupt by ibus0 abandon counter overflow. + */ + +#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST (BIT(12)) +#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_M (EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_V << EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_S) +#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IBUS0_ABANDON_CNT_OVF_ST_S 12 + +/* EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST : RO; bitpos: [10]; default: 0; + * The bit is used to indicate interrupt by ibus2 miss counter overflow. + */ + +#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST (BIT(10)) +#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_M (EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_V << EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_S) +#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IBUS2_ACS_MISS_CNT_OVF_ST_S 10 + +/* EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST : RO; bitpos: [9]; default: 0; + * The bit is used to indicate interrupt by ibus1 miss counter overflow. + */ + +#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST (BIT(9)) +#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_M (EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_V << EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_S) +#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IBUS1_ACS_MISS_CNT_OVF_ST_S 9 + +/* EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST : RO; bitpos: [8]; default: 0; + * The bit is used to indicate interrupt by ibus0 miss counter overflow. + */ + +#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST (BIT(8)) +#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_M (EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_V << EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_S) +#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IBUS0_ACS_MISS_CNT_OVF_ST_S 8 + +/* EXTMEM_IBUS2_ACS_CNT_OVF_ST : RO; bitpos: [6]; default: 0; + * The bit is used to indicate interrupt by ibus2 counter overflow. + */ + +#define EXTMEM_IBUS2_ACS_CNT_OVF_ST (BIT(6)) +#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_M (EXTMEM_IBUS2_ACS_CNT_OVF_ST_V << EXTMEM_IBUS2_ACS_CNT_OVF_ST_S) +#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IBUS2_ACS_CNT_OVF_ST_S 6 + +/* EXTMEM_IBUS1_ACS_CNT_OVF_ST : RO; bitpos: [5]; default: 0; + * The bit is used to indicate interrupt by ibus1 counter overflow. + */ + +#define EXTMEM_IBUS1_ACS_CNT_OVF_ST (BIT(5)) +#define EXTMEM_IBUS1_ACS_CNT_OVF_ST_M (EXTMEM_IBUS1_ACS_CNT_OVF_ST_V << EXTMEM_IBUS1_ACS_CNT_OVF_ST_S) +#define EXTMEM_IBUS1_ACS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IBUS1_ACS_CNT_OVF_ST_S 5 + +/* EXTMEM_IBUS0_ACS_CNT_OVF_ST : RO; bitpos: [4]; default: 0; + * The bit is used to indicate interrupt by ibus0 counter overflow. + */ + +#define EXTMEM_IBUS0_ACS_CNT_OVF_ST (BIT(4)) +#define EXTMEM_IBUS0_ACS_CNT_OVF_ST_M (EXTMEM_IBUS0_ACS_CNT_OVF_ST_V << EXTMEM_IBUS0_ACS_CNT_OVF_ST_S) +#define EXTMEM_IBUS0_ACS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_IBUS0_ACS_CNT_OVF_ST_S 4 + +/* EXTMEM_IBUS2_ACS_MSK_ICACHE_ST : RO; bitpos: [2]; default: 0; + * The bit is used to indicate interrupt by cpu access icache while the + * ibus2 is disabled or icache is disabled which include speculative access. + */ + +#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST (BIT(2)) +#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_M (EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_V << EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_S) +#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_V 0x00000001 +#define EXTMEM_IBUS2_ACS_MSK_ICACHE_ST_S 2 + +/* EXTMEM_IBUS1_ACS_MSK_ICACHE_ST : RO; bitpos: [1]; default: 0; + * The bit is used to indicate interrupt by cpu access icache while the + * ibus1 is disabled or icache is disabled which include speculative access. + */ + +#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST (BIT(1)) +#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_M (EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_V << EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_S) +#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_V 0x00000001 +#define EXTMEM_IBUS1_ACS_MSK_ICACHE_ST_S 1 + +/* EXTMEM_IBUS0_ACS_MSK_ICACHE_ST : RO; bitpos: [0]; default: 0; + * The bit is used to indicate interrupt by cpu access icache while the + * ibus0 is disabled or icache is disabled which include speculative access. + */ + +#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST (BIT(0)) +#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_M (EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_V << EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_S) +#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_V 0x00000001 +#define EXTMEM_IBUS0_ACS_MSK_ICACHE_ST_S 0 + +/* EXTMEM_CACHE_DBG_STATUS1_REG register + * register description + */ + +#define EXTMEM_CACHE_DBG_STATUS1_REG (DR_REG_EXTMEM_BASE + 0xf4) + +/* EXTMEM_MMU_ENTRY_FAULT_ST : RO; bitpos: [30]; default: 0; + * The bit is used to indicate interrupt by mmu entry fault. + */ + +#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(30)) +#define EXTMEM_MMU_ENTRY_FAULT_ST_M (EXTMEM_MMU_ENTRY_FAULT_ST_V << EXTMEM_MMU_ENTRY_FAULT_ST_S) +#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x00000001 +#define EXTMEM_MMU_ENTRY_FAULT_ST_S 30 + +/* EXTMEM_DCACHE_SET_LOCK_ILG_ST : RO; bitpos: [29]; default: 0; + * The bit is used to indicate interrupt by illegal writing lock registers + * of icache while icache is busy to issue lock,sync or pre-load operations. + */ + +#define EXTMEM_DCACHE_SET_LOCK_ILG_ST (BIT(29)) +#define EXTMEM_DCACHE_SET_LOCK_ILG_ST_M (EXTMEM_DCACHE_SET_LOCK_ILG_ST_V << EXTMEM_DCACHE_SET_LOCK_ILG_ST_S) +#define EXTMEM_DCACHE_SET_LOCK_ILG_ST_V 0x00000001 +#define EXTMEM_DCACHE_SET_LOCK_ILG_ST_S 29 + +/* EXTMEM_DCACHE_SET_SYNC_ILG_ST : RO; bitpos: [28]; default: 0; + * The bit is used to indicate interrupt by illegal writing sync registers + * of icache while icache is busy to issue lock,sync and pre-load operations. + */ + +#define EXTMEM_DCACHE_SET_SYNC_ILG_ST (BIT(28)) +#define EXTMEM_DCACHE_SET_SYNC_ILG_ST_M (EXTMEM_DCACHE_SET_SYNC_ILG_ST_V << EXTMEM_DCACHE_SET_SYNC_ILG_ST_S) +#define EXTMEM_DCACHE_SET_SYNC_ILG_ST_V 0x00000001 +#define EXTMEM_DCACHE_SET_SYNC_ILG_ST_S 28 + +/* EXTMEM_DCACHE_SET_PRELOAD_ILG_ST : RO; bitpos: [27]; default: 0; + * The bit is used to indicate interrupt by illegal writing preload + * registers of icache while icache is busy to issue lock,sync and pre-load + * operations. + */ + +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST (BIT(27)) +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_M (EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_V << EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_S) +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_V 0x00000001 +#define EXTMEM_DCACHE_SET_PRELOAD_ILG_ST_S 27 + +/* EXTMEM_DCACHE_REJECT_ST : RO; bitpos: [26]; default: 0; + * The bit is used to indicate interrupt by authentication fail. + */ + +#define EXTMEM_DCACHE_REJECT_ST (BIT(26)) +#define EXTMEM_DCACHE_REJECT_ST_M (EXTMEM_DCACHE_REJECT_ST_V << EXTMEM_DCACHE_REJECT_ST_S) +#define EXTMEM_DCACHE_REJECT_ST_V 0x00000001 +#define EXTMEM_DCACHE_REJECT_ST_S 26 + +/* EXTMEM_DCACHE_WRITE_FLASH_ST : RO; bitpos: [25]; default: 0; + * The bit is used to indicate interrupt by dcache trying to write flash. + */ + +#define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(25)) +#define EXTMEM_DCACHE_WRITE_FLASH_ST_M (EXTMEM_DCACHE_WRITE_FLASH_ST_V << EXTMEM_DCACHE_WRITE_FLASH_ST_S) +#define EXTMEM_DCACHE_WRITE_FLASH_ST_V 0x00000001 +#define EXTMEM_DCACHE_WRITE_FLASH_ST_S 25 + +/* EXTMEM_DC_PRELOAD_SIZE_FAULT_ST : RO; bitpos: [24]; default: 0; + * The bit is used to indicate interrupt by manual pre-load configurations + * fault. + */ + +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST (BIT(24)) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_M (EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_V << EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_S) +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_V 0x00000001 +#define EXTMEM_DC_PRELOAD_SIZE_FAULT_ST_S 24 + +/* EXTMEM_DC_SYNC_SIZE_FAULT_ST : RO; bitpos: [23]; default: 0; + * The bit is used to indicate interrupt by manual sync configurations fault. + */ + +#define EXTMEM_DC_SYNC_SIZE_FAULT_ST (BIT(23)) +#define EXTMEM_DC_SYNC_SIZE_FAULT_ST_M (EXTMEM_DC_SYNC_SIZE_FAULT_ST_V << EXTMEM_DC_SYNC_SIZE_FAULT_ST_S) +#define EXTMEM_DC_SYNC_SIZE_FAULT_ST_V 0x00000001 +#define EXTMEM_DC_SYNC_SIZE_FAULT_ST_S 23 + +/* EXTMEM_DC_PRELOAD_CNT_OVF_ST : RO; bitpos: [22]; default: 0; + * The bit is used to indicate interrupt by pre-load counter overflow. + */ + +#define EXTMEM_DC_PRELOAD_CNT_OVF_ST (BIT(22)) +#define EXTMEM_DC_PRELOAD_CNT_OVF_ST_M (EXTMEM_DC_PRELOAD_CNT_OVF_ST_V << EXTMEM_DC_PRELOAD_CNT_OVF_ST_S) +#define EXTMEM_DC_PRELOAD_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DC_PRELOAD_CNT_OVF_ST_S 22 + +/* EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST : RO; bitpos: [21]; default: 0; + * The bit is used to indicate interrupt by pre-load eviction counter + * overflow. + */ + +#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST (BIT(21)) +#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_M (EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_V << EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_S) +#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DC_PRELOAD_EVICT_CNT_OVF_ST_S 21 + +/* EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST : RO; bitpos: [20]; default: 0; + * The bit is used to indicate interrupt by pre-load miss counter overflow. + */ + +#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST (BIT(20)) +#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_M (EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_V << EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_S) +#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DC_PRELOAD_MISS_CNT_OVF_ST_S 20 + +/* EXTMEM_DBUS2_ABANDON_CNT_OVF_ST : RO; bitpos: [18]; default: 0; + * The bit is used to indicate interrupt by dbus2 abandon counter overflow. + */ + +#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST (BIT(18)) +#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_M (EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_V << EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_S) +#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS2_ABANDON_CNT_OVF_ST_S 18 + +/* EXTMEM_DBUS1_ABANDON_CNT_OVF_ST : RO; bitpos: [17]; default: 0; + * The bit is used to indicate interrupt by dbus1 abandon counter overflow. + */ + +#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST (BIT(17)) +#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_M (EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_V << EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_S) +#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS1_ABANDON_CNT_OVF_ST_S 17 + +/* EXTMEM_DBUS0_ABANDON_CNT_OVF_ST : RO; bitpos: [16]; default: 0; + * The bit is used to indicate interrupt by dbus0 abandon counter overflow. + */ + +#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST (BIT(16)) +#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_M (EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_V << EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_S) +#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS0_ABANDON_CNT_OVF_ST_S 16 + +/* EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST : RO; bitpos: [14]; default: 0; + * The bit is used to indicate interrupt by dbus2 eviction counter overflow. + */ + +#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST (BIT(14)) +#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_M (EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_V << EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_S) +#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS2_ACS_WB_CNT_OVF_ST_S 14 + +/* EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST : RO; bitpos: [13]; default: 0; + * The bit is used to indicate interrupt by dbus1 eviction counter overflow. + */ + +#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST (BIT(13)) +#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_M (EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_V << EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_S) +#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS1_ACS_WB_CNT_OVF_ST_S 13 + +/* EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST : RO; bitpos: [12]; default: 0; + * The bit is used to indicate interrupt by dbus0 eviction counter overflow. + */ + +#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST (BIT(12)) +#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_M (EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_V << EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_S) +#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS0_ACS_WB_CNT_OVF_ST_S 12 + +/* EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST : RO; bitpos: [10]; default: 0; + * The bit is used to indicate interrupt by dbus2 miss counter overflow. + */ + +#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST (BIT(10)) +#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_M (EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_V << EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_S) +#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS2_ACS_MISS_CNT_OVF_ST_S 10 + +/* EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST : RO; bitpos: [9]; default: 0; + * The bit is used to indicate interrupt by dbus1 miss counter overflow. + */ + +#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST (BIT(9)) +#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_M (EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_V << EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_S) +#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS1_ACS_MISS_CNT_OVF_ST_S 9 + +/* EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST : RO; bitpos: [8]; default: 0; + * The bit is used to indicate interrupt by dbus0 miss counter overflow. + */ + +#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST (BIT(8)) +#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_M (EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_V << EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_S) +#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS0_ACS_MISS_CNT_OVF_ST_S 8 + +/* EXTMEM_DBUS2_ACS_CNT_OVF_ST : RO; bitpos: [6]; default: 0; + * The bit is used to indicate interrupt by dbus2 counter overflow. + */ + +#define EXTMEM_DBUS2_ACS_CNT_OVF_ST (BIT(6)) +#define EXTMEM_DBUS2_ACS_CNT_OVF_ST_M (EXTMEM_DBUS2_ACS_CNT_OVF_ST_V << EXTMEM_DBUS2_ACS_CNT_OVF_ST_S) +#define EXTMEM_DBUS2_ACS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS2_ACS_CNT_OVF_ST_S 6 + +/* EXTMEM_DBUS1_ACS_CNT_OVF_ST : RO; bitpos: [5]; default: 0; + * The bit is used to indicate interrupt by dbus1 counter overflow. + */ + +#define EXTMEM_DBUS1_ACS_CNT_OVF_ST (BIT(5)) +#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_M (EXTMEM_DBUS1_ACS_CNT_OVF_ST_V << EXTMEM_DBUS1_ACS_CNT_OVF_ST_S) +#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS1_ACS_CNT_OVF_ST_S 5 + +/* EXTMEM_DBUS0_ACS_CNT_OVF_ST : RO; bitpos: [4]; default: 0; + * The bit is used to indicate interrupt by dbus0 counter overflow. + */ + +#define EXTMEM_DBUS0_ACS_CNT_OVF_ST (BIT(4)) +#define EXTMEM_DBUS0_ACS_CNT_OVF_ST_M (EXTMEM_DBUS0_ACS_CNT_OVF_ST_V << EXTMEM_DBUS0_ACS_CNT_OVF_ST_S) +#define EXTMEM_DBUS0_ACS_CNT_OVF_ST_V 0x00000001 +#define EXTMEM_DBUS0_ACS_CNT_OVF_ST_S 4 + +/* EXTMEM_DBUS2_ACS_MSK_DCACHE_ST : RO; bitpos: [2]; default: 0; + * The bit is used to indicate interrupt by cpu access dcache while the + * dbus2 is disabled or dcache is disabled which include speculative access. + */ + +#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST (BIT(2)) +#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_M (EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_V << EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_S) +#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_V 0x00000001 +#define EXTMEM_DBUS2_ACS_MSK_DCACHE_ST_S 2 + +/* EXTMEM_DBUS1_ACS_MSK_DCACHE_ST : RO; bitpos: [1]; default: 0; + * The bit is used to indicate interrupt by cpu access dcache while the + * dbus1 is disabled or dcache is disabled which include speculative access. + */ + +#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST (BIT(1)) +#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_M (EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_V << EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_S) +#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_V 0x00000001 +#define EXTMEM_DBUS1_ACS_MSK_DCACHE_ST_S 1 + +/* EXTMEM_DBUS0_ACS_MSK_DCACHE_ST : RO; bitpos: [0]; default: 0; + * The bit is used to indicate interrupt by cpu access dcache while the + * dbus0 is disabled or dcache is disabled which include speculative access. + */ + +#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST (BIT(0)) +#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_M (EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_V << EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_S) +#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_V 0x00000001 +#define EXTMEM_DBUS0_ACS_MSK_DCACHE_ST_S 0 + +/* EXTMEM_PRO_CACHE_ACS_CNT_CLR_REG register + * register description + */ + +#define EXTMEM_PRO_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0xf8) + +/* EXTMEM_PRO_ICACHE_ACS_CNT_CLR : WOD; bitpos: [1]; default: 0; + * The bit is used to clear icache counter which include IC_PRELOAD_CNT_REG, + * IC_PRELOAD_MISS_CNT_REG, IBUS0-2_ABANDON_CNT_REG, + * IBUS0-2_ACS_MISS_CNT_REG and IBUS0-2_ACS_CNT_REG. + */ + +#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR (BIT(1)) +#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_M (EXTMEM_PRO_ICACHE_ACS_CNT_CLR_V << EXTMEM_PRO_ICACHE_ACS_CNT_CLR_S) +#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_V 0x00000001 +#define EXTMEM_PRO_ICACHE_ACS_CNT_CLR_S 1 + +/* EXTMEM_PRO_DCACHE_ACS_CNT_CLR : WOD; bitpos: [0]; default: 0; + * The bit is used to clear dcache counter which include DC_PRELOAD_CNT_REG, + * DC_PRELOAD_EVICT_CNT_REG, DC_PRELOAD_MISS_CNT_REG, + * DBUS0-2_ABANDON_CNT_REG, DBUS0-2_ACS_WB_CNT_REG, DBUS0-2_ACS_MISS_CNT_REG + * and DBUS0-2_ACS_CNT_REG. + */ + +#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR (BIT(0)) +#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_M (EXTMEM_PRO_DCACHE_ACS_CNT_CLR_V << EXTMEM_PRO_DCACHE_ACS_CNT_CLR_S) +#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_V 0x00000001 +#define EXTMEM_PRO_DCACHE_ACS_CNT_CLR_S 0 + +/* EXTMEM_PRO_DCACHE_REJECT_ST_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0xfc) + +/* EXTMEM_PRO_DCACHE_CPU_ATTR : RO; bitpos: [5:3]; default: 0; + * The bits are used to indicate the attribute of CPU access dcache when + * authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: + * write-able. + */ + +#define EXTMEM_PRO_DCACHE_CPU_ATTR 0x00000007 +#define EXTMEM_PRO_DCACHE_CPU_ATTR_M (EXTMEM_PRO_DCACHE_CPU_ATTR_V << EXTMEM_PRO_DCACHE_CPU_ATTR_S) +#define EXTMEM_PRO_DCACHE_CPU_ATTR_V 0x00000007 +#define EXTMEM_PRO_DCACHE_CPU_ATTR_S 3 + +/* EXTMEM_PRO_DCACHE_TAG_ATTR : RO; bitpos: [2:0]; default: 0; + * The bits are used to indicate the attribute of data from external memory + * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, + * 4: write-able. + */ + +#define EXTMEM_PRO_DCACHE_TAG_ATTR 0x00000007 +#define EXTMEM_PRO_DCACHE_TAG_ATTR_M (EXTMEM_PRO_DCACHE_TAG_ATTR_V << EXTMEM_PRO_DCACHE_TAG_ATTR_S) +#define EXTMEM_PRO_DCACHE_TAG_ATTR_V 0x00000007 +#define EXTMEM_PRO_DCACHE_TAG_ATTR_S 0 + +/* EXTMEM_PRO_DCACHE_REJECT_VADDR_REG register + * register description + */ + +#define EXTMEM_PRO_DCACHE_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x100) + +/* EXTMEM_PRO_DCACHE_CPU_VADDR : RO; bitpos: [31:0]; default: 0; + * The bits are used to indicate the virtual address of CPU access dcache + * when authentication fail. + */ + +#define EXTMEM_PRO_DCACHE_CPU_VADDR 0xffffffff +#define EXTMEM_PRO_DCACHE_CPU_VADDR_M (EXTMEM_PRO_DCACHE_CPU_VADDR_V << EXTMEM_PRO_DCACHE_CPU_VADDR_S) +#define EXTMEM_PRO_DCACHE_CPU_VADDR_V 0xffffffff +#define EXTMEM_PRO_DCACHE_CPU_VADDR_S 0 + +/* EXTMEM_PRO_ICACHE_REJECT_ST_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x104) + +/* EXTMEM_PRO_ICACHE_CPU_ATTR : RO; bitpos: [5:3]; default: 0; + * The bits are used to indicate the attribute of CPU access icache when + * authentication fail. 0: invalidate, 1: execute-able, 2: read-able + */ + +#define EXTMEM_PRO_ICACHE_CPU_ATTR 0x00000007 +#define EXTMEM_PRO_ICACHE_CPU_ATTR_M (EXTMEM_PRO_ICACHE_CPU_ATTR_V << EXTMEM_PRO_ICACHE_CPU_ATTR_S) +#define EXTMEM_PRO_ICACHE_CPU_ATTR_V 0x00000007 +#define EXTMEM_PRO_ICACHE_CPU_ATTR_S 3 + +/* EXTMEM_PRO_ICACHE_TAG_ATTR : RO; bitpos: [2:0]; default: 0; + * The bits are used to indicate the attribute of data from external memory + * when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, + * 4: write-able. + */ + +#define EXTMEM_PRO_ICACHE_TAG_ATTR 0x00000007 +#define EXTMEM_PRO_ICACHE_TAG_ATTR_M (EXTMEM_PRO_ICACHE_TAG_ATTR_V << EXTMEM_PRO_ICACHE_TAG_ATTR_S) +#define EXTMEM_PRO_ICACHE_TAG_ATTR_V 0x00000007 +#define EXTMEM_PRO_ICACHE_TAG_ATTR_S 0 + +/* EXTMEM_PRO_ICACHE_REJECT_VADDR_REG register + * register description + */ + +#define EXTMEM_PRO_ICACHE_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x108) + +/* EXTMEM_PRO_ICACHE_CPU_VADDR : RO; bitpos: [31:0]; default: 0; + * The bits are used to indicate the virtual address of CPU access icache + * when authentication fail. + */ + +#define EXTMEM_PRO_ICACHE_CPU_VADDR 0xffffffff +#define EXTMEM_PRO_ICACHE_CPU_VADDR_M (EXTMEM_PRO_ICACHE_CPU_VADDR_V << EXTMEM_PRO_ICACHE_CPU_VADDR_S) +#define EXTMEM_PRO_ICACHE_CPU_VADDR_V 0xffffffff +#define EXTMEM_PRO_ICACHE_CPU_VADDR_S 0 + +/* EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG register + * register description + */ + +#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x10c) + +/* EXTMEM_PRO_CACHE_MMU_FAULT_CODE : RO; bitpos: [19:17]; default: 0; + * The bits are used to indicate the operations which cause mmu fault + * occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: flush, 4: cpu + * miss evict recovery address, 5: load miss evict recovery address, 6: + * external dma tx, 7: external dma rx + */ + +#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE 0x00000007 +#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_M (EXTMEM_PRO_CACHE_MMU_FAULT_CODE_V << EXTMEM_PRO_CACHE_MMU_FAULT_CODE_S) +#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_V 0x00000007 +#define EXTMEM_PRO_CACHE_MMU_FAULT_CODE_S 17 + +/* EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT : RO; bitpos: [16:0]; default: 0; + * The bits are used to indicate the content of mmu entry which cause mmu + * fault.. + */ + +#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT 0x0001ffff +#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_M (EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_V << EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_S) +#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_V 0x0001ffff +#define EXTMEM_PRO_CACHE_MMU_FAULT_CONTENT_S 0 + +/* EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG register + * register description + */ + +#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x110) + +/* EXTMEM_PRO_CACHE_MMU_FAULT_VADDR : RO; bitpos: [31:0]; default: 0; + * The bits are used to indicate the virtual address which cause mmu fault.. + */ + +#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR 0xffffffff +#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_M (EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_V << EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_S) +#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_V 0xffffffff +#define EXTMEM_PRO_CACHE_MMU_FAULT_VADDR_S 0 + +/* EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG register + * register description + */ + +#define EXTMEM_PRO_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x114) + +/* EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND : R/W; bitpos: [1]; default: 0; + * The bit is used to enable wrap around mode when read data from spiram. + */ + +#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND (BIT(1)) +#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_M (EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_V << EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_S) +#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_V 0x00000001 +#define EXTMEM_PRO_CACHE_SRAM_RD_WRAP_AROUND_S 1 + +/* EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND : R/W; bitpos: [0]; default: 0; + * The bit is used to enable wrap around mode when read data from flash. + */ + +#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND (BIT(0)) +#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_M (EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_V << EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_S) +#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_V 0x00000001 +#define EXTMEM_PRO_CACHE_FLASH_WRAP_AROUND_S 0 + +/* EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG register + * register description + */ + +#define EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x118) + +/* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1; + * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power + * up + */ + +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_M (EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_V << EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_S) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_V 0x00000001 +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PU_S 2 + +/* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0; + * The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power + * down + */ + +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_M (EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_V << EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_S) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_V 0x00000001 +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_PD_S 1 + +/* EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1; + * The bit is used to enable clock gating to save power when access mmu + * memory, 0: enable, 1: disable + */ + +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_M (EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_V << EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_S) +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_V 0x00000001 +#define EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON_S 0 + +/* EXTMEM_PRO_CACHE_STATE_REG register + * register description + */ + +#define EXTMEM_PRO_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x11c) + +/* EXTMEM_PRO_DCACHE_STATE : RO; bitpos: [23:12]; default: 0; + * The bit is used to indicate dcache main fsm is in idle state or not. 1: + * in idle state, 0: not in idle state + */ + +#define EXTMEM_PRO_DCACHE_STATE 0x00000fff +#define EXTMEM_PRO_DCACHE_STATE_M (EXTMEM_PRO_DCACHE_STATE_V << EXTMEM_PRO_DCACHE_STATE_S) +#define EXTMEM_PRO_DCACHE_STATE_V 0x00000fff +#define EXTMEM_PRO_DCACHE_STATE_S 12 + +/* EXTMEM_PRO_ICACHE_STATE : RO; bitpos: [11:0]; default: 0; + * The bit is used to indicate icache main fsm is in idle state or not. 1: + * in idle state, 0: not in idle state + */ + +#define EXTMEM_PRO_ICACHE_STATE 0x00000fff +#define EXTMEM_PRO_ICACHE_STATE_M (EXTMEM_PRO_ICACHE_STATE_V << EXTMEM_PRO_ICACHE_STATE_S) +#define EXTMEM_PRO_ICACHE_STATE_V 0x00000fff +#define EXTMEM_PRO_ICACHE_STATE_S 0 + +/* EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG register + * register description + */ + +#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x120) + +/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W; bitpos: [1]; default: 0; + * Reserved. + */ + +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V << EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S) +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x00000001 +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 + +/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W; bitpos: [0]; default: 0; + * Reserved. + */ + +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V << EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S) +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x00000001 +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 + +/* EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG register + * register description + */ + +#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x124) + +/* EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT : R/W; bitpos: [2]; + * default: 1; + * The bit is used to close clock gating of encrypt and decrypt clock. 1: + * close gating, 0: open clock gating. + */ + +#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT (BIT(2)) +#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_M (EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_V << EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_S) +#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_V 0x00000001 +#define EXTMEM_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_S 2 + +/* EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT : R/W; bitpos: [1]; default: 1; + * The bit is used to close clock gating of decrypt clock. 1: close gating, + * 0: open clock gating. + */ + +#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT (BIT(1)) +#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_M (EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_V << EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_S) +#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_V 0x00000001 +#define EXTMEM_CLK_FORCE_ON_G0CB_DECRYPT_S 1 + +/* EXTMEM_CLK_FORCE_ON_DB_ENCRYPT : R/W; bitpos: [0]; default: 1; + * The bit is used to close clock gating of encrypt clock. 1: close gating, + * 0: open clock gating. + */ + +#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT (BIT(0)) +#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_M (EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_V << EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_S) +#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_V 0x00000001 +#define EXTMEM_CLK_FORCE_ON_DB_ENCRYPT_S 0 + +/* EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG register + * register description + */ + +#define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x128) + +/* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W; bitpos: [0]; default: 0; + * Reserved. + */ + +#define EXTMEM_ALLOC_WB_HOLD_ARBITER (BIT(0)) +#define EXTMEM_ALLOC_WB_HOLD_ARBITER_M (EXTMEM_ALLOC_WB_HOLD_ARBITER_V << EXTMEM_ALLOC_WB_HOLD_ARBITER_S) +#define EXTMEM_ALLOC_WB_HOLD_ARBITER_V 0x00000001 +#define EXTMEM_ALLOC_WB_HOLD_ARBITER_S 0 + +/* EXTMEM_CACHE_PRELOAD_INT_CTRL_REG register + * register description + */ + +#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x12c) + +/* EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR : WOD; bitpos: [5]; default: 0; + * The bit is used to clear the interrupt by dcache pre-load done. + */ + +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR (BIT(5)) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_M (EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_V << EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_S) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_V 0x00000001 +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_CLR_S 5 + +/* EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable the interrupt by dcache pre-load done. + */ + +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA (BIT(4)) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_M (EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_V << EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_S) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ENA_S 4 + +/* EXTMEM_PRO_DCACHE_PRELOAD_INT_ST : RO; bitpos: [3]; default: 0; + * The bit is used to indicate the interrupt by dcache pre-load done. + */ + +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST (BIT(3)) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_M (EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_V << EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_S) +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_V 0x00000001 +#define EXTMEM_PRO_DCACHE_PRELOAD_INT_ST_S 3 + +/* EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR : WOD; bitpos: [2]; default: 0; + * The bit is used to clear the interrupt by icache pre-load done. + */ + +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR (BIT(2)) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_M (EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_V << EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_S) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_V 0x00000001 +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_CLR_S 2 + +/* EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the interrupt by icache pre-load done. + */ + +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA (BIT(1)) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_M (EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_V << EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_S) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_V 0x00000001 +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ENA_S 1 + +/* EXTMEM_PRO_ICACHE_PRELOAD_INT_ST : RO; bitpos: [0]; default: 0; + * The bit is used to indicate the interrupt by icache pre-load done. + */ + +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST (BIT(0)) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_M (EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_V << EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_S) +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_V 0x00000001 +#define EXTMEM_PRO_ICACHE_PRELOAD_INT_ST_S 0 + +/* EXTMEM_CACHE_SYNC_INT_CTRL_REG register + * register description + */ + +#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x130) + +/* EXTMEM_PRO_DCACHE_SYNC_INT_CLR : WOD; bitpos: [5]; default: 0; + * The bit is used to clear the interrupt by dcache sync done. + */ + +#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR (BIT(5)) +#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_M (EXTMEM_PRO_DCACHE_SYNC_INT_CLR_V << EXTMEM_PRO_DCACHE_SYNC_INT_CLR_S) +#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_V 0x00000001 +#define EXTMEM_PRO_DCACHE_SYNC_INT_CLR_S 5 + +/* EXTMEM_PRO_DCACHE_SYNC_INT_ENA : R/W; bitpos: [4]; default: 0; + * The bit is used to enable the interrupt by dcache sync done. + */ + +#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA (BIT(4)) +#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_M (EXTMEM_PRO_DCACHE_SYNC_INT_ENA_V << EXTMEM_PRO_DCACHE_SYNC_INT_ENA_S) +#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_V 0x00000001 +#define EXTMEM_PRO_DCACHE_SYNC_INT_ENA_S 4 + +/* EXTMEM_PRO_DCACHE_SYNC_INT_ST : RO; bitpos: [3]; default: 0; + * The bit is used to indicate the interrupt by dcache sync done. + */ + +#define EXTMEM_PRO_DCACHE_SYNC_INT_ST (BIT(3)) +#define EXTMEM_PRO_DCACHE_SYNC_INT_ST_M (EXTMEM_PRO_DCACHE_SYNC_INT_ST_V << EXTMEM_PRO_DCACHE_SYNC_INT_ST_S) +#define EXTMEM_PRO_DCACHE_SYNC_INT_ST_V 0x00000001 +#define EXTMEM_PRO_DCACHE_SYNC_INT_ST_S 3 + +/* EXTMEM_PRO_ICACHE_SYNC_INT_CLR : WOD; bitpos: [2]; default: 0; + * The bit is used to clear the interrupt by icache sync done. + */ + +#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR (BIT(2)) +#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_M (EXTMEM_PRO_ICACHE_SYNC_INT_CLR_V << EXTMEM_PRO_ICACHE_SYNC_INT_CLR_S) +#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_V 0x00000001 +#define EXTMEM_PRO_ICACHE_SYNC_INT_CLR_S 2 + +/* EXTMEM_PRO_ICACHE_SYNC_INT_ENA : R/W; bitpos: [1]; default: 0; + * The bit is used to enable the interrupt by icache sync done. + */ + +#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA (BIT(1)) +#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_M (EXTMEM_PRO_ICACHE_SYNC_INT_ENA_V << EXTMEM_PRO_ICACHE_SYNC_INT_ENA_S) +#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_V 0x00000001 +#define EXTMEM_PRO_ICACHE_SYNC_INT_ENA_S 1 + +/* EXTMEM_PRO_ICACHE_SYNC_INT_ST : RO; bitpos: [0]; default: 0; + * The bit is used to indicate the interrupt by icache sync done. + */ + +#define EXTMEM_PRO_ICACHE_SYNC_INT_ST (BIT(0)) +#define EXTMEM_PRO_ICACHE_SYNC_INT_ST_M (EXTMEM_PRO_ICACHE_SYNC_INT_ST_V << EXTMEM_PRO_ICACHE_SYNC_INT_ST_S) +#define EXTMEM_PRO_ICACHE_SYNC_INT_ST_V 0x00000001 +#define EXTMEM_PRO_ICACHE_SYNC_INT_ST_S 0 + +/* EXTMEM_CACHE_CONF_MISC_REG register + * register description + */ + +#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x134) + +/* EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W; bitpos: [1]; default: + * 1; + * The bit is used to disable checking mmu entry fault by sync operation. + */ + +#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) +#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V << EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S) +#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x00000001 +#define EXTMEM_PRO_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 + +/* EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W; bitpos: [0]; + * default: 1; + * The bit is used to disable checking mmu entry fault by preload operation. + */ + +#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) +#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V << EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S) +#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x00000001 +#define EXTMEM_PRO_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 + +/* EXTMEM_CLOCK_GATE_REG register + * register description + */ + +#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x138) + +/* EXTMEM_CLK_EN : R/W; bitpos: [0]; default: 1; + * Reserved. + */ + +#define EXTMEM_CLK_EN (BIT(0)) +#define EXTMEM_CLK_EN_M (EXTMEM_CLK_EN_V << EXTMEM_CLK_EN_S) +#define EXTMEM_CLK_EN_V 0x00000001 +#define EXTMEM_CLK_EN_S 0 + +/* EXTMEM_PRO_EXTMEM_REG_DATE_REG register + * register description + */ + +#define EXTMEM_PRO_EXTMEM_REG_DATE_REG (DR_REG_EXTMEM_BASE + 0x3fc) + +/* EXTMEM_PRO_EXTMEM_REG_DATE : R/W; bitpos: [27:0]; default: 26231168; + * Reserved. + */ + +#define EXTMEM_PRO_EXTMEM_REG_DATE 0x0fffffff +#define EXTMEM_PRO_EXTMEM_REG_DATE_M (EXTMEM_PRO_EXTMEM_REG_DATE_V << EXTMEM_PRO_EXTMEM_REG_DATE_S) +#define EXTMEM_PRO_EXTMEM_REG_DATE_V 0x0fffffff +#define EXTMEM_PRO_EXTMEM_REG_DATE_S 0 #endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EXTMEM_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h index 205f262b330f2..a3500c4074da8 100644 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h @@ -58,10 +58,17 @@ #define RTC_CNTL_SWD_WKEY_VALUE 0x8f1d312a +#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG +#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG + #define DPORT_CPUPERIOD_SEL_80 0 #define DPORT_CPUPERIOD_SEL_160 1 #define DPORT_CPUPERIOD_SEL_240 2 +#define DPORT_SOC_CLK_SEL_XTAL 0 +#define DPORT_SOC_CLK_SEL_PLL 1 +#define DPORT_SOC_CLK_SEL_8M 2 + #define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG /* RTC_CNTL_OPTIONS0_REG register diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_syscon.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_syscon.h new file mode 100644 index 0000000000000..04a333c0ac9e0 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/esp32s2_syscon.h @@ -0,0 +1,632 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/esp32s2_syscon.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSCON_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSCON_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) + +/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ + +#define SYSCON_RST_TICK_CNT (BIT(12)) +#define SYSCON_RST_TICK_CNT_M (BIT(12)) +#define SYSCON_RST_TICK_CNT_V 0x1 +#define SYSCON_RST_TICK_CNT_S 12 + +/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ + +#define SYSCON_CLK_EN (BIT(11)) +#define SYSCON_CLK_EN_M (BIT(11)) +#define SYSCON_CLK_EN_V 0x1 +#define SYSCON_CLK_EN_S 11 + +/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ + +#define SYSCON_CLK_320M_EN (BIT(10)) +#define SYSCON_CLK_320M_EN_M (BIT(10)) +#define SYSCON_CLK_320M_EN_V 0x1 +#define SYSCON_CLK_320M_EN_S 10 + +#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004) + +/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ + +#define SYSCON_TICK_ENABLE (BIT(16)) +#define SYSCON_TICK_ENABLE_M (BIT(16)) +#define SYSCON_TICK_ENABLE_V 0x1 +#define SYSCON_TICK_ENABLE_S 16 + +/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ + +#define SYSCON_CK8M_TICK_NUM 0x000000FF +#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S)) +#define SYSCON_CK8M_TICK_NUM_V 0xFF +#define SYSCON_CK8M_TICK_NUM_S 8 + +/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ + +#define SYSCON_XTAL_TICK_NUM 0x000000FF +#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S)) +#define SYSCON_XTAL_TICK_NUM_V 0xFF +#define SYSCON_XTAL_TICK_NUM_S 0 + +#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008) + +/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ + +#define SYSCON_CLK_XTAL_OEN (BIT(10)) +#define SYSCON_CLK_XTAL_OEN_M (BIT(10)) +#define SYSCON_CLK_XTAL_OEN_V 0x1 +#define SYSCON_CLK_XTAL_OEN_S 10 + +/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ + +#define SYSCON_CLK40X_BB_OEN (BIT(9)) +#define SYSCON_CLK40X_BB_OEN_M (BIT(9)) +#define SYSCON_CLK40X_BB_OEN_V 0x1 +#define SYSCON_CLK40X_BB_OEN_S 9 + +/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ + +#define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) +#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) +#define SYSCON_CLK_DAC_CPU_OEN_V 0x1 +#define SYSCON_CLK_DAC_CPU_OEN_S 8 + +/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ + +#define SYSCON_CLK_ADC_INF_OEN (BIT(7)) +#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) +#define SYSCON_CLK_ADC_INF_OEN_V 0x1 +#define SYSCON_CLK_ADC_INF_OEN_S 7 + +/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ + +#define SYSCON_CLK_320M_OEN (BIT(6)) +#define SYSCON_CLK_320M_OEN_M (BIT(6)) +#define SYSCON_CLK_320M_OEN_V 0x1 +#define SYSCON_CLK_320M_OEN_S 6 + +/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ + +#define SYSCON_CLK160_OEN (BIT(5)) +#define SYSCON_CLK160_OEN_M (BIT(5)) +#define SYSCON_CLK160_OEN_V 0x1 +#define SYSCON_CLK160_OEN_S 5 + +/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ + +#define SYSCON_CLK80_OEN (BIT(4)) +#define SYSCON_CLK80_OEN_M (BIT(4)) +#define SYSCON_CLK80_OEN_V 0x1 +#define SYSCON_CLK80_OEN_S 4 + +/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ + +#define SYSCON_CLK_BB_OEN (BIT(3)) +#define SYSCON_CLK_BB_OEN_M (BIT(3)) +#define SYSCON_CLK_BB_OEN_V 0x1 +#define SYSCON_CLK_BB_OEN_S 3 + +/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ + +#define SYSCON_CLK44_OEN (BIT(2)) +#define SYSCON_CLK44_OEN_M (BIT(2)) +#define SYSCON_CLK44_OEN_V 0x1 +#define SYSCON_CLK44_OEN_S 2 + +/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ + +#define SYSCON_CLK22_OEN (BIT(1)) +#define SYSCON_CLK22_OEN_M (BIT(1)) +#define SYSCON_CLK22_OEN_V 0x1 +#define SYSCON_CLK22_OEN_S 1 + +/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ + +#define SYSCON_CLK20_OEN (BIT(0)) +#define SYSCON_CLK20_OEN_M (BIT(0)) +#define SYSCON_CLK20_OEN_V 0x1 +#define SYSCON_CLK20_OEN_S 0 + +#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x00C) + +/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ + +#define SYSCON_PERI_IO_SWAP 0x000000FF +#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S)) +#define SYSCON_PERI_IO_SWAP_V 0xFF +#define SYSCON_PERI_IO_SWAP_S 0 + +#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x010) + +/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ + +#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) +#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) +#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 +#define SYSCON_EXT_MEM_PMS_LOCK_S 0 + +#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x014) + +/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ + +#define SYSCON_FLASH_ACE0_ATTR 0x00000007 +#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S)) +#define SYSCON_FLASH_ACE0_ATTR_V 0x7 +#define SYSCON_FLASH_ACE0_ATTR_S 0 + +#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x018) + +/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ + +#define SYSCON_FLASH_ACE1_ATTR 0x00000007 +#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S)) +#define SYSCON_FLASH_ACE1_ATTR_V 0x7 +#define SYSCON_FLASH_ACE1_ATTR_S 0 + +#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x01C) + +/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ + +#define SYSCON_FLASH_ACE2_ATTR 0x00000007 +#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S)) +#define SYSCON_FLASH_ACE2_ATTR_V 0x7 +#define SYSCON_FLASH_ACE2_ATTR_S 0 + +#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x020) + +/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ + +#define SYSCON_FLASH_ACE3_ATTR 0x00000007 +#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S)) +#define SYSCON_FLASH_ACE3_ATTR_V 0x7 +#define SYSCON_FLASH_ACE3_ATTR_S 0 + +#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x024) + +/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S)) +#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE0_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x028) + +/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ + +#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S)) +#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE1_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x02C) + +/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ + +#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S)) +#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE2_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x030) + +/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ + +#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S)) +#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE3_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x034) + +/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ + +#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S)) +#define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE0_SIZE_S 0 + +#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x038) + +/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ + +#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S)) +#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE1_SIZE_S 0 + +#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x03C) + +/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ + +#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S)) +#define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE2_SIZE_S 0 + +#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x040) + +/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ + +#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S)) +#define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE3_SIZE_S 0 + +#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x044) + +/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ + +#define SYSCON_SRAM_ACE0_ATTR 0x00000007 +#define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S)) +#define SYSCON_SRAM_ACE0_ATTR_V 0x7 +#define SYSCON_SRAM_ACE0_ATTR_S 0 + +#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x048) + +/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ + +#define SYSCON_SRAM_ACE1_ATTR 0x00000007 +#define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S)) +#define SYSCON_SRAM_ACE1_ATTR_V 0x7 +#define SYSCON_SRAM_ACE1_ATTR_S 0 + +#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x04C) + +/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ + +#define SYSCON_SRAM_ACE2_ATTR 0x00000007 +#define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S)) +#define SYSCON_SRAM_ACE2_ATTR_V 0x7 +#define SYSCON_SRAM_ACE2_ATTR_S 0 + +#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x050) + +/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */ + +#define SYSCON_SRAM_ACE3_ATTR 0x00000007 +#define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S)) +#define SYSCON_SRAM_ACE3_ATTR_V 0x7 +#define SYSCON_SRAM_ACE3_ATTR_S 0 + +#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x054) + +/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE0_ADDR_S_M ((SYSCON_SRAM_ACE0_ADDR_S_V)<<(SYSCON_SRAM_ACE0_ADDR_S_S)) +#define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE0_ADDR_S_S 0 + +#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x058) + +/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ + +#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE1_ADDR_S_M ((SYSCON_SRAM_ACE1_ADDR_S_V)<<(SYSCON_SRAM_ACE1_ADDR_S_S)) +#define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE1_ADDR_S_S 0 + +#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x05C) + +/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ + +#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S)) +#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE2_ADDR_S_S 0 + +#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x060) + +/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ + +#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE3_ADDR_S_M ((SYSCON_SRAM_ACE3_ADDR_S_V)<<(SYSCON_SRAM_ACE3_ADDR_S_S)) +#define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE3_ADDR_S_S 0 + +#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x064) + +/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ + +#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE0_SIZE_M ((SYSCON_SRAM_ACE0_SIZE_V)<<(SYSCON_SRAM_ACE0_SIZE_S)) +#define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE0_SIZE_S 0 + +#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x068) + +/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ + +#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S)) +#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE1_SIZE_S 0 + +#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x06C) + +/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ + +#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE2_SIZE_M ((SYSCON_SRAM_ACE2_SIZE_V)<<(SYSCON_SRAM_ACE2_SIZE_S)) +#define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE2_SIZE_S 0 + +#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x070) + +/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ + +#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE3_SIZE_M ((SYSCON_SRAM_ACE3_SIZE_V)<<(SYSCON_SRAM_ACE3_SIZE_S)) +#define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE3_SIZE_S 0 + +#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x074) + +/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ + +#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F +#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V)<<(SYSCON_SPI_MEM_REJECT_CDE_S)) +#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F +#define SYSCON_SPI_MEM_REJECT_CDE_S 2 + +/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ + +#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) +#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) +#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 +#define SYSCON_SPI_MEM_REJECT_CLR_S 1 + +/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ + +#define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) +#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) +#define SYSCON_SPI_MEM_REJECT_INT_V 0x1 +#define SYSCON_SPI_MEM_REJECT_INT_S 0 + +#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x078) + +/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF +#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V)<<(SYSCON_SPI_MEM_REJECT_ADDR_S)) +#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF +#define SYSCON_SPI_MEM_REJECT_ADDR_S 0 + +#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x07C) + +/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ + +#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) +#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) +#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 +#define SYSCON_SDIO_WIN_ACCESS_EN_S 0 + +#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x080) + +/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ + +#define SYSCON_REDCY_ANDOR (BIT(31)) +#define SYSCON_REDCY_ANDOR_M (BIT(31)) +#define SYSCON_REDCY_ANDOR_V 0x1 +#define SYSCON_REDCY_ANDOR_S 31 + +/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ + +#define SYSCON_REDCY_SIG0 0x7FFFFFFF +#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S)) +#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF +#define SYSCON_REDCY_SIG0_S 0 + +#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x084) + +/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ + +#define SYSCON_REDCY_NANDOR (BIT(31)) +#define SYSCON_REDCY_NANDOR_M (BIT(31)) +#define SYSCON_REDCY_NANDOR_V 0x1 +#define SYSCON_REDCY_NANDOR_S 31 + +/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ + +#define SYSCON_REDCY_SIG1 0x7FFFFFFF +#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S)) +#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF +#define SYSCON_REDCY_SIG1_S 0 + +#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x088) + +/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S)) +#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_S 0 + +#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x08C) + +/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S)) +#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_2_S 0 + +#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x090) + +/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ + +#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF +#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S)) +#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF +#define SYSCON_WIFI_CLK_EN_S 0 + +#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x094) + +/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define SYSCON_WIFI_RST 0xFFFFFFFF +#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S)) +#define SYSCON_WIFI_RST_V 0xFFFFFFFF +#define SYSCON_WIFI_RST_S 0 + +#define DPORT_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG + +/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ + +#define DPORT_WIFI_CLK_EN 0xFFFFFFFF +#define DPORT_WIFI_CLK_EN_M ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S)) +#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF +#define DPORT_WIFI_CLK_EN_S 0 + +/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21 + * Bit15 not included here because of the bit now can't be cleared + */ + +#define DPORT_WIFI_CLK_WIFI_EN 0x003807cf +#define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S)) +#define DPORT_WIFI_CLK_WIFI_EN_V 0x7cf +#define DPORT_WIFI_CLK_WIFI_EN_S 0 + +/* Mask for all Bluetooth clock bits - 11, 16, 17 */ + +#define DPORT_WIFI_CLK_BT_EN 0x61 +#define DPORT_WIFI_CLK_BT_EN_M ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S)) +#define DPORT_WIFI_CLK_BT_EN_V 0x61 +#define DPORT_WIFI_CLK_BT_EN_S 11 + +/* Mask for clock bits used by both WIFI and Bluetooth, + * bit 0, 3, 6, 7, 8, 9 + */ + +#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9 +#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M + +/* bluetooth baseband bit11 */ + +#define DPORT_BT_BASEBAND_EN BIT(11) + +/* bluetooth LC bit16 and bit17 */ + +#define DPORT_BT_LC_EN (BIT(16)|BIT(17)) + +/* Remaining single bit clock masks */ + +#define DPORT_WIFI_CLK_SDIOSLAVE_EN BIT(4) +#define DPORT_WIFI_CLK_UNUSED_BIT5 BIT(5) +#define DPORT_WIFI_CLK_UNUSED_BIT12 BIT(12) +#define DPORT_WIFI_CLK_SDIO_HOST_EN BIT(13) +#define DPORT_WIFI_CLK_EMAC_EN BIT(14) +#define DPORT_WIFI_CLK_RNG_EN BIT(15) + +#define DPORT_CORE_RST_EN_REG DPORT_WIFI_RST_EN_REG +#define DPORT_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG + +/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ + +#define DPORT_WIFI_RST 0xFFFFFFFF +#define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S)) +#define DPORT_WIFI_RST_V 0xFFFFFFFF +#define DPORT_WIFI_RST_S 0 + +#define DPORT_WIFIBB_RST BIT(0) +#define DPORT_FE_RST BIT(1) +#define DPORT_WIFIMAC_RST BIT(2) +#define DPORT_BTBB_RST BIT(3) +#define DPORT_BTMAC_RST BIT(4) +#define DPORT_SDIO_RST BIT(5) +#define DPORT_EMAC_RST BIT(7) +#define DPORT_MACPWR_RST BIT(8) +#define DPORT_RW_BTMAC_RST BIT(9) +#define DPORT_RW_BTLP_RST BIT(10) + +#define MODEM_RESET_FIELD_WHEN_PU (DPORT_WIFIBB_RST | \ + DPORT_FE_RST | \ + DPORT_WIFIMAC_RST | \ + DPORT_BTBB_RST | \ + DPORT_BTMAC_RST | \ + DPORT_RW_BTMAC_RST) + +#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098) + +/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ + +#define SYSCON_DC_MEM_FORCE_PD (BIT(5)) +#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) +#define SYSCON_DC_MEM_FORCE_PD_V 0x1 +#define SYSCON_DC_MEM_FORCE_PD_S 5 + +/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ + +#define SYSCON_DC_MEM_FORCE_PU (BIT(4)) +#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) +#define SYSCON_DC_MEM_FORCE_PU_V 0x1 +#define SYSCON_DC_MEM_FORCE_PU_S 4 + +/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ + +#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) +#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 +#define SYSCON_PBUS_MEM_FORCE_PD_S 3 + +/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ + +#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) +#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 +#define SYSCON_PBUS_MEM_FORCE_PU_S 2 + +/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ + +#define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) +#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) +#define SYSCON_AGC_MEM_FORCE_PD_V 0x1 +#define SYSCON_AGC_MEM_FORCE_PD_S 1 + +/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ + +#define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) +#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) +#define SYSCON_AGC_MEM_FORCE_PU_V 0x1 +#define SYSCON_AGC_MEM_FORCE_PU_S 0 + +#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) + +/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h1907010 ; */ + +#define SYSCON_DATE 0xFFFFFFFF +#define SYSCON_DATE_M ((SYSCON_DATE_V)<<(SYSCON_DATE_S)) +#define SYSCON_DATE_V 0xFFFFFFFF +#define SYSCON_DATE_S 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSCON_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/regi2c_bbpll.h b/arch/xtensa/src/esp32s2/hardware/regi2c_bbpll.h new file mode 100644 index 0000000000000..9cd617be778d2 --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/regi2c_bbpll.h @@ -0,0 +1,192 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/regi2c_bbpll.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_BBPLL_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_BBPLL_H + +/** + * @file regi2c_bbpll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal + * configuration bus. These definitions are used via macros defined + * in regi2c_ctrl.h, by rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 1 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_ENB_FCAL 2 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_RSTB_DIV_ADC 4 +#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 +#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_DIV_ADC 4 +#define I2C_BBPLL_DIV_ADC_MSB 3 +#define I2C_BBPLL_DIV_ADC_LSB 2 + +#define I2C_BBPLL_DIV_DAC 4 +#define I2C_BBPLL_DIV_DAC_MSB 4 +#define I2C_BBPLL_DIV_DAC_LSB 4 + +#define I2C_BBPLL_DIV_CPU 4 +#define I2C_BBPLL_DIV_CPU_MSB 5 +#define I2C_BBPLL_DIV_CPU_LSB 5 + +#define I2C_BBPLL_OC_ENB_VCON 4 +#define I2C_BBPLL_OC_ENB_VCON_MSB 6 +#define I2C_BBPLL_OC_ENB_VCON_LSB 6 + +#define I2C_BBPLL_OC_TSCHGP 4 +#define I2C_BBPLL_OC_TSCHGP_MSB 7 +#define I2C_BBPLL_OC_TSCHGP_LSB 7 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_EN_USB 5 +#define I2C_BBPLL_EN_USB_MSB 7 +#define I2C_BBPLL_EN_USB_LSB 7 + +#define I2C_BBPLL_OC_DCUR 6 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_INC_CUR 6 +#define I2C_BBPLL_INC_CUR_MSB 3 +#define I2C_BBPLL_INC_CUR_LSB 3 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_CAL_CAP 8 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 8 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 8 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 8 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 7 +#define I2C_BBPLL_OR_LOCK_LSB 7 + +#define I2C_BBPLL_BBADC_DELAY1 9 +#define I2C_BBPLL_BBADC_DELAY1_MSB 1 +#define I2C_BBPLL_BBADC_DELAY1_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 9 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DVDD 9 +#define I2C_BBPLL_BBADC_DVDD_MSB 5 +#define I2C_BBPLL_BBADC_DVDD_LSB 4 + +#define I2C_BBPLL_BBADC_DREF 9 +#define I2C_BBPLL_BBADC_DREF_MSB 7 +#define I2C_BBPLL_BBADC_DREF_LSB 6 + +#define I2C_BBPLL_BBADC_DCUR 10 +#define I2C_BBPLL_BBADC_DCUR_MSB 1 +#define I2C_BBPLL_BBADC_DCUR_LSB 0 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 10 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 7 +#define I2C_BBPLL_ENT_ADC_LSB 6 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_BBPLL_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/regi2c_ctrl.h b/arch/xtensa/src/esp32s2/hardware/regi2c_ctrl.h new file mode 100644 index 0000000000000..c94b82f4628bb --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/regi2c_ctrl.h @@ -0,0 +1,54 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/regi2c_ctrl.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_CTRL_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_CTRL_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "esp32s2_soc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Convenience macros for the above functions, these use register + * definitions from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/ + * regi2c_bias.h header files. + */ + +#define REGI2C_WRITE_MASK(block, reg_add, indata) \ + rom_i2c_writereg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, \ + reg_add##_LSB, indata) + +#define REGI2C_READ_MASK(block, reg_add) \ + rom_i2c_readreg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, \ + reg_add##_LSB) + +#define REGI2C_WRITE(block, reg_add, indata) \ + rom_i2c_writereg(block, block##_HOSTID, reg_add, indata) + +#define REGI2C_READ(block, reg_add) \ + rom_i2c_readreg(block, block##_HOSTID, reg_add) + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_CTRL_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/regi2c_lp_bias.h b/arch/xtensa/src/esp32s2/hardware/regi2c_lp_bias.h new file mode 100644 index 0000000000000..31e45f768355f --- /dev/null +++ b/arch/xtensa/src/esp32s2/hardware/regi2c_lp_bias.h @@ -0,0 +1,56 @@ +/**************************************************************************** + * arch/xtensa/src/esp32s2/hardware/regi2c_lp_bias.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_LP_BIAS_H +#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_LP_BIAS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register definitions for analog to calibrate o_code for getting a more + * precise voltage. This file lists register fields of low power dbais, + * located on an internal configuration bus. + */ + +#define I2C_ULP 0x61 +#define I2C_ULP_HOSTID 1 + +#define I2C_ULP_IR_RESETB 0 +#define I2C_ULP_IR_RESETB_MSB 0 +#define I2C_ULP_IR_RESETB_LSB 0 + +#define I2C_ULP_O_DONE_FLAG 3 +#define I2C_ULP_O_DONE_FLAG_MSB 0 +#define I2C_ULP_O_DONE_FLAG_LSB 0 + +#define I2C_ULP_BG_O_DONE_FLAG 3 +#define I2C_ULP_BG_O_DONE_FLAG_MSB 3 +#define I2C_ULP_BG_O_DONE_FLAG_LSB 3 + +#define I2C_ULP_IR_FORCE_CODE 5 +#define I2C_ULP_IR_FORCE_CODE_MSB 6 +#define I2C_ULP_IR_FORCE_CODE_LSB 6 + +#define I2C_ULP_EXT_CODE 6 +#define I2C_ULP_EXT_CODE_MSB 7 +#define I2C_ULP_EXT_CODE_LSB 0 + +#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_REGI2C_LP_BIAS_H */ diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/rtc/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/rtc/defconfig new file mode 100644 index 0000000000000..f52e1ecc21123 --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/rtc/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32s2-kaluga-1" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y +CONFIG_ARCH_CHIP="esp32s2" +CONFIG_ARCH_CHIP_ESP32S2=y +CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32S2_RT_TIMER=y +CONFIG_ESP32S2_UART0=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_RTC_NALARMS=2 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_bringup.c b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_bringup.c index 1571c7d9f0aac..7a57898a24b90 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_bringup.c +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_bringup.c @@ -84,6 +84,10 @@ # include "esp32s2_board_spislavedev.h" #endif +#ifdef CONFIG_RTC_DRIVER +# include "esp32s2_rtc_lowerhalf.h" +#endif + #include "esp32s2-kaluga-1.h" /**************************************************************************** @@ -312,6 +316,17 @@ int esp32s2_bringup(void) #endif /* CONFIG_ESP32S2_I2S */ +#ifdef CONFIG_RTC_DRIVER + /* Instantiate the ESP32 RTC driver */ + + ret = esp32s2_rtc_driverinit(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to Instantiate the RTC driver: %d\n", ret); + } +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities. diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rtc/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rtc/defconfig new file mode 100644 index 0000000000000..f47194ac9a10a --- /dev/null +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rtc/defconfig @@ -0,0 +1,51 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_ARCH_LEDS is not set +# CONFIG_NSH_ARGCAT is not set +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_ARCH="xtensa" +CONFIG_ARCH_BOARD="esp32s2-saola-1" +CONFIG_ARCH_BOARD_COMMON=y +CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y +CONFIG_ARCH_CHIP="esp32s2" +CONFIG_ARCH_CHIP_ESP32S2=y +CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH_XTENSA=y +CONFIG_BOARD_LOOPSPERMSEC=16717 +CONFIG_BUILTIN=y +CONFIG_ESP32S2_RT_TIMER=y +CONFIG_ESP32S2_UART0=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +CONFIG_IDLETHREAD_STACKSIZE=3072 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_MM_REGIONS=3 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=114688 +CONFIG_RAM_START=0x20000000 +CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_ALARM=y +CONFIG_RTC_DRIVER=y +CONFIG_RTC_NALARMS=2 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_SYSLOG_BUFFER=y +CONFIG_SYSTEM_NSH=y +CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c index e1c67318b094f..9c5bf5ce0c426 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c @@ -84,6 +84,10 @@ # include "esp32s2_board_spislavedev.h" #endif +#ifdef CONFIG_RTC_DRIVER +# include "esp32s2_rtc_lowerhalf.h" +#endif + #include "esp32s2-saola-1.h" /**************************************************************************** @@ -358,6 +362,17 @@ int esp32s2_bringup(void) #endif /* CONFIG_ESP32S2_I2S */ +#ifdef CONFIG_RTC_DRIVER + /* Instantiate the ESP32 RTC driver */ + + ret = esp32s2_rtc_driverinit(); + if (ret < 0) + { + syslog(LOG_ERR, + "ERROR: Failed to Instantiate the RTC driver: %d\n", ret); + } +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities.