From e3fdd64c2bf2cb3252f197da52b13f91685259c7 Mon Sep 17 00:00:00 2001
From: Dylan McKay <dylanmckay34@gmail.com>
Date: Fri, 30 Sep 2016 04:26:03 +1300
Subject: [PATCH] [AVR] Add 16-bit STS instruction

---
 lib/Target/AVR/AVRInstrFormats.td | 13 +++++++++++++
 lib/Target/AVR/AVRInstrInfo.td    | 27 +++++++++++++++++++++++++++
 lib/Target/AVR/AVRRegisterInfo.td |  7 +++++++
 3 files changed, 47 insertions(+)

diff --git a/lib/Target/AVR/AVRInstrFormats.td b/lib/Target/AVR/AVRInstrFormats.td
index ce5e606f978..1d2fa020900 100644
--- a/lib/Target/AVR/AVRInstrFormats.td
+++ b/lib/Target/AVR/AVRInstrFormats.td
@@ -377,6 +377,19 @@ class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
   let Inst{2-0} = b{2-0};
 }
 
+class FIO16<bit type, dag outs, dag ins, string asmstr, list<dag> pattern>
+  : AVRInst16<outs, ins, asmstr, pattern>
+{
+  bits<7> k;
+  bits<4> d;
+
+  let Inst{15-12} = 0b1010;
+  let Inst{11} = type;
+  let Inst{10-8} = k{6-4};
+  let Inst{7-4} = d;
+  let Inst{3-0} = k{3-0};
+}
+
 //===----------------------------------------------------------------------===//
 // BST/BLD instruction.
 // <|1111|1ttd|dddd|0bbb>
diff --git a/lib/Target/AVR/AVRInstrInfo.td b/lib/Target/AVR/AVRInstrInfo.td
index f30cbf0b2e2..1d03a38eb6f 100644
--- a/lib/Target/AVR/AVRInstrInfo.td
+++ b/lib/Target/AVR/AVRInstrInfo.td
@@ -87,6 +87,7 @@ def imm0_63_neg : PatLeaf<(imm),
 }], imm16_neg_XFORM>;
 
 def uimm6 : PatLeaf<(imm), [{ return isUInt<6>(N->getZExtValue()); }]>;
+def uimm7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>;
 
 def ioaddr_XFORM : SDNodeXForm<imm,
 [{
@@ -1135,6 +1136,19 @@ isReMaterializable = 1 in
                 Requires<[HasSRAM]>;
 }
 
+// Indirect load from data space to register.
+// FIXME:
+// - make this a physical instruction (not a pseudo)
+// - map r0..r15 onto r16..r31 so that the numbers match up.
+// - do weird MSB inversion as specified in datsheet
+// encoding:
+def LDS16KRr : FIO16<0,
+                     (outs),
+                     (ins uimm7:$k, GPR8hi:$rd),
+                     "sts\t$k, $rd",
+                     [store i8:$rd, imm:$k]>,
+               Requires<[HasTinyEncoding]>;
+
 // Indirect loads.
 let canFoldAsLoad = 1,
 isReMaterializable = 1 in
@@ -1275,6 +1289,19 @@ def STSKRr : F32DM<0b1,
                    [(store i8:$rd, imm:$k)]>,
              Requires<[HasSRAM]>;
 
+// Indirect store from register to data space.
+// FIXME:
+// - make this a physical instruction (not a pseudo)
+// - map r0..r15 onto r16..r31 so that the numbers match up.
+// - do weird MSB inversion as specified in datsheet
+// encoding:
+def STS16KRr : FIO16<1,
+                     (outs),
+                     (ins uimm7:$k, GPR8hi:$rd),
+                     "sts\t$k, $rd",
+                     [store i8:$rd, imm:$k]>,
+               Requires<[HasTinyEncoding]>;
+
 // STSW K+1:K, Rr+1:Rr
 //
 // Expands to:
diff --git a/lib/Target/AVR/AVRRegisterInfo.td b/lib/Target/AVR/AVRRegisterInfo.td
index 32650fc6675..c5d9589d531 100644
--- a/lib/Target/AVR/AVRRegisterInfo.td
+++ b/lib/Target/AVR/AVRRegisterInfo.td
@@ -130,6 +130,13 @@ def GPR8lo : RegisterClass<"AVR", [i8], 8,
     add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
   )>;
 
+// Upper registers r0..r15
+def GPR8hi : RegisterClass<"AVR", [i8], 8,
+  (
+    add R16, R17, R18, R19, R20, R21, R22, R23,
+        R24, R25, R26, R27, R28, R29, R30, R31
+  )>;
+
 // 8-bit register class for instructions which take immediates.
 def LD8 : RegisterClass<"AVR", [i8], 8,
   (