Modify default intermediate AIGER file name.

alanminko · alanminko · commit cd6e9b582ba7 · 2026-05-21T23:41:12.000-07:00
diff --git a/src/base/abci/abc.c b/src/base/abci/abc.c
@@ -43284,6 +43284,7 @@ static Gia_Man_t * Abc_ReadAigerOrVerilogFile( char * pFileName, char * pFileNam
     Gia_Man_t * pGia;
     char * pTemp;
     char * pOrigFileName = NULL;
+    char * pFileTemp = NULL;
     int fVerilog, fSystemVerilog;
 
     *pAbc_ReadAigerOrVerilogFileStatus = 0;
@@ -43312,17 +43313,24 @@ static Gia_Man_t * Abc_ReadAigerOrVerilogFile( char * pFileName, char * pFileNam
         extern Aig_Man_t * Abc_NtkToDar( Abc_Ntk_t * pNtk, int fExors, int fRegisters );
         Aig_Man_t * pAig = NULL;
         char pCommand[2000];
+        char * pFileBase;
         int RetValue;
         int fSystemVerilog2 = pFileName2 && Extra_FileIsType( pFileName2, ".sv", NULL, NULL );
         // Save the original filename before changing it
         pOrigFileName = pFileName;
+        pFileBase = pTopModule ? Abc_UtilStrsav(pTopModule) :
+            Extra_FileNameGeneric( Extra_FileNameWithoutPath(pFileName) );
+        pFileTemp = ABC_ALLOC( char, strlen(pFileBase) + 5 );
+        sprintf( pFileTemp, "%s.aig", pFileBase );
+        ABC_FREE( pFileBase );
         snprintf( pCommand, sizeof(pCommand),
-            "yosys -qp \"read_verilog %s%s %s%s%s%s; hierarchy %s%s; flatten; proc; opt; async2sync; opt; setundef -undriven -zero; techmap; memory -nomap; memory_map; dffunmap; opt_clean; opt_expr; %saigmap; write_aiger -symbols _temp_.aig\"",
+            "yosys -qp \"read_verilog %s%s %s%s%s%s; hierarchy %s%s; flatten; proc; opt; async2sync; opt; setundef -undriven -zero; techmap; memory -nomap; memory_map; dffunmap; opt_clean; opt_expr; %saigmap; write_aiger -symbols %s\"",
             pDefines ? "-D" : "", pDefines ? pDefines : "",
             (fSystemVerilog || fSystemVerilog2) ? "-sv " : "", pFileName,
             pFileName2 ? " " : "", pFileName2 ? pFileName2 : "",
             pTopModule ? "-top "    : "-auto-top", pTopModule ? pTopModule : "",
-            pFileName2 ? "delete t:\\$scopeinfo; " : "" );
+            pFileName2 ? "delete t:\\$scopeinfo; " : "",
+            pFileTemp );
 #if defined(__wasm)
         RetValue = 1;
 #else
@@ -43331,29 +43339,32 @@ static Gia_Man_t * Abc_ReadAigerOrVerilogFile( char * pFileName, char * pFileNam
         if ( RetValue != 0 )
         {
             Abc_Print( -1, "Yosys command failed: \"%s\".\n", pCommand );
+            ABC_FREE( pFileTemp );
             return NULL;
         }
         if ( pFileName2 )
         {
-            Abc_Ntk_t * pNtk = Io_Read( "_temp_.aig", IO_FILE_AIGER, 1, 0 );
+            Abc_Ntk_t * pNtk = Io_Read( pFileTemp, IO_FILE_AIGER, 1, 0 );
             if ( pNtk == NULL )
             {
-                Abc_Print( -1, "Reading AIGER from file \"%s\" has failed.\n", "_temp_.aig" );
+                Abc_Print( -1, "Reading AIGER from file \"%s\" has failed.\n", pFileTemp );
+                ABC_FREE( pFileTemp );
                 return NULL;
             }
             pAig = Abc_NtkToDar( pNtk, 0, 1 );
             Abc_NtkDelete( pNtk );
             if ( pAig == NULL )
             {
                 Abc_Print( -1, "Converting the AIGER network into an internal AIG has failed.\n" );
+                ABC_FREE( pFileTemp );
                 return NULL;
             }
             pGia = Gia_ManFromAig( pAig );
             Aig_ManStop( pAig );
         }
         else
         {
-            pFileName = "_temp_.aig";
+            pFileName = pFileTemp;
             pGia = Gia_AigerRead( pFileName, 0, 0, 0 );
         }
     }
@@ -43362,6 +43373,7 @@ static Gia_Man_t * Abc_ReadAigerOrVerilogFile( char * pFileName, char * pFileNam
     if ( pGia == NULL )
     {
         Abc_Print( -1, "Reading AIGER from file \"%s\" has failed.\n", pFileName );
+        ABC_FREE( pFileTemp );
         return NULL;
     }
 
@@ -43372,6 +43384,7 @@ static Gia_Man_t * Abc_ReadAigerOrVerilogFile( char * pFileName, char * pFileNam
         pGia->pSpec = Abc_UtilStrsav( pOrigFileName );
     }
 
+    ABC_FREE( pFileTemp );
     return pGia;
 }
 
diff --git a/src/base/wln/wlnRtl.c b/src/base/wln/wlnRtl.c
@@ -212,10 +212,15 @@ Gia_Man_t * Wln_BlastSystemVerilog( char ** ppFileNames, int nFileNames, char *
 {
     Gia_Man_t * pGia = NULL;
     char * pFileNames, * pCommand;
-    char * pFileTemp = "_temp_.aig";
+    char * pFileTemp, * pFileBase;
     int fRtlil = nFileNames == 1 && strstr(ppFileNames[0], ".rtl") != NULL;
     int fSVlog = Wln_FileNamesHasSv(ppFileNames, nFileNames);
     int nCommand;
+    pFileBase = pTopModule ? Abc_UtilStrsav(pTopModule) :
+        Extra_FileNameGeneric( Extra_FileNameWithoutPath(ppFileNames[0]) );
+    pFileTemp = ABC_ALLOC( char, strlen(pFileBase) + 5 );
+    sprintf( pFileTemp, "%s.aig", pFileBase );
+    ABC_FREE( pFileBase );
     pFileNames = Wln_FileNamesJoin( ppFileNames, nFileNames );
     nCommand = strlen(Wln_GetYosysName()) + strlen(pFileNames) + (pDefines ? strlen(pDefines) : 0) + (pTopModule ? strlen(pTopModule) : 0) + strlen(pFileTemp) + 500;
     pCommand = ABC_ALLOC( char, nCommand );
@@ -238,6 +243,7 @@ Gia_Man_t * Wln_BlastSystemVerilog( char ** ppFileNames, int nFileNames, char *
     {
         ABC_FREE( pCommand );
         ABC_FREE( pFileNames );
+        ABC_FREE( pFileTemp );
         return NULL;
     }
     ABC_FREE( pCommand );
@@ -250,13 +256,15 @@ Gia_Man_t * Wln_BlastSystemVerilog( char ** ppFileNames, int nFileNames, char *
         if ( pNtk == NULL )
         {
             printf( "Reading AIGER from file \"%s\" has failed.\n", pFileTemp );
+            ABC_FREE( pFileTemp );
             return NULL;
         }
         pAig = Abc_NtkToDar( pNtk, 0, 1 );
         Abc_NtkDelete( pNtk );
         if ( pAig == NULL )
         {
             printf( "Converting the AIGER network into an internal AIG has failed.\n" );
+            ABC_FREE( pFileTemp );
             return NULL;
         }
         pGia = fSkipStrash ? Gia_ManFromAigSimple(pAig) : Gia_ManFromAig(pAig);
@@ -267,12 +275,14 @@ Gia_Man_t * Wln_BlastSystemVerilog( char ** ppFileNames, int nFileNames, char *
     if ( pGia == NULL )
     {
         printf( "Converting to AIG has failed.\n" );
+        ABC_FREE( pFileTemp );
         return NULL;
     }
     ABC_FREE( pGia->pName );
     pGia->pName = pTopModule ? Abc_UtilStrsav(pTopModule) :
         Extra_FileNameGeneric( Extra_FileNameWithoutPath(ppFileNames[0]) );
     unlink( pFileTemp );
+    ABC_FREE( pFileTemp );
     // complement the outputs
     if ( fInvert )
     {

Original file line number	Diff line number	Diff line change
`@@ -43284,6 +43284,7 @@ static Gia_Man_t * Abc_ReadAigerOrVerilogFile( char * pFileName, char * pFileNam`
`43284`	`43284`	`Gia_Man_t * pGia;`
`43285`	`43285`	`char * pTemp;`
`43286`	`43286`	`char * pOrigFileName = NULL;`
	`43287`	`+ char * pFileTemp = NULL;`
`43287`	`43288`	`int fVerilog, fSystemVerilog;`
`43288`	`43289`
`43289`	`43290`	`*pAbc_ReadAigerOrVerilogFileStatus = 0;`
`@@ -43312,17 +43313,24 @@ static Gia_Man_t * Abc_ReadAigerOrVerilogFile( char * pFileName, char * pFileNam`
`43312`	`43313`	`extern Aig_Man_t * Abc_NtkToDar( Abc_Ntk_t * pNtk, int fExors, int fRegisters );`
`43313`	`43314`	`Aig_Man_t * pAig = NULL;`
`43314`	`43315`	`char pCommand[2000];`
	`43316`	`+ char * pFileBase;`
`43315`	`43317`	`int RetValue;`
`43316`	`43318`	`int fSystemVerilog2 = pFileName2 && Extra_FileIsType( pFileName2, ".sv", NULL, NULL );`
`43317`	`43319`	`// Save the original filename before changing it`
`43318`	`43320`	`pOrigFileName = pFileName;`
	`43321`	`+ pFileBase = pTopModule ? Abc_UtilStrsav(pTopModule) :`
	`43322`	`+ Extra_FileNameGeneric( Extra_FileNameWithoutPath(pFileName) );`
	`43323`	`+ pFileTemp = ABC_ALLOC( char, strlen(pFileBase) + 5 );`
	`43324`	`+ sprintf( pFileTemp, "%s.aig", pFileBase );`
	`43325`	`+ ABC_FREE( pFileBase );`
`43319`	`43326`	`snprintf( pCommand, sizeof(pCommand),`
`43320`		`- "yosys -qp \"read_verilog %s%s %s%s%s%s; hierarchy %s%s; flatten; proc; opt; async2sync; opt; setundef -undriven -zero; techmap; memory -nomap; memory_map; dffunmap; opt_clean; opt_expr; %saigmap; write_aiger -symbols _temp_.aig\"",`
	`43327`	`+ "yosys -qp \"read_verilog %s%s %s%s%s%s; hierarchy %s%s; flatten; proc; opt; async2sync; opt; setundef -undriven -zero; techmap; memory -nomap; memory_map; dffunmap; opt_clean; opt_expr; %saigmap; write_aiger -symbols %s\"",`
`43321`	`43328`	`pDefines ? "-D" : "", pDefines ? pDefines : "",`
`43322`	`43329`	`(fSystemVerilog \|\| fSystemVerilog2) ? "-sv " : "", pFileName,`
`43323`	`43330`	`pFileName2 ? " " : "", pFileName2 ? pFileName2 : "",`
`43324`	`43331`	`pTopModule ? "-top " : "-auto-top", pTopModule ? pTopModule : "",`
`43325`		`- pFileName2 ? "delete t:\\$scopeinfo; " : "" );`
	`43332`	`+ pFileName2 ? "delete t:\\$scopeinfo; " : "",`
	`43333`	`+ pFileTemp );`
`43326`	`43334`	`#if defined(__wasm)`
`43327`	`43335`	`RetValue = 1;`
`43328`	`43336`	`#else`
`@@ -43331,29 +43339,32 @@ static Gia_Man_t * Abc_ReadAigerOrVerilogFile( char * pFileName, char * pFileNam`
`43331`	`43339`	`if ( RetValue != 0 )`
`43332`	`43340`	`{`
`43333`	`43341`	`Abc_Print( -1, "Yosys command failed: \"%s\".\n", pCommand );`
	`43342`	`+ ABC_FREE( pFileTemp );`
`43334`	`43343`	`return NULL;`
`43335`	`43344`	`}`
`43336`	`43345`	`if ( pFileName2 )`
`43337`	`43346`	`{`
`43338`		`- Abc_Ntk_t * pNtk = Io_Read( "_temp_.aig", IO_FILE_AIGER, 1, 0 );`
	`43347`	`+ Abc_Ntk_t * pNtk = Io_Read( pFileTemp, IO_FILE_AIGER, 1, 0 );`
`43339`	`43348`	`if ( pNtk == NULL )`
`43340`	`43349`	`{`
`43341`		`- Abc_Print( -1, "Reading AIGER from file \"%s\" has failed.\n", "_temp_.aig" );`
	`43350`	`+ Abc_Print( -1, "Reading AIGER from file \"%s\" has failed.\n", pFileTemp );`
	`43351`	`+ ABC_FREE( pFileTemp );`
`43342`	`43352`	`return NULL;`
`43343`	`43353`	`}`
`43344`	`43354`	`pAig = Abc_NtkToDar( pNtk, 0, 1 );`
`43345`	`43355`	`Abc_NtkDelete( pNtk );`
`43346`	`43356`	`if ( pAig == NULL )`
`43347`	`43357`	`{`
`43348`	`43358`	`Abc_Print( -1, "Converting the AIGER network into an internal AIG has failed.\n" );`
	`43359`	`+ ABC_FREE( pFileTemp );`
`43349`	`43360`	`return NULL;`
`43350`	`43361`	`}`
`43351`	`43362`	`pGia = Gia_ManFromAig( pAig );`
`43352`	`43363`	`Aig_ManStop( pAig );`
`43353`	`43364`	`}`
`43354`	`43365`	`else`
`43355`	`43366`	`{`
`43356`		`- pFileName = "_temp_.aig";`
	`43367`	`+ pFileName = pFileTemp;`
`43357`	`43368`	`pGia = Gia_AigerRead( pFileName, 0, 0, 0 );`
`43358`	`43369`	`}`
`43359`	`43370`	`}`
`@@ -43362,6 +43373,7 @@ static Gia_Man_t * Abc_ReadAigerOrVerilogFile( char * pFileName, char * pFileNam`
`43362`	`43373`	`if ( pGia == NULL )`
`43363`	`43374`	`{`
`43364`	`43375`	`Abc_Print( -1, "Reading AIGER from file \"%s\" has failed.\n", pFileName );`
	`43376`	`+ ABC_FREE( pFileTemp );`
`43365`	`43377`	`return NULL;`
`43366`	`43378`	`}`
`43367`	`43379`
`@@ -43372,6 +43384,7 @@ static Gia_Man_t * Abc_ReadAigerOrVerilogFile( char * pFileName, char * pFileNam`
`43372`	`43384`	`pGia->pSpec = Abc_UtilStrsav( pOrigFileName );`
`43373`	`43385`	`}`
`43374`	`43386`
	`43387`	`+ ABC_FREE( pFileTemp );`
`43375`	`43388`	`return pGia;`
`43376`	`43389`	`}`
`43377`	`43390`
Original file line number	Diff line number	Diff line change
`@@ -212,10 +212,15 @@ Gia_Man_t * Wln_BlastSystemVerilog( char ** ppFileNames, int nFileNames, char *`
`212`	`212`	`{`
`213`	`213`	`Gia_Man_t * pGia = NULL;`
`214`	`214`	`char * pFileNames, * pCommand;`
`215`		`- char * pFileTemp = "_temp_.aig";`
	`215`	`+ char * pFileTemp, * pFileBase;`
`216`	`216`	`int fRtlil = nFileNames == 1 && strstr(ppFileNames[0], ".rtl") != NULL;`
`217`	`217`	`int fSVlog = Wln_FileNamesHasSv(ppFileNames, nFileNames);`
`218`	`218`	`int nCommand;`
	`219`	`+ pFileBase = pTopModule ? Abc_UtilStrsav(pTopModule) :`
	`220`	`+ Extra_FileNameGeneric( Extra_FileNameWithoutPath(ppFileNames[0]) );`
	`221`	`+ pFileTemp = ABC_ALLOC( char, strlen(pFileBase) + 5 );`
	`222`	`+ sprintf( pFileTemp, "%s.aig", pFileBase );`
	`223`	`+ ABC_FREE( pFileBase );`
`219`	`224`	`pFileNames = Wln_FileNamesJoin( ppFileNames, nFileNames );`
`220`	`225`	`nCommand = strlen(Wln_GetYosysName()) + strlen(pFileNames) + (pDefines ? strlen(pDefines) : 0) + (pTopModule ? strlen(pTopModule) : 0) + strlen(pFileTemp) + 500;`
`221`	`226`	`pCommand = ABC_ALLOC( char, nCommand );`
`@@ -238,6 +243,7 @@ Gia_Man_t * Wln_BlastSystemVerilog( char ** ppFileNames, int nFileNames, char *`
`238`	`243`	`{`
`239`	`244`	`ABC_FREE( pCommand );`
`240`	`245`	`ABC_FREE( pFileNames );`
	`246`	`+ ABC_FREE( pFileTemp );`
`241`	`247`	`return NULL;`
`242`	`248`	`}`
`243`	`249`	`ABC_FREE( pCommand );`
`@@ -250,13 +256,15 @@ Gia_Man_t * Wln_BlastSystemVerilog( char ** ppFileNames, int nFileNames, char *`
`250`	`256`	`if ( pNtk == NULL )`
`251`	`257`	`{`
`252`	`258`	`printf( "Reading AIGER from file \"%s\" has failed.\n", pFileTemp );`
	`259`	`+ ABC_FREE( pFileTemp );`
`253`	`260`	`return NULL;`
`254`	`261`	`}`
`255`	`262`	`pAig = Abc_NtkToDar( pNtk, 0, 1 );`
`256`	`263`	`Abc_NtkDelete( pNtk );`
`257`	`264`	`if ( pAig == NULL )`
`258`	`265`	`{`
`259`	`266`	`printf( "Converting the AIGER network into an internal AIG has failed.\n" );`
	`267`	`+ ABC_FREE( pFileTemp );`
`260`	`268`	`return NULL;`
`261`	`269`	`}`
`262`	`270`	`pGia = fSkipStrash ? Gia_ManFromAigSimple(pAig) : Gia_ManFromAig(pAig);`
`@@ -267,12 +275,14 @@ Gia_Man_t * Wln_BlastSystemVerilog( char ** ppFileNames, int nFileNames, char *`
`267`	`275`	`if ( pGia == NULL )`
`268`	`276`	`{`
`269`	`277`	`printf( "Converting to AIG has failed.\n" );`
	`278`	`+ ABC_FREE( pFileTemp );`
`270`	`279`	`return NULL;`
`271`	`280`	`}`
`272`	`281`	`ABC_FREE( pGia->pName );`
`273`	`282`	`pGia->pName = pTopModule ? Abc_UtilStrsav(pTopModule) :`
`274`	`283`	`Extra_FileNameGeneric( Extra_FileNameWithoutPath(ppFileNames[0]) );`
`275`	`284`	`unlink( pFileTemp );`
	`285`	`+ ABC_FREE( pFileTemp );`
`276`	`286`	`// complement the outputs`
`277`	`287`	`if ( fInvert )`
`278`	`288`	`{`